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Linux Kernel
3.7.1
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Macros | |
| #define | AT91_DDRSDRC_MR 0x00 /* Mode Register */ |
| #define | AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ |
| #define | AT91_DDRSDRC_MODE_NORMAL 0 |
| #define | AT91_DDRSDRC_MODE_NOP 1 |
| #define | AT91_DDRSDRC_MODE_PRECHARGE 2 |
| #define | AT91_DDRSDRC_MODE_LMR 3 |
| #define | AT91_DDRSDRC_MODE_REFRESH 4 |
| #define | AT91_DDRSDRC_MODE_EXT_LMR 5 |
| #define | AT91_DDRSDRC_MODE_DEEP 6 |
| #define | AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ |
| #define | AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ |
| #define | AT91_DDRSDRC_CR 0x08 /* Configuration Register */ |
| #define | AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ |
| #define | AT91_DDRSDRC_NC_SDR8 (0 << 0) |
| #define | AT91_DDRSDRC_NC_SDR9 (1 << 0) |
| #define | AT91_DDRSDRC_NC_SDR10 (2 << 0) |
| #define | AT91_DDRSDRC_NC_SDR11 (3 << 0) |
| #define | AT91_DDRSDRC_NC_DDR9 (0 << 0) |
| #define | AT91_DDRSDRC_NC_DDR10 (1 << 0) |
| #define | AT91_DDRSDRC_NC_DDR11 (2 << 0) |
| #define | AT91_DDRSDRC_NC_DDR12 (3 << 0) |
| #define | AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ |
| #define | AT91_DDRSDRC_NR_11 (0 << 2) |
| #define | AT91_DDRSDRC_NR_12 (1 << 2) |
| #define | AT91_DDRSDRC_NR_13 (2 << 2) |
| #define | AT91_DDRSDRC_NR_14 (3 << 2) |
| #define | AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ |
| #define | AT91_DDRSDRC_CAS_2 (2 << 4) |
| #define | AT91_DDRSDRC_CAS_3 (3 << 4) |
| #define | AT91_DDRSDRC_CAS_25 (6 << 4) |
| #define | AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ |
| #define | AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ |
| #define | AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ |
| #define | AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ |
| #define | AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ |
| #define | AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ |
| #define | AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ |
| #define | AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ |
| #define | AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ |
| #define | AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ |
| #define | AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ |
| #define | AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
| #define | AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
| #define | AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
| #define | AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ |
| #define | AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
| #define | AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ |
| #define | AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ |
| #define | AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ |
| #define | AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ |
| #define | AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ |
| #define | AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ |
| #define | AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ |
| #define | AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ |
| #define | AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ |
| #define | AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
| #define | AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
| #define | AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
| #define | AT91_DDRSDRC_LPCB_DISABLE 0 |
| #define | AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
| #define | AT91_DDRSDRC_LPCB_POWER_DOWN 2 |
| #define | AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 |
| #define | AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ |
| #define | AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ |
| #define | AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ |
| #define | AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ |
| #define | AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ |
| #define | AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) |
| #define | AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) |
| #define | AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) |
| #define | AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ |
| #define | AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ |
| #define | AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
| #define | AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ |
| #define | AT91_DDRSDRC_MD_SDR 0 |
| #define | AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
| #define | AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
| #define | AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
| #define | AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
| #define | AT91_DDRSDRC_DBW_32BITS (0 << 4) |
| #define | AT91_DDRSDRC_DBW_16BITS (1 << 4) |
| #define | AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
| #define | AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
| #define | AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
| #define | AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
| #define | AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
| #define | AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ |
| #define | AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ |
| #define | AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ |
| #define | AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ |
| #define | AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ |
| #define | AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ |
| #define | AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ |
| #define | AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ |
| #define | AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ |
| #define | AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ |
| #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ |
Definition at line 52 of file at91sam9_ddrsdr.h.
Definition at line 91 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ |
Definition at line 43 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CAS_2 (2 << 4) |
Definition at line 44 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CAS_25 (6 << 4) |
Definition at line 46 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CAS_3 (3 << 4) |
Definition at line 45 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ |
Definition at line 83 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ |
Definition at line 26 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ |
Definition at line 28 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
Definition at line 100 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |
Definition at line 102 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DBW_32BITS (0 << 4) |
Definition at line 101 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DELAY | ( | n | ) | (0x30 + (0x4 * (n))) /* Delay I/O Register n */ |
Definition at line 113 of file at91sam9_ddrsdr.h.
Definition at line 48 of file at91sam9_ddrsdr.h.
Definition at line 111 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ |
Definition at line 49 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
Definition at line 104 of file at91sam9_ddrsdr.h.
Definition at line 51 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ |
Definition at line 86 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ |
Definition at line 110 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ |
Definition at line 118 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
Definition at line 78 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 |
Definition at line 82 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPCB_DISABLE 0 |
Definition at line 79 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 |
Definition at line 81 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
Definition at line 80 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
Definition at line 77 of file at91sam9_ddrsdr.h.
Definition at line 95 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
Definition at line 99 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
Definition at line 98 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
Definition at line 97 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MD_SDR 0 |
Definition at line 96 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
Definition at line 106 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
Definition at line 105 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
Definition at line 107 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
Definition at line 94 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
Definition at line 108 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ |
Definition at line 16 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_DEEP 6 |
Definition at line 23 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_EXT_LMR 5 |
Definition at line 22 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_LMR 3 |
Definition at line 20 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_NOP 1 |
Definition at line 18 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_NORMAL 0 |
Definition at line 17 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_PRECHARGE 2 |
Definition at line 19 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MODE_REFRESH 4 |
Definition at line 21 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ |
Definition at line 15 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ |
Definition at line 29 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_DDR10 (1 << 0) |
Definition at line 35 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_DDR11 (2 << 0) |
Definition at line 36 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_DDR12 (3 << 0) |
Definition at line 37 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_DDR9 (0 << 0) |
Definition at line 34 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_SDR10 (2 << 0) |
Definition at line 32 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_SDR11 (3 << 0) |
Definition at line 33 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_SDR8 (0 << 0) |
Definition at line 30 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NC_SDR9 (1 << 0) |
Definition at line 31 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ |
Definition at line 38 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NR_11 (0 << 2) |
Definition at line 39 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NR_12 (1 << 2) |
Definition at line 40 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NR_13 (2 << 2) |
Definition at line 41 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_NR_14 (3 << 2) |
Definition at line 42 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ |
Definition at line 50 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ |
Definition at line 84 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ |
Definition at line 62 of file at91sam9_ddrsdr.h.
Definition at line 47 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ |
Definition at line 25 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ |
Definition at line 54 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ |
Definition at line 65 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ |
Definition at line 71 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ |
Definition at line 85 of file at91sam9_ddrsdr.h.
Definition at line 87 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) |
Definition at line 88 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) |
Definition at line 90 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) |
Definition at line 89 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
Definition at line 63 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ |
Definition at line 55 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ |
Definition at line 58 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ |
Definition at line 56 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ |
Definition at line 66 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
Definition at line 59 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ |
Definition at line 74 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
Definition at line 60 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
Definition at line 75 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ |
Definition at line 57 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
Definition at line 61 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ |
Definition at line 72 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ |
Definition at line 73 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ |
Definition at line 69 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ |
Definition at line 67 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ |
Definition at line 68 of file at91sam9_ddrsdr.h.
Definition at line 92 of file at91sam9_ddrsdr.h.
Definition at line 116 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ |
Definition at line 117 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ |
Definition at line 115 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ |
Definition at line 120 of file at91sam9_ddrsdr.h.
Definition at line 121 of file at91sam9_ddrsdr.h.
| #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ |
Definition at line 122 of file at91sam9_ddrsdr.h.
1.8.2