at91sam9_wdt.h File Reference

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Macros
#define	AT91_WDT_CR   0x00 /* Watchdog Control Register */
#define	AT91_WDT_WDRSTT   (1 << 0) /* Restart */
#define	AT91_WDT_KEY   (0xa5 << 24) /* KEY Password */
#define	AT91_WDT_MR   0x04 /* Watchdog Mode Register */
#define	AT91_WDT_WDV   (0xfff << 0) /* Counter Value */
#define	AT91_WDT_WDFIEN   (1 << 12) /* Fault Interrupt Enable */
#define	AT91_WDT_WDRSTEN   (1 << 13) /* Reset Processor */
#define	AT91_WDT_WDRPROC   (1 << 14) /* Timer Restart */
#define	AT91_WDT_WDDIS   (1 << 15) /* Watchdog Disable */
#define	AT91_WDT_WDD   (0xfff << 16) /* Delta Value */
#define	AT91_WDT_WDDBGHLT   (1 << 28) /* Debug Halt */
#define	AT91_WDT_WDIDLEHLT   (1 << 29) /* Idle Halt */
#define	AT91_WDT_SR   0x08 /* Watchdog Status Register */
#define	AT91_WDT_WDUNF   (1 << 0) /* Watchdog Underflow */
#define	AT91_WDT_WDERR   (1 << 1) /* Watchdog Error */

Macro Definition Documentation

#define AT91_WDT_CR   0x00 /* Watchdog Control Register */

Definition at line 19 of file at91sam9_wdt.h.

#define AT91_WDT_KEY   (0xa5 << 24) /* KEY Password */

Definition at line 21 of file at91sam9_wdt.h.

#define AT91_WDT_MR   0x04 /* Watchdog Mode Register */

Definition at line 23 of file at91sam9_wdt.h.

#define AT91_WDT_SR   0x08 /* Watchdog Status Register */

Definition at line 33 of file at91sam9_wdt.h.

#define AT91_WDT_WDD   (0xfff << 16) /* Delta Value */

Definition at line 29 of file at91sam9_wdt.h.

#define AT91_WDT_WDDBGHLT   (1 << 28) /* Debug Halt */

Definition at line 30 of file at91sam9_wdt.h.

#define AT91_WDT_WDDIS   (1 << 15) /* Watchdog Disable */

Definition at line 28 of file at91sam9_wdt.h.

#define AT91_WDT_WDERR   (1 << 1) /* Watchdog Error */

Definition at line 35 of file at91sam9_wdt.h.

#define AT91_WDT_WDFIEN   (1 << 12) /* Fault Interrupt Enable */

Definition at line 25 of file at91sam9_wdt.h.

#define AT91_WDT_WDIDLEHLT   (1 << 29) /* Idle Halt */

Definition at line 31 of file at91sam9_wdt.h.

#define AT91_WDT_WDRPROC   (1 << 14) /* Timer Restart */

Definition at line 27 of file at91sam9_wdt.h.

#define AT91_WDT_WDRSTEN   (1 << 13) /* Reset Processor */

Definition at line 26 of file at91sam9_wdt.h.

#define AT91_WDT_WDRSTT   (1 << 0) /* Restart */

Definition at line 20 of file at91sam9_wdt.h.

#define AT91_WDT_WDUNF   (1 << 0) /* Watchdog Underflow */

Definition at line 34 of file at91sam9_wdt.h.

#define AT91_WDT_WDV   (0xfff << 0) /* Counter Value */

Definition at line 24 of file at91sam9_wdt.h.