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at91sam9g45.h
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1 /*
2  * Chip-specific header file for the AT91SAM9G45 family
3  *
4  * Copyright (C) 2008-2009 Atmel Corporation.
5  *
6  * Common definitions.
7  * Based on AT91SAM9G45 preliminary datasheet.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14 
15 #ifndef AT91SAM9G45_H
16 #define AT91SAM9G45_H
17 
18 /*
19  * Peripheral identifiers/interrupts.
20  */
21 #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
22 #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
23 #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
24 #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
25 #define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
26 #define AT91SAM9G45_ID_US0 7 /* USART 0 */
27 #define AT91SAM9G45_ID_US1 8 /* USART 1 */
28 #define AT91SAM9G45_ID_US2 9 /* USART 2 */
29 #define AT91SAM9G45_ID_US3 10 /* USART 3 */
30 #define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
31 #define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
32 #define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
33 #define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
34 #define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
35 #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
36 #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
37 #define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38 #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
39 #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
40 #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
41 #define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
42 #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
43 #define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
44 #define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
45 #define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
46 #define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
47 #define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
48 #define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
49 #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
50 #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
51 
52 /*
53  * User Peripheral physical base addresses.
54  */
55 #define AT91SAM9G45_BASE_UDPHS 0xfff78000
56 #define AT91SAM9G45_BASE_TCB0 0xfff7c000
57 #define AT91SAM9G45_BASE_TC0 0xfff7c000
58 #define AT91SAM9G45_BASE_TC1 0xfff7c040
59 #define AT91SAM9G45_BASE_TC2 0xfff7c080
60 #define AT91SAM9G45_BASE_MCI0 0xfff80000
61 #define AT91SAM9G45_BASE_TWI0 0xfff84000
62 #define AT91SAM9G45_BASE_TWI1 0xfff88000
63 #define AT91SAM9G45_BASE_US0 0xfff8c000
64 #define AT91SAM9G45_BASE_US1 0xfff90000
65 #define AT91SAM9G45_BASE_US2 0xfff94000
66 #define AT91SAM9G45_BASE_US3 0xfff98000
67 #define AT91SAM9G45_BASE_SSC0 0xfff9c000
68 #define AT91SAM9G45_BASE_SSC1 0xfffa0000
69 #define AT91SAM9G45_BASE_SPI0 0xfffa4000
70 #define AT91SAM9G45_BASE_SPI1 0xfffa8000
71 #define AT91SAM9G45_BASE_AC97C 0xfffac000
72 #define AT91SAM9G45_BASE_TSC 0xfffb0000
73 #define AT91SAM9G45_BASE_ISI 0xfffb4000
74 #define AT91SAM9G45_BASE_PWMC 0xfffb8000
75 #define AT91SAM9G45_BASE_EMAC 0xfffbc000
76 #define AT91SAM9G45_BASE_AES 0xfffc0000
77 #define AT91SAM9G45_BASE_TDES 0xfffc4000
78 #define AT91SAM9G45_BASE_SHA 0xfffc8000
79 #define AT91SAM9G45_BASE_TRNG 0xfffcc000
80 #define AT91SAM9G45_BASE_MCI1 0xfffd0000
81 #define AT91SAM9G45_BASE_TCB1 0xfffd4000
82 #define AT91SAM9G45_BASE_TC3 0xfffd4000
83 #define AT91SAM9G45_BASE_TC4 0xfffd4040
84 #define AT91SAM9G45_BASE_TC5 0xfffd4080
85 
86 /*
87  * System Peripherals
88  */
89 #define AT91SAM9G45_BASE_ECC 0xffffe200
90 #define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
91 #define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
92 #define AT91SAM9G45_BASE_DMA 0xffffec00
93 #define AT91SAM9G45_BASE_SMC 0xffffe800
94 #define AT91SAM9G45_BASE_MATRIX 0xffffea00
95 #define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
96 #define AT91SAM9G45_BASE_PIOA 0xfffff200
97 #define AT91SAM9G45_BASE_PIOB 0xfffff400
98 #define AT91SAM9G45_BASE_PIOC 0xfffff600
99 #define AT91SAM9G45_BASE_PIOD 0xfffff800
100 #define AT91SAM9G45_BASE_PIOE 0xfffffa00
101 #define AT91SAM9G45_BASE_RSTC 0xfffffd00
102 #define AT91SAM9G45_BASE_SHDWC 0xfffffd10
103 #define AT91SAM9G45_BASE_RTT 0xfffffd20
104 #define AT91SAM9G45_BASE_PIT 0xfffffd30
105 #define AT91SAM9G45_BASE_WDT 0xfffffd40
106 #define AT91SAM9G45_BASE_RTC 0xfffffdb0
107 #define AT91SAM9G45_BASE_GPBR 0xfffffd60
108 
109 /*
110  * Internal Memory.
111  */
112 #define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
113 #define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
114 
115 #define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
116 #define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
117 
118 #define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
119 #define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
120 #define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
121 #define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
122 #define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
123 
124 /*
125  * DMA peripheral identifiers
126  * for hardware handshaking interface
127  */
128 #define AT_DMA_ID_MCI0 0
129 #define AT_DMA_ID_SPI0_TX 1
130 #define AT_DMA_ID_SPI0_RX 2
131 #define AT_DMA_ID_SPI1_TX 3
132 #define AT_DMA_ID_SPI1_RX 4
133 #define AT_DMA_ID_SSC0_TX 5
134 #define AT_DMA_ID_SSC0_RX 6
135 #define AT_DMA_ID_SSC1_TX 7
136 #define AT_DMA_ID_SSC1_RX 8
137 #define AT_DMA_ID_AC97_TX 9
138 #define AT_DMA_ID_AC97_RX 10
139 #define AT_DMA_ID_AES_TX 11
140 #define AT_DMA_ID_AES_RX 12
141 #define AT_DMA_ID_MCI1 13
142 
143 #endif