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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ |
| #define | AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ |
| #define | AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ |
| #define | AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ |
| #define | AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ |
| #define | AT91SAM9G45_ID_US0 7 /* USART 0 */ |
| #define | AT91SAM9G45_ID_US1 8 /* USART 1 */ |
| #define | AT91SAM9G45_ID_US2 9 /* USART 2 */ |
| #define | AT91SAM9G45_ID_US3 10 /* USART 3 */ |
| #define | AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ |
| #define | AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ |
| #define | AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ |
| #define | AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
| #define | AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
| #define | AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ |
| #define | AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ |
| #define | AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
| #define | AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
| #define | AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ |
| #define | AT91SAM9G45_ID_DMA 21 /* DMA Controller */ |
| #define | AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ |
| #define | AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ |
| #define | AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ |
| #define | AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ |
| #define | AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ |
| #define | AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ |
| #define | AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ |
| #define | AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ |
| #define | AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ |
| #define | AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ |
| #define | AT91SAM9G45_BASE_UDPHS 0xfff78000 |
| #define | AT91SAM9G45_BASE_TCB0 0xfff7c000 |
| #define | AT91SAM9G45_BASE_TC0 0xfff7c000 |
| #define | AT91SAM9G45_BASE_TC1 0xfff7c040 |
| #define | AT91SAM9G45_BASE_TC2 0xfff7c080 |
| #define | AT91SAM9G45_BASE_MCI0 0xfff80000 |
| #define | AT91SAM9G45_BASE_TWI0 0xfff84000 |
| #define | AT91SAM9G45_BASE_TWI1 0xfff88000 |
| #define | AT91SAM9G45_BASE_US0 0xfff8c000 |
| #define | AT91SAM9G45_BASE_US1 0xfff90000 |
| #define | AT91SAM9G45_BASE_US2 0xfff94000 |
| #define | AT91SAM9G45_BASE_US3 0xfff98000 |
| #define | AT91SAM9G45_BASE_SSC0 0xfff9c000 |
| #define | AT91SAM9G45_BASE_SSC1 0xfffa0000 |
| #define | AT91SAM9G45_BASE_SPI0 0xfffa4000 |
| #define | AT91SAM9G45_BASE_SPI1 0xfffa8000 |
| #define | AT91SAM9G45_BASE_AC97C 0xfffac000 |
| #define | AT91SAM9G45_BASE_TSC 0xfffb0000 |
| #define | AT91SAM9G45_BASE_ISI 0xfffb4000 |
| #define | AT91SAM9G45_BASE_PWMC 0xfffb8000 |
| #define | AT91SAM9G45_BASE_EMAC 0xfffbc000 |
| #define | AT91SAM9G45_BASE_AES 0xfffc0000 |
| #define | AT91SAM9G45_BASE_TDES 0xfffc4000 |
| #define | AT91SAM9G45_BASE_SHA 0xfffc8000 |
| #define | AT91SAM9G45_BASE_TRNG 0xfffcc000 |
| #define | AT91SAM9G45_BASE_MCI1 0xfffd0000 |
| #define | AT91SAM9G45_BASE_TCB1 0xfffd4000 |
| #define | AT91SAM9G45_BASE_TC3 0xfffd4000 |
| #define | AT91SAM9G45_BASE_TC4 0xfffd4040 |
| #define | AT91SAM9G45_BASE_TC5 0xfffd4080 |
| #define | AT91SAM9G45_BASE_ECC 0xffffe200 |
| #define | AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 |
| #define | AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 |
| #define | AT91SAM9G45_BASE_DMA 0xffffec00 |
| #define | AT91SAM9G45_BASE_SMC 0xffffe800 |
| #define | AT91SAM9G45_BASE_MATRIX 0xffffea00 |
| #define | AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 |
| #define | AT91SAM9G45_BASE_PIOA 0xfffff200 |
| #define | AT91SAM9G45_BASE_PIOB 0xfffff400 |
| #define | AT91SAM9G45_BASE_PIOC 0xfffff600 |
| #define | AT91SAM9G45_BASE_PIOD 0xfffff800 |
| #define | AT91SAM9G45_BASE_PIOE 0xfffffa00 |
| #define | AT91SAM9G45_BASE_RSTC 0xfffffd00 |
| #define | AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
| #define | AT91SAM9G45_BASE_RTT 0xfffffd20 |
| #define | AT91SAM9G45_BASE_PIT 0xfffffd30 |
| #define | AT91SAM9G45_BASE_WDT 0xfffffd40 |
| #define | AT91SAM9G45_BASE_RTC 0xfffffdb0 |
| #define | AT91SAM9G45_BASE_GPBR 0xfffffd60 |
| #define | AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| #define | AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ |
| #define | AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| #define | AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ |
| #define | AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ |
| #define | AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
| #define | AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ |
| #define | AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ |
| #define | AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ |
| #define | AT_DMA_ID_MCI0 0 |
| #define | AT_DMA_ID_SPI0_TX 1 |
| #define | AT_DMA_ID_SPI0_RX 2 |
| #define | AT_DMA_ID_SPI1_TX 3 |
| #define | AT_DMA_ID_SPI1_RX 4 |
| #define | AT_DMA_ID_SSC0_TX 5 |
| #define | AT_DMA_ID_SSC0_RX 6 |
| #define | AT_DMA_ID_SSC1_TX 7 |
| #define | AT_DMA_ID_SSC1_RX 8 |
| #define | AT_DMA_ID_AC97_TX 9 |
| #define | AT_DMA_ID_AC97_RX 10 |
| #define | AT_DMA_ID_AES_TX 11 |
| #define | AT_DMA_ID_AES_RX 12 |
| #define | AT_DMA_ID_MCI1 13 |
| #define AT91SAM9G45_BASE_AC97C 0xfffac000 |
Definition at line 71 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_AES 0xfffc0000 |
Definition at line 76 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 |
Definition at line 95 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 |
Definition at line 91 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 |
Definition at line 90 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_DMA 0xffffec00 |
Definition at line 92 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_ECC 0xffffe200 |
Definition at line 89 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_EMAC 0xfffbc000 |
Definition at line 75 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_GPBR 0xfffffd60 |
Definition at line 107 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_ISI 0xfffb4000 |
Definition at line 73 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_MATRIX 0xffffea00 |
Definition at line 94 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_MCI0 0xfff80000 |
Definition at line 60 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_MCI1 0xfffd0000 |
Definition at line 80 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIOA 0xfffff200 |
Definition at line 96 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIOB 0xfffff400 |
Definition at line 97 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIOC 0xfffff600 |
Definition at line 98 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIOD 0xfffff800 |
Definition at line 99 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIOE 0xfffffa00 |
Definition at line 100 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PIT 0xfffffd30 |
Definition at line 104 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_PWMC 0xfffb8000 |
Definition at line 74 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_RSTC 0xfffffd00 |
Definition at line 101 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_RTC 0xfffffdb0 |
Definition at line 106 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_RTT 0xfffffd20 |
Definition at line 103 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SHA 0xfffc8000 |
Definition at line 78 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SHDWC 0xfffffd10 |
Definition at line 102 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SMC 0xffffe800 |
Definition at line 93 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SPI0 0xfffa4000 |
Definition at line 69 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SPI1 0xfffa8000 |
Definition at line 70 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SSC0 0xfff9c000 |
Definition at line 67 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_SSC1 0xfffa0000 |
Definition at line 68 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC0 0xfff7c000 |
Definition at line 57 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC1 0xfff7c040 |
Definition at line 58 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC2 0xfff7c080 |
Definition at line 59 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC3 0xfffd4000 |
Definition at line 82 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC4 0xfffd4040 |
Definition at line 83 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TC5 0xfffd4080 |
Definition at line 84 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TCB0 0xfff7c000 |
Definition at line 56 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TCB1 0xfffd4000 |
Definition at line 81 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TDES 0xfffc4000 |
Definition at line 77 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TRNG 0xfffcc000 |
Definition at line 79 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TSC 0xfffb0000 |
Definition at line 72 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TWI0 0xfff84000 |
Definition at line 61 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_TWI1 0xfff88000 |
Definition at line 62 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_UDPHS 0xfff78000 |
Definition at line 55 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_US0 0xfff8c000 |
Definition at line 63 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_US1 0xfff90000 |
Definition at line 64 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_US2 0xfff94000 |
Definition at line 65 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_US3 0xfff98000 |
Definition at line 66 of file at91sam9g45.h.
| #define AT91SAM9G45_BASE_WDT 0xfffffd40 |
Definition at line 105 of file at91sam9g45.h.
| #define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ |
Definition at line 121 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ |
Definition at line 43 of file at91sam9g45.h.
Definition at line 47 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ |
Definition at line 40 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ |
Definition at line 44 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ |
Definition at line 50 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ |
Definition at line 45 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ |
Definition at line 42 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ |
Definition at line 30 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ |
Definition at line 48 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ |
Definition at line 21 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ |
Definition at line 22 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ |
Definition at line 23 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ |
Definition at line 24 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ |
Definition at line 38 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ |
Definition at line 33 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ |
Definition at line 34 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ |
Definition at line 35 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ |
Definition at line 36 of file at91sam9g45.h.
Definition at line 37 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ |
Definition at line 25 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ |
Definition at line 39 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ |
Definition at line 31 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ |
Definition at line 32 of file at91sam9g45.h.
Definition at line 46 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ |
Definition at line 41 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_US0 7 /* USART 0 */ |
Definition at line 26 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_US1 8 /* USART 1 */ |
Definition at line 27 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_US2 9 /* USART 2 */ |
Definition at line 28 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_US3 10 /* USART 3 */ |
Definition at line 29 of file at91sam9g45.h.
| #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ |
Definition at line 49 of file at91sam9g45.h.
| #define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ |
Definition at line 118 of file at91sam9g45.h.
| #define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ |
Definition at line 120 of file at91sam9g45.h.
| #define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ |
Definition at line 115 of file at91sam9g45.h.
Definition at line 116 of file at91sam9g45.h.
| #define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
Definition at line 112 of file at91sam9g45.h.
Definition at line 113 of file at91sam9g45.h.
| #define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ |
Definition at line 119 of file at91sam9g45.h.
| #define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ |
Definition at line 122 of file at91sam9g45.h.
| #define AT_DMA_ID_AC97_RX 10 |
Definition at line 138 of file at91sam9g45.h.
| #define AT_DMA_ID_AC97_TX 9 |
Definition at line 137 of file at91sam9g45.h.
| #define AT_DMA_ID_AES_RX 12 |
Definition at line 140 of file at91sam9g45.h.
| #define AT_DMA_ID_AES_TX 11 |
Definition at line 139 of file at91sam9g45.h.
| #define AT_DMA_ID_MCI0 0 |
Definition at line 128 of file at91sam9g45.h.
| #define AT_DMA_ID_MCI1 13 |
Definition at line 141 of file at91sam9g45.h.
| #define AT_DMA_ID_SPI0_RX 2 |
Definition at line 130 of file at91sam9g45.h.
| #define AT_DMA_ID_SPI0_TX 1 |
Definition at line 129 of file at91sam9g45.h.
| #define AT_DMA_ID_SPI1_RX 4 |
Definition at line 132 of file at91sam9g45.h.
| #define AT_DMA_ID_SPI1_TX 3 |
Definition at line 131 of file at91sam9g45.h.
| #define AT_DMA_ID_SSC0_RX 6 |
Definition at line 134 of file at91sam9g45.h.
| #define AT_DMA_ID_SSC0_TX 5 |
Definition at line 133 of file at91sam9g45.h.
| #define AT_DMA_ID_SSC1_RX 8 |
Definition at line 136 of file at91sam9g45.h.
| #define AT_DMA_ID_SSC1_TX 7 |
Definition at line 135 of file at91sam9g45.h.
1.8.2