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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ |
| #define | AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ |
| #define | AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ |
| #define | AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ |
| #define | AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ |
| #define | AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ |
| #define | AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
| #define | AT91_MATRIX_ULBT_INFINITE (0 << 0) |
| #define | AT91_MATRIX_ULBT_SINGLE (1 << 0) |
| #define | AT91_MATRIX_ULBT_FOUR (2 << 0) |
| #define | AT91_MATRIX_ULBT_EIGHT (3 << 0) |
| #define | AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
| #define | AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ |
| #define | AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ |
| #define | AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ |
| #define | AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ |
| #define | AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ |
| #define | AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ |
| #define | AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
| #define | AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
| #define | AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
| #define | AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
| #define | AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
| #define | AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
| #define | AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
| #define | AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
| #define | AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
| #define | AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ |
| #define | AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ |
| #define | AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ |
| #define | AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ |
| #define | AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ |
| #define | AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ |
| #define | AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
| #define | AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
| #define | AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
| #define | AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
| #define | AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
| #define | AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
| #define | AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ |
| #define | AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
| #define | AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
| #define | AT91_MATRIX_RCB2 (1 << 2) |
| #define | AT91_MATRIX_RCB3 (1 << 3) |
| #define | AT91_MATRIX_RCB4 (1 << 4) |
| #define | AT91_MATRIX_RCB5 (1 << 5) |
| #define | AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ |
| #define | AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
| #define | AT91_MATRIX_ITCM_0 (0 << 0) |
| #define | AT91_MATRIX_ITCM_16 (5 << 0) |
| #define | AT91_MATRIX_ITCM_32 (6 << 0) |
| #define | AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
| #define | AT91_MATRIX_DTCM_0 (0 << 4) |
| #define | AT91_MATRIX_DTCM_16 (5 << 4) |
| #define | AT91_MATRIX_DTCM_32 (6 << 4) |
| #define | AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */ |
| #define | AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
| #define | AT91_MATRIX_CS1A_SMC (0 << 1) |
| #define | AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
| #define | AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
| #define | AT91_MATRIX_CS3A_SMC (0 << 3) |
| #define | AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) |
| #define | AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
| #define | AT91_MATRIX_CS4A_SMC (0 << 4) |
| #define | AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) |
| #define | AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
| #define | AT91_MATRIX_CS5A_SMC (0 << 5) |
| #define | AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
| #define | AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
| #define | AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
| #define | AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) |
| #define | AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) |
| #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ |
Definition at line 42 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) |
Definition at line 44 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) |
Definition at line 43 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
Definition at line 78 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
Definition at line 80 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS1A_SMC (0 << 1) |
Definition at line 79 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ |
Definition at line 81 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS3A_SMC (0 << 3) |
Definition at line 82 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) |
Definition at line 83 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ |
Definition at line 84 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS4A_SMC (0 << 4) |
Definition at line 85 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) |
Definition at line 86 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ |
Definition at line 87 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS5A_SMC (0 << 5) |
Definition at line 88 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
Definition at line 89 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
Definition at line 90 of file at91sam9rl_matrix.h.
Definition at line 37 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
Definition at line 40 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) |
Definition at line 39 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
Definition at line 38 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DTCM_0 (0 << 4) |
Definition at line 73 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DTCM_16 (5 << 4) |
Definition at line 74 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DTCM_32 (6 << 4) |
Definition at line 75 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ |
Definition at line 72 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */ |
Definition at line 77 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
Definition at line 41 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ITCM_0 (0 << 0) |
Definition at line 69 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ITCM_16 (5 << 0) |
Definition at line 70 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ITCM_32 (6 << 0) |
Definition at line 71 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
Definition at line 68 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
Definition at line 52 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
Definition at line 53 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
Definition at line 54 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ |
Definition at line 55 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ |
Definition at line 56 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ |
Definition at line 57 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ |
Definition at line 17 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ |
Definition at line 18 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ |
Definition at line 19 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ |
Definition at line 20 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ |
Definition at line 21 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ |
Definition at line 22 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ |
Definition at line 59 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ |
Definition at line 46 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ |
Definition at line 47 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ |
Definition at line 48 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ |
Definition at line 49 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ |
Definition at line 50 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ |
Definition at line 51 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
Definition at line 60 of file at91sam9rl_matrix.h.
Definition at line 61 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_RCB2 (1 << 2) |
Definition at line 62 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_RCB3 (1 << 3) |
Definition at line 63 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_RCB4 (1 << 4) |
Definition at line 64 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_RCB5 (1 << 5) |
Definition at line 65 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ |
Definition at line 30 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ |
Definition at line 31 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ |
Definition at line 32 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ |
Definition at line 33 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ |
Definition at line 34 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ |
Definition at line 35 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
Definition at line 36 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ |
Definition at line 67 of file at91sam9rl_matrix.h.
Definition at line 23 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ULBT_EIGHT (3 << 0) |
Definition at line 27 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ULBT_FOUR (2 << 0) |
Definition at line 26 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
Definition at line 24 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
Definition at line 25 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) |
Definition at line 28 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ |
Definition at line 91 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) |
Definition at line 92 of file at91sam9rl_matrix.h.
| #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) |
Definition at line 93 of file at91sam9rl_matrix.h.
1.8.2