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atombios.h
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1 /*
2  * Copyright 2006-2007 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 
24 /****************************************************************************/
25 /*Portion I: Definitions shared between VBIOS and Driver */
26 /****************************************************************************/
27 
28 
29 #ifndef _ATOMBIOS_H
30 #define _ATOMBIOS_H
31 
32 #define ATOM_VERSION_MAJOR 0x00020000
33 #define ATOM_VERSION_MINOR 0x00000002
34 
35 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
36 
37 /* Endianness should be specified before inclusion,
38  * default to little endian
39  */
40 #ifndef ATOM_BIG_ENDIAN
41 #error Endian not specified
42 #endif
43 
44 #ifdef _H2INC
45  #ifndef ULONG
46  typedef unsigned long ULONG;
47  #endif
48 
49  #ifndef UCHAR
50  typedef unsigned char UCHAR;
51  #endif
52 
53  #ifndef USHORT
54  typedef unsigned short USHORT;
55  #endif
56 #endif
57 
58 #define ATOM_DAC_A 0
59 #define ATOM_DAC_B 1
60 #define ATOM_EXT_DAC 2
61 
62 #define ATOM_CRTC1 0
63 #define ATOM_CRTC2 1
64 #define ATOM_CRTC3 2
65 #define ATOM_CRTC4 3
66 #define ATOM_CRTC5 4
67 #define ATOM_CRTC6 5
68 #define ATOM_CRTC_INVALID 0xFF
69 
70 #define ATOM_DIGA 0
71 #define ATOM_DIGB 1
72 
73 #define ATOM_PPLL1 0
74 #define ATOM_PPLL2 1
75 #define ATOM_DCPLL 2
76 #define ATOM_PPLL0 2
77 #define ATOM_EXT_PLL1 8
78 #define ATOM_EXT_PLL2 9
79 #define ATOM_EXT_CLOCK 10
80 #define ATOM_PPLL_INVALID 0xFF
81 
82 #define ENCODER_REFCLK_SRC_P1PLL 0
83 #define ENCODER_REFCLK_SRC_P2PLL 1
84 #define ENCODER_REFCLK_SRC_DCPLL 2
85 #define ENCODER_REFCLK_SRC_EXTCLK 3
86 #define ENCODER_REFCLK_SRC_INVALID 0xFF
87 
88 #define ATOM_SCALER1 0
89 #define ATOM_SCALER2 1
90 
91 #define ATOM_SCALER_DISABLE 0
92 #define ATOM_SCALER_CENTER 1
93 #define ATOM_SCALER_EXPANSION 2
94 #define ATOM_SCALER_MULTI_EX 3
95 
96 #define ATOM_DISABLE 0
97 #define ATOM_ENABLE 1
98 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
99 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
100 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
101 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
102 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
103 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
104 #define ATOM_INIT (ATOM_DISABLE+7)
105 #define ATOM_GET_STATUS (ATOM_DISABLE+8)
106 
107 #define ATOM_BLANKING 1
108 #define ATOM_BLANKING_OFF 0
109 
110 #define ATOM_CURSOR1 0
111 #define ATOM_CURSOR2 1
112 
113 #define ATOM_ICON1 0
114 #define ATOM_ICON2 1
115 
116 #define ATOM_CRT1 0
117 #define ATOM_CRT2 1
118 
119 #define ATOM_TV_NTSC 1
120 #define ATOM_TV_NTSCJ 2
121 #define ATOM_TV_PAL 3
122 #define ATOM_TV_PALM 4
123 #define ATOM_TV_PALCN 5
124 #define ATOM_TV_PALN 6
125 #define ATOM_TV_PAL60 7
126 #define ATOM_TV_SECAM 8
127 #define ATOM_TV_CV 16
128 
129 #define ATOM_DAC1_PS2 1
130 #define ATOM_DAC1_CV 2
131 #define ATOM_DAC1_NTSC 3
132 #define ATOM_DAC1_PAL 4
133 
134 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2
135 #define ATOM_DAC2_CV ATOM_DAC1_CV
136 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
137 #define ATOM_DAC2_PAL ATOM_DAC1_PAL
138 
139 #define ATOM_PM_ON 0
140 #define ATOM_PM_STANDBY 1
141 #define ATOM_PM_SUSPEND 2
142 #define ATOM_PM_OFF 3
143 
144 /* Bit0:{=0:single, =1:dual},
145  Bit1 {=0:666RGB, =1:888RGB},
146  Bit2:3:{Grey level}
147  Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
148 
149 #define ATOM_PANEL_MISC_DUAL 0x00000001
150 #define ATOM_PANEL_MISC_888RGB 0x00000002
151 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
152 #define ATOM_PANEL_MISC_FPDI 0x00000010
153 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
154 #define ATOM_PANEL_MISC_SPATIAL 0x00000020
155 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040
156 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080
157 
158 
159 #define MEMTYPE_DDR1 "DDR1"
160 #define MEMTYPE_DDR2 "DDR2"
161 #define MEMTYPE_DDR3 "DDR3"
162 #define MEMTYPE_DDR4 "DDR4"
163 
164 #define ASIC_BUS_TYPE_PCI "PCI"
165 #define ASIC_BUS_TYPE_AGP "AGP"
166 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
167 
168 /* Maximum size of that FireGL flag string */
169 
170 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
171 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
172 
173 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
174 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
175 
176 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
177 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
178 
179 #define HW_ASSISTED_I2C_STATUS_FAILURE 2
180 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
181 
182 #pragma pack(1) /* BIOS data must use byte aligment */
183 
184 /* Define offset to location of ROM header. */
185 
186 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
187 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
188 
189 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
190 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
191 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
192 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
193 
194 /* Common header for all ROM Data tables.
195  Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
196  And the pointer actually points to this header. */
197 
199 {
201  UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
202  UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
203  /*Image can't be updated, while Driver needs to carry the new table! */
205 
206 /****************************************************************************/
207 // Structure stores the ROM header.
208 /****************************************************************************/
209 typedef struct _ATOM_ROM_HEADER
210 {
212  UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
213  atombios should init it as "ATOM", don't change the position */
225  USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
226  USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
230 
231 /*==============================Command Table Portion==================================== */
232 
233 #ifdef UEFI_BUILD
234  #define UTEMP USHORT
235  #define USHORT void*
236 #endif
237 
238 /****************************************************************************/
239 // Structures used in Command.mtb
240 /****************************************************************************/
242  USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
243  USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
244  USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
245  USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
246  USHORT DIGxEncoderControl; //Only used by Bios
247  USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
248  USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
249  USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
250  USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
251  USHORT GPIOPinControl; //Atomic Table, only used by Bios
252  USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
253  USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
254  USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
255  USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
256  USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
257  USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
258  USHORT MemoryPLLInit; //Atomic Table, used only by Bios
259  USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
260  USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
261  USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
262  USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios
263  USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
264  USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
265  USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
266  USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
267  USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
268  USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
269  USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
270  USHORT GetConditionalGoldenSetting; //Only used by Bios
271  USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
272  USHORT PatchMCSetting; //only used by BIOS
273  USHORT MC_SEQ_Control; //only used by BIOS
274  USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
275  USHORT EnableScaler; //Atomic Table, used only by Bios
276  USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
277  USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
278  USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
279  USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
280  USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
281  USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
282  USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
283  USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
284  USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
285  USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
286  USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
287  USHORT LUT_AutoFill; //Atomic Table, only used by Bios
288  USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
289  USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
290  USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
291  USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
292  USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
293  USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
294  USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
295  USHORT MemoryCleanUp; //Atomic Table, only used by Bios
296  USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
297  USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
298  USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
299  USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
300  USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
301  USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
302  USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
303  USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
304  USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
305  USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
306  USHORT MemoryTraining; //Atomic Table, used only by Bios
307  USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
308  USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
309  USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
310  USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
311  USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
312  USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
313  USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
314  USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
315  USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
316  USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
317  USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
318  USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
319  USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
320  USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
321  USHORT DPEncoderService; //Function Table,only used by Bios
322  USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
324 
325 // For backward compatible
326 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
327 #define DPTranslatorControl DIG2EncoderControl
328 #define UNIPHYTransmitterControl DIG1TransmitterControl
329 #define LVTMATransmitterControl DIG2TransmitterControl
330 #define SetCRTC_DPM_State GetConditionalGoldenSetting
331 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange
332 #define HPDInterruptService ReadHWAssistedI2CStatus
333 #define EnableVGA_Access GetSCLKOverMCLKRatio
334 #define EnableYUV GetDispObjectInfo
335 #define DynamicClockGating EnableDispPowerGating
336 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam
337 
338 #define TMDSAEncoderControl PatchMCSetting
339 #define LVDSEncoderControl MC_SEQ_Control
340 #define LCD1OutputControl HW_Misc_Operation
341 
342 
344 {
348 
349 /****************************************************************************/
350 // Structures used in every command table
351 /****************************************************************************/
352 typedef struct _ATOM_TABLE_ATTRIBUTE
353 {
354 #if ATOM_BIG_ENDIAN
355  USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
356  USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
357  USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
358 #else
359  USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360  USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
361  USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
362 #endif
364 
366 {
370 
371 /****************************************************************************/
372 // Common header for all command tables.
373 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
374 // And the pointer actually points to this header.
375 /****************************************************************************/
377 {
381 
382 /****************************************************************************/
383 // Structures used by ComputeMemoryEnginePLLTable
384 /****************************************************************************/
385 #define COMPUTE_MEMORY_PLL_PARAM 1
386 #define COMPUTE_ENGINE_PLL_PARAM 2
387 #define ADJUST_MC_SETTING_PARAM 3
388 
389 /****************************************************************************/
390 // Structures used by AdjustMemoryControllerTable
391 /****************************************************************************/
393 {
394 #if ATOM_BIG_ENDIAN
395  ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
396  ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
397  ULONG ulClockFreq:24;
398 #else
400  ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
401  ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
402 #endif
404 #define POINTER_RETURN_FLAG 0x80
405 
407 {
408  ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
409  UCHAR ucAction; //0:reserved //1:Memory //2:Engine
410  UCHAR ucReserved; //may expand to return larger Fbdiv later
411  UCHAR ucFbDiv; //return value
412  UCHAR ucPostDiv; //return value
414 
416 {
417  ULONG ulClock; //When return, [23:0] return real clock
418  UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
419  USHORT usFbDiv; //return Feedback value to be written to register
420  UCHAR ucPostDiv; //return post div to be written to register
422 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
423 
424 
425 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
426 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
427 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
428 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
429 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
430 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
431 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
432 
433 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
434 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
435 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
436 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
437 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
438 
440 {
441 #if ATOM_BIG_ENDIAN
442  ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
443  ULONG ulClockFreq:24; // in unit of 10kHz
444 #else
445  ULONG ulClockFreq:24; // in unit of 10kHz
446  ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
447 #endif
449 
451 {
455 
457 {
458  union
459  {
460  ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
461  ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
462  };
463  UCHAR ucRefDiv; //Output Parameter
464  UCHAR ucPostDiv; //Output Parameter
465  UCHAR ucCntlFlag; //Output Parameter
468 
469 // ucCntlFlag
470 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
471 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
472 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
473 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
474 
475 
476 // V4 are only used for APU which PLL outside GPU
478 {
479 #if ATOM_BIG_ENDIAN
480  ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
481  ULONG ulClock:24; //Input= target clock, output = actual clock
482 #else
483  ULONG ulClock:24; //Input= target clock, output = actual clock
484  ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly
485 #endif
487 
489 {
490  union
491  {
492  ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
493  ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
494  };
495  UCHAR ucRefDiv; //Output Parameter
496  UCHAR ucPostDiv; //Output Parameter
497  union
498  {
499  UCHAR ucCntlFlag; //Output Flags
500  UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
501  };
504 
505 // ucInputFlag
506 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
507 
508 // use for ComputeMemoryClockParamTable
510 {
511  union
512  {
514  ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
515  };
516  UCHAR ucDllSpeed; //Output
517  UCHAR ucPostDiv; //Output
518  union{
519  UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
520  UCHAR ucPllCntlFlag; //Output:
521  };
524 
525 // definition of ucInputFlag
526 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
527 // definition of ucPllCntlFlag
528 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
529 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
530 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
531 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
532 
533 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
534 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
535 
537 {
541 
543 {
548 
549 /****************************************************************************/
550 // Structures used by SetEngineClockTable
551 /****************************************************************************/
553 {
554  ULONG ulTargetEngineClock; //In 10Khz unit
556 
558 {
559  ULONG ulTargetEngineClock; //In 10Khz unit
562 
563 /****************************************************************************/
564 // Structures used by SetMemoryClockTable
565 /****************************************************************************/
567 {
568  ULONG ulTargetMemoryClock; //In 10Khz unit
570 
572 {
573  ULONG ulTargetMemoryClock; //In 10Khz unit
576 
577 /****************************************************************************/
578 // Structures used by ASIC_Init.ctb
579 /****************************************************************************/
580 typedef struct _ASIC_INIT_PARAMETERS
581 {
582  ULONG ulDefaultEngineClock; //In 10Khz unit
583  ULONG ulDefaultMemoryClock; //In 10Khz unit
585 
587 {
589  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
591 
592 /****************************************************************************/
593 // Structure used by DynamicClockGatingTable.ctb
594 /****************************************************************************/
596 {
597  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
600 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
601 
602 /****************************************************************************/
603 // Structure used by EnableDispPowerGatingTable.ctb
604 /****************************************************************************/
606 {
607  UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
608  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
611 
612 /****************************************************************************/
613 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
614 /****************************************************************************/
616 {
617  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
620 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
621 
622 /****************************************************************************/
623 // Structures used by DAC_LoadDetectionTable.ctb
624 /****************************************************************************/
626 {
627  USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
628  UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
629  UCHAR ucMisc; //Valid only when table revision =1.3 and above
631 
632 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
633 #define DAC_LOAD_MISC_YPrPb 0x01
634 
636 {
638  ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
640 
641 /****************************************************************************/
642 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
643 /****************************************************************************/
645 {
646  USHORT usPixelClock; // in 10KHz; for bios convenient
647  UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
648  UCHAR ucAction; // 0: turn off encoder
649  // 1: setup and turn on encoder
650  // 7: ATOM_ENCODER_INIT Initialize DAC
652 
653 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
654 
655 /****************************************************************************/
656 // Structures used by DIG1EncoderControlTable
657 // DIG2EncoderControlTable
658 // ExternalEncoderControlTable
659 /****************************************************************************/
661 {
662  USHORT usPixelClock; // in 10KHz; for bios convenient
664  // [2] Link Select:
665  // =0: PHY linkA if bfLane<3
666  // =1: PHY linkB if bfLanes<3
667  // =0: PHY linkA+B if bfLanes=3
668  // [3] Transmitter Sel
669  // =0: UNIPHY or PCIEPHY
670  // =1: LVTMA
671  UCHAR ucAction; // =0: turn off encoder
672  // =1: turn on encoder
674  // =0: DP encoder
675  // =1: LVDS encoder
676  // =2: DVI encoder
677  // =3: HDMI encoder
678  // =4: SDVO encoder
679  UCHAR ucLaneNum; // how many lanes to enable
682 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
683 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
684 
685 //ucConfig
686 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
687 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
688 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
689 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
690 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
691 #define ATOM_ENCODER_CONFIG_LINKA 0x00
692 #define ATOM_ENCODER_CONFIG_LINKB 0x04
693 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
694 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
695 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
696 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00
697 #define ATOM_ENCODER_CONFIG_LVTMA 0x08
698 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
699 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
700 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
701 // ucAction
702 // ATOM_ENABLE: Enable Encoder
703 // ATOM_DISABLE: Disable Encoder
704 
705 //ucEncoderMode
706 #define ATOM_ENCODER_MODE_DP 0
707 #define ATOM_ENCODER_MODE_LVDS 1
708 #define ATOM_ENCODER_MODE_DVI 2
709 #define ATOM_ENCODER_MODE_HDMI 3
710 #define ATOM_ENCODER_MODE_SDVO 4
711 #define ATOM_ENCODER_MODE_DP_AUDIO 5
712 #define ATOM_ENCODER_MODE_TV 13
713 #define ATOM_ENCODER_MODE_CV 14
714 #define ATOM_ENCODER_MODE_CRT 15
715 #define ATOM_ENCODER_MODE_DVO 16
716 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
717 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
718 
720 {
721 #if ATOM_BIG_ENDIAN
722  UCHAR ucReserved1:2;
723  UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
724  UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
725  UCHAR ucReserved:1;
726  UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
727 #else
728  UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
730  UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
731  UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
733 #endif
735 
736 
738 {
739  USHORT usPixelClock; // in 10KHz; for bios convenient
743  // =0: DP encoder
744  // =1: LVDS encoder
745  // =2: DVI encoder
746  // =3: HDMI encoder
747  // =4: SDVO encoder
748  UCHAR ucLaneNum; // how many lanes to enable
749  UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
752 
753 //ucConfig
754 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
755 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
756 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
757 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
758 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
759 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
760 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
761 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
762 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
763 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
764 
765 // ucAction:
766 // ATOM_DISABLE
767 // ATOM_ENABLE
768 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
769 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
770 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
771 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
773 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
774 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
775 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
776 #define ATOM_ENCODER_CMD_SETUP 0x0f
777 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
778 
779 // ucStatus
780 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
781 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
782 
783 //ucTableFormatRevision=1
784 //ucTableContentRevision=3
785 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
787 {
788 #if ATOM_BIG_ENDIAN
789  UCHAR ucReserved1:1;
790  UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
791  UCHAR ucReserved:3;
792  UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
793 #else
794  UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
796  UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
798 #endif
800 
801 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
802 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
803 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
804 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
805 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
806 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
807 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
808 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
809 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
810 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
811 
813 {
814  USHORT usPixelClock; // in 10KHz; for bios convenient
817  union {
819  // =0: DP encoder
820  // =1: LVDS encoder
821  // =2: DVI encoder
822  // =3: HDMI encoder
823  // =4: SDVO encoder
824  // =5: DP audio
825  UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
826  // =0: external DP
827  // =1: internal DP2
828  // =0x11: internal DP1 for NutMeg/Travis DP translator
829  };
830  UCHAR ucLaneNum; // how many lanes to enable
831  UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
834 
835 //ucTableFormatRevision=1
836 //ucTableContentRevision=4
837 // start from NI
838 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
840 {
841 #if ATOM_BIG_ENDIAN
842  UCHAR ucReserved1:1;
843  UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
844  UCHAR ucReserved:2;
845  UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
846 #else
847  UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
849  UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
851 #endif
853 
854 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
855 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
856 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
857 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
859 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
860 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
861 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
862 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
863 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
864 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
865 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
866 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
867 
869 {
870  USHORT usPixelClock; // in 10KHz; for bios convenient
871  union{
874  };
876  union {
878  // =0: DP encoder
879  // =1: LVDS encoder
880  // =2: DVI encoder
881  // =3: HDMI encoder
882  // =4: SDVO encoder
883  // =5: DP audio
884  UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
885  // =0: external DP
886  // =1: internal DP2
887  // =0x11: internal DP1 for NutMeg/Travis DP translator
888  };
889  UCHAR ucLaneNum; // how many lanes to enable
890  UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
891  UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
893 
894 // define ucBitPerColor:
895 #define PANEL_BPC_UNDEFINE 0x00
896 #define PANEL_6BIT_PER_COLOR 0x01
897 #define PANEL_8BIT_PER_COLOR 0x02
898 #define PANEL_10BIT_PER_COLOR 0x03
899 #define PANEL_12BIT_PER_COLOR 0x04
900 #define PANEL_16BIT_PER_COLOR 0x05
901 
902 //define ucPanelMode
903 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
904 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
905 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
906 
907 /****************************************************************************/
908 // Structures used by UNIPHYTransmitterControlTable
909 // LVTMATransmitterControlTable
910 // DVOOutputControlTable
911 /****************************************************************************/
912 typedef struct _ATOM_DP_VS_MODE
913 {
917 
919 {
920  union
921  {
922  USHORT usPixelClock; // in 10KHz; for bios convenient
923  USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
924  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
925  };
927  // [0]=0: 4 lane Link,
928  // =1: 8 lane Link ( Dual Links TMDS )
929  // [1]=0: InCoherent mode
930  // =1: Coherent Mode
931  // [2] Link Select:
932  // =0: PHY linkA if bfLane<3
933  // =1: PHY linkB if bfLanes<3
934  // =0: PHY linkA+B if bfLanes=3
935  // [5:4]PCIE lane Sel
936  // =0: lane 0~3 or 0~7
937  // =1: lane 4~7
938  // =2: lane 8~11 or 8~15
939  // =3: lane 12~15
940  UCHAR ucAction; // =0: turn off encoder
941  // =1: turn on encoder
944 
945 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
946 
947 //ucInitInfo
948 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
949 
950 //ucConfig
951 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
952 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
953 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
954 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
955 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
956 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
957 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
958 
959 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
960 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
961 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
962 
963 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
964 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
965 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
966 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
967 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
968 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
969 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
970 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
971 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
972 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
973 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
974 
975 //ucAction
976 #define ATOM_TRANSMITTER_ACTION_DISABLE 0
977 #define ATOM_TRANSMITTER_ACTION_ENABLE 1
978 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
979 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
980 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
981 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
982 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
983 #define ATOM_TRANSMITTER_ACTION_INIT 7
984 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
985 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
986 #define ATOM_TRANSMITTER_ACTION_SETUP 10
987 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
988 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12
989 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
990 
991 // Following are used for DigTransmitterControlTable ver1.2
993 {
994 #if ATOM_BIG_ENDIAN
995  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
996  // =1 Dig Transmitter 2 ( Uniphy CD )
997  // =2 Dig Transmitter 3 ( Uniphy EF )
998  UCHAR ucReserved:1;
999  UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1000  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1001  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1002  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1003 
1004  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1005  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1006 #else
1007  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1008  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1009  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1010  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1011  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1012  UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1014  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1015  // =1 Dig Transmitter 2 ( Uniphy CD )
1016  // =2 Dig Transmitter 3 ( Uniphy EF )
1017 #endif
1019 
1020 //ucConfig
1021 //Bit0
1022 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1023 
1024 //Bit1
1025 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1026 
1027 //Bit2
1028 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1029 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1030 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1031 
1032 // Bit3
1033 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1034 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1035 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1036 
1037 // Bit4
1038 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1039 
1040 // Bit7:6
1041 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1042 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1043 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1044 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1045 
1047 {
1048  union
1049  {
1050  USHORT usPixelClock; // in 10KHz; for bios convenient
1051  USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1052  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1053  };
1055  UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1058 
1060 {
1061 #if ATOM_BIG_ENDIAN
1062  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1063  // =1 Dig Transmitter 2 ( Uniphy CD )
1064  // =2 Dig Transmitter 3 ( Uniphy EF )
1065  UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1066  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1067  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1068  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1069  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1070  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1071 #else
1072  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1073  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1074  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1075  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1076  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1077  UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1078  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1079  // =1 Dig Transmitter 2 ( Uniphy CD )
1080  // =2 Dig Transmitter 3 ( Uniphy EF )
1081 #endif
1083 
1084 
1086 {
1087  union
1088  {
1089  USHORT usPixelClock; // in 10KHz; for bios convenient
1090  USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1091  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1092  };
1094  UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1098 
1099 //ucConfig
1100 //Bit0
1101 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1102 
1103 //Bit1
1104 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1105 
1106 //Bit2
1107 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1108 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1109 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1110 
1111 // Bit3
1112 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1113 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1114 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1115 
1116 // Bit5:4
1117 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1118 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1119 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1120 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1121 
1122 // Bit7:6
1123 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1124 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1125 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1126 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1127 
1128 
1129 /****************************************************************************/
1130 // Structures used by UNIPHYTransmitterControlTable V1.4
1131 // ASIC Families: NI
1132 // ucTableFormatRevision=1
1133 // ucTableContentRevision=4
1134 /****************************************************************************/
1135 typedef struct _ATOM_DP_VS_MODE_V4
1136 {
1138  union
1139  {
1141  struct {
1142 #if ATOM_BIG_ENDIAN
1143  UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1144  UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1145  UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1146 #else
1147  UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1148  UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1149  UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1150 #endif
1151  };
1152  };
1154 
1156 {
1157 #if ATOM_BIG_ENDIAN
1158  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1159  // =1 Dig Transmitter 2 ( Uniphy CD )
1160  // =2 Dig Transmitter 3 ( Uniphy EF )
1161  UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1162  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1163  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1164  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1165  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1166  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1167 #else
1168  UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1169  UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1170  UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1171  // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1172  UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1173  UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1174  UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1175  // =1 Dig Transmitter 2 ( Uniphy CD )
1176  // =2 Dig Transmitter 3 ( Uniphy EF )
1177 #endif
1179 
1181 {
1182  union
1183  {
1184  USHORT usPixelClock; // in 10KHz; for bios convenient
1185  USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1186  ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1187  };
1188  union
1189  {
1192  };
1193  UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1197 
1198 //ucConfig
1199 //Bit0
1200 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1201 //Bit1
1202 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1203 //Bit2
1204 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1205 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1206 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1207 // Bit3
1208 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1209 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1210 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1211 // Bit5:4
1212 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1213 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1214 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1215 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1216 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1217 // Bit7:6
1218 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1219 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1220 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1221 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1222 
1223 
1225 {
1226 #if ATOM_BIG_ENDIAN
1227  UCHAR ucReservd1:1;
1228  UCHAR ucHPDSel:3;
1229  UCHAR ucPhyClkSrcId:2;
1230  UCHAR ucCoherentMode:1;
1231  UCHAR ucReserved:1;
1232 #else
1238 #endif
1240 
1242 {
1243  USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1244  UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1245  UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1246  UCHAR ucLaneNum; // indicate lane number 1-8
1247  UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1248  UCHAR ucDigMode; // indicate DIG mode
1249  union{
1252  };
1253  UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1258 
1259 //ucPhyId
1260 #define ATOM_PHY_ID_UNIPHYA 0
1261 #define ATOM_PHY_ID_UNIPHYB 1
1262 #define ATOM_PHY_ID_UNIPHYC 2
1263 #define ATOM_PHY_ID_UNIPHYD 3
1264 #define ATOM_PHY_ID_UNIPHYE 4
1265 #define ATOM_PHY_ID_UNIPHYF 5
1266 #define ATOM_PHY_ID_UNIPHYG 6
1267 
1268 // ucDigEncoderSel
1269 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1270 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1271 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1272 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1273 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1274 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1275 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1276 
1277 // ucDigMode
1278 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1279 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1280 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1281 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1282 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1283 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1284 
1285 // ucDPLaneSet
1286 #define DP_LANE_SET__0DB_0_4V 0x00
1287 #define DP_LANE_SET__0DB_0_6V 0x01
1288 #define DP_LANE_SET__0DB_0_8V 0x02
1289 #define DP_LANE_SET__0DB_1_2V 0x03
1290 #define DP_LANE_SET__3_5DB_0_4V 0x08
1291 #define DP_LANE_SET__3_5DB_0_6V 0x09
1292 #define DP_LANE_SET__3_5DB_0_8V 0x0a
1293 #define DP_LANE_SET__6DB_0_4V 0x10
1294 #define DP_LANE_SET__6DB_0_6V 0x11
1295 #define DP_LANE_SET__9_5DB_0_4V 0x18
1296 
1297 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1298 // Bit1
1299 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1300 
1301 // Bit3:2
1302 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1303 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1304 
1305 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1306 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1307 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1308 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1309 // Bit6:4
1310 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1311 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1312 
1313 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1314 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1315 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1316 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1317 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1320 
1321 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1322 
1323 
1324 /****************************************************************************/
1325 // Structures used by ExternalEncoderControlTable V1.3
1326 // ASIC Families: Evergreen, Llano, NI
1327 // ucTableFormatRevision=1
1328 // ucTableContentRevision=3
1329 /****************************************************************************/
1330 
1332 {
1333  union{
1334  USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1335  USHORT usConnectorId; // connector id, valid when ucAction = INIT
1336  };
1337  UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1339  UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1340  UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1341  UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1344 
1345 // ucAction
1346 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1347 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1348 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1349 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1350 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1351 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1352 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1353 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1354 
1355 // ucConfig
1356 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1357 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1358 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1359 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1360 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
1361 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1362 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1363 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1364 
1366 {
1370 
1371 
1372 /****************************************************************************/
1373 // Structures used by DAC1OuputControlTable
1374 // DAC2OuputControlTable
1375 // LVTMAOutputControlTable (Before DEC30)
1376 // TMDSAOutputControlTable (Before DEC30)
1377 /****************************************************************************/
1379 {
1380  UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1381  // When the display is LCD, in addition to above:
1382  // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1383  // ATOM_LCD_SELFTEST_STOP
1384 
1385  UCHAR aucPadding[3]; // padding to DWORD aligned
1387 
1388 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1389 
1390 
1391 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1392 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1393 
1394 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1395 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1396 
1397 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1398 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1399 
1400 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1401 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1402 
1403 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1404 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1405 
1406 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1407 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1408 
1409 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1410 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1411 
1412 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1413 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1414 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1415 
1416 /****************************************************************************/
1417 // Structures used by BlankCRTCTable
1418 /****************************************************************************/
1420 {
1421  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1422  UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1427 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1428 
1429 /****************************************************************************/
1430 // Structures used by EnableCRTCTable
1431 // EnableCRTCMemReqTable
1432 // UpdateCRTC_DoubleBufferRegistersTable
1433 /****************************************************************************/
1435 {
1436  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1437  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1440 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1441 
1442 /****************************************************************************/
1443 // Structures used by SetCRTC_OverScanTable
1444 /****************************************************************************/
1446 {
1451  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1454 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1455 
1456 /****************************************************************************/
1457 // Structures used by SetCRTC_ReplicationTable
1458 /****************************************************************************/
1460 {
1461  UCHAR ucH_Replication; // horizontal replication
1462  UCHAR ucV_Replication; // vertical replication
1463  UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1466 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1467 
1468 /****************************************************************************/
1469 // Structures used by SelectCRTC_SourceTable
1470 /****************************************************************************/
1472 {
1473  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1474  UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1477 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1478 
1480 {
1481  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1482  UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1483  UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1486 
1487 //ucEncoderID
1488 //#define ASIC_INT_DAC1_ENCODER_ID 0x00
1489 //#define ASIC_INT_TV_ENCODER_ID 0x02
1490 //#define ASIC_INT_DIG1_ENCODER_ID 0x03
1491 //#define ASIC_INT_DAC2_ENCODER_ID 0x04
1492 //#define ASIC_EXT_TV_ENCODER_ID 0x06
1493 //#define ASIC_INT_DVO_ENCODER_ID 0x07
1494 //#define ASIC_INT_DIG2_ENCODER_ID 0x09
1495 //#define ASIC_EXT_DIG_ENCODER_ID 0x05
1496 
1497 //ucEncodeMode
1498 //#define ATOM_ENCODER_MODE_DP 0
1499 //#define ATOM_ENCODER_MODE_LVDS 1
1500 //#define ATOM_ENCODER_MODE_DVI 2
1501 //#define ATOM_ENCODER_MODE_HDMI 3
1502 //#define ATOM_ENCODER_MODE_SDVO 4
1503 //#define ATOM_ENCODER_MODE_TV 13
1504 //#define ATOM_ENCODER_MODE_CV 14
1505 //#define ATOM_ENCODER_MODE_CRT 15
1506 
1507 /****************************************************************************/
1508 // Structures used by SetPixelClockTable
1509 // GetPixelClockTable
1510 /****************************************************************************/
1511 //Major revision=1., Minor revision=1
1513 {
1514  USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1515  // 0 means disable PPLL
1516  USHORT usRefDiv; // Reference divider
1517  USHORT usFbDiv; // feedback divider
1518  UCHAR ucPostDiv; // post divider
1519  UCHAR ucFracFbDiv; // fractional feedback divider
1520  UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1521  UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1522  UCHAR ucCRTC; // Which CRTC uses this Ppll
1525 
1526 //Major revision=1., Minor revision=2, add ucMiscIfno
1527 //ucMiscInfo:
1528 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1529 #define MISC_DEVICE_INDEX_MASK 0xF0
1530 #define MISC_DEVICE_INDEX_SHIFT 4
1531 
1533 {
1534  USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1535  // 0 means disable PPLL
1536  USHORT usRefDiv; // Reference divider
1537  USHORT usFbDiv; // feedback divider
1538  UCHAR ucPostDiv; // post divider
1539  UCHAR ucFracFbDiv; // fractional feedback divider
1540  UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1541  UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1542  UCHAR ucCRTC; // Which CRTC uses this Ppll
1543  UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1545 
1546 //Major revision=1., Minor revision=3, structure/definition change
1547 //ucEncoderMode:
1548 //ATOM_ENCODER_MODE_DP
1549 //ATOM_ENOCDER_MODE_LVDS
1550 //ATOM_ENOCDER_MODE_DVI
1551 //ATOM_ENOCDER_MODE_HDMI
1552 //ATOM_ENOCDER_MODE_SDVO
1553 //ATOM_ENCODER_MODE_TV 13
1554 //ATOM_ENCODER_MODE_CV 14
1555 //ATOM_ENCODER_MODE_CRT 15
1556 
1557 //ucDVOConfig
1558 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1559 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1560 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1561 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1562 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1563 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1564 //#define DVO_ENCODER_CONFIG_24BIT 0x08
1565 
1566 //ucMiscInfo: also changed, see below
1567 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1568 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1569 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1570 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1571 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1572 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1573 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1574 // V1.4 for RoadRunner
1575 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1576 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1577 
1578 
1580 {
1581  USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1582  // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1583  USHORT usRefDiv; // Reference divider
1584  USHORT usFbDiv; // feedback divider
1585  UCHAR ucPostDiv; // post divider
1586  UCHAR ucFracFbDiv; // fractional feedback divider
1587  UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1588  UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1589  union
1590  {
1591  UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1592  UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1593  };
1594  UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1595  // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1596  // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1598 
1599 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1600 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1601 
1603 {
1604  UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1605  // drive the pixel clock. not used for DCPLL case.
1606  union{
1608  UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1609  };
1610  USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1611  // 0 means disable PPLL/DCPLL.
1612  USHORT usFbDiv; // feedback divider integer part.
1613  UCHAR ucPostDiv; // post divider.
1614  UCHAR ucRefDiv; // Reference divider
1615  UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1616  UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1617  // indicate which graphic encoder will be used.
1618  UCHAR ucEncoderMode; // Encoder mode:
1619  UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1620  // bit[1]= when VGA timing is used.
1621  // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1622  // bit[4]= RefClock source for PPLL.
1623  // =0: XTLAIN( default mode )
1624  // =1: other external clock source, which is pre-defined
1625  // by VBIOS depend on the feature required.
1626  // bit[7:5]: reserved.
1627  ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1628 
1630 
1631 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1632 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1633 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1634 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1635 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1636 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1637 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1638 
1640 {
1641 #if ATOM_BIG_ENDIAN
1642  ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1643  // drive the pixel clock. not used for DCPLL case.
1644  ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1645  // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1646 #else
1647  ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1648  // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1649  ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1650  // drive the pixel clock. not used for DCPLL case.
1651 #endif
1653 
1655 {
1656  union{
1657  CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1658  ULONG ulDispEngClkFreq; // dispclk frequency
1659  };
1660  USHORT usFbDiv; // feedback divider integer part.
1661  UCHAR ucPostDiv; // post divider.
1662  UCHAR ucRefDiv; // Reference divider
1663  UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1664  UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1665  // indicate which graphic encoder will be used.
1666  UCHAR ucEncoderMode; // Encoder mode:
1667  UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1668  // bit[1]= when VGA timing is used.
1669  // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1670  // bit[4]= RefClock source for PPLL.
1671  // =0: XTLAIN( default mode )
1672  // =1: other external clock source, which is pre-defined
1673  // by VBIOS depend on the feature required.
1674  // bit[7:5]: reserved.
1675  ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1676 
1678 
1679 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1680 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1681 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1682 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1683 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1684 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1685 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1686 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1687 
1689 {
1692 
1694 {
1696  UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1699 
1701 {
1704 
1705 /****************************************************************************/
1706 // Structures used by AdjustDisplayPllTable
1707 /****************************************************************************/
1709 {
1713  union
1714  {
1715  UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1716  UCHAR ucConfig; //if none DVO, not defined yet
1717  };
1720 
1721 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
1722 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
1723 
1725 {
1726  USHORT usPixelClock; // target pixel clock
1727  UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1728  UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1729  UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1730  UCHAR ucExtTransmitterID; // external encoder id.
1733 
1734 // usDispPllConfig v1.2 for RoadRunner
1735 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
1736 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
1737 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
1738 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
1739 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
1740 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
1741 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
1742 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
1743 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
1744 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
1745 
1746 
1748 {
1749  ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1750  UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1751  UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1754 
1756 {
1757  union
1758  {
1761  };
1763 
1764 /****************************************************************************/
1765 // Structures used by EnableYUVTable
1766 /****************************************************************************/
1768 {
1769  UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1770  UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1773 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1774 
1775 /****************************************************************************/
1776 // Structures used by GetMemoryClockTable
1777 /****************************************************************************/
1779 {
1780  ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1782 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
1783 
1784 /****************************************************************************/
1785 // Structures used by GetEngineClockTable
1786 /****************************************************************************/
1788 {
1789  ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1791 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
1792 
1793 /****************************************************************************/
1794 // Following Structures and constant may be obsolete
1795 /****************************************************************************/
1796 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1797 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1799 {
1800  USHORT usPrescale; //Ratio between Engine clock and I2C clock
1801  USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
1802  USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
1803  //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
1804  UCHAR ucSlaveAddr; //Read from which slave
1805  UCHAR ucLineNumber; //Read from which HW assisted line
1807 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1808 
1809 
1810 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
1811 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
1812 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
1813 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
1814 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
1815 
1817 {
1818  USHORT usPrescale; //Ratio between Engine clock and I2C clock
1819  USHORT usByteOffset; //Write to which byte
1820  //Upper portion of usByteOffset is Format of data
1821  //1bytePS+offsetPS
1822  //2bytesPS+offsetPS
1823  //blockID+offsetPS
1824  //blockID+offsetID
1825  //blockID+counterID+offsetID
1826  UCHAR ucData; //PS data1
1827  UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1828  UCHAR ucSlaveAddr; //Write to which slave
1829  UCHAR ucLineNumber; //Write from which HW assisted line
1831 
1832 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1833 
1835 {
1836  USHORT usPrescale; //Ratio between Engine clock and I2C clock
1837  UCHAR ucSlaveAddr; //Write to which slave
1838  UCHAR ucLineNumber; //Write from which HW assisted line
1840 
1841 
1842 /**************************************************************************/
1843 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1844 
1845 
1846 /****************************************************************************/
1847 // Structures used by PowerConnectorDetectionTable
1848 /****************************************************************************/
1850 {
1851  UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1853  USHORT usPwrBudget; //how much power currently boot to in unit of watt
1855 
1857 {
1858  UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1860  USHORT usPwrBudget; //how much power currently boot to in unit of watt
1863 
1864 /****************************LVDS SS Command Table Definitions**********************/
1865 
1866 /****************************************************************************/
1867 // Structures used by EnableSpreadSpectrumOnPPLLTable
1868 /****************************************************************************/
1870 {
1872  UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1873  UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1874  UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1877 
1878 //ucTableFormatRevision=1,ucTableContentRevision=2
1880 {
1882  UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1884  UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1889 
1890 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1892 {
1894  UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1896  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1899  UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1901 
1903 {
1905  UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1906  // Bit[1]: 1-Ext. 0-Int.
1907  // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1908  // Bits[7:4] reserved
1909  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1910  USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1911  USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1913 
1914 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
1915 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
1916 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
1917 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
1918 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
1919 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
1920 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
1921 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
1922 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
1923 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
1924 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1925 
1926 // Used by DCE5.0
1928 {
1929  USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
1930  UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1931  // Bit[1]: 1-Ext. 0-Int.
1932  // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1933  // Bits[7:4] reserved
1934  UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1935  USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1936  USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1938 
1939 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
1940 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
1941 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
1942 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
1943 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
1944 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
1945 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
1946 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
1947 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
1948 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
1949 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
1950 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
1951 
1952 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
1953 
1954 /**************************************************************************/
1955 
1957 {
1959  ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
1961 
1962 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
1963 
1964 /****************************************************************************/
1965 // Structures used by ###
1966 /****************************************************************************/
1968 {
1969  ULONG ulTargetMemoryClock; //In 10Khz unit
1971 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
1972 
1973 
1974 /****************************LVDS and other encoder command table definitions **********************/
1975 
1976 
1977 /****************************************************************************/
1978 // Structures used by LVDSEncoderControlTable (Before DCE30)
1979 // LVTMAEncoderControlTable (Before DCE30)
1980 // TMDSAEncoderControlTable (Before DCE30)
1981 /****************************************************************************/
1983 {
1984  USHORT usPixelClock; // in 10KHz; for bios convenient
1985  UCHAR ucMisc; // bit0=0: Enable single link
1986  // =1: Enable dual link
1987  // Bit1=0: 666RGB
1988  // =1: 888RGB
1989  UCHAR ucAction; // 0: turn off encoder
1990  // 1: setup and turn on encoder
1992 
1993 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
1994 
1995 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
1996 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
1997 
1998 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
1999 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2000 
2001 
2002 //ucTableFormatRevision=1,ucTableContentRevision=2
2004 {
2005  USHORT usPixelClock; // in 10KHz; for bios convenient
2006  UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2007  UCHAR ucAction; // 0: turn off encoder
2008  // 1: setup and turn on encoder
2009  UCHAR ucTruncate; // bit0=0: Disable truncate
2010  // =1: Enable truncate
2011  // bit4=0: 666RGB
2012  // =1: 888RGB
2013  UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2014  // =1: Enable spatial dithering
2015  // bit4=0: 666RGB
2016  // =1: 888RGB
2017  UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2018  // =1: Enable temporal dithering
2019  // bit4=0: 666RGB
2020  // =1: 888RGB
2021  // bit5=0: Gray level 2
2022  // =1: Gray level 4
2023  UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2024  // =1: 25FRC_SEL pattern F
2025  // bit6:5=0: 50FRC_SEL pattern A
2026  // =1: 50FRC_SEL pattern B
2027  // =2: 50FRC_SEL pattern C
2028  // =3: 50FRC_SEL pattern D
2029  // bit7=0: 75FRC_SEL pattern E
2030  // =1: 75FRC_SEL pattern F
2032 
2033 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2034 
2035 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2036 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2037 
2038 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2039 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2040 
2041 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2042 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2043 
2044 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2045 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2046 
2047 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2048 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2049 
2050 /****************************************************************************/
2051 // Structures used by ###
2052 /****************************************************************************/
2054 {
2055  UCHAR ucEnable; // Enable or Disable External TMDS encoder
2056  UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2059 
2061 {
2063  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2065 
2066 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2067 
2069 {
2071  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2073 
2075 {
2079 
2080 /****************************************************************************/
2081 // Structures used by DVOEncoderControlTable
2082 /****************************************************************************/
2083 //ucTableFormatRevision=1,ucTableContentRevision=3
2084 
2085 //ucDVOConfig:
2086 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2087 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2088 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2089 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2090 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2091 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2092 #define DVO_ENCODER_CONFIG_24BIT 0x08
2093 
2095 {
2098  UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2101 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2102 
2103 //ucTableFormatRevision=1
2104 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2105 // bit1=0: non-coherent mode
2106 // =1: coherent mode
2107 
2108 //==========================================================================================
2109 //Only change is here next time when changing encoder parameter definitions again!
2110 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2111 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2112 
2113 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2114 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2115 
2116 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2117 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2118 
2119 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2120 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2121 
2122 //==========================================================================================
2123 #define PANEL_ENCODER_MISC_DUAL 0x01
2124 #define PANEL_ENCODER_MISC_COHERENT 0x02
2125 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2126 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2127 
2128 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2129 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2130 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2131 
2132 #define PANEL_ENCODER_TRUNCATE_EN 0x01
2133 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2134 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2135 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2136 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2137 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2138 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2139 #define PANEL_ENCODER_25FRC_MASK 0x10
2140 #define PANEL_ENCODER_25FRC_E 0x00
2141 #define PANEL_ENCODER_25FRC_F 0x10
2142 #define PANEL_ENCODER_50FRC_MASK 0x60
2143 #define PANEL_ENCODER_50FRC_A 0x00
2144 #define PANEL_ENCODER_50FRC_B 0x20
2145 #define PANEL_ENCODER_50FRC_C 0x40
2146 #define PANEL_ENCODER_50FRC_D 0x60
2147 #define PANEL_ENCODER_75FRC_MASK 0x80
2148 #define PANEL_ENCODER_75FRC_E 0x00
2149 #define PANEL_ENCODER_75FRC_F 0x80
2150 
2151 /****************************************************************************/
2152 // Structures used by SetVoltageTable
2153 /****************************************************************************/
2154 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2155 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2156 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2157 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2158 #define SET_VOLTAGE_INIT_MODE 5
2159 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2160 
2161 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2162 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2163 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2164 
2165 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2166 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2167 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2168 
2170 {
2171  UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2172  UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2173  UCHAR ucVoltageIndex; // An index to tell which voltage level
2176 
2178 {
2179  UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2180  UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2181  USHORT usVoltageLevel; // real voltage level
2183 
2184 
2186 {
2187  UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2188  UCHAR ucVoltageMode; // Indicate action: Set voltage level
2189  USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2191 
2192 //ucVoltageType
2193 #define VOLTAGE_TYPE_VDDC 1
2194 #define VOLTAGE_TYPE_MVDDC 2
2195 #define VOLTAGE_TYPE_MVDDQ 3
2196 #define VOLTAGE_TYPE_VDDCI 4
2197 
2198 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2199 #define ATOM_SET_VOLTAGE 0 //Set voltage Level
2200 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2201 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase
2202 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3
2203 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID
2204 
2205 // define vitual voltage id in usVoltageLevel
2206 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2207 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2208 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2209 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2210 
2212 {
2216 
2217 // New Added from SI for GetVoltageInfoTable, input parameter structure
2219 {
2220  UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2221  UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2222  USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2225 
2226 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2228 {
2232 
2233 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2235 {
2237  USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2240 
2241 
2242 // GetVoltageInfo v1.1 ucVoltageMode
2243 #define ATOM_GET_VOLTAGE_VID 0x00
2244 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2245 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2246 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2247 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2248 
2249 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2250 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2251 // undefined power state
2252 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2253 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2254 
2255 /****************************************************************************/
2256 // Structures used by TVEncoderControlTable
2257 /****************************************************************************/
2259 {
2260  USHORT usPixelClock; // in 10KHz; for bios convenient
2261  UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2262  UCHAR ucAction; // 0: turn off encoder
2263  // 1: setup and turn on encoder
2265 
2267 {
2271 
2272 //==============================Data Table Portion====================================
2273 
2274 /****************************************************************************/
2275 // Structure used in Data.mtb
2276 /****************************************************************************/
2278 {
2279  USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2280  USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2281  USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2282  USHORT StandardVESA_Timing; // Only used by Bios
2283  USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2284  USHORT PaletteData; // Only used by BIOS
2285  USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2286  USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2287  USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2288  USHORT SupportedDevicesInfo; // Will be obsolete from R600
2289  USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2290  USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2291  USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2292  USHORT VESA_ToInternalModeLUT; // Only used by Bios
2293  USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2294  USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2295  USHORT CompassionateData; // Will be obsolete from R600
2296  USHORT SaveRestoreInfo; // Only used by Bios
2297  USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2298  USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2299  USHORT XTMDS_Info; // Will be obsolete from R600
2300  USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2301  USHORT Object_Header; // Shared by various SW components,latest version 1.1
2302  USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2303  USHORT MC_InitParameter; // Only used by command table
2304  USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2305  USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2306  USHORT TV_VideoMode; // Only used by command table
2307  USHORT VRAM_Info; // Only used by command table, latest version 1.3
2308  USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2309  USHORT IntegratedSystemInfo; // Shared by various SW components
2310  USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2311  USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2312  USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2314 
2316 {
2320 
2321 // For backward compatible
2322 #define LVDS_Info LCD_Info
2323 #define DAC_Info PaletteData
2324 #define TMDS_Info DIGTransmitterInfo
2325 
2326 /****************************************************************************/
2327 // Structure used in MultimediaCapabilityInfoTable
2328 /****************************************************************************/
2330 {
2332  ULONG ulSignature; // HW info table signature string "$ATI"
2333  UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2334  UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2335  UCHAR ucVideoPortInfo; // Provides the video port capabilities
2336  UCHAR ucHostPortInfo; // Provides host port configuration information
2338 
2339 /****************************************************************************/
2340 // Structure used in MultimediaConfigInfoTable
2341 /****************************************************************************/
2343 {
2345  ULONG ulSignature; // MM info table signature sting "$MMT"
2346  UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2347  UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2348  UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2349  UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2350  UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2351  UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2352  UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2353  UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2354  UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2355  UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2356  UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2357  UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2359 
2360 
2361 /****************************************************************************/
2362 // Structures used in FirmwareInfoTable
2363 /****************************************************************************/
2364 
2365 // usBIOSCapability Definition:
2366 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2367 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2368 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2369 // Others: Reserved
2370 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2371 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2372 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2373 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2374 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2375 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2376 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2377 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2378 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2379 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2380 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2381 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2382 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2383 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2384 
2385 #ifndef _H2INC
2386 
2387 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2389 {
2390 #if ATOM_BIG_ENDIAN
2391  USHORT Reserved:1;
2397  USHORT WMI_SUPPORT:1;
2404 #else
2418 #endif
2420 
2422 {
2426 
2427 #else
2428 
2430 {
2431  USHORT susAccess;
2433 
2434 #endif
2435 
2436 typedef struct _ATOM_FIRMWARE_INFO
2437 {
2440  ULONG ulDefaultEngineClock; //In 10Khz unit
2441  ULONG ulDefaultMemoryClock; //In 10Khz unit
2447  ULONG ulASICMaxEngineClock; //In 10Khz unit
2448  ULONG ulASICMaxMemoryClock; //In 10Khz unit
2450  UCHAR ucPadding[3]; //Don't use them
2451  ULONG aulReservedForBIOS[3]; //Don't use them
2458  USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2461  USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2463  USHORT usReferenceClock; //In 10Khz unit
2464  USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2465  UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2466  UCHAR ucDesign_ID; //Indicate what is the board design
2467  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2469 
2471 {
2474  ULONG ulDefaultEngineClock; //In 10Khz unit
2475  ULONG ulDefaultMemoryClock; //In 10Khz unit
2481  ULONG ulASICMaxEngineClock; //In 10Khz unit
2482  ULONG ulASICMaxMemoryClock; //In 10Khz unit
2485  UCHAR ucPadding[2]; //Don't use them
2486  ULONG aulReservedForBIOS[2]; //Don't use them
2494  USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2497  USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2499  USHORT usReferenceClock; //In 10Khz unit
2500  USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2501  UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2502  UCHAR ucDesign_ID; //Indicate what is the board design
2503  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2505 
2507 {
2510  ULONG ulDefaultEngineClock; //In 10Khz unit
2511  ULONG ulDefaultMemoryClock; //In 10Khz unit
2517  ULONG ulASICMaxEngineClock; //In 10Khz unit
2518  ULONG ulASICMaxMemoryClock; //In 10Khz unit
2521  UCHAR ucPadding[2]; //Don't use them
2522  ULONG aulReservedForBIOS; //Don't use them
2531  USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2534  USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2536  USHORT usReferenceClock; //In 10Khz unit
2537  USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2538  UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2539  UCHAR ucDesign_ID; //Indicate what is the board design
2540  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2542 
2544 {
2547  ULONG ulDefaultEngineClock; //In 10Khz unit
2548  ULONG ulDefaultMemoryClock; //In 10Khz unit
2554  ULONG ulASICMaxEngineClock; //In 10Khz unit
2555  ULONG ulASICMaxMemoryClock; //In 10Khz unit
2569  USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2572  USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2574  USHORT usReferenceClock; //In 10Khz unit
2575  USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2576  UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2577  UCHAR ucDesign_ID; //Indicate what is the board design
2578  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2580 
2581 //the structure below to be used from Cypress
2583 {
2586  ULONG ulDefaultEngineClock; //In 10Khz unit
2587  ULONG ulDefaultMemoryClock; //In 10Khz unit
2593  ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2595  UCHAR ucReserved1; //Was ucASICMaxTemperature;
2600  ULONG ulReserved4; //Was ulAsicMaximumVoltage
2608  USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2611  USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2613  USHORT usCoreReferenceClock; //In 10Khz unit
2614  USHORT usMemoryReferenceClock; //In 10Khz unit
2615  USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2616  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2619 
2620 //the structure below to be used from NI
2621 //ucTableFormatRevision=2
2622 //ucTableContentRevision=2
2624 {
2627  ULONG ulDefaultEngineClock; //In 10Khz unit
2628  ULONG ulDefaultMemoryClock; //In 10Khz unit
2630  ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2631  ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2633  ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2634  ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2635  UCHAR ucReserved3; //Was ucASICMaxTemperature;
2640  ULONG ulReserved4; //Was ulAsicMaximumVoltage
2643  UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2644  ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2645  ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2646  USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
2649  USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2651  USHORT usCoreReferenceClock; //In 10Khz unit
2652  USHORT usMemoryReferenceClock; //In 10Khz unit
2653  USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2654  UCHAR ucMemoryModule_ID; //Indicate what is the board design
2656  USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2658  ULONG ulReserved10[3]; // New added comparing to previous version
2660 
2661 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
2662 
2663 
2664 // definition of ucRemoteDisplayConfig
2665 #define REMOTE_DISPLAY_DISABLE 0x00
2666 #define REMOTE_DISPLAY_ENABLE 0x01
2667 
2668 /****************************************************************************/
2669 // Structures used in IntegratedSystemInfoTable
2670 /****************************************************************************/
2671 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
2672 #define IGP_CAP_FLAG_AC_CARD 0x4
2673 #define IGP_CAP_FLAG_SDVO_CARD 0x8
2674 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
2675 
2677 {
2679  ULONG ulBootUpEngineClock; //in 10kHz unit
2680  ULONG ulBootUpMemoryClock; //in 10kHz unit
2684  UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2686  USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
2687  USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
2689 
2690  USHORT usFSBClock; //In MHz unit
2691  USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2692  //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2693  //Bit[4]==1: P/2 mode, ==0: P/1 mode
2694  USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2695  USHORT usK8MemoryClock; //in MHz unit
2696  USHORT usK8SyncStartDelay; //in 0.01 us unit
2697  USHORT usK8DataReturnTime; //in 0.01 us unit
2700  UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2701  UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2702  UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2703  UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2707 
2708 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2709 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
2710  For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2711 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2712  For AMD IGP,for now this can be 0
2713 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2714  For AMD IGP,for now this can be 0
2715 
2716 usFSBClock: For Intel IGP,it's FSB Freq
2717  For AMD IGP,it's HT Link Speed
2718 
2719 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
2720 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2721 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2722 
2723 VC:Voltage Control
2724 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2725 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2726 
2727 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2728 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2729 
2730 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2731 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2732 
2733 
2734 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2735 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2736 */
2737 
2738 
2739 /*
2740 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2741 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2742 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2743 
2744 SW components can access the IGP system infor structure in the same way as before
2745 */
2746 
2747 
2749 {
2751  ULONG ulBootUpEngineClock; //in 10kHz unit
2752  ULONG ulReserved1[2]; //must be 0x0 for the reserved
2753  ULONG ulBootUpUMAClock; //in 10kHz unit
2754  ULONG ulBootUpSidePortClock; //in 10kHz unit
2755  ULONG ulMinSidePortClock; //in 10kHz unit
2756  ULONG ulReserved2[6]; //must be 0x0 for the reserved
2757  ULONG ulSystemConfig; //see explanation below
2762  UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2772  ULONG ulHTLinkFreq; //in 10Khz
2778  USHORT usDACEfuse; //for storing badgap value (for RS880 only)
2785  USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2786  USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2787  ULONG ulReserved3[96]; //must be 0x0
2789 
2790 /*
2791 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2792 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2793 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2794 
2795 ulSystemConfig:
2796 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2797 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2798  =0: system boots up at driver control state. Power state depends on PowerPlay table.
2799 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2800 Bit[3]=1: Only one power state(Performance) will be supported.
2801  =0: Multiple power states supported from PowerPlay table.
2802 Bit[4]=1: CLMC is supported and enabled on current system.
2803  =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2804 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2805  =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2806 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2807  =0: Voltage settings is determined by powerplay table.
2808 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2809  =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2810 Bit[8]=1: CDLF is supported and enabled on current system.
2811  =0: CDLF is not supported or enabled on current system.
2812 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2813  =0: DLL Shut Down feature is not enabled or supported on current system.
2814 
2815 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2816 
2817 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2818  [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2819 
2820 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2821  [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2822  [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2823  When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2824  in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2825  one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2826 
2827  [15:8] - Lane configuration attribute;
2828  [23:16]- Connector type, possible value:
2829  CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2830  CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2831  CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2832  CONNECTOR_OBJECT_ID_DISPLAYPORT
2833  CONNECTOR_OBJECT_ID_eDP
2834  [31:24]- Reserved
2835 
2836 ulDDISlot2Config: Same as Slot1.
2837 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2838 For IGP, Hypermemory is the only memory type showed in CCC.
2839 
2840 ucUMAChannelNumber: how many channels for the UMA;
2841 
2842 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2843 ucDockingPinBit: which bit in this register to read the pin status;
2844 ucDockingPinPolarity:Polarity of the pin when docked;
2845 
2846 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2847 
2848 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2849 
2850 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2851 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2852  GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2853  PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2854  GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2855 
2856 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2857 
2858 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2859 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
2860  If CDLW enabled, both upstream and downstream width should be the same during bootup.
2861 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
2862  If CDLW enabled, both upstream and downstream width should be the same during bootup.
2863 
2864 usUMASyncStartDelay: Memory access latency, required for watermark calculation
2865 usUMADataReturnTime: Memory access latency, required for watermark calculation
2866 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
2867 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2868  if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2869  if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2870  if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2871  if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2872 
2873 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2874  This must be less than or equal to ulHTLinkFreq(bootup frequency).
2875 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2876  This must be less than or equal to ulHighVoltageHTLinkFreq.
2877 
2878 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2879 usMaxDownStreamHTLinkWidth: same as above.
2880 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2881 usMinDownStreamHTLinkWidth: same as above.
2882 */
2883 
2884 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2885 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
2886 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2887 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2888 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
2889 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2890 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
2891 
2892 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
2893 
2894 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
2895 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
2896 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
2897 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
2898 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
2899 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
2900 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
2901 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
2902 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
2903 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
2904 
2905 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
2906 
2907 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
2908 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
2909 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
2910 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
2911 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
2912 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
2913 
2914 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
2915 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
2916 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
2917 
2918 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
2919 
2920 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2922 {
2924  ULONG ulBootUpEngineClock; //in 10kHz unit
2925  ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2926  ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2927  ULONG ulBootUpUMAClock; //in 10kHz unit
2928  ULONG ulReserved1[8]; //must be 0x0 for the reserved
2931  ULONG ulReserved2[4]; //must be 0x0 for the reserved
2934  USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2935  USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2936  USHORT usBootUpNBVoltage; //boot up NB voltage
2937  UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2938  UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2939  ULONG ulReserved3[4]; //must be 0x0 for the reserved
2940  ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
2944  ULONG ulReserved4[4]; //must be 0x0 for the reserved
2945  UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2948  ULONG ulReserved5[4]; //must be 0x0 for the reserved
2949  ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2950  ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2951  ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2952  ULONG ulReserved6[61]; //must be 0x0
2954 
2955 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
2956 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
2957 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
2958 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
2959 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
2960 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
2961 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
2962 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
2963 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
2964 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
2965 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
2966 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
2967 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
2968 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
2969 
2970 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
2971 #define ASIC_INT_DAC1_ENCODER_ID 0x00
2972 #define ASIC_INT_TV_ENCODER_ID 0x02
2973 #define ASIC_INT_DIG1_ENCODER_ID 0x03
2974 #define ASIC_INT_DAC2_ENCODER_ID 0x04
2975 #define ASIC_EXT_TV_ENCODER_ID 0x06
2976 #define ASIC_INT_DVO_ENCODER_ID 0x07
2977 #define ASIC_INT_DIG2_ENCODER_ID 0x09
2978 #define ASIC_EXT_DIG_ENCODER_ID 0x05
2979 #define ASIC_EXT_DIG2_ENCODER_ID 0x08
2980 #define ASIC_INT_DIG3_ENCODER_ID 0x0a
2981 #define ASIC_INT_DIG4_ENCODER_ID 0x0b
2982 #define ASIC_INT_DIG5_ENCODER_ID 0x0c
2983 #define ASIC_INT_DIG6_ENCODER_ID 0x0d
2984 #define ASIC_INT_DIG7_ENCODER_ID 0x0e
2985 
2986 //define Encoder attribute
2987 #define ATOM_ANALOG_ENCODER 0
2988 #define ATOM_DIGITAL_ENCODER 1
2989 #define ATOM_DP_ENCODER 2
2990 
2991 #define ATOM_ENCODER_ENUM_MASK 0x70
2992 #define ATOM_ENCODER_ENUM_ID1 0x00
2993 #define ATOM_ENCODER_ENUM_ID2 0x10
2994 #define ATOM_ENCODER_ENUM_ID3 0x20
2995 #define ATOM_ENCODER_ENUM_ID4 0x30
2996 #define ATOM_ENCODER_ENUM_ID5 0x40
2997 #define ATOM_ENCODER_ENUM_ID6 0x50
2998 
2999 #define ATOM_DEVICE_CRT1_INDEX 0x00000000
3000 #define ATOM_DEVICE_LCD1_INDEX 0x00000001
3001 #define ATOM_DEVICE_TV1_INDEX 0x00000002
3002 #define ATOM_DEVICE_DFP1_INDEX 0x00000003
3003 #define ATOM_DEVICE_CRT2_INDEX 0x00000004
3004 #define ATOM_DEVICE_LCD2_INDEX 0x00000005
3005 #define ATOM_DEVICE_DFP6_INDEX 0x00000006
3006 #define ATOM_DEVICE_DFP2_INDEX 0x00000007
3007 #define ATOM_DEVICE_CV_INDEX 0x00000008
3008 #define ATOM_DEVICE_DFP3_INDEX 0x00000009
3009 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3010 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3011 
3012 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3013 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3014 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3015 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3016 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3017 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3018 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3019 
3020 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3021 
3022 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3023 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3024 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3025 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3026 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3027 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3028 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3029 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3030 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3031 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3032 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3033 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3034 
3035 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3036 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3037 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
3038 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3039 
3040 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3041 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3042 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3043 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3044 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3045 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3046 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3047 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3048 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3049 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3050 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3051 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3052 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3053 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3054 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3055 
3056 
3057 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3058 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3059 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3060 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3061 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3062 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3063 
3064 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3065 
3066 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3067 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3068 
3069 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3070 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3071 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3072 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3073 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3074 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3075 
3076 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3077 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3078 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3079 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3080 
3081 // usDeviceSupport:
3082 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3083 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3084 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3085 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3086 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3087 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3088 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3089 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3090 // Bit 8 = 0 - no CV support= 1- CV is supported
3091 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3092 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3093 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3094 //
3095 //
3096 
3097 /****************************************************************************/
3098 /* Structure used in MclkSS_InfoTable */
3099 /****************************************************************************/
3100 // ucI2C_ConfigID
3101 // [7:0] - I2C LINE Associate ID
3102 // = 0 - no I2C
3103 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3104 // = 0, [6:0]=SW assisted I2C ID
3105 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3106 // = 2, HW engine for Multimedia use
3107 // = 3-7 Reserved for future I2C engines
3108 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3109 
3110 typedef struct _ATOM_I2C_ID_CONFIG
3111 {
3112 #if ATOM_BIG_ENDIAN
3113  UCHAR bfHW_Capable:1;
3114  UCHAR bfHW_EngineID:3;
3115  UCHAR bfI2C_LineMux:4;
3116 #else
3120 #endif
3122 
3124 {
3128 
3129 
3130 /****************************************************************************/
3131 // Structure used in GPIO_I2C_InfoTable
3132 /****************************************************************************/
3134 {
3155 
3156 typedef struct _ATOM_GPIO_I2C_INFO
3157 {
3161 
3162 /****************************************************************************/
3163 // Common Structure used in other structures
3164 /****************************************************************************/
3165 
3166 #ifndef _H2INC
3167 
3168 //Please don't add or expand this bitfield structure below, this one will retire soon.!
3169 typedef struct _ATOM_MODE_MISC_INFO
3170 {
3171 #if ATOM_BIG_ENDIAN
3172  USHORT Reserved:6;
3173  USHORT RGB888:1;
3174  USHORT DoubleClock:1;
3175  USHORT Interlace:1;
3180  USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3181  USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3183 #else
3185  USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3186  USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3195 #endif
3197 
3199 {
3203 
3204 #else
3205 
3206 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3207 {
3208  USHORT usAccess;
3210 
3211 #endif
3212 
3213 // usModeMiscInfo-
3214 #define ATOM_H_CUTOFF 0x01
3215 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3216 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3217 #define ATOM_V_CUTOFF 0x08
3218 #define ATOM_H_REPLICATIONBY2 0x10
3219 #define ATOM_V_REPLICATIONBY2 0x20
3220 #define ATOM_COMPOSITESYNC 0x40
3221 #define ATOM_INTERLACE 0x80
3222 #define ATOM_DOUBLE_CLOCK_MODE 0x100
3223 #define ATOM_RGB888_MODE 0x200
3224 
3225 //usRefreshRate-
3226 #define ATOM_REFRESH_43 43
3227 #define ATOM_REFRESH_47 47
3228 #define ATOM_REFRESH_56 56
3229 #define ATOM_REFRESH_60 60
3230 #define ATOM_REFRESH_65 65
3231 #define ATOM_REFRESH_70 70
3232 #define ATOM_REFRESH_72 72
3233 #define ATOM_REFRESH_75 75
3234 #define ATOM_REFRESH_85 85
3235 
3236 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3237 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3238 //
3239 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3240 // = EDID_HA + EDID_HBL
3241 // VESA_HDISP = VESA_ACTIVE = EDID_HA
3242 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3243 // = EDID_HA + EDID_HSO
3244 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3245 // VESA_BORDER = EDID_BORDER
3246 
3247 /****************************************************************************/
3248 // Structure used in SetCRTC_UsingDTDTimingTable
3249 /****************************************************************************/
3251 {
3261  UCHAR ucH_Border; // From DFP EDID
3263  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3266 
3267 /****************************************************************************/
3268 // Structure used in SetCRTC_TimingTable
3269 /****************************************************************************/
3271 {
3272  USHORT usH_Total; // horizontal total
3273  USHORT usH_Disp; // horizontal display
3274  USHORT usH_SyncStart; // horozontal Sync start
3275  USHORT usH_SyncWidth; // horizontal Sync width
3276  USHORT usV_Total; // vertical total
3277  USHORT usV_Disp; // vertical display
3278  USHORT usV_SyncStart; // vertical Sync start
3279  USHORT usV_SyncWidth; // vertical Sync width
3281  UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3288 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3289 
3290 /****************************************************************************/
3291 // Structure used in StandardVESA_TimingTable
3292 // AnalogTV_InfoTable
3293 // ComponentVideoInfoTable
3294 /****************************************************************************/
3295 typedef struct _ATOM_MODE_TIMING
3296 {
3305  USHORT usPixelClock; //in 10Khz unit
3315 
3316 typedef struct _ATOM_DTD_FORMAT
3317 {
3335 
3336 /****************************************************************************/
3337 // Structure used in LVDS_InfoTable
3338 // * Need a document to describe this table
3339 /****************************************************************************/
3340 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3341 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3342 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3343 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3344 
3345 //ucTableFormatRevision=1
3346 //ucTableContentRevision=1
3347 typedef struct _ATOM_LVDS_INFO
3348 {
3352  USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3356  UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3357  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3358  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3359  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3364 
3365 //ucTableFormatRevision=1
3366 //ucTableContentRevision=2
3367 typedef struct _ATOM_LVDS_INFO_V12
3368 {
3372  USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3376  UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3377  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3378  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3379  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3386  UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3389 
3390 //Definitions for ucLCDPanel_SpecialHandlingCap:
3391 
3392 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3393 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3394 #define LCDPANEL_CAP_READ_EDID 0x1
3395 
3396 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3397 //with multiple supported refresh [email protected] This cap should not be set when only slow refresh rate is supported (static
3398 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3399 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3400 
3401 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3402 #define LCDPANEL_CAP_eDP 0x4
3403 
3404 
3405 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3406 //Bit 6 5 4
3407  // 0 0 0 - Color bit depth is undefined
3408  // 0 0 1 - 6 Bits per Primary Color
3409  // 0 1 0 - 8 Bits per Primary Color
3410  // 0 1 1 - 10 Bits per Primary Color
3411  // 1 0 0 - 12 Bits per Primary Color
3412  // 1 0 1 - 14 Bits per Primary Color
3413  // 1 1 0 - 16 Bits per Primary Color
3414  // 1 1 1 - Reserved
3415 
3416 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3417 
3418 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3419 #define PANEL_RANDOM_DITHER 0x80
3420 #define PANEL_RANDOM_DITHER_MASK 0x80
3421 
3422 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3423 
3424 /****************************************************************************/
3425 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3426 // ASIC Families: NI
3427 // ucTableFormatRevision=1
3428 // ucTableContentRevision=3
3429 /****************************************************************************/
3430 typedef struct _ATOM_LCD_INFO_V13
3431 {
3435  USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3437  UCHAR ucLCD_Misc; // Reorganized in V13
3438  // Bit0: {=0:single, =1:dual},
3439  // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3440  // Bit3:2: {Grey level}
3441  // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3442  // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3448  UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3449  // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3450  // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3451  // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3452  // Bit7-3: Reserved
3453  UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3454  USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3455 
3460 
3465