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atombios.h File Reference

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Data Structures

struct  _ATOM_COMMON_TABLE_HEADER
 
struct  _ATOM_ROM_HEADER
 
struct  _ATOM_MASTER_LIST_OF_COMMAND_TABLES
 
struct  _ATOM_MASTER_COMMAND_TABLE
 
struct  _ATOM_TABLE_ATTRIBUTE
 
union  _ATOM_TABLE_ATTRIBUTE_ACCESS
 
struct  _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 
struct  _ATOM_ADJUST_MEMORY_CLOCK_FREQ
 
struct  _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 
struct  _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 
struct  _ATOM_COMPUTE_CLOCK_FREQ
 
struct  _ATOM_S_MPLL_FB_DIVIDER
 
struct  _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
 
struct  _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
 
struct  _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
 
struct  _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
 
struct  _DYNAMICE_MEMORY_SETTINGS_PARAMETER
 
struct  _DYNAMICE_ENGINE_SETTINGS_PARAMETER
 
struct  _SET_ENGINE_CLOCK_PARAMETERS
 
struct  _SET_ENGINE_CLOCK_PS_ALLOCATION
 
struct  _SET_MEMORY_CLOCK_PARAMETERS
 
struct  _SET_MEMORY_CLOCK_PS_ALLOCATION
 
struct  _ASIC_INIT_PARAMETERS
 
struct  _ASIC_INIT_PS_ALLOCATION
 
struct  _DYNAMIC_CLOCK_GATING_PARAMETERS
 
struct  _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
 
struct  _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 
struct  _DAC_LOAD_DETECTION_PARAMETERS
 
struct  _DAC_LOAD_DETECTION_PS_ALLOCATION
 
struct  _DAC_ENCODER_CONTROL_PARAMETERS
 
struct  _DIG_ENCODER_CONTROL_PARAMETERS
 
struct  _ATOM_DIG_ENCODER_CONFIG_V2
 
struct  _DIG_ENCODER_CONTROL_PARAMETERS_V2
 
struct  _ATOM_DIG_ENCODER_CONFIG_V3
 
struct  _DIG_ENCODER_CONTROL_PARAMETERS_V3
 
struct  _ATOM_DIG_ENCODER_CONFIG_V4
 
struct  _DIG_ENCODER_CONTROL_PARAMETERS_V4
 
struct  _ATOM_DP_VS_MODE
 
struct  _DIG_TRANSMITTER_CONTROL_PARAMETERS
 
struct  _ATOM_DIG_TRANSMITTER_CONFIG_V2
 
struct  _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
 
struct  _ATOM_DIG_TRANSMITTER_CONFIG_V3
 
struct  _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
 
struct  _ATOM_DP_VS_MODE_V4
 
struct  _ATOM_DIG_TRANSMITTER_CONFIG_V4
 
struct  _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
 
struct  _ATOM_DIG_TRANSMITTER_CONFIG_V5
 
struct  _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
 
struct  _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
 
struct  _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
 
struct  _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
struct  _BLANK_CRTC_PARAMETERS
 
struct  _ENABLE_CRTC_PARAMETERS
 
struct  _SET_CRTC_OVERSCAN_PARAMETERS
 
struct  _SET_CRTC_REPLICATION_PARAMETERS
 
struct  _SELECT_CRTC_SOURCE_PARAMETERS
 
struct  _SELECT_CRTC_SOURCE_PARAMETERS_V2
 
struct  _PIXEL_CLOCK_PARAMETERS
 
struct  _PIXEL_CLOCK_PARAMETERS_V2
 
struct  _PIXEL_CLOCK_PARAMETERS_V3
 
struct  _PIXEL_CLOCK_PARAMETERS_V5
 
struct  _CRTC_PIXEL_CLOCK_FREQ
 
struct  _PIXEL_CLOCK_PARAMETERS_V6
 
struct  _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
 
struct  _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
 
struct  _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
 
struct  _ADJUST_DISPLAY_PLL_PARAMETERS
 
struct  _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
 
struct  _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
 
struct  _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
 
struct  _ENABLE_YUV_PARAMETERS
 
struct  _GET_MEMORY_CLOCK_PARAMETERS
 
struct  _GET_ENGINE_CLOCK_PARAMETERS
 
struct  _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
 
struct  _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 
struct  _SET_UP_HW_I2C_DATA_PARAMETERS
 
struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
 
struct  POWER_CONNECTOR_DETECTION_PS_ALLOCATION
 
struct  _ENABLE_LVDS_SS_PARAMETERS
 
struct  _ENABLE_LVDS_SS_PARAMETERS_V2
 
struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
 
struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
 
struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
 
struct  _SET_PIXEL_CLOCK_PS_ALLOCATION
 
struct  _MEMORY_TRAINING_PARAMETERS
 
struct  _LVDS_ENCODER_CONTROL_PARAMETERS
 
struct  _LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
struct  _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
 
struct  _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
 
struct  _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
 
struct  _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
 
struct  _DVO_ENCODER_CONTROL_PARAMETERS_V3
 
struct  _SET_VOLTAGE_PARAMETERS
 
struct  _SET_VOLTAGE_PARAMETERS_V2
 
struct  _SET_VOLTAGE_PARAMETERS_V1_3
 
struct  _SET_VOLTAGE_PS_ALLOCATION
 
struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
 
struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
 
struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
 
struct  _TV_ENCODER_CONTROL_PARAMETERS
 
struct  _TV_ENCODER_CONTROL_PS_ALLOCATION
 
struct  _ATOM_MASTER_LIST_OF_DATA_TABLES
 
struct  _ATOM_MASTER_DATA_TABLE
 
struct  _ATOM_MULTIMEDIA_CAPABILITY_INFO
 
struct  _ATOM_MULTIMEDIA_CONFIG_INFO
 
struct  _ATOM_FIRMWARE_CAPABILITY
 
union  _ATOM_FIRMWARE_CAPABILITY_ACCESS
 
struct  _ATOM_FIRMWARE_INFO
 
struct  _ATOM_FIRMWARE_INFO_V1_2
 
struct  _ATOM_FIRMWARE_INFO_V1_3
 
struct  _ATOM_FIRMWARE_INFO_V1_4
 
struct  _ATOM_FIRMWARE_INFO_V2_1
 
struct  _ATOM_FIRMWARE_INFO_V2_2
 
struct  _ATOM_INTEGRATED_SYSTEM_INFO
 
struct  _ATOM_INTEGRATED_SYSTEM_INFO_V2
 
struct  _ATOM_INTEGRATED_SYSTEM_INFO_V5
 
struct  _ATOM_I2C_ID_CONFIG
 
union  _ATOM_I2C_ID_CONFIG_ACCESS
 
struct  _ATOM_GPIO_I2C_ASSIGMENT
 
struct  _ATOM_GPIO_I2C_INFO
 
struct  _ATOM_MODE_MISC_INFO
 
union  _ATOM_MODE_MISC_INFO_ACCESS
 
struct  _SET_CRTC_USING_DTD_TIMING_PARAMETERS
 
struct  _SET_CRTC_TIMING_PARAMETERS
 
struct  _ATOM_MODE_TIMING
 
struct  _ATOM_DTD_FORMAT
 
struct  _ATOM_LVDS_INFO
 
struct  _ATOM_LVDS_INFO_V12
 
struct  _ATOM_LCD_INFO_V13
 
struct  _ATOM_PATCH_RECORD_MODE
 
struct  _ATOM_LCD_RTS_RECORD
 
struct  _ATOM_LCD_MODE_CONTROL_CAP
 ! If the record below exits, it shoud always be the first record for easy use in command table!!! More...
 
struct  _ATOM_FAKE_EDID_PATCH_RECORD
 
struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
 
struct  _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
 
struct  _ATOM_SPREAD_SPECTRUM_INFO
 
struct  _ATOM_ANALOG_TV_INFO
 
struct  _ATOM_ANALOG_TV_INFO_V1_2
 
struct  _ATOM_DPCD_INFO
 
struct  _ATOM_FIRMWARE_VRAM_RESERVE_INFO
 
struct  _ATOM_VRAM_USAGE_BY_FIRMWARE
 
struct  _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
 
struct  _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
 
struct  _ATOM_GPIO_PIN_ASSIGNMENT
 
struct  _ATOM_GPIO_PIN_LUT
 
struct  _ATOM_GPIO_INFO
 
struct  _ATOM_COMPONENT_VIDEO_INFO
 
struct  _ATOM_COMPONENT_VIDEO_INFO_V21
 
struct  _ATOM_OBJECT_HEADER
 
struct  _ATOM_OBJECT_HEADER_V3
 
struct  _ATOM_DISPLAY_OBJECT_PATH
 
struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
 
struct  _ATOM_DISPLAY_OBJECT_PATH_TABLE
 
struct  _ATOM_OBJECT
 
struct  _ATOM_OBJECT_TABLE
 
struct  _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
 
struct  _ATOM_DP_CONN_CHANNEL_MAPPING
 
struct  _ATOM_DVI_CONN_CHANNEL_MAPPING
 
struct  _EXT_DISPLAY_PATH
 
struct  _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
 
struct  _ATOM_COMMON_RECORD_HEADER
 
struct  _ATOM_I2C_RECORD
 
struct  _ATOM_HPD_INT_RECORD
 
struct  _ATOM_OUTPUT_PROTECTION_RECORD
 
struct  _ATOM_CONNECTOR_DEVICE_TAG
 
struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
 
struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
 
struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
 
struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
 
struct  _ATOM_JTAG_RECORD
 
struct  _ATOM_GPIO_PIN_CONTROL_PAIR
 
struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
 
struct  _ATOM_ENCODER_DVO_CF_RECORD
 
struct  _ATOM_ENCODER_CAP_RECORD
 
struct  _ATOM_CONNECTOR_CF_RECORD
 
struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
 
struct  _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
 
struct  _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
 
struct  _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
 
struct  _ATOM_CONNECTOR_HPDPIN_LUT_RECORD
 
struct  _ATOM_CONNECTOR_AUXDDC_LUT_RECORD
 
struct  _ATOM_OBJECT_LINK_RECORD
 
struct  _ATOM_CONNECTOR_REMOTE_CAP_RECORD
 
struct  _ATOM_VOLTAGE_INFO_HEADER
 
struct  _ATOM_VOLTAGE_INFO
 
struct  _ATOM_VOLTAGE_FORMULA
 
struct  _VOLTAGE_LUT_ENTRY
 
struct  _ATOM_VOLTAGE_FORMULA_V2
 
struct  _ATOM_VOLTAGE_CONTROL
 
struct  _ATOM_VOLTAGE_OBJECT
 
struct  _ATOM_VOLTAGE_OBJECT_V2
 
struct  _ATOM_VOLTAGE_OBJECT_INFO
 
struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
 
struct  _ATOM_LEAKID_VOLTAGE
 
struct  _ATOM_VOLTAGE_OBJECT_HEADER_V3
 
struct  _VOLTAGE_LUT_ENTRY_V2
 
struct  _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
 
struct  _ATOM_I2C_VOLTAGE_OBJECT_V3
 
struct  _ATOM_GPIO_VOLTAGE_OBJECT_V3
 
struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
 
union  _ATOM_VOLTAGE_OBJECT_V3
 
struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
 
struct  _ATOM_ASIC_PROFILE_VOLTAGE
 
struct  _ATOM_ASIC_PROFILING_INFO
 
struct  _ATOM_POWER_SOURCE_OBJECT
 
struct  _ATOM_POWER_SOURCE_INFO
 
struct  _ATOM_CLK_VOLT_CAPABILITY
 
struct  _ATOM_AVAILABLE_SCLK_LIST
 
struct  _ATOM_INTEGRATED_SYSTEM_INFO_V6
 
struct  _ATOM_FUSION_SYSTEM_INFO_V1
 
struct  _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 
struct  _ATOM_I2C_DATA_RECORD
 
struct  _ATOM_I2C_DEVICE_SETUP_INFO
 
struct  _ATOM_ASIC_MVDD_INFO
 
struct  _ATOM_ASIC_SS_ASSIGNMENT
 
struct  _ATOM_ASIC_SS_ASSIGNMENT_V2
 
struct  _ATOM_ASIC_INTERNAL_SS_INFO
 
struct  _ATOM_ASIC_INTERNAL_SS_INFO_V2
 
struct  _ATOM_ASIC_SS_ASSIGNMENT_V3
 
struct  _ATOM_ASIC_INTERNAL_SS_INFO_V3
 
struct  _MEMORY_PLLINIT_PARAMETERS
 
struct  _GPIO_PIN_CONTROL_PARAMETERS
 
struct  _ENABLE_SCALER_PARAMETERS
 
struct  _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
 
struct  _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
 
struct  _ENABLE_GRAPH_SURFACE_PARAMETERS
 
struct  _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
 
struct  _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
 
struct  _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
 
struct  _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
 
struct  _MEMORY_CLEAN_UP_PARAMETERS
 
struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
 
struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
 
struct  _PALETTE_DATA_CONTROL_PARAMETERS_V3
 
struct  _INTERRUPT_SERVICE_PARAMETERS_V2
 
struct  _INDIRECT_IO_ACCESS
 
struct  _ATOM_OEM_INFO
 
struct  _ATOM_TV_MODE
 
struct  _ATOM_BIOS_INT_TVSTD_MODE
 
struct  _ATOM_TV_MODE_SCALER_PTR
 
struct  _ATOM_STANDARD_VESA_TIMING
 
struct  _ATOM_STD_FORMAT
 
struct  _ATOM_VESA_TO_EXTENDED_MODE
 
struct  _ATOM_VESA_TO_INTENAL_MODE_LUT
 
struct  _ATOM_MEMORY_VENDOR_BLOCK
 
struct  _ATOM_MEMORY_SETTING_ID_CONFIG
 
union  _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
 
struct  _ATOM_MEMORY_SETTING_DATA_BLOCK
 
struct  _ATOM_INIT_REG_INDEX_FORMAT
 
struct  _ATOM_INIT_REG_BLOCK
 
struct  _ATOM_MC_INIT_PARAM_TABLE
 
struct  _MCuCodeHeader
 
struct  _ATOM_VRAM_MODULE_V1
 
struct  _ATOM_VRAM_MODULE_V2
 
struct  _ATOM_MEMORY_TIMING_FORMAT
 
struct  _ATOM_MEMORY_TIMING_FORMAT_V1
 
struct  _ATOM_MEMORY_TIMING_FORMAT_V2
 
struct  _ATOM_MEMORY_FORMAT
 
struct  _ATOM_VRAM_MODULE_V3
 
struct  _ATOM_VRAM_MODULE_V4
 
struct  _ATOM_VRAM_MODULE_V5
 
struct  _ATOM_VRAM_MODULE_V6
 
struct  _ATOM_VRAM_MODULE_V7
 
struct  _ATOM_VRAM_INFO_V2
 
struct  _ATOM_VRAM_INFO_V3
 
struct  _ATOM_VRAM_INFO_V4
 
struct  _ATOM_VRAM_INFO_HEADER_V2_1
 
struct  _ATOM_VRAM_GPIO_DETECTION_INFO
 
struct  _ATOM_MEMORY_TRAINING_INFO
 
struct  SW_I2C_CNTL_DATA_PARAMETERS
 
struct  _SW_I2C_IO_DATA_PARAMETERS
 
struct  _PTR_32_BIT_STRUCTURE
 
union  _PTR_32_BIT_UNION
 
struct  _VBE_1_2_INFO_BLOCK_UPDATABLE
 
struct  _VBE_2_0_INFO_BLOCK_UPDATABLE
 
union  _VBE_VERSION_UNION
 
struct  _VBE_INFO_BLOCK
 
struct  _VBE_FP_INFO
 
struct  _VESA_MODE_INFO_BLOCK
 
struct  _ASIC_TRANSMITTER_INFO
 
struct  _ASIC_ENCODER_INFO
 
struct  _ATOM_DISP_OUT_INFO
 
struct  _ATOM_DISP_OUT_INFO_V2
 
struct  _ATOM_DISP_CLOCK_ID
 
struct  _ASIC_TRANSMITTER_INFO_V2
 
struct  _ATOM_DISP_OUT_INFO_V3
 
struct  _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
 
struct  _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
 
struct  _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
 
struct  _DP_ENCODER_SERVICE_PARAMETERS
 
struct  _DP_ENCODER_SERVICE_PARAMETERS_V2
 
struct  _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
 
struct  _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
 
struct  _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
 
struct  _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
 
struct  _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
 
struct  _SET_HWBLOCK_INSTANCE_PARAMETER_V2
 
struct  _DIG_TRANSMITTER_INFO_HEADER_V3_1
 
struct  _CLOCK_CONDITION_REGESTER_INFO
 
struct  _CLOCK_CONDITION_SETTING_ENTRY
 
struct  _CLOCK_CONDITION_SETTING_INFO
 
struct  _PHY_CONDITION_REG_VAL
 
struct  _PHY_CONDITION_REG_INFO
 
struct  _PHY_ANALOG_SETTING_INFO
 
struct  _ATOM_DAC_INFO
 
struct  _COMPASSIONATE_DATA
 
struct  _ATOM_CONNECTOR_INFO
 
union  _ATOM_CONNECTOR_INFO_ACCESS
 
struct  _ATOM_CONNECTOR_INFO_I2C
 
struct  _ATOM_SUPPORTED_DEVICES_INFO
 
struct  _ATOM_CONNECTOR_INC_SRC_BITMAP
 
struct  _ATOM_SUPPORTED_DEVICES_INFO_2
 
struct  _ATOM_SUPPORTED_DEVICES_INFO_2d1
 
struct  _ATOM_MISC_CONTROL_INFO
 
struct  _ATOM_TMDS_INFO
 
struct  _ATOM_ENCODER_ANALOG_ATTRIBUTE
 
struct  _ATOM_ENCODER_DIGITAL_ATTRIBUTE
 
union  _ATOM_ENCODER_ATTRIBUTE
 
struct  _DVO_ENCODER_CONTROL_PARAMETERS
 
struct  _DVO_ENCODER_CONTROL_PS_ALLOCATION
 
struct  _ATOM_XTMDS_INFO
 
struct  _DFP_DPMS_STATUS_CHANGE_PARAMETERS
 
struct  _ATOM_POWERMODE_INFO
 
struct  _ATOM_POWERMODE_INFO_V2
 
struct  _ATOM_POWERMODE_INFO_V3
 
struct  _ATOM_POWERPLAY_INFO
 
struct  _ATOM_POWERPLAY_INFO_V2
 
struct  _ATOM_POWERPLAY_INFO_V3
 
struct  _ATOM_PPLIB_THERMALCONTROLLER
 
struct  _ATOM_PPLIB_STATE
 
struct  _ATOM_PPLIB_FANTABLE
 
struct  _ATOM_PPLIB_FANTABLE2
 
struct  _ATOM_PPLIB_EXTENDEDHEADER
 
struct  _ATOM_PPLIB_POWERPLAYTABLE
 
struct  _ATOM_PPLIB_POWERPLAYTABLE2
 
struct  _ATOM_PPLIB_POWERPLAYTABLE3
 
struct  _ATOM_PPLIB_POWERPLAYTABLE4
 
struct  _ATOM_PPLIB_POWERPLAYTABLE5
 
struct  _ATOM_PPLIB_THERMAL_STATE
 
struct  _ATOM_PPLIB_NONCLOCK_INFO
 
struct  _ATOM_PPLIB_R600_CLOCK_INFO
 
struct  _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
 
struct  _ATOM_PPLIB_SI_CLOCK_INFO
 
struct  _ATOM_PPLIB_RS780_CLOCK_INFO
 
struct  _ATOM_PPLIB_SUMO_CLOCK_INFO
 
struct  _ATOM_PPLIB_STATE_V2
 
struct  _StateArray
 
struct  _ClockInfoArray
 
struct  _NonClockInfoArray
 
struct  _ATOM_PPLIB_Clock_Voltage_Dependency_Record
 
struct  _ATOM_PPLIB_Clock_Voltage_Dependency_Table
 
struct  _ATOM_PPLIB_Clock_Voltage_Limit_Record
 
struct  _ATOM_PPLIB_Clock_Voltage_Limit_Table
 
struct  _ATOM_PPLIB_CAC_Leakage_Record
 
struct  _ATOM_PPLIB_CAC_Leakage_Table
 
struct  _ATOM_PPLIB_PhaseSheddingLimits_Record
 
struct  _ATOM_PPLIB_PhaseSheddingLimits_Table
 
struct  _VCEClockInfo
 
struct  _VCEClockInfoArray
 
struct  _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
 
struct  _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
 
struct  _ATOM_PPLIB_VCE_State_Record
 
struct  _ATOM_PPLIB_VCE_State_Table
 
struct  _ATOM_PPLIB_VCE_Table
 
struct  _UVDClockInfo
 
struct  _UVDClockInfoArray
 
struct  _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
 
struct  _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
 
struct  _ATOM_PPLIB_UVD_State_Record
 
struct  _ATOM_PPLIB_UVD_State_Table
 
struct  _ATOM_PPLIB_UVD_Table
 
struct  AMD_ACPI_DESCRIPTION_HEADER
 
struct  UEFI_ACPI_VFCT
 
struct  VFCT_IMAGE_HEADER
 
struct  GOP_VBIOS_CONTENT
 
struct  GOP_LIB1_CONTENT
 

Macros

#define ATOM_VERSION_MAJOR   0x00020000
 
#define ATOM_VERSION_MINOR   0x00000002
 
#define ATOM_HEADER_VERSION   (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
 
#define ATOM_DAC_A   0
 
#define ATOM_DAC_B   1
 
#define ATOM_EXT_DAC   2
 
#define ATOM_CRTC1   0
 
#define ATOM_CRTC2   1
 
#define ATOM_CRTC3   2
 
#define ATOM_CRTC4   3
 
#define ATOM_CRTC5   4
 
#define ATOM_CRTC6   5
 
#define ATOM_CRTC_INVALID   0xFF
 
#define ATOM_DIGA   0
 
#define ATOM_DIGB   1
 
#define ATOM_PPLL1   0
 
#define ATOM_PPLL2   1
 
#define ATOM_DCPLL   2
 
#define ATOM_PPLL0   2
 
#define ATOM_EXT_PLL1   8
 
#define ATOM_EXT_PLL2   9
 
#define ATOM_EXT_CLOCK   10
 
#define ATOM_PPLL_INVALID   0xFF
 
#define ENCODER_REFCLK_SRC_P1PLL   0
 
#define ENCODER_REFCLK_SRC_P2PLL   1
 
#define ENCODER_REFCLK_SRC_DCPLL   2
 
#define ENCODER_REFCLK_SRC_EXTCLK   3
 
#define ENCODER_REFCLK_SRC_INVALID   0xFF
 
#define ATOM_SCALER1   0
 
#define ATOM_SCALER2   1
 
#define ATOM_SCALER_DISABLE   0
 
#define ATOM_SCALER_CENTER   1
 
#define ATOM_SCALER_EXPANSION   2
 
#define ATOM_SCALER_MULTI_EX   3
 
#define ATOM_DISABLE   0
 
#define ATOM_ENABLE   1
 
#define ATOM_LCD_BLOFF   (ATOM_DISABLE+2)
 
#define ATOM_LCD_BLON   (ATOM_ENABLE+2)
 
#define ATOM_LCD_BL_BRIGHTNESS_CONTROL   (ATOM_ENABLE+3)
 
#define ATOM_LCD_SELFTEST_START   (ATOM_DISABLE+5)
 
#define ATOM_LCD_SELFTEST_STOP   (ATOM_ENABLE+5)
 
#define ATOM_ENCODER_INIT   (ATOM_DISABLE+7)
 
#define ATOM_INIT   (ATOM_DISABLE+7)
 
#define ATOM_GET_STATUS   (ATOM_DISABLE+8)
 
#define ATOM_BLANKING   1
 
#define ATOM_BLANKING_OFF   0
 
#define ATOM_CURSOR1   0
 
#define ATOM_CURSOR2   1
 
#define ATOM_ICON1   0
 
#define ATOM_ICON2   1
 
#define ATOM_CRT1   0
 
#define ATOM_CRT2   1
 
#define ATOM_TV_NTSC   1
 
#define ATOM_TV_NTSCJ   2
 
#define ATOM_TV_PAL   3
 
#define ATOM_TV_PALM   4
 
#define ATOM_TV_PALCN   5
 
#define ATOM_TV_PALN   6
 
#define ATOM_TV_PAL60   7
 
#define ATOM_TV_SECAM   8
 
#define ATOM_TV_CV   16
 
#define ATOM_DAC1_PS2   1
 
#define ATOM_DAC1_CV   2
 
#define ATOM_DAC1_NTSC   3
 
#define ATOM_DAC1_PAL   4
 
#define ATOM_DAC2_PS2   ATOM_DAC1_PS2
 
#define ATOM_DAC2_CV   ATOM_DAC1_CV
 
#define ATOM_DAC2_NTSC   ATOM_DAC1_NTSC
 
#define ATOM_DAC2_PAL   ATOM_DAC1_PAL
 
#define ATOM_PM_ON   0
 
#define ATOM_PM_STANDBY   1
 
#define ATOM_PM_SUSPEND   2
 
#define ATOM_PM_OFF   3
 
#define ATOM_PANEL_MISC_DUAL   0x00000001
 
#define ATOM_PANEL_MISC_888RGB   0x00000002
 
#define ATOM_PANEL_MISC_GREY_LEVEL   0x0000000C
 
#define ATOM_PANEL_MISC_FPDI   0x00000010
 
#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
 
#define ATOM_PANEL_MISC_SPATIAL   0x00000020
 
#define ATOM_PANEL_MISC_TEMPORAL   0x00000040
 
#define ATOM_PANEL_MISC_API_ENABLED   0x00000080
 
#define MEMTYPE_DDR1   "DDR1"
 
#define MEMTYPE_DDR2   "DDR2"
 
#define MEMTYPE_DDR3   "DDR3"
 
#define MEMTYPE_DDR4   "DDR4"
 
#define ASIC_BUS_TYPE_PCI   "PCI"
 
#define ASIC_BUS_TYPE_AGP   "AGP"
 
#define ASIC_BUS_TYPE_PCIE   "PCI_EXPRESS"
 
#define ATOM_FIREGL_FLAG_STRING   "FGL"
 
#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING   3
 
#define ATOM_FAKE_DESKTOP_STRING   "DSK"
 
#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING   ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
 
#define ATOM_M54T_FLAG_STRING   "M54T"
 
#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING   4
 
#define HW_ASSISTED_I2C_STATUS_FAILURE   2
 
#define HW_ASSISTED_I2C_STATUS_SUCCESS   1
 
#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER   0x00000048L
 
#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE   0x00000002L
 
#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE   0x94
 
#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20 /* including the terminator 0x0! */
 
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER   0x002f
 
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START   0x006e
 
#define ReadEDIDFromHWAssistedI2C   ProcessI2cChannelTransaction
 
#define DPTranslatorControl   DIG2EncoderControl
 
#define UNIPHYTransmitterControl   DIG1TransmitterControl
 
#define LVTMATransmitterControl   DIG2TransmitterControl
 
#define SetCRTC_DPM_State   GetConditionalGoldenSetting
 
#define SetUniphyInstance   ASIC_StaticPwrMgtStatusChange
 
#define HPDInterruptService   ReadHWAssistedI2CStatus
 
#define EnableVGA_Access   GetSCLKOverMCLKRatio
 
#define EnableYUV   GetDispObjectInfo
 
#define DynamicClockGating   EnableDispPowerGating
 
#define SetupHWAssistedI2CStatus   ComputeMemoryClockParam
 
#define TMDSAEncoderControl   PatchMCSetting
 
#define LVDSEncoderControl   MC_SEQ_Control
 
#define LCD1OutputControl   HW_Misc_Operation
 
#define COMPUTE_MEMORY_PLL_PARAM   1
 
#define COMPUTE_ENGINE_PLL_PARAM   2
 
#define ADJUST_MC_SETTING_PARAM   3
 
#define POINTER_RETURN_FLAG   0x80
 
#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 
#define SET_CLOCK_FREQ_MASK   0x00FFFFFF
 
#define USE_NON_BUS_CLOCK_MASK   0x01000000
 
#define USE_MEMORY_SELF_REFRESH_MASK   0x02000000
 
#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000
 
#define FIRST_TIME_CHANGE_CLOCK   0x08000000
 
#define SKIP_SW_PROGRAM_PLL   0x10000000
 
#define USE_SS_ENABLED_PIXEL_CLOCK   USE_NON_BUS_CLOCK_MASK
 
#define b3USE_NON_BUS_CLOCK_MASK   0x01
 
#define b3USE_MEMORY_SELF_REFRESH   0x02
 
#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04
 
#define b3FIRST_TIME_CHANGE_CLOCK   0x08
 
#define b3SKIP_SW_PROGRAM_PLL   0x10
 
#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN   1
 
#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE   2
 
#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE   4
 
#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9   8
 
#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN   1
 
#define MPLL_INPUT_FLAG_STROBE_MODE_EN   0x01
 
#define MPLL_CNTL_FLAG_VCO_MODE_MASK   0x03
 
#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL   0x04
 
#define MPLL_CNTL_FLAG_QDR_ENABLE   0x08
 
#define MPLL_CNTL_FLAG_AD_HALF_RATE   0x10
 
#define MPLL_CNTL_FLAG_BYPASS_AD_PLL   0x04
 
#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION   DYNAMIC_CLOCK_GATING_PARAMETERS
 
#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION   ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 
#define DAC_LOAD_MISC_YPrPb   0x01
 
#define DAC_ENCODER_CONTROL_PS_ALLOCATION   DAC_ENCODER_CONTROL_PARAMETERS
 
#define DIG_ENCODER_CONTROL_PS_ALLOCATION   DIG_ENCODER_CONTROL_PARAMETERS
 
#define EXTERNAL_ENCODER_CONTROL_PARAMETER   DIG_ENCODER_CONTROL_PARAMETERS
 
#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK   0x01
 
#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ   0x00
 
#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ   0x01
 
#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ   0x02
 
#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK   0x04
 
#define ATOM_ENCODER_CONFIG_LINKA   0x00
 
#define ATOM_ENCODER_CONFIG_LINKB   0x04
 
#define ATOM_ENCODER_CONFIG_LINKA_B   ATOM_TRANSMITTER_CONFIG_LINKA
 
#define ATOM_ENCODER_CONFIG_LINKB_A   ATOM_ENCODER_CONFIG_LINKB
 
#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK   0x08
 
#define ATOM_ENCODER_CONFIG_UNIPHY   0x00
 
#define ATOM_ENCODER_CONFIG_LVTMA   0x08
 
#define ATOM_ENCODER_CONFIG_TRANSMITTER1   0x00
 
#define ATOM_ENCODER_CONFIG_TRANSMITTER2   0x08
 
#define ATOM_ENCODER_CONFIG_DIGB   0x80
 
#define ATOM_ENCODER_MODE_DP   0
 
#define ATOM_ENCODER_MODE_LVDS   1
 
#define ATOM_ENCODER_MODE_DVI   2
 
#define ATOM_ENCODER_MODE_HDMI   3
 
#define ATOM_ENCODER_MODE_SDVO   4
 
#define ATOM_ENCODER_MODE_DP_AUDIO   5
 
#define ATOM_ENCODER_MODE_TV   13
 
#define ATOM_ENCODER_MODE_CV   14
 
#define ATOM_ENCODER_MODE_CRT   15
 
#define ATOM_ENCODER_MODE_DVO   16
 
#define ATOM_ENCODER_MODE_DP_SST   ATOM_ENCODER_MODE_DP
 
#define ATOM_ENCODER_MODE_DP_MST   5
 
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK   0x01
 
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ   0x00
 
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ   0x01
 
#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK   0x04
 
#define ATOM_ENCODER_CONFIG_V2_LINKA   0x00
 
#define ATOM_ENCODER_CONFIG_V2_LINKB   0x04
 
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK   0x18
 
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1   0x00
 
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2   0x08
 
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3   0x10
 
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START   0x08
 
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1   0x09
 
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2   0x0a
 
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3   0x13
 
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE   0x0b
 
#define ATOM_ENCODER_CMD_DP_VIDEO_OFF   0x0c
 
#define ATOM_ENCODER_CMD_DP_VIDEO_ON   0x0d
 
#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS   0x0e
 
#define ATOM_ENCODER_CMD_SETUP   0x0f
 
#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE   0x10
 
#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE   0x10
 
#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE   0x00
 
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK   0x03
 
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ   0x00
 
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ   0x01
 
#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL   0x70
 
#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER   0x00
 
#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER   0x10
 
#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER   0x20
 
#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER   0x30
 
#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER   0x40
 
#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER   0x50
 
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK   0x03
 
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ   0x00
 
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ   0x01
 
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ   0x02
 
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ   0x03
 
#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL   0x70
 
#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER   0x00
 
#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER   0x10
 
#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER   0x20
 
#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER   0x30
 
#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER   0x40
 
#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER   0x50
 
#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER   0x60
 
#define PANEL_BPC_UNDEFINE   0x00
 
#define PANEL_6BIT_PER_COLOR   0x01
 
#define PANEL_8BIT_PER_COLOR   0x02
 
#define PANEL_10BIT_PER_COLOR   0x03
 
#define PANEL_12BIT_PER_COLOR   0x04
 
#define PANEL_16BIT_PER_COLOR   0x05
 
#define DP_PANEL_MODE_EXTERNAL_DP_MODE   0x00
 
#define DP_PANEL_MODE_INTERNAL_DP2_MODE   0x01
 
#define DP_PANEL_MODE_INTERNAL_DP1_MODE   0x11
 
#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PARAMETERS
 
#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK   0x00ff
 
#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK   0x01
 
#define ATOM_TRANSMITTER_CONFIG_COHERENT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK   0x04
 
#define ATOM_TRANSMITTER_CONFIG_LINKA   0x00
 
#define ATOM_TRANSMITTER_CONFIG_LINKB   0x04
 
#define ATOM_TRANSMITTER_CONFIG_LINKA_B   0x00
 
#define ATOM_TRANSMITTER_CONFIG_LINKB_A   0x04
 
#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK   0x08
 
#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER   0x00
 
#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER   0x08
 
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK   0x30
 
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL   0x00
 
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE   0x20
 
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN   0x30
 
#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK   0xc0
 
#define ATOM_TRANSMITTER_CONFIG_LANE_0_3   0x00
 
#define ATOM_TRANSMITTER_CONFIG_LANE_0_7   0x00
 
#define ATOM_TRANSMITTER_CONFIG_LANE_4_7   0x40
 
#define ATOM_TRANSMITTER_CONFIG_LANE_8_11   0x80
 
#define ATOM_TRANSMITTER_CONFIG_LANE_8_15   0x80
 
#define ATOM_TRANSMITTER_CONFIG_LANE_12_15   0xc0
 
#define ATOM_TRANSMITTER_ACTION_DISABLE   0
 
#define ATOM_TRANSMITTER_ACTION_ENABLE   1
 
#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF   2
 
#define ATOM_TRANSMITTER_ACTION_LCD_BLON   3
 
#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL   4
 
#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START   5
 
#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP   6
 
#define ATOM_TRANSMITTER_ACTION_INIT   7
 
#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT   8
 
#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT   9
 
#define ATOM_TRANSMITTER_ACTION_SETUP   10
 
#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH   11
 
#define ATOM_TRANSMITTER_ACTION_POWER_ON   12
 
#define ATOM_TRANSMITTER_ACTION_POWER_OFF   13
 
#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR   0x01
 
#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V2_LINKA   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V2_LINKB   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK   0x08
 
#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER   0x08
 
#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR   0x10
 
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK   0xC0
 
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2   0x40
 
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3   0x80
 
#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR   0x01
 
#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V3_LINKA   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V3_LINKB   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK   0x08
 
#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER   0x08
 
#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK   0x30
 
#define ATOM_TRASMITTER_CONFIG_V3_P1PLL   0x00
 
#define ATOM_TRASMITTER_CONFIG_V3_P2PLL   0x10
 
#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT   0x20
 
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK   0xC0
 
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2   0x40
 
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3   0x80
 
#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR   0x01
 
#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V4_LINKA   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V4_LINKB   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK   0x08
 
#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER   0x08
 
#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK   0x30
 
#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL   0x10
 
#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL   0x20
 
#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT   0x30
 
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK   0xC0
 
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2   0x40
 
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3   0x80
 
#define ATOM_PHY_ID_UNIPHYA   0
 
#define ATOM_PHY_ID_UNIPHYB   1
 
#define ATOM_PHY_ID_UNIPHYC   2
 
#define ATOM_PHY_ID_UNIPHYD   3
 
#define ATOM_PHY_ID_UNIPHYE   4
 
#define ATOM_PHY_ID_UNIPHYF   5
 
#define ATOM_PHY_ID_UNIPHYG   6
 
#define ATOM_TRANMSITTER_V5__DIGA_SEL   0x01
 
#define ATOM_TRANMSITTER_V5__DIGB_SEL   0x02
 
#define ATOM_TRANMSITTER_V5__DIGC_SEL   0x04
 
#define ATOM_TRANMSITTER_V5__DIGD_SEL   0x08
 
#define ATOM_TRANMSITTER_V5__DIGE_SEL   0x10
 
#define ATOM_TRANMSITTER_V5__DIGF_SEL   0x20
 
#define ATOM_TRANMSITTER_V5__DIGG_SEL   0x40
 
#define ATOM_TRANSMITTER_DIGMODE_V5_DP   0
 
#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS   1
 
#define ATOM_TRANSMITTER_DIGMODE_V5_DVI   2
 
#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI   3
 
#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO   4
 
#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST   5
 
#define DP_LANE_SET__0DB_0_4V   0x00
 
#define DP_LANE_SET__0DB_0_6V   0x01
 
#define DP_LANE_SET__0DB_0_8V   0x02
 
#define DP_LANE_SET__0DB_1_2V   0x03
 
#define DP_LANE_SET__3_5DB_0_4V   0x08
 
#define DP_LANE_SET__3_5DB_0_6V   0x09
 
#define DP_LANE_SET__3_5DB_0_8V   0x0a
 
#define DP_LANE_SET__6DB_0_4V   0x10
 
#define DP_LANE_SET__6DB_0_6V   0x11
 
#define DP_LANE_SET__9_5DB_0_4V   0x18
 
#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK   0x0c
 
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT   0x02
 
#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL   0x08
 
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT   0x0c
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK   0x70
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT   0x04
 
#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL   0x00
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL   0x10
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL   0x20
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL   0x30
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL   0x40
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL   0x50
 
#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL   0x60
 
#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5   DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
 
#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT   0x00
 
#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT   0x01
 
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT   0x07
 
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP   0x0f
 
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
 
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING   0x11
 
#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION   0x12
 
#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP   0x14
 
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK   0x03
 
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ   0x00
 
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ   0x01
 
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ   0x02
 
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK   0x70
 
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1   0x00
 
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2   0x10
 
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3   0x20
 
#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define CRT1_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define CRT2_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define CV1_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define TV1_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define DFP1_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define DFP2_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define LCD1_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
 
#define DVO_OUTPUT_CONTROL_PARAMETERS   DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
 
#define DVO_OUTPUT_CONTROL_PARAMETERS_V3   DIG_TRANSMITTER_CONTROL_PARAMETERS
 
#define BLANK_CRTC_PS_ALLOCATION   BLANK_CRTC_PARAMETERS
 
#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
 
#define SET_CRTC_OVERSCAN_PS_ALLOCATION   SET_CRTC_OVERSCAN_PARAMETERS
 
#define SET_CRTC_REPLICATION_PS_ALLOCATION   SET_CRTC_REPLICATION_PARAMETERS
 
#define SELECT_CRTC_SOURCE_PS_ALLOCATION   SELECT_CRTC_SOURCE_PARAMETERS
 
#define MISC_FORCE_REPROG_PIXEL_CLOCK   0x1
 
#define MISC_DEVICE_INDEX_MASK   0xF0
 
#define MISC_DEVICE_INDEX_SHIFT   4
 
#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL   0x01
 
#define PIXEL_CLOCK_MISC_VGA_MODE   0x02
 
#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK   0x04
 
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1   0x00
 
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2   0x04
 
#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK   0x08
 
#define PIXEL_CLOCK_MISC_REF_DIV_SRC   0x10
 
#define PIXEL_CLOCK_V4_MISC_SS_ENABLE   0x10
 
#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE   0x20
 
#define PIXEL_CLOCK_PARAMETERS_LAST   PIXEL_CLOCK_PARAMETERS_V2
 
#define GET_PIXEL_CLOCK_PS_ALLOCATION   PIXEL_CLOCK_PARAMETERS_LAST
 
#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL   0x01
 
#define PIXEL_CLOCK_V5_MISC_VGA_MODE   0x02
 
#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK   0x0c
 
#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP   0x00
 
#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP   0x04
 
#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP   0x08
 
#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC   0x10
 
#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL   0x01
 
#define PIXEL_CLOCK_V6_MISC_VGA_MODE   0x02
 
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK   0x0c
 
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP   0x00
 
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP   0x04
 
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP   0x08
 
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP   0x0c
 
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC   0x10
 
#define ADJUST_DISPLAY_CONFIG_SS_ENABLE   0x10
 
#define ADJUST_DISPLAY_PLL_PS_ALLOCATION   ADJUST_DISPLAY_PLL_PARAMETERS
 
#define DISPPLL_CONFIG_DVO_RATE_SEL   0x0001
 
#define DISPPLL_CONFIG_DVO_DDR_SPEED   0x0000
 
#define DISPPLL_CONFIG_DVO_SDR_SPEED   0x0001
 
#define DISPPLL_CONFIG_DVO_OUTPUT_SEL   0x000c
 
#define DISPPLL_CONFIG_DVO_LOW12BIT   0x0000
 
#define DISPPLL_CONFIG_DVO_UPPER12BIT   0x0004
 
#define DISPPLL_CONFIG_DVO_24BIT   0x0008
 
#define DISPPLL_CONFIG_SS_ENABLE   0x0010
 
#define DISPPLL_CONFIG_COHERENT_MODE   0x0020
 
#define DISPPLL_CONFIG_DUAL_LINK   0x0040
 
#define ENABLE_YUV_PS_ALLOCATION   ENABLE_YUV_PARAMETERS
 
#define GET_MEMORY_CLOCK_PS_ALLOCATION   GET_MEMORY_CLOCK_PARAMETERS
 
#define GET_ENGINE_CLOCK_PS_ALLOCATION   GET_ENGINE_CLOCK_PARAMETERS
 
#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION   READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
 
#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE   0
 
#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES   1
 
#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK   2
 
#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK   3
 
#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK   4
 
#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 
#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 
#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD   0x00
 
#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD   0x01
 
#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD   0x02
 
#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK   0x0c
 
#define ATOM_PPLL_SS_TYPE_V2_P1PLL   0x00
 
#define ATOM_PPLL_SS_TYPE_V2_P2PLL   0x04
 
#define ATOM_PPLL_SS_TYPE_V2_DCPLL   0x08
 
#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK   0x00FF
 
#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT   0
 
#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK   0x0F00
 
#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT   8
 
#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD   0x00
 
#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD   0x01
 
#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD   0x02
 
#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK   0x0c
 
#define ATOM_PPLL_SS_TYPE_V3_P1PLL   0x00
 
#define ATOM_PPLL_SS_TYPE_V3_P2PLL   0x04
 
#define ATOM_PPLL_SS_TYPE_V3_DCPLL   0x08
 
#define ATOM_PPLL_SS_TYPE_V3_P0PLL   ATOM_PPLL_SS_TYPE_V3_DCPLL
 
#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK   0x00FF
 
#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT   0
 
#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK   0x0F00
 
#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT   8
 
#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION   ENABLE_SPREAD_SPECTRUM_ON_PPLL
 
#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
 
#define MEMORY_TRAINING_PS_ALLOCATION   MEMORY_TRAINING_PARAMETERS
 
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION   LVDS_ENCODER_CONTROL_PARAMETERS
 
#define TMDS1_ENCODER_CONTROL_PARAMETERS   LVDS_ENCODER_CONTROL_PARAMETERS
 
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION   TMDS1_ENCODER_CONTROL_PARAMETERS
 
#define TMDS2_ENCODER_CONTROL_PARAMETERS   TMDS1_ENCODER_CONTROL_PARAMETERS
 
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION   TMDS2_ENCODER_CONTROL_PARAMETERS
 
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2   LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2   LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2   TMDS1_ENCODER_CONTROL_PARAMETERS_V2
 
#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2   TMDS1_ENCODER_CONTROL_PARAMETERS_V2
 
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2   TMDS2_ENCODER_CONTROL_PARAMETERS_V2
 
#define LVDS_ENCODER_CONTROL_PARAMETERS_V3   LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3   TMDS1_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3   TMDS2_ENCODER_CONTROL_PARAMETERS_V3
 
#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2   LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
#define DVO_ENCODER_CONFIG_RATE_SEL   0x01
 
#define DVO_ENCODER_CONFIG_DDR_SPEED   0x00
 
#define DVO_ENCODER_CONFIG_SDR_SPEED   0x01
 
#define DVO_ENCODER_CONFIG_OUTPUT_SEL   0x0c
 
#define DVO_ENCODER_CONFIG_LOW12BIT   0x00
 
#define DVO_ENCODER_CONFIG_UPPER12BIT   0x04
 
#define DVO_ENCODER_CONFIG_24BIT   0x08
 
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3   DVO_ENCODER_CONTROL_PARAMETERS_V3
 
#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST   LVDS_ENCODER_CONTROL_PARAMETERS_LAST
 
#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST   TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
 
#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST   LVDS_ENCODER_CONTROL_PARAMETERS_V3
 
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST   TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
 
#define DVO_ENCODER_CONTROL_PARAMETERS_LAST   DVO_ENCODER_CONTROL_PARAMETERS
 
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
 
#define PANEL_ENCODER_MISC_DUAL   0x01
 
#define PANEL_ENCODER_MISC_COHERENT   0x02
 
#define PANEL_ENCODER_MISC_TMDS_LINKB   0x04
 
#define PANEL_ENCODER_MISC_HDMI_TYPE   0x08
 
#define PANEL_ENCODER_ACTION_DISABLE   ATOM_DISABLE
 
#define PANEL_ENCODER_ACTION_ENABLE   ATOM_ENABLE
 
#define PANEL_ENCODER_ACTION_COHERENTSEQ   (ATOM_ENABLE+1)
 
#define PANEL_ENCODER_TRUNCATE_EN   0x01
 
#define PANEL_ENCODER_TRUNCATE_DEPTH   0x10
 
#define PANEL_ENCODER_SPATIAL_DITHER_EN   0x01
 
#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH   0x10
 
#define PANEL_ENCODER_TEMPORAL_DITHER_EN   0x01
 
#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH   0x10
 
#define PANEL_ENCODER_TEMPORAL_LEVEL_4   0x20
 
#define PANEL_ENCODER_25FRC_MASK   0x10
 
#define PANEL_ENCODER_25FRC_E   0x00
 
#define PANEL_ENCODER_25FRC_F   0x10
 
#define PANEL_ENCODER_50FRC_MASK   0x60
 
#define PANEL_ENCODER_50FRC_A   0x00
 
#define PANEL_ENCODER_50FRC_B   0x20
 
#define PANEL_ENCODER_50FRC_C   0x40
 
#define PANEL_ENCODER_50FRC_D   0x60
 
#define PANEL_ENCODER_75FRC_MASK   0x80
 
#define PANEL_ENCODER_75FRC_E   0x00
 
#define PANEL_ENCODER_75FRC_F   0x80
 
#define SET_VOLTAGE_TYPE_ASIC_VDDC   1
 
#define SET_VOLTAGE_TYPE_ASIC_MVDDC   2
 
#define SET_VOLTAGE_TYPE_ASIC_MVDDQ   3
 
#define SET_VOLTAGE_TYPE_ASIC_VDDCI   4
 
#define SET_VOLTAGE_INIT_MODE   5
 
#define SET_VOLTAGE_GET_MAX_VOLTAGE   6
 
#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE   0x1
 
#define SET_ASIC_VOLTAGE_MODE_SOURCE_A   0x2
 
#define SET_ASIC_VOLTAGE_MODE_SOURCE_B   0x4
 
#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE   0x0
 
#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL   0x1
 
#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK   0x2
 
#define VOLTAGE_TYPE_VDDC   1
 
#define VOLTAGE_TYPE_MVDDC   2
 
#define VOLTAGE_TYPE_MVDDQ   3
 
#define VOLTAGE_TYPE_VDDCI   4
 
#define ATOM_SET_VOLTAGE   0
 
#define ATOM_INIT_VOLTAGE_REGULATOR   3
 
#define ATOM_SET_VOLTAGE_PHASE   4
 
#define ATOM_GET_MAX_VOLTAGE   6
 
#define ATOM_GET_VOLTAGE_LEVEL   6
 
#define ATOM_VIRTUAL_VOLTAGE_ID0   0xff01
 
#define ATOM_VIRTUAL_VOLTAGE_ID1   0xff02
 
#define ATOM_VIRTUAL_VOLTAGE_ID2   0xff03
 
#define ATOM_VIRTUAL_VOLTAGE_ID3   0xff04
 
#define ATOM_GET_VOLTAGE_VID   0x00
 
#define ATOM_GET_VOTLAGE_INIT_SEQ   0x03
 
#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
 
#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID   0x10
 
#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID   0x11
 
#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID   0x12
 
#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID   0x13
 
#define LVDS_Info   LCD_Info
 
#define DAC_Info   PaletteData
 
#define TMDS_Info   DIGTransmitterInfo
 
#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED   0x0001
 
#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT   0x0002
 
#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT   0x0004
 
#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT   0x0008
 
#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT   0x0010
 
#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU   0x0020
 
#define ATOM_BIOS_INFO_WMI_SUPPORT   0x0040
 
#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
 
#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT   0x0100
 
#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK   0x1E00
 
#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET   0x2000
 
#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE   0x4000
 
#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT   0x0008
 
#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT   0x0010
 
#define ATOM_FIRMWARE_INFO_LAST   ATOM_FIRMWARE_INFO_V2_2
 
#define REMOTE_DISPLAY_DISABLE   0x00
 
#define REMOTE_DISPLAY_ENABLE   0x01
 
#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN   0x2
 
#define IGP_CAP_FLAG_AC_CARD   0x4
 
#define IGP_CAP_FLAG_SDVO_CARD   0x8
 
#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE   0x10
 
#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU   0
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN   1
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND   2
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8   3
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH   4
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI   5
 
#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE   INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI
 
#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE   0x00000001
 
#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE   0x00000002
 
#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE   0x00000004
 
#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY   0x00000008
 
#define SYSTEM_CONFIG_CLMC_ENABLED   0x00000010
 
#define SYSTEM_CONFIG_CDLW_ENABLED   0x00000020
 
#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED   0x00000040
 
#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED   0x00000080
 
#define SYSTEM_CONFIG_CDLF_ENABLED   0x00000100
 
#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED   0x00000200
 
#define IGP_DDI_SLOT_LANE_CONFIG_MASK   0x000000FF
 
#define b0IGP_DDI_SLOT_LANE_MAP_MASK   0x0F
 
#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK   0xF0
 
#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3   0x01
 
#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7   0x02
 
#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11   0x04
 
#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15   0x08
 
#define IGP_DDI_SLOT_ATTRIBUTE_MASK   0x0000FF00
 
#define IGP_DDI_SLOT_CONFIG_REVERSED   0x00000100
 
#define b1IGP_DDI_SLOT_CONFIG_REVERSED   0x01
 
#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK   0x00FF0000
 
#define ATOM_CRT_INT_ENCODER1_INDEX   0x00000000
 
#define ATOM_LCD_INT_ENCODER1_INDEX   0x00000001
 
#define ATOM_TV_INT_ENCODER1_INDEX   0x00000002
 
#define ATOM_DFP_INT_ENCODER1_INDEX   0x00000003
 
#define ATOM_CRT_INT_ENCODER2_INDEX   0x00000004
 
#define ATOM_LCD_EXT_ENCODER1_INDEX   0x00000005
 
#define ATOM_TV_EXT_ENCODER1_INDEX   0x00000006
 
#define ATOM_DFP_EXT_ENCODER1_INDEX   0x00000007
 
#define ATOM_CV_INT_ENCODER1_INDEX   0x00000008
 
#define ATOM_DFP_INT_ENCODER2_INDEX   0x00000009
 
#define ATOM_CRT_EXT_ENCODER1_INDEX   0x0000000A
 
#define ATOM_CV_EXT_ENCODER1_INDEX   0x0000000B
 
#define ATOM_DFP_INT_ENCODER3_INDEX   0x0000000C
 
#define ATOM_DFP_INT_ENCODER4_INDEX   0x0000000D
 
#define ASIC_INT_DAC1_ENCODER_ID   0x00
 
#define ASIC_INT_TV_ENCODER_ID   0x02
 
#define ASIC_INT_DIG1_ENCODER_ID   0x03
 
#define ASIC_INT_DAC2_ENCODER_ID   0x04
 
#define ASIC_EXT_TV_ENCODER_ID   0x06
 
#define ASIC_INT_DVO_ENCODER_ID   0x07
 
#define ASIC_INT_DIG2_ENCODER_ID   0x09
 
#define ASIC_EXT_DIG_ENCODER_ID   0x05
 
#define ASIC_EXT_DIG2_ENCODER_ID   0x08
 
#define ASIC_INT_DIG3_ENCODER_ID   0x0a
 
#define ASIC_INT_DIG4_ENCODER_ID   0x0b
 
#define ASIC_INT_DIG5_ENCODER_ID   0x0c
 
#define ASIC_INT_DIG6_ENCODER_ID   0x0d
 
#define ASIC_INT_DIG7_ENCODER_ID   0x0e
 
#define ATOM_ANALOG_ENCODER   0
 
#define ATOM_DIGITAL_ENCODER   1
 
#define ATOM_DP_ENCODER   2
 
#define ATOM_ENCODER_ENUM_MASK   0x70
 
#define ATOM_ENCODER_ENUM_ID1   0x00
 
#define ATOM_ENCODER_ENUM_ID2   0x10
 
#define ATOM_ENCODER_ENUM_ID3   0x20
 
#define ATOM_ENCODER_ENUM_ID4   0x30
 
#define ATOM_ENCODER_ENUM_ID5   0x40
 
#define ATOM_ENCODER_ENUM_ID6   0x50
 
#define ATOM_DEVICE_CRT1_INDEX   0x00000000
 
#define ATOM_DEVICE_LCD1_INDEX   0x00000001
 
#define ATOM_DEVICE_TV1_INDEX   0x00000002
 
#define ATOM_DEVICE_DFP1_INDEX   0x00000003
 
#define ATOM_DEVICE_CRT2_INDEX   0x00000004
 
#define ATOM_DEVICE_LCD2_INDEX   0x00000005
 
#define ATOM_DEVICE_DFP6_INDEX   0x00000006
 
#define ATOM_DEVICE_DFP2_INDEX   0x00000007
 
#define ATOM_DEVICE_CV_INDEX   0x00000008
 
#define ATOM_DEVICE_DFP3_INDEX   0x00000009
 
#define ATOM_DEVICE_DFP4_INDEX   0x0000000A
 
#define ATOM_DEVICE_DFP5_INDEX   0x0000000B
 
#define ATOM_DEVICE_RESERVEDC_INDEX   0x0000000C
 
#define ATOM_DEVICE_RESERVEDD_INDEX   0x0000000D
 
#define ATOM_DEVICE_RESERVEDE_INDEX   0x0000000E
 
#define ATOM_DEVICE_RESERVEDF_INDEX   0x0000000F
 
#define ATOM_MAX_SUPPORTED_DEVICE_INFO   (ATOM_DEVICE_DFP3_INDEX+1)
 
#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2   ATOM_MAX_SUPPORTED_DEVICE_INFO
 
#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3   (ATOM_DEVICE_DFP5_INDEX + 1 )
 
#define ATOM_MAX_SUPPORTED_DEVICE   (ATOM_DEVICE_RESERVEDF_INDEX+1)
 
#define ATOM_DEVICE_CRT1_SUPPORT   (0x1L << ATOM_DEVICE_CRT1_INDEX )
 
#define ATOM_DEVICE_LCD1_SUPPORT   (0x1L << ATOM_DEVICE_LCD1_INDEX )
 
#define ATOM_DEVICE_TV1_SUPPORT   (0x1L << ATOM_DEVICE_TV1_INDEX )
 
#define ATOM_DEVICE_DFP1_SUPPORT   (0x1L << ATOM_DEVICE_DFP1_INDEX )
 
#define ATOM_DEVICE_CRT2_SUPPORT   (0x1L << ATOM_DEVICE_CRT2_INDEX )
 
#define ATOM_DEVICE_LCD2_SUPPORT   (0x1L << ATOM_DEVICE_LCD2_INDEX )
 
#define ATOM_DEVICE_DFP6_SUPPORT   (0x1L << ATOM_DEVICE_DFP6_INDEX )
 
#define ATOM_DEVICE_DFP2_SUPPORT   (0x1L << ATOM_DEVICE_DFP2_INDEX )
 
#define ATOM_DEVICE_CV_SUPPORT   (0x1L << ATOM_DEVICE_CV_INDEX )
 
#define ATOM_DEVICE_DFP3_SUPPORT   (0x1L << ATOM_DEVICE_DFP3_INDEX )
 
#define ATOM_DEVICE_DFP4_SUPPORT   (0x1L << ATOM_DEVICE_DFP4_INDEX )
 
#define ATOM_DEVICE_DFP5_SUPPORT   (0x1L << ATOM_DEVICE_DFP5_INDEX )
 
#define ATOM_DEVICE_CRT_SUPPORT   (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
 
#define ATOM_DEVICE_DFP_SUPPORT   (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
 
#define ATOM_DEVICE_TV_SUPPORT   (ATOM_DEVICE_TV1_SUPPORT)
 
#define ATOM_DEVICE_LCD_SUPPORT   (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
 
#define ATOM_DEVICE_CONNECTOR_TYPE_MASK   0x000000F0
 
#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT   0x00000004
 
#define ATOM_DEVICE_CONNECTOR_VGA   0x00000001
 
#define ATOM_DEVICE_CONNECTOR_DVI_I   0x00000002
 
#define ATOM_DEVICE_CONNECTOR_DVI_D   0x00000003
 
#define ATOM_DEVICE_CONNECTOR_DVI_A   0x00000004
 
#define ATOM_DEVICE_CONNECTOR_SVIDEO   0x00000005
 
#define ATOM_DEVICE_CONNECTOR_COMPOSITE   0x00000006
 
#define ATOM_DEVICE_CONNECTOR_LVDS   0x00000007
 
#define ATOM_DEVICE_CONNECTOR_DIGI_LINK   0x00000008
 
#define ATOM_DEVICE_CONNECTOR_SCART   0x00000009
 
#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A   0x0000000A
 
#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B   0x0000000B
 
#define ATOM_DEVICE_CONNECTOR_CASE_1   0x0000000E
 
#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT   0x0000000F
 
#define ATOM_DEVICE_DAC_INFO_MASK   0x0000000F
 
#define ATOM_DEVICE_DAC_INFO_SHIFT   0x00000000
 
#define ATOM_DEVICE_DAC_INFO_NODAC   0x00000000
 
#define ATOM_DEVICE_DAC_INFO_DACA   0x00000001
 
#define ATOM_DEVICE_DAC_INFO_DACB   0x00000002
 
#define ATOM_DEVICE_DAC_INFO_EXDAC   0x00000003
 
#define ATOM_DEVICE_I2C_ID_NOI2C   0x00000000
 
#define ATOM_DEVICE_I2C_LINEMUX_MASK   0x0000000F
 
#define ATOM_DEVICE_I2C_LINEMUX_SHIFT   0x00000000
 
#define ATOM_DEVICE_I2C_ID_MASK   0x00000070
 
#define ATOM_DEVICE_I2C_ID_SHIFT   0x00000004
 
#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE   0x00000001
 
#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE   0x00000002
 
#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE   0x00000003
 
#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL   0x00000004
 
#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK   0x00000080
 
#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT   0x00000007
 
#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C   0x00000000
 
#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C   0x00000001
 
#define ATOM_H_CUTOFF   0x01
 
#define ATOM_HSYNC_POLARITY   0x02
 
#define ATOM_VSYNC_POLARITY   0x04
 
#define ATOM_V_CUTOFF   0x08
 
#define ATOM_H_REPLICATIONBY2   0x10
 
#define ATOM_V_REPLICATIONBY2   0x20
 
#define ATOM_COMPOSITESYNC   0x40
 
#define ATOM_INTERLACE   0x80
 
#define ATOM_DOUBLE_CLOCK_MODE   0x100
 
#define ATOM_RGB888_MODE   0x200
 
#define ATOM_REFRESH_43   43
 
#define ATOM_REFRESH_47   47
 
#define ATOM_REFRESH_56   56
 
#define ATOM_REFRESH_60   60
 
#define ATOM_REFRESH_65   65
 
#define ATOM_REFRESH_70   70
 
#define ATOM_REFRESH_72   72
 
#define ATOM_REFRESH_75   75
 
#define ATOM_REFRESH_85   85
 
#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION   SET_CRTC_TIMING_PARAMETERS
 
#define SUPPORTED_LCD_REFRESHRATE_30Hz   0x0004
 
#define SUPPORTED_LCD_REFRESHRATE_40Hz   0x0008
 
#define SUPPORTED_LCD_REFRESHRATE_50Hz   0x0010
 
#define SUPPORTED_LCD_REFRESHRATE_60Hz   0x0020
 
#define LCDPANEL_CAP_READ_EDID   0x1
 
#define LCDPANEL_CAP_DRR_SUPPORTED   0x2
 
#define LCDPANEL_CAP_eDP   0x4
 
#define PANEL_COLOR_BIT_DEPTH_MASK   0x70
 
#define PANEL_RANDOM_DITHER   0x80
 
#define PANEL_RANDOM_DITHER_MASK   0x80
 
#define ATOM_LVDS_INFO_LAST   ATOM_LVDS_INFO_V12
 
#define ATOM_LCD_INFO_LAST   ATOM_LCD_INFO_V13
 
#define ATOM_PANEL_MISC_V13_DUAL   0x00000001
 
#define ATOM_PANEL_MISC_V13_FPDI   0x00000002
 
#define ATOM_PANEL_MISC_V13_GREY_LEVEL   0x0000000C
 
#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT   2
 
#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
 
#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR   0x10
 
#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR   0x20
 
#define LCDPANEL_CAP_V13_READ_EDID   0x1
 
#define LCDPANEL_CAP_V13_DRR_SUPPORTED   0x2
 
#define LCDPANEL_CAP_V13_eDP   0x4
 
#define eDP_TO_LVDS_RX_DISABLE   0x00
 
#define eDP_TO_LVDS_COMMON_ID   0x01
 
#define eDP_TO_LVDS_RT_ID   0x02
 
#define LCD_MODE_CAP_BL_OFF   1
 
#define LCD_MODE_CAP_CRTC_OFF   2
 
#define LCD_MODE_CAP_PANEL_OFF   4
 
#define LCD_MODE_PATCH_RECORD_MODE_TYPE   1
 
#define LCD_RTS_RECORD_TYPE   2
 
#define LCD_CAP_RECORD_TYPE   3
 
#define LCD_FAKE_EDID_PATCH_RECORD_TYPE   4
 
#define LCD_PANEL_RESOLUTION_RECORD_TYPE   5
 
#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE   6
 
#define ATOM_RECORD_END_TYPE   0xFF
 
#define ATOM_MAX_SS_ENTRY   16
 
#define ATOM_DP_SS_ID1   0x0f1
 
#define ATOM_DP_SS_ID2   0x0f2
 
#define ATOM_LVLINK_2700MHz_SS_ID   0x0f3
 
#define ATOM_LVLINK_1620MHz_SS_ID   0x0f4
 
#define ATOM_SS_DOWN_SPREAD_MODE_MASK   0x00000000
 
#define ATOM_SS_DOWN_SPREAD_MODE   0x00000000
 
#define ATOM_SS_CENTRE_SPREAD_MODE_MASK   0x00000001
 
#define ATOM_SS_CENTRE_SPREAD_MODE   0x00000001
 
#define ATOM_INTERNAL_SS_MASK   0x00000000
 
#define ATOM_EXTERNAL_SS_MASK   0x00000002
 
#define EXEC_SS_STEP_SIZE_SHIFT   2
 
#define EXEC_SS_DELAY_SHIFT   4
 
#define ACTIVEDATA_TO_BLON_DELAY_SHIFT   4
 
#define NTSC_SUPPORT   0x1
 
#define NTSCJ_SUPPORT   0x2
 
#define PAL_SUPPORT   0x4
 
#define PALM_SUPPORT   0x8
 
#define PALCN_SUPPORT   0x10
 
#define PALN_SUPPORT   0x20
 
#define PAL60_SUPPORT   0x40
 
#define SECAM_SUPPORT   0x80
 
#define MAX_SUPPORTED_TV_TIMING   2
 
#define MAX_SUPPORTED_TV_TIMING_V1_2   3
 
#define ATOM_DPCD_MAX_LANE_MASK   0x1F
 
#define VESA_MEMORY_IN_64K_BLOCK   0x100
 
#define ATOM_EDID_RAW_DATASIZE   256
 
#define ATOM_HWICON_SURFACE_SIZE   4096
 
#define ATOM_HWICON_INFOTABLE_SIZE   32
 
#define MAX_DTD_MODE_IN_VRAM   6
 
#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE   (MAX_DTD_MODE_IN_VRAM*28)
 
#define ATOM_STD_MODE_SUPPORT_TBL_SIZE   32*8
 
#define DFP_ENCODER_TYPE_OFFSET   (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
 
#define ATOM_DP_DPCD_OFFSET   (DFP_ENCODER_TYPE_OFFSET + 4 )
 
#define ATOM_HWICON1_SURFACE_ADDR   0
 
#define ATOM_HWICON2_SURFACE_ADDR   (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
 
#define ATOM_HWICON_INFOTABLE_ADDR   (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
 
#define ATOM_CRT1_EDID_ADDR   (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
 
#define ATOM_CRT1_DTD_MODE_TBL_ADDR   (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_CRT1_STD_MODE_TBL_ADDR   (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_LCD1_EDID_ADDR   (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_LCD1_DTD_MODE_TBL_ADDR   (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_LCD1_STD_MODE_TBL_ADDR   (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_TV1_DTD_MODE_TBL_ADDR   (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP1_EDID_ADDR   (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP1_DTD_MODE_TBL_ADDR   (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP1_STD_MODE_TBL_ADDR   (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_CRT2_EDID_ADDR   (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_CRT2_DTD_MODE_TBL_ADDR   (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_CRT2_STD_MODE_TBL_ADDR   (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_LCD2_EDID_ADDR   (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_LCD2_DTD_MODE_TBL_ADDR   (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_LCD2_STD_MODE_TBL_ADDR   (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP6_EDID_ADDR   (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP6_DTD_MODE_TBL_ADDR   (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP6_STD_MODE_TBL_ADDR   (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP2_EDID_ADDR   (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP2_DTD_MODE_TBL_ADDR   (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP2_STD_MODE_TBL_ADDR   (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_CV_EDID_ADDR   (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_CV_DTD_MODE_TBL_ADDR   (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_CV_STD_MODE_TBL_ADDR   (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP3_EDID_ADDR   (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP3_DTD_MODE_TBL_ADDR   (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP3_STD_MODE_TBL_ADDR   (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP4_EDID_ADDR   (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP4_DTD_MODE_TBL_ADDR   (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP4_STD_MODE_TBL_ADDR   (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP5_EDID_ADDR   (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DFP5_DTD_MODE_TBL_ADDR   (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
 
#define ATOM_DFP5_STD_MODE_TBL_ADDR   (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_DP_TRAINING_TBL_ADDR   (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
 
#define ATOM_STACK_STORAGE_START   (ATOM_DP_TRAINING_TBL_ADDR + 1024)
 
#define ATOM_STACK_STORAGE_END   ATOM_STACK_STORAGE_START + 512
 
#define ATOM_VRAM_RESERVE_SIZE   ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
 
#define ATOM_VRAM_RESERVE_V2_SIZE   32
 
#define ATOM_VRAM_OPERATION_FLAGS_MASK   0xC0000000L
 
#define ATOM_VRAM_OPERATION_FLAGS_SHIFT   30
 
#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
 
#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION   0x0
 
#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO   1
 
#define GPIO_PIN_ACTIVE_HIGH   0x1
 
#define MAX_SUPPORTED_CV_STANDARDS   5
 
#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK   0x1F
 
#define ATOM_GPIO_SETTINGS_RESERVED_MASK   0x60
 
#define ATOM_GPIO_SETTINGS_ACTIVE_MASK   0x80
 
#define ATOM_CV_RESTRICT_FORMAT_SELECTION   0x2
 
#define ATOM_GPIO_DEFAULT_MODE_EN   0x80
 
#define ATOM_GPIO_SETTING_PERMODE_MASK   0x7F
 
#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A   0x01
 
#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B   0x02
 
#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A   0x04
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B   0x08
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT   0x2
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A   0x10
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B   0x20
 
#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT   0x4
 
#define ATOM_CV_LINE3_ASPECTRATIO_MASK   0x3F
 
#define ATOM_CV_LINE3_ASPECTRATIO_EXIST   0x80
 
#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3
 
#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4
 
#define ATOM_COMPONENT_VIDEO_INFO_LAST   ATOM_COMPONENT_VIDEO_INFO_V21
 
#define EXT_HPDPIN_LUTINDEX_0   0
 
#define EXT_HPDPIN_LUTINDEX_1   1
 
#define EXT_HPDPIN_LUTINDEX_2   2
 
#define EXT_HPDPIN_LUTINDEX_3   3
 
#define EXT_HPDPIN_LUTINDEX_4   4
 
#define EXT_HPDPIN_LUTINDEX_5   5
 
#define EXT_HPDPIN_LUTINDEX_6   6
 
#define EXT_HPDPIN_LUTINDEX_7   7
 
#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
 
#define EXT_AUXDDC_LUTINDEX_0   0
 
#define EXT_AUXDDC_LUTINDEX_1   1
 
#define EXT_AUXDDC_LUTINDEX_2   2
 
#define EXT_AUXDDC_LUTINDEX_3   3
 
#define EXT_AUXDDC_LUTINDEX_4   4
 
#define EXT_AUXDDC_LUTINDEX_5   5
 
#define EXT_AUXDDC_LUTINDEX_6   6
 
#define EXT_AUXDDC_LUTINDEX_7   7
 
#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
 
#define NUMBER_OF_UCHAR_FOR_GUID   16
 
#define MAX_NUMBER_OF_EXT_DISPLAY_PATH   7
 
#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE   0x01
 
#define ATOM_I2C_RECORD_TYPE   1
 
#define ATOM_HPD_INT_RECORD_TYPE   2
 
#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE   3
 
#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE   4
 
#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE   5
 
#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE   6
 
#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE   7
 
#define ATOM_JTAG_RECORD_TYPE   8
 
#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE   9
 
#define ATOM_ENCODER_DVO_CF_RECORD_TYPE   10
 
#define ATOM_CONNECTOR_CF_RECORD_TYPE   11
 
#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE   12
 
#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE   13
 
#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE   14
 
#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE   15
 
#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE   16
 
#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE   17
 
#define ATOM_OBJECT_LINK_RECORD_TYPE   18
 
#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE   19
 
#define ATOM_ENCODER_CAP_RECORD_TYPE   20
 
#define ATOM_MAX_OBJECT_RECORD_NUMBER   ATOM_ENCODER_CAP_RECORD_TYPE
 
#define GPIO_PIN_TYPE_INPUT   0x00
 
#define GPIO_PIN_TYPE_OUTPUT   0x10
 
#define GPIO_PIN_TYPE_HW_CONTROL   0x20
 
#define GPIO_PIN_OUTPUT_STATE_MASK   0x01
 
#define GPIO_PIN_OUTPUT_STATE_SHIFT   0
 
#define GPIO_PIN_STATE_ACTIVE_LOW   0x0
 
#define GPIO_PIN_STATE_ACTIVE_HIGH   0x1
 
#define ATOM_GPIO_INDEX_GLSYNC_REFCLK   0
 
#define ATOM_GPIO_INDEX_GLSYNC_HSYNC   1
 
#define ATOM_GPIO_INDEX_GLSYNC_VSYNC   2
 
#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ   3
 
#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT   4
 
#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT   5
 
#define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
 
#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL   7
 
#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL   8
 
#define ATOM_GPIO_INDEX_GLSYNC_MAX   9
 
#define ATOM_ENCODER_CAP_RECORD_HBR2   0x01
 
#define ATOM_ENCODER_CAP_RECORD_HBR2_EN   0x02
 
#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
 
#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
 
#define ATOM_ROUTER_MUX_PIN_STATE_MASK   0x0f
 
#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT   0x01
 
#define VOLTAGE_CONTROLLED_BY_HW   0x00
 
#define VOLTAGE_CONTROLLED_BY_I2C_MASK   0x7F
 
#define VOLTAGE_CONTROLLED_BY_GPIO   0x80
 
#define VOLTAGE_CONTROL_ID_LM64   0x01
 
#define VOLTAGE_CONTROL_ID_DAC   0x02
 
#define VOLTAGE_CONTROL_ID_VT116xM   0x03
 
#define VOLTAGE_CONTROL_ID_DS4402   0x04
 
#define VOLTAGE_CONTROL_ID_UP6266   0x05
 
#define VOLTAGE_CONTROL_ID_SCORPIO   0x06
 
#define VOLTAGE_CONTROL_ID_VT1556M   0x07
 
#define VOLTAGE_CONTROL_ID_CHL822x   0x08
 
#define VOLTAGE_CONTROL_ID_VT1586M   0x09
 
#define VOLTAGE_CONTROL_ID_UP1637   0x0A
 
#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE   1
 
#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE   1
 
#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE   2
 
#define POWERSOURCE_PCIE_ID1   0x00
 
#define POWERSOURCE_6PIN_CONNECTOR_ID1   0x01
 
#define POWERSOURCE_8PIN_CONNECTOR_ID1   0x02
 
#define POWERSOURCE_6PIN_CONNECTOR_ID2   0x04
 
#define POWERSOURCE_8PIN_CONNECTOR_ID2   0x08
 
#define POWER_SENSOR_ALWAYS   0x00
 
#define POWER_SENSOR_GPIO   0x01
 
#define POWER_SENSOR_I2C   0x02
 
#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE   1
 
#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE   0x01
 
#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION   0x08
 
#define SYS_INFO_LVDSMISC__888_FPDI_MODE   0x01
 
#define SYS_INFO_LVDSMISC__DL_CH_SWAP   0x02
 
#define SYS_INFO_LVDSMISC__888_BPC   0x04
 
#define SYS_INFO_LVDSMISC__OVERRIDE_EN   0x08
 
#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW   0x10
 
#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW   0x04
 
#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW   0x08
 
#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT   0x01
 
#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT   0x02
 
#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT   0x04
 
#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT   0x08
 
#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE   0x01
 
#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE   0x02
 
#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT   0x08
 
#define ICS91719   1
 
#define ICS91720   2
 
#define ATOM_MCLK_SS_INFO   ATOM_ASIC_MVDD_INFO
 
#define ASIC_INTERNAL_MEMORY_SS   1
 
#define ASIC_INTERNAL_ENGINE_SS   2
 
#define ASIC_INTERNAL_UVD_SS   3
 
#define ASIC_INTERNAL_SS_ON_TMDS   4
 
#define ASIC_INTERNAL_SS_ON_HDMI   5
 
#define ASIC_INTERNAL_SS_ON_LVDS   6
 
#define ASIC_INTERNAL_SS_ON_DP   7
 
#define ASIC_INTERNAL_SS_ON_DCPLL   8
 
#define ASIC_EXTERNAL_SS_ON_DP_CLOCK   9
 
#define ASIC_INTERNAL_VCE_SS   10
 
#define ATOM_DEVICE_CONNECT_INFO_DEF   0
 
#define ATOM_ROM_LOCATION_DEF   1
 
#define ATOM_TV_STANDARD_DEF   2
 
#define ATOM_ACTIVE_INFO_DEF   3
 
#define ATOM_LCD_INFO_DEF   4
 
#define ATOM_DOS_REQ_INFO_DEF   5
 
#define ATOM_ACC_CHANGE_INFO_DEF   6
 
#define ATOM_DOS_MODE_INFO_DEF   7
 
#define ATOM_I2C_CHANNEL_STATUS_DEF   8
 
#define ATOM_I2C_CHANNEL_STATUS1_DEF   9
 
#define ATOM_INTERNAL_TIMER_DEF   10
 
#define ATOM_S0_CRT1_MONO   0x00000001L
 
#define ATOM_S0_CRT1_COLOR   0x00000002L
 
#define ATOM_S0_CRT1_MASK   (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
 
#define ATOM_S0_TV1_COMPOSITE_A   0x00000004L
 
#define ATOM_S0_TV1_SVIDEO_A   0x00000008L
 
#define ATOM_S0_TV1_MASK_A   (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
 
#define ATOM_S0_CV_A   0x00000010L
 
#define ATOM_S0_CV_DIN_A   0x00000020L
 
#define ATOM_S0_CV_MASK_A   (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
 
#define ATOM_S0_CRT2_MONO   0x00000100L
 
#define ATOM_S0_CRT2_COLOR   0x00000200L
 
#define ATOM_S0_CRT2_MASK   (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
 
#define ATOM_S0_TV1_COMPOSITE   0x00000400L
 
#define ATOM_S0_TV1_SVIDEO   0x00000800L
 
#define ATOM_S0_TV1_SCART   0x00004000L
 
#define ATOM_S0_TV1_MASK   (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
 
#define ATOM_S0_CV   0x00001000L
 
#define ATOM_S0_CV_DIN   0x00002000L
 
#define ATOM_S0_CV_MASK   (ATOM_S0_CV+ATOM_S0_CV_DIN)
 
#define ATOM_S0_DFP1   0x00010000L
 
#define ATOM_S0_DFP2   0x00020000L
 
#define ATOM_S0_LCD1   0x00040000L
 
#define ATOM_S0_LCD2   0x00080000L
 
#define ATOM_S0_DFP6   0x00100000L
 
#define ATOM_S0_DFP3   0x00200000L
 
#define ATOM_S0_DFP4   0x00400000L
 
#define ATOM_S0_DFP5   0x00800000L
 
#define ATOM_S0_DFP_MASK   ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
 
#define ATOM_S0_FAD_REGISTER_BUG   0x02000000L
 
#define ATOM_S0_THERMAL_STATE_MASK   0x1C000000L
 
#define ATOM_S0_THERMAL_STATE_SHIFT   26
 
#define ATOM_S0_SYSTEM_POWER_STATE_MASK   0xE0000000L
 
#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT   29
 
#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC   1
 
#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC   2
 
#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC   3
 
#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC   4
 
#define ATOM_S0_CRT1_MONOb0   0x01
 
#define ATOM_S0_CRT1_COLORb0   0x02
 
#define ATOM_S0_CRT1_MASKb0   (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
 
#define ATOM_S0_TV1_COMPOSITEb0   0x04
 
#define ATOM_S0_TV1_SVIDEOb0   0x08
 
#define ATOM_S0_TV1_MASKb0   (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
 
#define ATOM_S0_CVb0   0x10
 
#define ATOM_S0_CV_DINb0   0x20
 
#define ATOM_S0_CV_MASKb0   (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
 
#define ATOM_S0_CRT2_MONOb1   0x01
 
#define ATOM_S0_CRT2_COLORb1   0x02
 
#define ATOM_S0_CRT2_MASKb1   (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
 
#define ATOM_S0_TV1_COMPOSITEb1   0x04
 
#define ATOM_S0_TV1_SVIDEOb1   0x08
 
#define ATOM_S0_TV1_SCARTb1   0x40
 
#define ATOM_S0_TV1_MASKb1   (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
 
#define ATOM_S0_CVb1   0x10
 
#define ATOM_S0_CV_DINb1   0x20
 
#define ATOM_S0_CV_MASKb1   (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
 
#define ATOM_S0_DFP1b2   0x01
 
#define ATOM_S0_DFP2b2   0x02
 
#define ATOM_S0_LCD1b2   0x04
 
#define ATOM_S0_LCD2b2   0x08
 
#define ATOM_S0_DFP6b2   0x10
 
#define ATOM_S0_DFP3b2   0x20
 
#define ATOM_S0_DFP4b2   0x40
 
#define ATOM_S0_DFP5b2   0x80
 
#define ATOM_S0_THERMAL_STATE_MASKb3   0x1C
 
#define ATOM_S0_THERMAL_STATE_SHIFTb3   2
 
#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3   0xE0
 
#define ATOM_S0_LCD1_SHIFT   18
 
#define ATOM_S1_ROM_LOCATION_MASK   0x0000FFFFL
 
#define ATOM_S1_PCI_BUS_DEV_MASK   0xFFFF0000L
 
#define ATOM_S2_TV1_STANDARD_MASK   0x0000000FL
 
#define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
 
#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT   8
 
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK   0x0C000000L
 
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT   26
 
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE   0x10000000L
 
#define ATOM_S2_DEVICE_DPMS_STATE   0x00010000L
 
#define ATOM_S2_VRI_BRIGHT_ENABLE   0x20000000L
 
#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE   0x0
 
#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE   0x1
 
#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
 
#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
 
#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT   30
 
#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
 
#define ATOM_S2_TV1_STANDARD_MASKb0   0x0F
 
#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1   0xFF
 
#define ATOM_S2_DEVICE_DPMS_STATEb2   0x01
 
#define ATOM_S2_DEVICE_DPMS_MASKw1   0x3FF
 
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3   0x0C
 
#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
 
#define ATOM_S2_TMDS_COHERENT_MODEb3   0x10
 
#define ATOM_S2_VRI_BRIGHT_ENABLEb3   0x20
 
#define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
 
#define ATOM_S3_CRT1_ACTIVE   0x00000001L
 
#define ATOM_S3_LCD1_ACTIVE   0x00000002L
 
#define ATOM_S3_TV1_ACTIVE   0x00000004L
 
#define ATOM_S3_DFP1_ACTIVE   0x00000008L
 
#define ATOM_S3_CRT2_ACTIVE   0x00000010L
 
#define ATOM_S3_LCD2_ACTIVE   0x00000020L
 
#define ATOM_S3_DFP6_ACTIVE   0x00000040L
 
#define ATOM_S3_DFP2_ACTIVE   0x00000080L
 
#define ATOM_S3_CV_ACTIVE   0x00000100L
 
#define ATOM_S3_DFP3_ACTIVE   0x00000200L
 
#define ATOM_S3_DFP4_ACTIVE   0x00000400L
 
#define ATOM_S3_DFP5_ACTIVE   0x00000800L
 
#define ATOM_S3_DEVICE_ACTIVE_MASK   0x00000FFFL
 
#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE   0x00001000L
 
#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE   0x00002000L
 
#define ATOM_S3_CRT1_CRTC_ACTIVE   0x00010000L
 
#define ATOM_S3_LCD1_CRTC_ACTIVE   0x00020000L
 
#define ATOM_S3_TV1_CRTC_ACTIVE   0x00040000L
 
#define ATOM_S3_DFP1_CRTC_ACTIVE   0x00080000L
 
#define ATOM_S3_CRT2_CRTC_ACTIVE   0x00100000L
 
#define ATOM_S3_LCD2_CRTC_ACTIVE   0x00200000L
 
#define ATOM_S3_DFP6_CRTC_ACTIVE   0x00400000L
 
#define ATOM_S3_DFP2_CRTC_ACTIVE   0x00800000L
 
#define ATOM_S3_CV_CRTC_ACTIVE   0x01000000L
 
#define ATOM_S3_DFP3_CRTC_ACTIVE   0x02000000L
 
#define ATOM_S3_DFP4_CRTC_ACTIVE   0x04000000L
 
#define ATOM_S3_DFP5_CRTC_ACTIVE   0x08000000L
 
#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK   0x0FFF0000L
 
#define ATOM_S3_ASIC_GUI_ENGINE_HUNG   0x20000000L
 
#define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
 
#define ATOM_S3_RQST_GPU_USE_MIN_PWR   0x80000000L
 
#define ATOM_S3_CRT1_ACTIVEb0   0x01
 
#define ATOM_S3_LCD1_ACTIVEb0   0x02
 
#define ATOM_S3_TV1_ACTIVEb0   0x04
 
#define ATOM_S3_DFP1_ACTIVEb0   0x08
 
#define ATOM_S3_CRT2_ACTIVEb0   0x10
 
#define ATOM_S3_LCD2_ACTIVEb0   0x20
 
#define ATOM_S3_DFP6_ACTIVEb0   0x40
 
#define ATOM_S3_DFP2_ACTIVEb0   0x80
 
#define ATOM_S3_CV_ACTIVEb1   0x01
 
#define ATOM_S3_DFP3_ACTIVEb1   0x02
 
#define ATOM_S3_DFP4_ACTIVEb1   0x04
 
#define ATOM_S3_DFP5_ACTIVEb1   0x08
 
#define ATOM_S3_ACTIVE_CRTC1w0   0xFFF
 
#define ATOM_S3_CRT1_CRTC_ACTIVEb2   0x01
 
#define ATOM_S3_LCD1_CRTC_ACTIVEb2   0x02
 
#define ATOM_S3_TV1_CRTC_ACTIVEb2   0x04
 
#define ATOM_S3_DFP1_CRTC_ACTIVEb2   0x08
 
#define ATOM_S3_CRT2_CRTC_ACTIVEb2   0x10
 
#define ATOM_S3_LCD2_CRTC_ACTIVEb2   0x20
 
#define ATOM_S3_DFP6_CRTC_ACTIVEb2   0x40
 
#define ATOM_S3_DFP2_CRTC_ACTIVEb2   0x80
 
#define ATOM_S3_CV_CRTC_ACTIVEb3   0x01
 
#define ATOM_S3_DFP3_CRTC_ACTIVEb3   0x02
 
#define ATOM_S3_DFP4_CRTC_ACTIVEb3   0x04
 
#define ATOM_S3_DFP5_CRTC_ACTIVEb3   0x08
 
#define ATOM_S3_ACTIVE_CRTC2w1   0xFFF
 
#define ATOM_S4_LCD1_PANEL_ID_MASK   0x000000FFL
 
#define ATOM_S4_LCD1_REFRESH_MASK   0x0000FF00L
 
#define ATOM_S4_LCD1_REFRESH_SHIFT   8
 
#define ATOM_S4_LCD1_PANEL_ID_MASKb0   0x0FF
 
#define ATOM_S4_LCD1_REFRESH_MASKb1   ATOM_S4_LCD1_PANEL_ID_MASKb0
 
#define ATOM_S4_VRAM_INFO_MASKb2   ATOM_S4_LCD1_PANEL_ID_MASKb0
 
#define ATOM_S5_DOS_REQ_CRT1b0   0x01
 
#define ATOM_S5_DOS_REQ_LCD1b0   0x02
 
#define ATOM_S5_DOS_REQ_TV1b0   0x04
 
#define ATOM_S5_DOS_REQ_DFP1b0   0x08
 
#define ATOM_S5_DOS_REQ_CRT2b0   0x10
 
#define ATOM_S5_DOS_REQ_LCD2b0   0x20
 
#define ATOM_S5_DOS_REQ_DFP6b0   0x40
 
#define ATOM_S5_DOS_REQ_DFP2b0   0x80
 
#define ATOM_S5_DOS_REQ_CVb1   0x01
 
#define ATOM_S5_DOS_REQ_DFP3b1   0x02
 
#define ATOM_S5_DOS_REQ_DFP4b1   0x04
 
#define ATOM_S5_DOS_REQ_DFP5b1   0x08
 
#define ATOM_S5_DOS_REQ_DEVICEw0   0x0FFF
 
#define ATOM_S5_DOS_REQ_CRT1   0x0001
 
#define ATOM_S5_DOS_REQ_LCD1   0x0002
 
#define ATOM_S5_DOS_REQ_TV1   0x0004
 
#define ATOM_S5_DOS_REQ_DFP1   0x0008
 
#define ATOM_S5_DOS_REQ_CRT2   0x0010
 
#define ATOM_S5_DOS_REQ_LCD2   0x0020
 
#define ATOM_S5_DOS_REQ_DFP6   0x0040
 
#define ATOM_S5_DOS_REQ_DFP2   0x0080
 
#define ATOM_S5_DOS_REQ_CV   0x0100
 
#define ATOM_S5_DOS_REQ_DFP3   0x0200
 
#define ATOM_S5_DOS_REQ_DFP4   0x0400
 
#define ATOM_S5_DOS_REQ_DFP5   0x0800
 
#define ATOM_S5_DOS_FORCE_CRT1b2   ATOM_S5_DOS_REQ_CRT1b0
 
#define ATOM_S5_DOS_FORCE_TV1b2   ATOM_S5_DOS_REQ_TV1b0
 
#define ATOM_S5_DOS_FORCE_CRT2b2   ATOM_S5_DOS_REQ_CRT2b0
 
#define ATOM_S5_DOS_FORCE_CVb3   ATOM_S5_DOS_REQ_CVb1
 
#define ATOM_S5_DOS_FORCE_DEVICEw1
 
#define ATOM_S6_DEVICE_CHANGE   0x00000001L
 
#define ATOM_S6_SCALER_CHANGE   0x00000002L
 
#define ATOM_S6_LID_CHANGE   0x00000004L
 
#define ATOM_S6_DOCKING_CHANGE   0x00000008L
 
#define ATOM_S6_ACC_MODE   0x00000010L
 
#define ATOM_S6_EXT_DESKTOP_MODE   0x00000020L
 
#define ATOM_S6_LID_STATE   0x00000040L
 
#define ATOM_S6_DOCK_STATE   0x00000080L
 
#define ATOM_S6_CRITICAL_STATE   0x00000100L
 
#define ATOM_S6_HW_I2C_BUSY_STATE   0x00000200L
 
#define ATOM_S6_THERMAL_STATE_CHANGE   0x00000400L
 
#define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
 
#define ATOM_S6_REQ_LCD_EXPANSION_FULL   0x00001000L
 
#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO   0x00002000L
 
#define ATOM_S6_DISPLAY_STATE_CHANGE   0x00004000L
 
#define ATOM_S6_I2C_STATE_CHANGE   0x00008000L
 
#define ATOM_S6_ACC_REQ_CRT1   0x00010000L
 
#define ATOM_S6_ACC_REQ_LCD1   0x00020000L
 
#define ATOM_S6_ACC_REQ_TV1   0x00040000L
 
#define ATOM_S6_ACC_REQ_DFP1   0x00080000L
 
#define ATOM_S6_ACC_REQ_CRT2   0x00100000L
 
#define ATOM_S6_ACC_REQ_LCD2   0x00200000L
 
#define ATOM_S6_ACC_REQ_DFP6   0x00400000L
 
#define ATOM_S6_ACC_REQ_DFP2   0x00800000L
 
#define ATOM_S6_ACC_REQ_CV   0x01000000L
 
#define ATOM_S6_ACC_REQ_DFP3   0x02000000L
 
#define ATOM_S6_ACC_REQ_DFP4   0x04000000L
 
#define ATOM_S6_ACC_REQ_DFP5   0x08000000L
 
#define ATOM_S6_ACC_REQ_MASK   0x0FFF0000L
 
#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE   0x10000000L
 
#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH   0x20000000L
 
#define ATOM_S6_VRI_BRIGHTNESS_CHANGE   0x40000000L
 
#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK   0x80000000L
 
#define ATOM_S6_DEVICE_CHANGEb0   0x01
 
#define ATOM_S6_SCALER_CHANGEb0   0x02
 
#define ATOM_S6_LID_CHANGEb0   0x04
 
#define ATOM_S6_DOCKING_CHANGEb0   0x08
 
#define ATOM_S6_ACC_MODEb0   0x10
 
#define ATOM_S6_EXT_DESKTOP_MODEb0   0x20
 
#define ATOM_S6_LID_STATEb0   0x40
 
#define ATOM_S6_DOCK_STATEb0   0x80
 
#define ATOM_S6_CRITICAL_STATEb1   0x01
 
#define ATOM_S6_HW_I2C_BUSY_STATEb1   0x02
 
#define ATOM_S6_THERMAL_STATE_CHANGEb1   0x04
 
#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1   0x08
 
#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1   0x10
 
#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1   0x20
 
#define ATOM_S6_ACC_REQ_CRT1b2   0x01
 
#define ATOM_S6_ACC_REQ_LCD1b2   0x02
 
#define ATOM_S6_ACC_REQ_TV1b2   0x04
 
#define ATOM_S6_ACC_REQ_DFP1b2   0x08
 
#define ATOM_S6_ACC_REQ_CRT2b2   0x10
 
#define ATOM_S6_ACC_REQ_LCD2b2   0x20
 
#define ATOM_S6_ACC_REQ_DFP6b2   0x40
 
#define ATOM_S6_ACC_REQ_DFP2b2   0x80
 
#define ATOM_S6_ACC_REQ_CVb3   0x01
 
#define ATOM_S6_ACC_REQ_DFP3b3   0x02
 
#define ATOM_S6_ACC_REQ_DFP4b3   0x04
 
#define ATOM_S6_ACC_REQ_DFP5b3   0x08
 
#define ATOM_S6_ACC_REQ_DEVICEw1   ATOM_S5_DOS_REQ_DEVICEw0
 
#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3   0x10
 
#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3   0x20
 
#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3   0x40
 
#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3   0x80
 
#define ATOM_S6_DEVICE_CHANGE_SHIFT   0
 
#define ATOM_S6_SCALER_CHANGE_SHIFT   1
 
#define ATOM_S6_LID_CHANGE_SHIFT   2
 
#define ATOM_S6_DOCKING_CHANGE_SHIFT   3
 
#define ATOM_S6_ACC_MODE_SHIFT   4
 
#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT   5
 
#define ATOM_S6_LID_STATE_SHIFT   6
 
#define ATOM_S6_DOCK_STATE_SHIFT   7
 
#define ATOM_S6_CRITICAL_STATE_SHIFT   8
 
#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT   9
 
#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT   10
 
#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT   11
 
#define ATOM_S6_REQ_SCALER_SHIFT   12
 
#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT   13
 
#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT   14
 
#define ATOM_S6_I2C_STATE_CHANGE_SHIFT   15
 
#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT   28
 
#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT   29
 
#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT   30
 
#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT   31
 
#define ATOM_S7_DOS_MODE_TYPEb0   0x03
 
#define ATOM_S7_DOS_MODE_VGAb0   0x00
 
#define ATOM_S7_DOS_MODE_VESAb0   0x01
 
#define ATOM_S7_DOS_MODE_EXTb0   0x02
 
#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0   0x0C
 
#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0   0xF0
 
#define ATOM_S7_DOS_8BIT_DAC_ENb1   0x01
 
#define ATOM_S7_DOS_MODE_NUMBERw1   0x0FFFF
 
#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT   8
 
#define ATOM_S8_I2C_CHANNEL_BUSY_MASK   0x00000FFFF
 
#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK   0x0FFFF0000
 
#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT   0
 
#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT   16
 
#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK   0x0000FFFF
 
#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK   0xFFFF0000
 
#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT   0
 
#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
 
#define ATOM_FLAG_SET   0x20
 
#define ATOM_FLAG_CLEAR   0
 
#define CLEAR_ATOM_S6_ACC_MODE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
 
#define SET_ATOM_S6_DEVICE_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_SCALER_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_LID_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_LID_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
 
#define CLEAR_ATOM_S6_LID_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
 
#define SET_ATOM_S6_DOCK_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_DOCK_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
 
#define CLEAR_ATOM_S6_DOCK_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
 
#define SET_ATOM_S6_THERMAL_STATE_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
 
#define SET_ATOM_S6_CRITICAL_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
 
#define CLEAR_ATOM_S6_CRITICAL_STATE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
 
#define SET_ATOM_S6_REQ_SCALER   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
 
#define CLEAR_ATOM_S6_REQ_SCALER   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
 
#define SET_ATOM_S6_REQ_SCALER_ARATIO   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
 
#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
 
#define SET_ATOM_S6_I2C_STATE_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
 
#define SET_ATOM_S6_DISPLAY_STATE_CHANGE   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
 
#define SET_ATOM_S6_DEVICE_RECONFIG   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
 
#define CLEAR_ATOM_S0_LCD1   ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
 
#define SET_ATOM_S7_DOS_8BIT_DAC_EN   ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
 
#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN   ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
 
#define GetIndexIntoMasterTable(MasterOrData, FieldName)   (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
 
#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET)   ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
 
#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)   ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
 
#define GET_DATA_TABLE_MAJOR_REVISION   GET_COMMAND_TABLE_COMMANDSET_REVISION
 
#define GET_DATA_TABLE_MINOR_REVISION   GET_COMMAND_TABLE_PARAMETER_REVISION
 
#define ATOM_DAC_SRC   0x80
 
#define ATOM_SRC_DAC1   0
 
#define ATOM_SRC_DAC2   0x80
 
#define MEMORY_PLLINIT_PS_ALLOCATION   MEMORY_PLLINIT_PARAMETERS
 
#define GPIO_PIN_WRITE   0x01
 
#define GPIO_PIN_READ   0x00
 
#define ENABLE_SCALER_PS_ALLOCATION   ENABLE_SCALER_PARAMETERS
 
#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION   0
 
#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION   1
 
#define SCALER_ENABLE_2TAP_ALPHA_MODE   2
 
#define SCALER_ENABLE_MULTITAP_MODE   3
 
#define ATOM_GRAPH_CONTROL_SET_PITCH   0x0f
 
#define ATOM_GRAPH_CONTROL_SET_DISP_START   0x10
 
#define MEMORY_CLEAN_UP_PS_ALLOCATION   MEMORY_CLEAN_UP_PARAMETERS
 
#define PALETTE_DATA_AUTO_FILL   1
 
#define PALETTE_DATA_READ   2
 
#define PALETTE_DATA_WRITE   3
 
#define HDP1_INTERRUPT_ID   1
 
#define HDP2_INTERRUPT_ID   2
 
#define HDP3_INTERRUPT_ID   3
 
#define HDP4_INTERRUPT_ID   4
 
#define HDP5_INTERRUPT_ID   5
 
#define HDP6_INTERRUPT_ID   6
 
#define SW_INTERRUPT_ID   11
 
#define INTERRUPT_SERVICE_GEN_SW_INT   1
 
#define INTERRUPT_SERVICE_GET_STATUS   2
 
#define INTERRUPT_STATUS__INT_TRIGGER   1
 
#define INTERRUPT_STATUS__HPD_HIGH   2
 
#define INDIRECT_READ   0x00
 
#define INDIRECT_WRITE   0x80
 
#define INDIRECT_IO_MM   0
 
#define INDIRECT_IO_PLL   1
 
#define INDIRECT_IO_MC   2
 
#define INDIRECT_IO_PCIE   3
 
#define INDIRECT_IO_PCIEP   4
 
#define INDIRECT_IO_NBMISC   5
 
#define INDIRECT_IO_PLL_READ   INDIRECT_IO_PLL | INDIRECT_READ
 
#define INDIRECT_IO_PLL_WRITE   INDIRECT_IO_PLL | INDIRECT_WRITE
 
#define INDIRECT_IO_MC_READ   INDIRECT_IO_MC | INDIRECT_READ
 
#define INDIRECT_IO_MC_WRITE   INDIRECT_IO_MC | INDIRECT_WRITE
 
#define INDIRECT_IO_PCIE_READ   INDIRECT_IO_PCIE | INDIRECT_READ
 
#define INDIRECT_IO_PCIE_WRITE   INDIRECT_IO_PCIE | INDIRECT_WRITE
 
#define INDIRECT_IO_PCIEP_READ   INDIRECT_IO_PCIEP | INDIRECT_READ
 
#define INDIRECT_IO_PCIEP_WRITE   INDIRECT_IO_PCIEP | INDIRECT_WRITE
 
#define INDIRECT_IO_NBMISC_READ   INDIRECT_IO_NBMISC | INDIRECT_READ
 
#define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
 
#define END_OF_REG_INDEX_BLOCK   0x0ffff
 
#define END_OF_REG_DATA_BLOCK   0x00000000
 
#define ATOM_INIT_REG_MASK_FLAG   0x80
 
#define CLOCK_RANGE_HIGHEST   0x00ffffff
 
#define VALUE_DWORD   SIZEOF ULONG
 
#define VALUE_SAME_AS_ABOVE   0
 
#define VALUE_MASK_DWORD   0x84
 
#define INDEX_ACCESS_RANGE_BEGIN   (VALUE_DWORD + 1)
 
#define INDEX_ACCESS_RANGE_END   (INDEX_ACCESS_RANGE_BEGIN + 1)
 
#define VALUE_INDEX_ACCESS_SINGLE   (INDEX_ACCESS_RANGE_END + 1)
 
#define ACCESS_PLACEHOLDER   0x80
 
#define _4Mx16   0x2
 
#define _4Mx32   0x3
 
#define _8Mx16   0x12
 
#define _8Mx32   0x13
 
#define _16Mx16   0x22
 
#define _16Mx32   0x23
 
#define _32Mx16   0x32
 
#define _32Mx32   0x33
 
#define _64Mx8   0x41
 
#define _64Mx16   0x42
 
#define _64Mx32   0x43
 
#define _128Mx8   0x51
 
#define _128Mx16   0x52
 
#define _256Mx8   0x61
 
#define _256Mx16   0x62
 
#define SAMSUNG   0x1
 
#define INFINEON   0x2
 
#define ELPIDA   0x3
 
#define ETRON   0x4
 
#define NANYA   0x5
 
#define HYNIX   0x6
 
#define MOSEL   0x7
 
#define WINBOND   0x8
 
#define ESMT   0x9
 
#define MICRON   0xF
 
#define QIMONDA   INFINEON
 
#define PROMOS   MOSEL
 
#define KRETON   INFINEON
 
#define ELIXIR   NANYA
 
#define UCODE_ROM_START_ADDRESS   0x1b800
 
#define UCODE_SIGNATURE   0x4375434d
 
#define ATOM_MAX_NUMBER_OF_VRAM_MODULE   16
 
#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK   0xF
 
#define NPL_RT_MASK   0x0f
 
#define BATTERY_ODT_MASK   0xc0
 
#define ATOM_VRAM_MODULE   ATOM_VRAM_MODULE_V3
 
#define VRAM_MODULE_V4_MISC_RANK_MASK   0x3
 
#define VRAM_MODULE_V4_MISC_DUAL_RANK   0x1
 
#define VRAM_MODULE_V4_MISC_BL_MASK   0x4
 
#define VRAM_MODULE_V4_MISC_BL8   0x4
 
#define VRAM_MODULE_V4_MISC_DUAL_CS   0x10
 
#define ATOM_VRAM_INFO_LAST   ATOM_VRAM_INFO_V3
 
#define SW_I2C_CNTL_DATA_PS_ALLOCATION   SW_I2C_CNTL_DATA_PARAMETERS
 
#define SW_I2C_IO_DATA_PS_ALLOCATION   SW_I2C_IO_DATA_PARAMETERS
 
#define SW_I2C_IO_RESET   0
 
#define SW_I2C_IO_GET   1
 
#define SW_I2C_IO_DRIVE   2
 
#define SW_I2C_IO_SET   3
 
#define SW_I2C_IO_START   4
 
#define SW_I2C_IO_CLOCK   0
 
#define SW_I2C_IO_DATA   0x80
 
#define SW_I2C_IO_ZERO   0
 
#define SW_I2C_IO_ONE   0x100
 
#define SW_I2C_CNTL_READ   0
 
#define SW_I2C_CNTL_WRITE   1
 
#define SW_I2C_CNTL_START   2
 
#define SW_I2C_CNTL_STOP   3
 
#define SW_I2C_CNTL_OPEN   4
 
#define SW_I2C_CNTL_CLOSE   5
 
#define SW_I2C_CNTL_WRITE1BIT   6
 
#define VESA_OEM_PRODUCT_REV   "01.00"
 
#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT   0xBB
 
#define VESA_MODE_WIN_ATTRIBUTE   7
 
#define VESA_WIN_SIZE   64
 
#define ATOM_BIOS_EXTENDED_FUNCTION_CODE   0xA0
 
#define ATOM_BIOS_FUNCTION_COP_MODE   0x00
 
#define ATOM_BIOS_FUNCTION_SHORT_QUERY1   0x04
 
#define ATOM_BIOS_FUNCTION_SHORT_QUERY2   0x05
 
#define ATOM_BIOS_FUNCTION_SHORT_QUERY3   0x06
 
#define ATOM_BIOS_FUNCTION_GET_DDC   0x0B
 
#define ATOM_BIOS_FUNCTION_ASIC_DSTATE   0x0E
 
#define ATOM_BIOS_FUNCTION_DEBUG_PLAY   0x0F
 
#define ATOM_BIOS_FUNCTION_STV_STD   0x16
 
#define ATOM_BIOS_FUNCTION_DEVICE_DET   0x17
 
#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH   0x18
 
#define ATOM_BIOS_FUNCTION_PANEL_CONTROL   0x82
 
#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET   0x83
 
#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH   0x84
 
#define ATOM_BIOS_FUNCTION_HW_ICON   0x8A
 
#define ATOM_BIOS_FUNCTION_SET_CMOS   0x8B
 
#define SUB_FUNCTION_UPDATE_DISPLAY_INFO   0x8000
 
#define SUB_FUNCTION_UPDATE_EXPANSION_INFO   0x8100
 
#define ATOM_BIOS_FUNCTION_DISPLAY_INFO   0x8D
 
#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF   0x8E
 
#define ATOM_BIOS_FUNCTION_VIDEO_STATE   0x8F
 
#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE   0x0300
 
#define ATOM_SUB_FUNCTION_GET_LIDSTATE   0x0700
 
#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE   0x1400
 
#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE   0x8300
 
#define ATOM_SUB_FUNCTION_SET_LIDSTATE   0x8500
 
#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE   0x8900
 
#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT   0x9400
 
#define ATOM_BIOS_FUNCTION_VESA_DPMS   0x4F10
 
#define ATOM_SUB_FUNCTION_SET_DPMS   0x0001
 
#define ATOM_SUB_FUNCTION_GET_DPMS   0x0002
 
#define ATOM_PARAMETER_VESA_DPMS_ON   0x0000
 
#define ATOM_PARAMETER_VESA_DPMS_STANDBY   0x0100
 
#define ATOM_PARAMETER_VESA_DPMS_SUSPEND   0x0200
 
#define ATOM_PARAMETER_VESA_DPMS_OFF   0x0400
 
#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON   0x0800
 
#define ATOM_BIOS_RETURN_CODE_MASK   0x0000FF00L
 
#define ATOM_BIOS_REG_HIGH_MASK   0x0000FF00L
 
#define ATOM_BIOS_REG_LOW_MASK   0x000000FFL
 
#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE   0x01
 
#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE   0x02
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK   0xc4
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A   0x00
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B   0x04
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C   0x40
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D   0x44
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E   0x80
 
#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F   0x84
 
#define CLOCK_SOURCE_SHAREABLE   0x01
 
#define CLOCK_SOURCE_DP_MODE   0x02
 
#define CLOCK_SOURCE_NONE_DP_MODE   0x04
 
#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
 
#define ATOM_DP_ACTION_GET_SINK_TYPE   0x01
 
#define ATOM_DP_ACTION_TRAINING_START   0x02
 
#define ATOM_DP_ACTION_TRAINING_COMPLETE   0x03
 
#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL   0x04
 
#define ATOM_DP_ACTION_SET_VSWING_PREEMP   0x05
 
#define ATOM_DP_ACTION_GET_VSWING_PREEMP   0x06
 
#define ATOM_DP_ACTION_BLANKING   0x07
 
#define ATOM_DP_CONFIG_ENCODER_SEL_MASK   0x03
 
#define ATOM_DP_CONFIG_DIG1_ENCODER   0x00
 
#define ATOM_DP_CONFIG_DIG2_ENCODER   0x01
 
#define ATOM_DP_CONFIG_EXTERNAL_ENCODER   0x02
 
#define ATOM_DP_CONFIG_LINK_SEL_MASK   0x04
 
#define ATOM_DP_CONFIG_LINK_A   0x00
 
#define ATOM_DP_CONFIG_LINK_B   0x04
 
#define DP_ENCODER_SERVICE_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 
#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE   0x01
 
#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION   0x02
 
#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR   ATOM_DP_TRAINING_TBL_ADDR
 
#define DPCD_SET_SS_CNTL_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 8 )
 
#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 16 )
 
#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 24 )
 
#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 32)
 
#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 40)
 
#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 48)
 
#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 60)
 
#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 64)
 
#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 72)
 
#define DP_I2C_AUX_DDC_READ_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 76)
 
#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 80)
 
#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR   (ATOM_DP_TRAINING_TBL_ADDR + 84)
 
#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION   PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
 
#define HW_I2C_WRITE   1
 
#define HW_I2C_READ   0
 
#define I2C_2BYTE_ADDR   0x02
 
#define ATOM_GET_SDI_SUPPORT   0xF0
 
#define ATOM_UNKNOWN_CMD   0
 
#define ATOM_FEATURE_NOT_SUPPORTED   1
 
#define ATOM_FEATURE_SUPPORTED   2
 
#define HWBLKINST_INSTANCE_MASK   0x07
 
#define HWBLKINST_HWBLK_MASK   0xF0
 
#define HWBLKINST_HWBLK_SHIFT   0x04
 
#define SELECT_DISP_ENGINE   0
 
#define SELECT_DISP_PLL   1
 
#define SELECT_DCIO_UNIPHY_LINK0   2
 
#define SELECT_DCIO_UNIPHY_LINK1   3
 
#define SELECT_DCIO_IMPCAL   4
 
#define SELECT_DCIO_DIG   6
 
#define SELECT_CRTC_PIXEL_RATE   7
 
#define SELECT_VGA_BLK   8
 
#define MC_MISC0__MEMORY_TYPE_MASK   0xF0000000
 
#define MC_MISC0__MEMORY_TYPE__GDDR1   0x10000000
 
#define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
 
#define MC_MISC0__MEMORY_TYPE__GDDR3   0x30000000
 
#define MC_MISC0__MEMORY_TYPE__GDDR4   0x40000000
 
#define MC_MISC0__MEMORY_TYPE__GDDR5   0x50000000
 
#define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
 
#define NO_INT_SRC_MAPPED   0xFF
 
#define ATOM_SUPPORTED_DEVICES_INFO_LAST   ATOM_SUPPORTED_DEVICES_INFO_2d1
 
#define ATOM_MAX_MISC_INFO   4
 
#define ATOM_XTMDS_ASIC_SI164_ID   1
 
#define ATOM_XTMDS_ASIC_SI178_ID   2
 
#define ATOM_XTMDS_ASIC_TFP513_ID   3
 
#define ATOM_XTMDS_SUPPORTED_SINGLELINK   0x00000001
 
#define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
 
#define ATOM_XTMDS_MVPU_FPGA   0x00000004
 
#define ATOM_PM_MISCINFO_SPLIT_CLOCK   0x00000000L
 
#define ATOM_PM_MISCINFO_USING_MCLK_SRC   0x00000001L
 
#define ATOM_PM_MISCINFO_USING_SCLK_SRC   0x00000002L
 
#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT   0x00000004L
 
#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH   0x00000008L
 
#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN   0x00000010L
 
#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN   0x00000020L
 
#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN   0x00000040L
 
#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE   0x00000080L
 
#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN   0x00000100L
 
#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN   0x00000200L
 
#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN   0x00000400L
 
#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN   0x00000800L
 
#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE   0x00001000L
 
#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE   0x00002000L
 
#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE   0x00004000L
 
#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE   0x00008000L
 
#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE   0x00010000L
 
#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE   0x00020000L
 
#define ATOM_PM_MISCINFO_POWER_SAVING_MODE   0x00040000L
 
#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE   0x00080000L
 
#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK   0x00300000L
 
#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT   20
 
#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE   0x00400000L
 
#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2   0x00800000L
 
#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4   0x01000000L
 
#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN   0x02000000L
 
#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN   0x04000000L
 
#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN   0x08000000L
 
#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L
 
#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT   28
 
#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS   0x80000000L
 
#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE   0x00000001L
 
#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT   0x00000002L
 
#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN   0x00000004L
 
#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO   0x00000008L
 
#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE   0x00000010L
 
#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN   0x00000020L
 
#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE   0x00000040L
 
#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC   0x00000080L
 
#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN   0x00000100L
 
#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE   0x00000200L
 
#define ATOM_MAX_NUMBEROF_POWER_BLOCK   8
 
#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN   0x01
 
#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE   0x02
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63   0x01
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64   0x05
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375   0x06
 
#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07
 
#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK   0x0f
 
#define ATOM_PP_FANPARAMETERS_NOFAN   0x80
 
#define ATOM_PP_THERMALCONTROLLER_NONE   0
 
#define ATOM_PP_THERMALCONTROLLER_LM63   1
 
#define ATOM_PP_THERMALCONTROLLER_ADM1032   2
 
#define ATOM_PP_THERMALCONTROLLER_ADM1030   3
 
#define ATOM_PP_THERMALCONTROLLER_MUA6649   4
 
#define ATOM_PP_THERMALCONTROLLER_LM64   5
 
#define ATOM_PP_THERMALCONTROLLER_F75375   6
 
#define ATOM_PP_THERMALCONTROLLER_RV6xx   7
 
#define ATOM_PP_THERMALCONTROLLER_RV770   8
 
#define ATOM_PP_THERMALCONTROLLER_ADT7473   9
 
#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO   11
 
#define ATOM_PP_THERMALCONTROLLER_EVERGREEN   12
 
#define ATOM_PP_THERMALCONTROLLER_EMC2103   13 /* 0x0D */
 
#define ATOM_PP_THERMALCONTROLLER_SUMO   14 /* 0x0E */
 
#define ATOM_PP_THERMALCONTROLLER_NISLANDS   15
 
#define ATOM_PP_THERMALCONTROLLER_SISLANDS   16
 
#define ATOM_PP_THERMALCONTROLLER_LM96163   17
 
#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL   0x89
 
#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL   0x8D
 
#define ATOM_PP_PLATFORM_CAP_BACKBIAS   1
 
#define ATOM_PP_PLATFORM_CAP_POWERPLAY   2
 
#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE   4
 
#define ATOM_PP_PLATFORM_CAP_ASPM_L0s   8
 
#define ATOM_PP_PLATFORM_CAP_ASPM_L1   16
 
#define ATOM_PP_PLATFORM_CAP_HARDWAREDC   32
 
#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY   64
 
#define ATOM_PP_PLATFORM_CAP_STEPVDDC   128
 
#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL   256
 
#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL   512
 
#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1   1024
 
#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL   2048
 
#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL   4096
 
#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT   0x2000
 
#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT   0x4000
 
#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL   0x8000
 
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT   0x00010000
 
#define ATOM_PP_PLATFORM_CAP_BACO   0x00020000
 
#define ATOM_PPLIB_CLASSIFICATION_UI_MASK   0x0007
 
#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT   0
 
#define ATOM_PPLIB_CLASSIFICATION_UI_NONE   0
 
#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY   1
 
#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED   3
 
#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE   5
 
#define ATOM_PPLIB_CLASSIFICATION_BOOT   0x0008
 
#define ATOM_PPLIB_CLASSIFICATION_THERMAL   0x0010
 
#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE   0x0020
 
#define ATOM_PPLIB_CLASSIFICATION_REST   0x0040
 
#define ATOM_PPLIB_CLASSIFICATION_FORCED   0x0080
 
#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE   0x0100
 
#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE   0x0200
 
#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE   0x0400
 
#define ATOM_PPLIB_CLASSIFICATION_3DLOW   0x0800
 
#define ATOM_PPLIB_CLASSIFICATION_ACPI   0x1000
 
#define ATOM_PPLIB_CLASSIFICATION_HD2STATE   0x2000
 
#define ATOM_PPLIB_CLASSIFICATION_HDSTATE   0x4000
 
#define ATOM_PPLIB_CLASSIFICATION_SDSTATE   0x8000
 
#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2   0x0001
 
#define ATOM_PPLIB_CLASSIFICATION2_ULV   0x0002
 
#define ATOM_PPLIB_CLASSIFICATION2_MVC   0x0004
 
#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY   0x00000001
 
#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK   0x00000002
 
#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK   0x00000004
 
#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT   2
 
#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK   0x000000F8
 
#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT   3
 
#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK   0x00000F00
 
#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT   8
 
#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED   0
 
#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ   1
 
#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING   0x00001000
 
#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS   0x00002000
 
#define ATOM_PPLIB_DISALLOW_ON_DC   0x00004000
 
#define ATOM_PPLIB_ENABLE_VARIBRIGHT   0x00008000
 
#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF   0x000010000
 
#define ATOM_PPLIB_M3ARB_MASK   0x00060000
 
#define ATOM_PPLIB_M3ARB_SHIFT   17
 
#define ATOM_PPLIB_ENABLE_DRR   0x00080000
 
#define ATOM_PPLIB_NONCLOCKINFO_VER1   12
 
#define ATOM_PPLIB_NONCLOCKINFO_VER2   24
 
#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2   1
 
#define ATOM_PPLIB_R600_FLAGS_UVDSAFE   2
 
#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE   4
 
#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF   8
 
#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF   16
 
#define ATOM_PPLIB_R600_FLAGS_LOWPOWER   32
 
#define ATOM_PPLIB_RS780_VOLTAGE_NONE   0
 
#define ATOM_PPLIB_RS780_VOLTAGE_LOW   1
 
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH   2
 
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE   3
 
#define ATOM_PPLIB_RS780_SPMCLK_NONE   0
 
#define ATOM_PPLIB_RS780_SPMCLK_LOW   1
 
#define ATOM_PPLIB_RS780_SPMCLK_HIGH   2
 
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE   0
 
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW   1
 
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH   2
 
#define ATOM_MASTER_DATA_TABLE_REVISION   0x01
 
#define Object_Info   Object_Header
 
#define AdjustARB_SEQ   MC_InitParameter
 
#define VRAM_GPIO_DetectionInfo   VoltageObjectInfo
 
#define ASIC_VDDCI_Info   ASIC_ProfilingInfo
 
#define ASIC_MVDDQ_Info   MemoryTrainingInfo
 
#define SS_Info   PPLL_SS_Info
 
#define ASIC_MVDDC_Info   ASIC_InternalSS_Info
 
#define DispDevicePriorityInfo   SaveRestoreInfo
 
#define DispOutInfo   TV_VideoMode
 
#define ATOM_ENCODER_OBJECT_TABLE   ATOM_OBJECT_TABLE
 
#define ATOM_CONNECTOR_OBJECT_TABLE   ATOM_OBJECT_TABLE
 
#define DFP2I_OUTPUT_CONTROL_PARAMETERS   CRT1_OUTPUT_CONTROL_PARAMETERS
 
#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION   DFP2I_OUTPUT_CONTROL_PARAMETERS
 
#define DFP1X_OUTPUT_CONTROL_PARAMETERS   CRT1_OUTPUT_CONTROL_PARAMETERS
 
#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION   DFP1X_OUTPUT_CONTROL_PARAMETERS
 
#define DFP1I_OUTPUT_CONTROL_PARAMETERS   DFP1_OUTPUT_CONTROL_PARAMETERS
 
#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION   DFP1_OUTPUT_CONTROL_PS_ALLOCATION
 
#define ATOM_DEVICE_DFP1I_SUPPORT   ATOM_DEVICE_DFP1_SUPPORT
 
#define ATOM_DEVICE_DFP1X_SUPPORT   ATOM_DEVICE_DFP2_SUPPORT
 
#define ATOM_DEVICE_DFP1I_INDEX   ATOM_DEVICE_DFP1_INDEX
 
#define ATOM_DEVICE_DFP1X_INDEX   ATOM_DEVICE_DFP2_INDEX
 
#define ATOM_DEVICE_DFP2I_INDEX   0x00000009
 
#define ATOM_DEVICE_DFP2I_SUPPORT   (0x1L << ATOM_DEVICE_DFP2I_INDEX)
 
#define ATOM_S0_DFP1I   ATOM_S0_DFP1
 
#define ATOM_S0_DFP1X   ATOM_S0_DFP2
 
#define ATOM_S0_DFP2I   0x00200000L
 
#define ATOM_S0_DFP2Ib2   0x20
 
#define ATOM_S2_DFP1I_DPMS_STATE   ATOM_S2_DFP1_DPMS_STATE
 
#define ATOM_S2_DFP1X_DPMS_STATE   ATOM_S2_DFP2_DPMS_STATE
 
#define ATOM_S2_DFP2I_DPMS_STATE   0x02000000L
 
#define ATOM_S2_DFP2I_DPMS_STATEb3   0x02
 
#define ATOM_S3_DFP2I_ACTIVEb1   0x02
 
#define ATOM_S3_DFP1I_ACTIVE   ATOM_S3_DFP1_ACTIVE
 
#define ATOM_S3_DFP1X_ACTIVE   ATOM_S3_DFP2_ACTIVE
 
#define ATOM_S3_DFP2I_ACTIVE   0x00000200L
 
#define ATOM_S3_DFP1I_CRTC_ACTIVE   ATOM_S3_DFP1_CRTC_ACTIVE
 
#define ATOM_S3_DFP1X_CRTC_ACTIVE   ATOM_S3_DFP2_CRTC_ACTIVE
 
#define ATOM_S3_DFP2I_CRTC_ACTIVE   0x02000000L
 
#define ATOM_S3_DFP2I_CRTC_ACTIVEb3   0x02
 
#define ATOM_S5_DOS_REQ_DFP2Ib1   0x02
 
#define ATOM_S5_DOS_REQ_DFP2I   0x0200
 
#define ATOM_S6_ACC_REQ_DFP1I   ATOM_S6_ACC_REQ_DFP1
 
#define ATOM_S6_ACC_REQ_DFP1X   ATOM_S6_ACC_REQ_DFP2
 
#define ATOM_S6_ACC_REQ_DFP2Ib3   0x02
 
#define ATOM_S6_ACC_REQ_DFP2I   0x02000000L
 
#define TMDS1XEncoderControl   DVOEncoderControl
 
#define DFP1XOutputControl   DVOOutputControl
 
#define ExternalDFPOutputControl   DFP1XOutputControl
 
#define EnableExternalTMDS_Encoder   TMDS1XEncoderControl
 
#define DFP1IOutputControl   TMDSAOutputControl
 
#define DFP2IOutputControl   LVTMAOutputControl
 
#define DAC1_ENCODER_CONTROL_PARAMETERS   DAC_ENCODER_CONTROL_PARAMETERS
 
#define DAC1_ENCODER_CONTROL_PS_ALLOCATION   DAC_ENCODER_CONTROL_PS_ALLOCATION
 
#define DAC2_ENCODER_CONTROL_PARAMETERS   DAC_ENCODER_CONTROL_PARAMETERS
 
#define DAC2_ENCODER_CONTROL_PS_ALLOCATION   DAC_ENCODER_CONTROL_PS_ALLOCATION
 
#define ucDac1Standard   ucDacStandard
 
#define ucDac2Standard   ucDacStandard
 
#define TMDS1EncoderControl   TMDSAEncoderControl
 
#define TMDS2EncoderControl   LVTMAEncoderControl
 
#define DFP1OutputControl   TMDSAOutputControl
 
#define DFP2OutputControl   LVTMAOutputControl
 
#define CRT1OutputControl   DAC1OutputControl
 
#define CRT2OutputControl   DAC2OutputControl
 
#define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
 
#define ENABLE_LVDS_SS_PARAMETERS_V3   ENABLE_SPREAD_SPECTRUM_ON_PPLL
 
#define ATOM_S6_ACC_REQ_TV2   0x00400000L
 
#define ATOM_DEVICE_TV2_INDEX   0x00000006
 
#define ATOM_DEVICE_TV2_SUPPORT   (0x1L << ATOM_DEVICE_TV2_INDEX)
 
#define ATOM_S0_TV2   0x00100000L
 
#define ATOM_S3_TV2_ACTIVE   ATOM_S3_DFP6_ACTIVE
 
#define ATOM_S3_TV2_CRTC_ACTIVE   ATOM_S3_DFP6_CRTC_ACTIVE
 
#define ATOM_S2_CRT1_DPMS_STATE   0x00010000L
 
#define ATOM_S2_LCD1_DPMS_STATE   0x00020000L
 
#define ATOM_S2_TV1_DPMS_STATE   0x00040000L
 
#define ATOM_S2_DFP1_DPMS_STATE   0x00080000L
 
#define ATOM_S2_CRT2_DPMS_STATE   0x00100000L
 
#define ATOM_S2_LCD2_DPMS_STATE   0x00200000L
 
#define ATOM_S2_TV2_DPMS_STATE   0x00400000L
 
#define ATOM_S2_DFP2_DPMS_STATE   0x00800000L
 
#define ATOM_S2_CV_DPMS_STATE   0x01000000L
 
#define ATOM_S2_DFP3_DPMS_STATE   0x02000000L
 
#define ATOM_S2_DFP4_DPMS_STATE   0x04000000L
 
#define ATOM_S2_DFP5_DPMS_STATE   0x08000000L
 
#define ATOM_S2_CRT1_DPMS_STATEb2   0x01
 
#define ATOM_S2_LCD1_DPMS_STATEb2   0x02
 
#define ATOM_S2_TV1_DPMS_STATEb2   0x04
 
#define ATOM_S2_DFP1_DPMS_STATEb2   0x08
 
#define ATOM_S2_CRT2_DPMS_STATEb2   0x10
 
#define ATOM_S2_LCD2_DPMS_STATEb2   0x20
 
#define ATOM_S2_TV2_DPMS_STATEb2   0x40
 
#define ATOM_S2_DFP2_DPMS_STATEb2   0x80
 
#define ATOM_S2_CV_DPMS_STATEb3   0x01
 
#define ATOM_S2_DFP3_DPMS_STATEb3   0x02
 
#define ATOM_S2_DFP4_DPMS_STATEb3   0x04
 
#define ATOM_S2_DFP5_DPMS_STATEb3   0x08
 
#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3   0x20
 
#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3   0x40
 
#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3   0x80
 

Typedefs

typedef struct
_ATOM_COMMON_TABLE_HEADER 
ATOM_COMMON_TABLE_HEADER
 
typedef struct _ATOM_ROM_HEADER ATOM_ROM_HEADER
 
typedef struct
_ATOM_MASTER_LIST_OF_COMMAND_TABLES 
ATOM_MASTER_LIST_OF_COMMAND_TABLES
 
typedef struct
_ATOM_MASTER_COMMAND_TABLE 
ATOM_MASTER_COMMAND_TABLE
 
typedef struct
_ATOM_TABLE_ATTRIBUTE 
ATOM_TABLE_ATTRIBUTE
 
typedef union
_ATOM_TABLE_ATTRIBUTE_ACCESS 
ATOM_TABLE_ATTRIBUTE_ACCESS
 
typedef struct
_ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 
ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 
typedef struct
_ATOM_ADJUST_MEMORY_CLOCK_FREQ 
ATOM_ADJUST_MEMORY_CLOCK_FREQ
 
typedef struct
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 
typedef struct
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 
typedef struct
_ATOM_COMPUTE_CLOCK_FREQ 
ATOM_COMPUTE_CLOCK_FREQ
 
typedef struct
_ATOM_S_MPLL_FB_DIVIDER 
ATOM_S_MPLL_FB_DIVIDER
 
typedef struct
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
 
typedef struct
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
 
typedef struct
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
 
typedef struct
_COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
 
typedef struct
_DYNAMICE_MEMORY_SETTINGS_PARAMETER 
DYNAMICE_MEMORY_SETTINGS_PARAMETER
 
typedef struct
_DYNAMICE_ENGINE_SETTINGS_PARAMETER 
DYNAMICE_ENGINE_SETTINGS_PARAMETER
 
typedef struct
_SET_ENGINE_CLOCK_PARAMETERS 
SET_ENGINE_CLOCK_PARAMETERS
 
typedef struct
_SET_ENGINE_CLOCK_PS_ALLOCATION 
SET_ENGINE_CLOCK_PS_ALLOCATION
 
typedef struct
_SET_MEMORY_CLOCK_PARAMETERS 
SET_MEMORY_CLOCK_PARAMETERS
 
typedef struct
_SET_MEMORY_CLOCK_PS_ALLOCATION 
SET_MEMORY_CLOCK_PS_ALLOCATION
 
typedef struct
_ASIC_INIT_PARAMETERS 
ASIC_INIT_PARAMETERS
 
typedef struct
_ASIC_INIT_PS_ALLOCATION 
ASIC_INIT_PS_ALLOCATION
 
typedef struct
_DYNAMIC_CLOCK_GATING_PARAMETERS 
DYNAMIC_CLOCK_GATING_PARAMETERS
 
typedef struct
_ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 
ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
 
typedef struct
_ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 
ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 
typedef struct
_DAC_LOAD_DETECTION_PARAMETERS 
DAC_LOAD_DETECTION_PARAMETERS
 
typedef struct
_DAC_LOAD_DETECTION_PS_ALLOCATION 
DAC_LOAD_DETECTION_PS_ALLOCATION
 
typedef struct
_DAC_ENCODER_CONTROL_PARAMETERS 
DAC_ENCODER_CONTROL_PARAMETERS
 
typedef struct
_DIG_ENCODER_CONTROL_PARAMETERS 
DIG_ENCODER_CONTROL_PARAMETERS
 
typedef struct
_ATOM_DIG_ENCODER_CONFIG_V2 
ATOM_DIG_ENCODER_CONFIG_V2
 
typedef struct
_DIG_ENCODER_CONTROL_PARAMETERS_V2 
DIG_ENCODER_CONTROL_PARAMETERS_V2
 
typedef struct
_ATOM_DIG_ENCODER_CONFIG_V3 
ATOM_DIG_ENCODER_CONFIG_V3
 
typedef struct
_DIG_ENCODER_CONTROL_PARAMETERS_V3 
DIG_ENCODER_CONTROL_PARAMETERS_V3
 
typedef struct
_ATOM_DIG_ENCODER_CONFIG_V4 
ATOM_DIG_ENCODER_CONFIG_V4
 
typedef struct
_DIG_ENCODER_CONTROL_PARAMETERS_V4 
DIG_ENCODER_CONTROL_PARAMETERS_V4
 
typedef struct _ATOM_DP_VS_MODE ATOM_DP_VS_MODE
 
typedef struct
_DIG_TRANSMITTER_CONTROL_PARAMETERS 
DIG_TRANSMITTER_CONTROL_PARAMETERS
 
typedef struct
_ATOM_DIG_TRANSMITTER_CONFIG_V2 
ATOM_DIG_TRANSMITTER_CONFIG_V2
 
typedef struct
_DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
 
typedef struct
_ATOM_DIG_TRANSMITTER_CONFIG_V3 
ATOM_DIG_TRANSMITTER_CONFIG_V3
 
typedef struct
_DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
 
typedef struct _ATOM_DP_VS_MODE_V4 ATOM_DP_VS_MODE_V4
 
typedef struct
_ATOM_DIG_TRANSMITTER_CONFIG_V4 
ATOM_DIG_TRANSMITTER_CONFIG_V4
 
typedef struct
_DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
 
typedef struct
_ATOM_DIG_TRANSMITTER_CONFIG_V5 
ATOM_DIG_TRANSMITTER_CONFIG_V5
 
typedef struct
_DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 
DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
 
typedef struct
_EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 
EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
 
typedef struct
_EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
 
typedef struct
_DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
 
typedef struct
_BLANK_CRTC_PARAMETERS 
BLANK_CRTC_PARAMETERS
 
typedef struct
_ENABLE_CRTC_PARAMETERS 
ENABLE_CRTC_PARAMETERS
 
typedef struct
_SET_CRTC_OVERSCAN_PARAMETERS 
SET_CRTC_OVERSCAN_PARAMETERS
 
typedef struct
_SET_CRTC_REPLICATION_PARAMETERS 
SET_CRTC_REPLICATION_PARAMETERS
 
typedef struct
_SELECT_CRTC_SOURCE_PARAMETERS 
SELECT_CRTC_SOURCE_PARAMETERS
 
typedef struct
_SELECT_CRTC_SOURCE_PARAMETERS_V2 
SELECT_CRTC_SOURCE_PARAMETERS_V2
 
typedef struct
_PIXEL_CLOCK_PARAMETERS 
PIXEL_CLOCK_PARAMETERS
 
typedef struct
_PIXEL_CLOCK_PARAMETERS_V2 
PIXEL_CLOCK_PARAMETERS_V2
 
typedef struct
_PIXEL_CLOCK_PARAMETERS_V3 
PIXEL_CLOCK_PARAMETERS_V3
 
typedef struct
_PIXEL_CLOCK_PARAMETERS_V5 
PIXEL_CLOCK_PARAMETERS_V5
 
typedef struct
_CRTC_PIXEL_CLOCK_FREQ 
CRTC_PIXEL_CLOCK_FREQ
 
typedef struct
_PIXEL_CLOCK_PARAMETERS_V6 
PIXEL_CLOCK_PARAMETERS_V6
 
typedef struct
_GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 
GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
 
typedef struct
_GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 
GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
 
typedef struct
_GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 
GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
 
typedef struct
_ADJUST_DISPLAY_PLL_PARAMETERS 
ADJUST_DISPLAY_PLL_PARAMETERS
 
typedef struct
_ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 
ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
 
typedef struct
_ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 
ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
 
typedef struct
_ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 
ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
 
typedef struct
_ENABLE_YUV_PARAMETERS 
ENABLE_YUV_PARAMETERS
 
typedef struct
_GET_MEMORY_CLOCK_PARAMETERS 
GET_MEMORY_CLOCK_PARAMETERS
 
typedef struct
_GET_ENGINE_CLOCK_PARAMETERS 
GET_ENGINE_CLOCK_PARAMETERS
 
typedef struct
_READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 
READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
 
typedef struct
_WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 
WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
 
typedef struct
_SET_UP_HW_I2C_DATA_PARAMETERS 
SET_UP_HW_I2C_DATA_PARAMETERS
 
typedef struct
_POWER_CONNECTOR_DETECTION_PARAMETERS 
POWER_CONNECTOR_DETECTION_PARAMETERS
 
typedef struct
POWER_CONNECTOR_DETECTION_PS_ALLOCATION 
POWER_CONNECTOR_DETECTION_PS_ALLOCATION
 
typedef struct
_ENABLE_LVDS_SS_PARAMETERS 
ENABLE_LVDS_SS_PARAMETERS
 
typedef struct
_ENABLE_LVDS_SS_PARAMETERS_V2 
ENABLE_LVDS_SS_PARAMETERS_V2
 
typedef struct
_ENABLE_SPREAD_SPECTRUM_ON_PPLL 
ENABLE_SPREAD_SPECTRUM_ON_PPLL
 
typedef struct
_ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
 
typedef struct
_ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 
ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
 
typedef struct
_SET_PIXEL_CLOCK_PS_ALLOCATION 
SET_PIXEL_CLOCK_PS_ALLOCATION
 
typedef struct
_MEMORY_TRAINING_PARAMETERS 
MEMORY_TRAINING_PARAMETERS
 
typedef struct
_LVDS_ENCODER_CONTROL_PARAMETERS 
LVDS_ENCODER_CONTROL_PARAMETERS
 
typedef struct
_LVDS_ENCODER_CONTROL_PARAMETERS_V2 
LVDS_ENCODER_CONTROL_PARAMETERS_V2
 
typedef struct
_ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 
ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
 
typedef struct
_ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
 
typedef struct
_ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
 
typedef struct
_EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 
EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
 
typedef struct
_DVO_ENCODER_CONTROL_PARAMETERS_V3 
DVO_ENCODER_CONTROL_PARAMETERS_V3
 
typedef struct
_SET_VOLTAGE_PARAMETERS 
SET_VOLTAGE_PARAMETERS
 
typedef struct
_SET_VOLTAGE_PARAMETERS_V2 
SET_VOLTAGE_PARAMETERS_V2
 
typedef struct
_SET_VOLTAGE_PARAMETERS_V1_3 
SET_VOLTAGE_PARAMETERS_V1_3
 
typedef struct
_SET_VOLTAGE_PS_ALLOCATION 
SET_VOLTAGE_PS_ALLOCATION
 
typedef struct
_GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 
GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
 
typedef struct
_GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 
GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
 
typedef struct
_GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 
GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
 
typedef struct
_TV_ENCODER_CONTROL_PARAMETERS 
TV_ENCODER_CONTROL_PARAMETERS
 
typedef struct
_TV_ENCODER_CONTROL_PS_ALLOCATION 
TV_ENCODER_CONTROL_PS_ALLOCATION
 
typedef struct
_ATOM_MASTER_LIST_OF_DATA_TABLES 
ATOM_MASTER_LIST_OF_DATA_TABLES
 
typedef struct
_ATOM_MASTER_DATA_TABLE 
ATOM_MASTER_DATA_TABLE
 
typedef struct
_ATOM_MULTIMEDIA_CAPABILITY_INFO 
ATOM_MULTIMEDIA_CAPABILITY_INFO
 
typedef struct
_ATOM_MULTIMEDIA_CONFIG_INFO 
ATOM_MULTIMEDIA_CONFIG_INFO
 
typedef struct
_ATOM_FIRMWARE_CAPABILITY 
ATOM_FIRMWARE_CAPABILITY
 
typedef union
_ATOM_FIRMWARE_CAPABILITY_ACCESS 
ATOM_FIRMWARE_CAPABILITY_ACCESS
 
typedef struct _ATOM_FIRMWARE_INFO ATOM_FIRMWARE_INFO
 
typedef struct
_ATOM_FIRMWARE_INFO_V1_2 
ATOM_FIRMWARE_INFO_V1_2
 
typedef struct
_ATOM_FIRMWARE_INFO_V1_3 
ATOM_FIRMWARE_INFO_V1_3
 
typedef struct
_ATOM_FIRMWARE_INFO_V1_4 
ATOM_FIRMWARE_INFO_V1_4
 
typedef struct
_ATOM_FIRMWARE_INFO_V2_1 
ATOM_FIRMWARE_INFO_V2_1
 
typedef struct
_ATOM_FIRMWARE_INFO_V2_2 
ATOM_FIRMWARE_INFO_V2_2
 
typedef struct
_ATOM_INTEGRATED_SYSTEM_INFO 
ATOM_INTEGRATED_SYSTEM_INFO
 
typedef struct
_ATOM_INTEGRATED_SYSTEM_INFO_V2 
ATOM_INTEGRATED_SYSTEM_INFO_V2
 
typedef struct
_ATOM_INTEGRATED_SYSTEM_INFO_V5 
ATOM_INTEGRATED_SYSTEM_INFO_V5
 
typedef struct _ATOM_I2C_ID_CONFIG ATOM_I2C_ID_CONFIG
 
typedef union
_ATOM_I2C_ID_CONFIG_ACCESS 
ATOM_I2C_ID_CONFIG_ACCESS
 
typedef struct
_ATOM_GPIO_I2C_ASSIGMENT 
ATOM_GPIO_I2C_ASSIGMENT
 
typedef struct _ATOM_GPIO_I2C_INFO ATOM_GPIO_I2C_INFO
 
typedef struct _ATOM_MODE_MISC_INFO ATOM_MODE_MISC_INFO
 
typedef union
_ATOM_MODE_MISC_INFO_ACCESS 
ATOM_MODE_MISC_INFO_ACCESS
 
typedef struct
_SET_CRTC_USING_DTD_TIMING_PARAMETERS 
SET_CRTC_USING_DTD_TIMING_PARAMETERS
 
typedef struct
_SET_CRTC_TIMING_PARAMETERS 
SET_CRTC_TIMING_PARAMETERS
 
typedef struct _ATOM_MODE_TIMING ATOM_MODE_TIMING
 
typedef struct _ATOM_DTD_FORMAT ATOM_DTD_FORMAT
 
typedef struct _ATOM_LVDS_INFO ATOM_LVDS_INFO
 
typedef struct _ATOM_LVDS_INFO_V12 ATOM_LVDS_INFO_V12
 
typedef struct _ATOM_LCD_INFO_V13 ATOM_LCD_INFO_V13
 
typedef struct
_ATOM_PATCH_RECORD_MODE 
ATOM_PATCH_RECORD_MODE
 
typedef struct _ATOM_LCD_RTS_RECORD ATOM_LCD_RTS_RECORD
 
typedef struct
_ATOM_LCD_MODE_CONTROL_CAP 
ATOM_LCD_MODE_CONTROL_CAP
 ! If the record below exits, it shoud always be the first record for easy use in command table!!!
 
typedef struct
_ATOM_FAKE_EDID_PATCH_RECORD 
ATOM_FAKE_EDID_PATCH_RECORD
 
typedef struct
_ATOM_PANEL_RESOLUTION_PATCH_RECORD 
ATOM_PANEL_RESOLUTION_PATCH_RECORD
 
typedef struct
_ATOM_SPREAD_SPECTRUM_ASSIGNMENT 
ATOM_SPREAD_SPECTRUM_ASSIGNMENT
 
typedef struct
_ATOM_SPREAD_SPECTRUM_INFO 
ATOM_SPREAD_SPECTRUM_INFO
 
typedef struct _ATOM_ANALOG_TV_INFO ATOM_ANALOG_TV_INFO
 
typedef struct
_ATOM_ANALOG_TV_INFO_V1_2 
ATOM_ANALOG_TV_INFO_V1_2
 
typedef struct _ATOM_DPCD_INFO ATOM_DPCD_INFO
 
typedef struct
_ATOM_FIRMWARE_VRAM_RESERVE_INFO 
ATOM_FIRMWARE_VRAM_RESERVE_INFO
 
typedef struct
_ATOM_VRAM_USAGE_BY_FIRMWARE 
ATOM_VRAM_USAGE_BY_FIRMWARE
 
typedef struct
_ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 
ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
 
typedef struct
_ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 
ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
 
typedef struct
_ATOM_GPIO_PIN_ASSIGNMENT 
ATOM_GPIO_PIN_ASSIGNMENT
 
typedef struct _ATOM_GPIO_PIN_LUT ATOM_GPIO_PIN_LUT
 
typedef struct _ATOM_GPIO_INFO ATOM_GPIO_INFO
 
typedef struct
_ATOM_COMPONENT_VIDEO_INFO 
ATOM_COMPONENT_VIDEO_INFO
 
typedef struct
_ATOM_COMPONENT_VIDEO_INFO_V21 
ATOM_COMPONENT_VIDEO_INFO_V21
 
typedef struct _ATOM_OBJECT_HEADER ATOM_OBJECT_HEADER
 
typedef struct
_ATOM_OBJECT_HEADER_V3 
ATOM_OBJECT_HEADER_V3
 
typedef struct
_ATOM_DISPLAY_OBJECT_PATH 
ATOM_DISPLAY_OBJECT_PATH
 
typedef struct
_ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 
ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
 
typedef struct
_ATOM_DISPLAY_OBJECT_PATH_TABLE 
ATOM_DISPLAY_OBJECT_PATH_TABLE
 
typedef struct _ATOM_OBJECT ATOM_OBJECT
 
typedef struct _ATOM_OBJECT_TABLE ATOM_OBJECT_TABLE
 
typedef struct
_ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT 
ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
 
typedef struct
_ATOM_DP_CONN_CHANNEL_MAPPING 
ATOM_DP_CONN_CHANNEL_MAPPING
 
typedef struct
_ATOM_DVI_CONN_CHANNEL_MAPPING 
ATOM_DVI_CONN_CHANNEL_MAPPING
 
typedef struct _EXT_DISPLAY_PATH EXT_DISPLAY_PATH
 
typedef struct
_ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 
ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
 
typedef struct
_ATOM_COMMON_RECORD_HEADER 
ATOM_COMMON_RECORD_HEADER
 
typedef struct _ATOM_I2C_RECORD ATOM_I2C_RECORD
 
typedef struct _ATOM_HPD_INT_RECORD ATOM_HPD_INT_RECORD
 
typedef struct
_ATOM_OUTPUT_PROTECTION_RECORD 
ATOM_OUTPUT_PROTECTION_RECORD
 
typedef struct
_ATOM_CONNECTOR_DEVICE_TAG 
ATOM_CONNECTOR_DEVICE_TAG
 
typedef struct
_ATOM_CONNECTOR_DEVICE_TAG_RECORD 
ATOM_CONNECTOR_DEVICE_TAG_RECORD
 
typedef struct
_ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 
ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
 
typedef struct
_ATOM_ENCODER_FPGA_CONTROL_RECORD 
ATOM_ENCODER_FPGA_CONTROL_RECORD
 
typedef struct
_ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 
ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
 
typedef struct _ATOM_JTAG_RECORD ATOM_JTAG_RECORD
 
typedef struct
_ATOM_GPIO_PIN_CONTROL_PAIR 
ATOM_GPIO_PIN_CONTROL_PAIR
 
typedef struct
_ATOM_OBJECT_GPIO_CNTL_RECORD 
ATOM_OBJECT_GPIO_CNTL_RECORD
 
typedef struct
_ATOM_ENCODER_DVO_CF_RECORD 
ATOM_ENCODER_DVO_CF_RECORD
 
typedef struct
_ATOM_ENCODER_CAP_RECORD 
ATOM_ENCODER_CAP_RECORD
 
typedef struct
_ATOM_CONNECTOR_CF_RECORD 
ATOM_CONNECTOR_CF_RECORD
 
typedef struct
_ATOM_CONNECTOR_HARDCODE_DTD_RECORD 
ATOM_CONNECTOR_HARDCODE_DTD_RECORD
 
typedef struct
_ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 
ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
 
typedef struct
_ATOM_ROUTER_DDC_PATH_SELECT_RECORD 
ATOM_ROUTER_DDC_PATH_SELECT_RECORD
 
typedef struct
_ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 
ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
 
typedef struct
_ATOM_CONNECTOR_HPDPIN_LUT_RECORD 
ATOM_CONNECTOR_HPDPIN_LUT_RECORD
 
typedef struct
_ATOM_CONNECTOR_AUXDDC_LUT_RECORD 
ATOM_CONNECTOR_AUXDDC_LUT_RECORD
 
typedef struct
_ATOM_OBJECT_LINK_RECORD 
ATOM_OBJECT_LINK_RECORD
 
typedef struct
_ATOM_CONNECTOR_REMOTE_CAP_RECORD 
ATOM_CONNECTOR_REMOTE_CAP_RECORD
 
typedef struct
_ATOM_VOLTAGE_INFO_HEADER 
ATOM_VOLTAGE_INFO_HEADER
 
typedef struct _ATOM_VOLTAGE_INFO ATOM_VOLTAGE_INFO
 
typedef struct
_ATOM_VOLTAGE_FORMULA 
ATOM_VOLTAGE_FORMULA
 
typedef struct _VOLTAGE_LUT_ENTRY VOLTAGE_LUT_ENTRY
 
typedef struct
_ATOM_VOLTAGE_FORMULA_V2 
ATOM_VOLTAGE_FORMULA_V2
 
typedef struct
_ATOM_VOLTAGE_CONTROL 
ATOM_VOLTAGE_CONTROL
 
typedef struct _ATOM_VOLTAGE_OBJECT ATOM_VOLTAGE_OBJECT
 
typedef struct
_ATOM_VOLTAGE_OBJECT_V2 
ATOM_VOLTAGE_OBJECT_V2
 
typedef struct
_ATOM_VOLTAGE_OBJECT_INFO 
ATOM_VOLTAGE_OBJECT_INFO
 
typedef struct
_ATOM_VOLTAGE_OBJECT_INFO_V2 
ATOM_VOLTAGE_OBJECT_INFO_V2
 
typedef struct _ATOM_LEAKID_VOLTAGE ATOM_LEAKID_VOLTAGE
 
typedef struct
_ATOM_VOLTAGE_OBJECT_HEADER_V3 
ATOM_VOLTAGE_OBJECT_HEADER_V3
 
typedef struct
_VOLTAGE_LUT_ENTRY_V2 
VOLTAGE_LUT_ENTRY_V2
 
typedef struct
_LEAKAGE_VOLTAGE_LUT_ENTRY_V2 
LEAKAGE_VOLTAGE_LUT_ENTRY_V2
 
typedef struct
_ATOM_I2C_VOLTAGE_OBJECT_V3 
ATOM_I2C_VOLTAGE_OBJECT_V3
 
typedef struct
_ATOM_GPIO_VOLTAGE_OBJECT_V3 
ATOM_GPIO_VOLTAGE_OBJECT_V3
 
typedef struct
_ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 
ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
 
typedef union
_ATOM_VOLTAGE_OBJECT_V3 
ATOM_VOLTAGE_OBJECT_V3
 
typedef struct
_ATOM_VOLTAGE_OBJECT_INFO_V3_1 
ATOM_VOLTAGE_OBJECT_INFO_V3_1
 
typedef struct
_ATOM_ASIC_PROFILE_VOLTAGE 
ATOM_ASIC_PROFILE_VOLTAGE
 
typedef struct
_ATOM_ASIC_PROFILING_INFO 
ATOM_ASIC_PROFILING_INFO
 
typedef struct
_ATOM_POWER_SOURCE_OBJECT 
ATOM_POWER_SOURCE_OBJECT
 
typedef struct
_ATOM_POWER_SOURCE_INFO 
ATOM_POWER_SOURCE_INFO
 
typedef struct
_ATOM_CLK_VOLT_CAPABILITY 
ATOM_CLK_VOLT_CAPABILITY
 
typedef struct
_ATOM_AVAILABLE_SCLK_LIST 
ATOM_AVAILABLE_SCLK_LIST
 
typedef struct
_ATOM_INTEGRATED_SYSTEM_INFO_V6 
ATOM_INTEGRATED_SYSTEM_INFO_V6
 
typedef struct
_ATOM_FUSION_SYSTEM_INFO_V1 
ATOM_FUSION_SYSTEM_INFO_V1
 
typedef struct
_ATOM_INTEGRATED_SYSTEM_INFO_V1_7 
ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 
typedef struct
_ATOM_I2C_DATA_RECORD 
ATOM_I2C_DATA_RECORD
 
typedef struct
_ATOM_I2C_DEVICE_SETUP_INFO 
ATOM_I2C_DEVICE_SETUP_INFO
 
typedef struct _ATOM_ASIC_MVDD_INFO ATOM_ASIC_MVDD_INFO