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au1000_eth.h
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1 /*
2  *
3  * Alchemy Au1x00 ethernet driver include file
4  *
5  * Author: Pete Popov <[email protected]>
6  *
7  * Copyright 2001 MontaVista Software Inc.
8  *
9  * ########################################################################
10  *
11  * This program is free software; you can distribute it and/or modify it
12  * under the terms of the GNU General Public License (Version 2) as
13  * published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18  * for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, write to the Free Software Foundation, Inc.,
22  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23  *
24  * ########################################################################
25  *
26  *
27  */
28 
29 
30 #define MAC_IOSIZE 0x10000
31 #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
32 #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
33 
34 #define NUM_RX_BUFFS 4
35 #define NUM_TX_BUFFS 4
36 #define MAX_BUF_SIZE 2048
37 
38 #define ETH_TX_TIMEOUT (HZ/4)
39 #define MAC_MIN_PKT_SIZE 64
40 
41 #define MULTICAST_FILTER_LIMIT 64
42 
43 /*
44  * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
45  * boundary for both, receive and transmit.
46  */
47 struct db_dest {
48  struct db_dest *pnext;
51 };
52 
53 /*
54  * The transmit and receive descriptors are memory
55  * mapped registers.
56  */
57 struct tx_dma {
62 };
63 
64 struct rx_dma {
67  u32 pad[2];
68 };
69 
70 
71 /*
72  * MAC control registers, memory mapped.
73  */
74 struct mac_reg {
85 };
86 
87 
89  struct db_dest *pDBfree;
99 
100  int mac_id;
101 
102  int mac_enabled; /* whether MAC is currently enabled and running
103  * (req. for mdio)
104  */
105 
106  int old_link; /* used by au1000_adjust_link */
109 
111  struct mii_bus *mii_bus;
112 
113  /* PHY configuration */
117 
118  int phy_addr;
120  int phy_irq;
121 
122  /* These variables are just for quick access
123  * to certain regs addresses.
124  */
125  struct mac_reg *mac; /* mac registers */
126  u32 *enable; /* address of MAC Enable Register */
127  void __iomem *macdma; /* base of MAC DMA port */
128  u32 vaddr; /* virtual address of rx/tx buffers */
129  dma_addr_t dma_addr; /* dma address of rx/tx buffers */
130 
131  spinlock_t lock; /* Serialise access to device */
132 
134 };