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bcm63xx_cpu.h
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1 #ifndef BCM63XX_CPU_H_
2 #define BCM63XX_CPU_H_
3 
4 #include <linux/types.h>
5 #include <linux/init.h>
6 
7 /*
8  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9  * compile time if only one CPU support is enabled (idea stolen from
10  * arm mach-types)
11  */
12 #define BCM6328_CPU_ID 0x6328
13 #define BCM6338_CPU_ID 0x6338
14 #define BCM6345_CPU_ID 0x6345
15 #define BCM6348_CPU_ID 0x6348
16 #define BCM6358_CPU_ID 0x6358
17 #define BCM6368_CPU_ID 0x6368
18 
19 void __init bcm63xx_cpu_init(void);
20 u16 __bcm63xx_get_cpu_id(void);
21 u16 bcm63xx_get_cpu_rev(void);
22 unsigned int bcm63xx_get_cpu_freq(void);
23 
24 #ifdef CONFIG_BCM63XX_CPU_6328
25 # ifdef bcm63xx_get_cpu_id
26 # undef bcm63xx_get_cpu_id
27 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28 # define BCMCPU_RUNTIME_DETECT
29 # else
30 # define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31 # endif
32 # define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33 #else
34 # define BCMCPU_IS_6328() (0)
35 #endif
36 
37 #ifdef CONFIG_BCM63XX_CPU_6338
38 # ifdef bcm63xx_get_cpu_id
39 # undef bcm63xx_get_cpu_id
40 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
41 # define BCMCPU_RUNTIME_DETECT
42 # else
43 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
44 # endif
45 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
46 #else
47 # define BCMCPU_IS_6338() (0)
48 #endif
49 
50 #ifdef CONFIG_BCM63XX_CPU_6345
51 # ifdef bcm63xx_get_cpu_id
52 # undef bcm63xx_get_cpu_id
53 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
54 # define BCMCPU_RUNTIME_DETECT
55 # else
56 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
57 # endif
58 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
59 #else
60 # define BCMCPU_IS_6345() (0)
61 #endif
62 
63 #ifdef CONFIG_BCM63XX_CPU_6348
64 # ifdef bcm63xx_get_cpu_id
65 # undef bcm63xx_get_cpu_id
66 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
67 # define BCMCPU_RUNTIME_DETECT
68 # else
69 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
70 # endif
71 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
72 #else
73 # define BCMCPU_IS_6348() (0)
74 #endif
75 
76 #ifdef CONFIG_BCM63XX_CPU_6358
77 # ifdef bcm63xx_get_cpu_id
78 # undef bcm63xx_get_cpu_id
79 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
80 # define BCMCPU_RUNTIME_DETECT
81 # else
82 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
83 # endif
84 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
85 #else
86 # define BCMCPU_IS_6358() (0)
87 #endif
88 
89 #ifdef CONFIG_BCM63XX_CPU_6368
90 # ifdef bcm63xx_get_cpu_id
91 # undef bcm63xx_get_cpu_id
92 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
93 # define BCMCPU_RUNTIME_DETECT
94 # else
95 # define bcm63xx_get_cpu_id() BCM6368_CPU_ID
96 # endif
97 # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
98 #else
99 # define BCMCPU_IS_6368() (0)
100 #endif
101 
102 #ifndef bcm63xx_get_cpu_id
103 #error "No CPU support configured"
104 #endif
105 
106 /*
107  * While registers sets are (mostly) the same across 63xx CPU, base
108  * address of these sets do change.
109  */
110 enum bcm63xx_regs_set {
111  RSET_DSL_LMEM = 0,
112  RSET_PERF,
113  RSET_TIMER,
114  RSET_WDT,
115  RSET_UART0,
116  RSET_UART1,
117  RSET_GPIO,
118  RSET_SPI,
119  RSET_UDC0,
120  RSET_OHCI0,
121  RSET_OHCI_PRIV,
122  RSET_USBH_PRIV,
123  RSET_USBD,
124  RSET_USBDMA,
125  RSET_MPI,
126  RSET_PCMCIA,
127  RSET_PCIE,
128  RSET_DSL,
129  RSET_ENET0,
130  RSET_ENET1,
131  RSET_ENETDMA,
132  RSET_ENETDMAC,
133  RSET_ENETDMAS,
134  RSET_ENETSW,
135  RSET_EHCI0,
136  RSET_SDRAM,
137  RSET_MEMC,
138  RSET_DDR,
139  RSET_M2M,
140  RSET_ATM,
141  RSET_XTM,
142  RSET_XTMDMA,
143  RSET_XTMDMAC,
144  RSET_XTMDMAS,
145  RSET_PCM,
146  RSET_PCMDMA,
147  RSET_PCMDMAC,
148  RSET_PCMDMAS,
149  RSET_RNG,
150  RSET_MISC
151 };
152 
153 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
154 #define RSET_DSL_SIZE 4096
155 #define RSET_WDT_SIZE 12
156 #define BCM_6338_RSET_SPI_SIZE 64
157 #define BCM_6348_RSET_SPI_SIZE 64
158 #define BCM_6358_RSET_SPI_SIZE 1804
159 #define BCM_6368_RSET_SPI_SIZE 1804
160 #define RSET_ENET_SIZE 2048
161 #define RSET_ENETDMA_SIZE 2048
162 #define RSET_ENETSW_SIZE 65536
163 #define RSET_UART_SIZE 24
164 #define RSET_UDC_SIZE 256
165 #define RSET_OHCI_SIZE 256
166 #define RSET_EHCI_SIZE 256
167 #define RSET_USBD_SIZE 256
168 #define RSET_USBDMA_SIZE 1280
169 #define RSET_PCMCIA_SIZE 12
170 #define RSET_M2M_SIZE 256
171 #define RSET_ATM_SIZE 4096
172 #define RSET_XTM_SIZE 10240
173 #define RSET_XTMDMA_SIZE 256
174 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
175 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
176 #define RSET_RNG_SIZE 20
177 
178 /*
179  * 6328 register sets base address
180  */
181 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
182 #define BCM_6328_PERF_BASE (0xb0000000)
183 #define BCM_6328_TIMER_BASE (0xb0000040)
184 #define BCM_6328_WDT_BASE (0xb000005c)
185 #define BCM_6328_UART0_BASE (0xb0000100)
186 #define BCM_6328_UART1_BASE (0xb0000120)
187 #define BCM_6328_GPIO_BASE (0xb0000080)
188 #define BCM_6328_SPI_BASE (0xdeadbeef)
189 #define BCM_6328_UDC0_BASE (0xdeadbeef)
190 #define BCM_6328_USBDMA_BASE (0xb000c000)
191 #define BCM_6328_OHCI0_BASE (0xb0002600)
192 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
193 #define BCM_6328_USBH_PRIV_BASE (0xb0002700)
194 #define BCM_6328_USBD_BASE (0xb0002400)
195 #define BCM_6328_MPI_BASE (0xdeadbeef)
196 #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
197 #define BCM_6328_PCIE_BASE (0xb0e40000)
198 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
199 #define BCM_6328_DSL_BASE (0xb0001900)
200 #define BCM_6328_UBUS_BASE (0xdeadbeef)
201 #define BCM_6328_ENET0_BASE (0xdeadbeef)
202 #define BCM_6328_ENET1_BASE (0xdeadbeef)
203 #define BCM_6328_ENETDMA_BASE (0xb000d800)
204 #define BCM_6328_ENETDMAC_BASE (0xb000da00)
205 #define BCM_6328_ENETDMAS_BASE (0xb000dc00)
206 #define BCM_6328_ENETSW_BASE (0xb0e00000)
207 #define BCM_6328_EHCI0_BASE (0xb0002500)
208 #define BCM_6328_SDRAM_BASE (0xdeadbeef)
209 #define BCM_6328_MEMC_BASE (0xdeadbeef)
210 #define BCM_6328_DDR_BASE (0xb0003000)
211 #define BCM_6328_M2M_BASE (0xdeadbeef)
212 #define BCM_6328_ATM_BASE (0xdeadbeef)
213 #define BCM_6328_XTM_BASE (0xdeadbeef)
214 #define BCM_6328_XTMDMA_BASE (0xb000b800)
215 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
216 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
217 #define BCM_6328_PCM_BASE (0xb000a800)
218 #define BCM_6328_PCMDMA_BASE (0xdeadbeef)
219 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
220 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
221 #define BCM_6328_RNG_BASE (0xdeadbeef)
222 #define BCM_6328_MISC_BASE (0xb0001800)
223 /*
224  * 6338 register sets base address
225  */
226 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
227 #define BCM_6338_PERF_BASE (0xfffe0000)
228 #define BCM_6338_BB_BASE (0xfffe0100)
229 #define BCM_6338_TIMER_BASE (0xfffe0200)
230 #define BCM_6338_WDT_BASE (0xfffe021c)
231 #define BCM_6338_UART0_BASE (0xfffe0300)
232 #define BCM_6338_UART1_BASE (0xdeadbeef)
233 #define BCM_6338_GPIO_BASE (0xfffe0400)
234 #define BCM_6338_SPI_BASE (0xfffe0c00)
235 #define BCM_6338_UDC0_BASE (0xdeadbeef)
236 #define BCM_6338_USBDMA_BASE (0xfffe2400)
237 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
238 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
239 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
240 #define BCM_6338_USBD_BASE (0xdeadbeef)
241 #define BCM_6338_MPI_BASE (0xfffe3160)
242 #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
243 #define BCM_6338_PCIE_BASE (0xdeadbeef)
244 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
245 #define BCM_6338_DSL_BASE (0xfffe1000)
246 #define BCM_6338_UBUS_BASE (0xdeadbeef)
247 #define BCM_6338_ENET0_BASE (0xfffe2800)
248 #define BCM_6338_ENET1_BASE (0xdeadbeef)
249 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
250 #define BCM_6338_ENETDMAC_BASE (0xfffe2500)
251 #define BCM_6338_ENETDMAS_BASE (0xfffe2600)
252 #define BCM_6338_ENETSW_BASE (0xdeadbeef)
253 #define BCM_6338_EHCI0_BASE (0xdeadbeef)
254 #define BCM_6338_SDRAM_BASE (0xfffe3100)
255 #define BCM_6338_MEMC_BASE (0xdeadbeef)
256 #define BCM_6338_DDR_BASE (0xdeadbeef)
257 #define BCM_6338_M2M_BASE (0xdeadbeef)
258 #define BCM_6338_ATM_BASE (0xfffe2000)
259 #define BCM_6338_XTM_BASE (0xdeadbeef)
260 #define BCM_6338_XTMDMA_BASE (0xdeadbeef)
261 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
262 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
263 #define BCM_6338_PCM_BASE (0xdeadbeef)
264 #define BCM_6338_PCMDMA_BASE (0xdeadbeef)
265 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
266 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
267 #define BCM_6338_RNG_BASE (0xdeadbeef)
268 #define BCM_6338_MISC_BASE (0xdeadbeef)
269 
270 /*
271  * 6345 register sets base address
272  */
273 #define BCM_6345_DSL_LMEM_BASE (0xfff00000)
274 #define BCM_6345_PERF_BASE (0xfffe0000)
275 #define BCM_6345_BB_BASE (0xfffe0100)
276 #define BCM_6345_TIMER_BASE (0xfffe0200)
277 #define BCM_6345_WDT_BASE (0xfffe021c)
278 #define BCM_6345_UART0_BASE (0xfffe0300)
279 #define BCM_6345_UART1_BASE (0xdeadbeef)
280 #define BCM_6345_GPIO_BASE (0xfffe0400)
281 #define BCM_6345_SPI_BASE (0xdeadbeef)
282 #define BCM_6345_UDC0_BASE (0xdeadbeef)
283 #define BCM_6345_USBDMA_BASE (0xfffe2800)
284 #define BCM_6345_ENET0_BASE (0xfffe1800)
285 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
286 #define BCM_6345_ENETDMAC_BASE (0xfffe2900)
287 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
288 #define BCM_6345_ENETSW_BASE (0xdeadbeef)
289 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
290 #define BCM_6345_MPI_BASE (0xfffe2000)
291 #define BCM_6345_PCIE_BASE (0xdeadbeef)
292 #define BCM_6345_OHCI0_BASE (0xfffe2100)
293 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
294 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
295 #define BCM_6345_USBD_BASE (0xdeadbeef)
296 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
297 #define BCM_6345_DSL_BASE (0xdeadbeef)
298 #define BCM_6345_UBUS_BASE (0xdeadbeef)
299 #define BCM_6345_ENET1_BASE (0xdeadbeef)
300 #define BCM_6345_EHCI0_BASE (0xdeadbeef)
301 #define BCM_6345_SDRAM_BASE (0xfffe2300)
302 #define BCM_6345_MEMC_BASE (0xdeadbeef)
303 #define BCM_6345_DDR_BASE (0xdeadbeef)
304 #define BCM_6345_M2M_BASE (0xdeadbeef)
305 #define BCM_6345_ATM_BASE (0xfffe4000)
306 #define BCM_6345_XTM_BASE (0xdeadbeef)
307 #define BCM_6345_XTMDMA_BASE (0xdeadbeef)
308 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
309 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
310 #define BCM_6345_PCM_BASE (0xdeadbeef)
311 #define BCM_6345_PCMDMA_BASE (0xdeadbeef)
312 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
313 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
314 #define BCM_6345_RNG_BASE (0xdeadbeef)
315 #define BCM_6345_MISC_BASE (0xdeadbeef)
316 
317 /*
318  * 6348 register sets base address
319  */
320 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
321 #define BCM_6348_PERF_BASE (0xfffe0000)
322 #define BCM_6348_TIMER_BASE (0xfffe0200)
323 #define BCM_6348_WDT_BASE (0xfffe021c)
324 #define BCM_6348_UART0_BASE (0xfffe0300)
325 #define BCM_6348_UART1_BASE (0xdeadbeef)
326 #define BCM_6348_GPIO_BASE (0xfffe0400)
327 #define BCM_6348_SPI_BASE (0xfffe0c00)
328 #define BCM_6348_UDC0_BASE (0xfffe1000)
329 #define BCM_6348_USBDMA_BASE (0xdeadbeef)
330 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
331 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
332 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
333 #define BCM_6348_USBD_BASE (0xdeadbeef)
334 #define BCM_6348_MPI_BASE (0xfffe2000)
335 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
336 #define BCM_6348_PCIE_BASE (0xdeadbeef)
337 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
338 #define BCM_6348_M2M_BASE (0xfffe2800)
339 #define BCM_6348_DSL_BASE (0xfffe3000)
340 #define BCM_6348_ENET0_BASE (0xfffe6000)
341 #define BCM_6348_ENET1_BASE (0xfffe6800)
342 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
343 #define BCM_6348_ENETDMAC_BASE (0xfffe7100)
344 #define BCM_6348_ENETDMAS_BASE (0xfffe7200)
345 #define BCM_6348_ENETSW_BASE (0xdeadbeef)
346 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
347 #define BCM_6348_SDRAM_BASE (0xfffe2300)
348 #define BCM_6348_MEMC_BASE (0xdeadbeef)
349 #define BCM_6348_DDR_BASE (0xdeadbeef)
350 #define BCM_6348_ATM_BASE (0xfffe4000)
351 #define BCM_6348_XTM_BASE (0xdeadbeef)
352 #define BCM_6348_XTMDMA_BASE (0xdeadbeef)
353 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
354 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
355 #define BCM_6348_PCM_BASE (0xdeadbeef)
356 #define BCM_6348_PCMDMA_BASE (0xdeadbeef)
357 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
358 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
359 #define BCM_6348_RNG_BASE (0xdeadbeef)
360 #define BCM_6348_MISC_BASE (0xdeadbeef)
361 
362 /*
363  * 6358 register sets base address
364  */
365 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
366 #define BCM_6358_PERF_BASE (0xfffe0000)
367 #define BCM_6358_TIMER_BASE (0xfffe0040)
368 #define BCM_6358_WDT_BASE (0xfffe005c)
369 #define BCM_6358_UART0_BASE (0xfffe0100)
370 #define BCM_6358_UART1_BASE (0xfffe0120)
371 #define BCM_6358_GPIO_BASE (0xfffe0080)
372 #define BCM_6358_SPI_BASE (0xfffe0800)
373 #define BCM_6358_UDC0_BASE (0xfffe0800)
374 #define BCM_6358_USBDMA_BASE (0xdeadbeef)
375 #define BCM_6358_OHCI0_BASE (0xfffe1400)
376 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
377 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
378 #define BCM_6358_USBD_BASE (0xdeadbeef)
379 #define BCM_6358_MPI_BASE (0xfffe1000)
380 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
381 #define BCM_6358_PCIE_BASE (0xdeadbeef)
382 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
383 #define BCM_6358_M2M_BASE (0xdeadbeef)
384 #define BCM_6358_DSL_BASE (0xfffe3000)
385 #define BCM_6358_ENET0_BASE (0xfffe4000)
386 #define BCM_6358_ENET1_BASE (0xfffe4800)
387 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
388 #define BCM_6358_ENETDMAC_BASE (0xfffe5100)
389 #define BCM_6358_ENETDMAS_BASE (0xfffe5200)
390 #define BCM_6358_ENETSW_BASE (0xdeadbeef)
391 #define BCM_6358_EHCI0_BASE (0xfffe1300)
392 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
393 #define BCM_6358_MEMC_BASE (0xfffe1200)
394 #define BCM_6358_DDR_BASE (0xfffe12a0)
395 #define BCM_6358_ATM_BASE (0xfffe2000)
396 #define BCM_6358_XTM_BASE (0xdeadbeef)
397 #define BCM_6358_XTMDMA_BASE (0xdeadbeef)
398 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
399 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
400 #define BCM_6358_PCM_BASE (0xfffe1600)
401 #define BCM_6358_PCMDMA_BASE (0xfffe1800)
402 #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
403 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
404 #define BCM_6358_RNG_BASE (0xdeadbeef)
405 #define BCM_6358_MISC_BASE (0xdeadbeef)
406 
407 
408 /*
409  * 6368 register sets base address
410  */
411 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
412 #define BCM_6368_PERF_BASE (0xb0000000)
413 #define BCM_6368_TIMER_BASE (0xb0000040)
414 #define BCM_6368_WDT_BASE (0xb000005c)
415 #define BCM_6368_UART0_BASE (0xb0000100)
416 #define BCM_6368_UART1_BASE (0xb0000120)
417 #define BCM_6368_GPIO_BASE (0xb0000080)
418 #define BCM_6368_SPI_BASE (0xb0000800)
419 #define BCM_6368_UDC0_BASE (0xdeadbeef)
420 #define BCM_6368_USBDMA_BASE (0xb0004800)
421 #define BCM_6368_OHCI0_BASE (0xb0001600)
422 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
423 #define BCM_6368_USBH_PRIV_BASE (0xb0001700)
424 #define BCM_6368_USBD_BASE (0xb0001400)
425 #define BCM_6368_MPI_BASE (0xb0001000)
426 #define BCM_6368_PCMCIA_BASE (0xb0001054)
427 #define BCM_6368_PCIE_BASE (0xdeadbeef)
428 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
429 #define BCM_6368_M2M_BASE (0xdeadbeef)
430 #define BCM_6368_DSL_BASE (0xdeadbeef)
431 #define BCM_6368_ENET0_BASE (0xdeadbeef)
432 #define BCM_6368_ENET1_BASE (0xdeadbeef)
433 #define BCM_6368_ENETDMA_BASE (0xb0006800)
434 #define BCM_6368_ENETDMAC_BASE (0xb0006a00)
435 #define BCM_6368_ENETDMAS_BASE (0xb0006c00)
436 #define BCM_6368_ENETSW_BASE (0xb0f00000)
437 #define BCM_6368_EHCI0_BASE (0xb0001500)
438 #define BCM_6368_SDRAM_BASE (0xdeadbeef)
439 #define BCM_6368_MEMC_BASE (0xb0001200)
440 #define BCM_6368_DDR_BASE (0xb0001280)
441 #define BCM_6368_ATM_BASE (0xdeadbeef)
442 #define BCM_6368_XTM_BASE (0xb0001800)
443 #define BCM_6368_XTMDMA_BASE (0xb0005000)
444 #define BCM_6368_XTMDMAC_BASE (0xb0005200)
445 #define BCM_6368_XTMDMAS_BASE (0xb0005400)
446 #define BCM_6368_PCM_BASE (0xb0004000)
447 #define BCM_6368_PCMDMA_BASE (0xb0005800)
448 #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
449 #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
450 #define BCM_6368_RNG_BASE (0xb0004180)
451 #define BCM_6368_MISC_BASE (0xdeadbeef)
452 
453 
454 extern const unsigned long *bcm63xx_regs_base;
455 
456 #define __GEN_RSET_BASE(__cpu, __rset) \
457  case RSET_## __rset : \
458  return BCM_## __cpu ##_## __rset ##_BASE;
459 
460 #define __GEN_RSET(__cpu) \
461  switch (set) { \
462  __GEN_RSET_BASE(__cpu, DSL_LMEM) \
463  __GEN_RSET_BASE(__cpu, PERF) \
464  __GEN_RSET_BASE(__cpu, TIMER) \
465  __GEN_RSET_BASE(__cpu, WDT) \
466  __GEN_RSET_BASE(__cpu, UART0) \
467  __GEN_RSET_BASE(__cpu, UART1) \
468  __GEN_RSET_BASE(__cpu, GPIO) \
469  __GEN_RSET_BASE(__cpu, SPI) \
470  __GEN_RSET_BASE(__cpu, UDC0) \
471  __GEN_RSET_BASE(__cpu, OHCI0) \
472  __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
473  __GEN_RSET_BASE(__cpu, USBH_PRIV) \
474  __GEN_RSET_BASE(__cpu, USBD) \
475  __GEN_RSET_BASE(__cpu, USBDMA) \
476  __GEN_RSET_BASE(__cpu, MPI) \
477  __GEN_RSET_BASE(__cpu, PCMCIA) \
478  __GEN_RSET_BASE(__cpu, PCIE) \
479  __GEN_RSET_BASE(__cpu, DSL) \
480  __GEN_RSET_BASE(__cpu, ENET0) \
481  __GEN_RSET_BASE(__cpu, ENET1) \
482  __GEN_RSET_BASE(__cpu, ENETDMA) \
483  __GEN_RSET_BASE(__cpu, ENETDMAC) \
484  __GEN_RSET_BASE(__cpu, ENETDMAS) \
485  __GEN_RSET_BASE(__cpu, ENETSW) \
486  __GEN_RSET_BASE(__cpu, EHCI0) \
487  __GEN_RSET_BASE(__cpu, SDRAM) \
488  __GEN_RSET_BASE(__cpu, MEMC) \
489  __GEN_RSET_BASE(__cpu, DDR) \
490  __GEN_RSET_BASE(__cpu, M2M) \
491  __GEN_RSET_BASE(__cpu, ATM) \
492  __GEN_RSET_BASE(__cpu, XTM) \
493  __GEN_RSET_BASE(__cpu, XTMDMA) \
494  __GEN_RSET_BASE(__cpu, XTMDMAC) \
495  __GEN_RSET_BASE(__cpu, XTMDMAS) \
496  __GEN_RSET_BASE(__cpu, PCM) \
497  __GEN_RSET_BASE(__cpu, PCMDMA) \
498  __GEN_RSET_BASE(__cpu, PCMDMAC) \
499  __GEN_RSET_BASE(__cpu, PCMDMAS) \
500  __GEN_RSET_BASE(__cpu, RNG) \
501  __GEN_RSET_BASE(__cpu, MISC) \
502  }
503 
504 #define __GEN_CPU_REGS_TABLE(__cpu) \
505  [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
506  [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
507  [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
508  [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
509  [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
510  [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
511  [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
512  [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
513  [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
514  [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
515  [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
516  [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
517  [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \
518  [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \
519  [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
520  [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
521  [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
522  [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
523  [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
524  [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
525  [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
526  [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
527  [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
528  [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
529  [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
530  [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
531  [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
532  [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
533  [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
534  [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
535  [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
536  [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
537  [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
538  [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
539  [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
540  [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
541  [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
542  [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
543  [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
544  [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
545 
546 
547 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
548 {
549 #ifdef BCMCPU_RUNTIME_DETECT
550  return bcm63xx_regs_base[set];
551 #else
552 #ifdef CONFIG_BCM63XX_CPU_6328
553  __GEN_RSET(6328)
554 #endif
555 #ifdef CONFIG_BCM63XX_CPU_6338
556  __GEN_RSET(6338)
557 #endif
558 #ifdef CONFIG_BCM63XX_CPU_6345
559  __GEN_RSET(6345)
560 #endif
561 #ifdef CONFIG_BCM63XX_CPU_6348
562  __GEN_RSET(6348)
563 #endif
564 #ifdef CONFIG_BCM63XX_CPU_6358
565  __GEN_RSET(6358)
566 #endif
567 #ifdef CONFIG_BCM63XX_CPU_6368
568  __GEN_RSET(6368)
569 #endif
570 #endif
571  /* unreached */
572  return 0;
573 }
574 
575 /*
576  * IRQ number changes across CPU too
577  */
578 enum bcm63xx_irq {
579  IRQ_TIMER = 0,
580  IRQ_SPI,
581  IRQ_UART0,
582  IRQ_UART1,
583  IRQ_DSL,
584  IRQ_ENET0,
585  IRQ_ENET1,
586  IRQ_ENET_PHY,
587  IRQ_OHCI0,
588  IRQ_EHCI0,
589  IRQ_USBD,
590  IRQ_USBD_RXDMA0,
591  IRQ_USBD_TXDMA0,
592  IRQ_USBD_RXDMA1,
593  IRQ_USBD_TXDMA1,
594  IRQ_USBD_RXDMA2,
595  IRQ_USBD_TXDMA2,
596  IRQ_ENET0_RXDMA,
597  IRQ_ENET0_TXDMA,
598  IRQ_ENET1_RXDMA,
599  IRQ_ENET1_TXDMA,
600  IRQ_PCI,
601  IRQ_PCMCIA,
602  IRQ_ATM,
603  IRQ_ENETSW_RXDMA0,
604  IRQ_ENETSW_RXDMA1,
605  IRQ_ENETSW_RXDMA2,
606  IRQ_ENETSW_RXDMA3,
607  IRQ_ENETSW_TXDMA0,
608  IRQ_ENETSW_TXDMA1,
609  IRQ_ENETSW_TXDMA2,
610  IRQ_ENETSW_TXDMA3,
611  IRQ_XTM,
612  IRQ_XTM_DMA0,
613 };
614 
615 /*
616  * 6328 irqs
617  */
618 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
619 
620 #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
621 #define BCM_6328_SPI_IRQ 0
622 #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
623 #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
624 #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
625 #define BCM_6328_UDC0_IRQ 0
626 #define BCM_6328_ENET0_IRQ 0
627 #define BCM_6328_ENET1_IRQ 0
628 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
629 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
630 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
631 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
632 #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
633 #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
634 #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
635 #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
636 #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
637 #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
638 #define BCM_6328_PCMCIA_IRQ 0
639 #define BCM_6328_ENET0_RXDMA_IRQ 0
640 #define BCM_6328_ENET0_TXDMA_IRQ 0
641 #define BCM_6328_ENET1_RXDMA_IRQ 0
642 #define BCM_6328_ENET1_TXDMA_IRQ 0
643 #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
644 #define BCM_6328_ATM_IRQ 0
645 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
646 #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
647 #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
648 #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
649 #define BCM_6328_ENETSW_TXDMA0_IRQ 0
650 #define BCM_6328_ENETSW_TXDMA1_IRQ 0
651 #define BCM_6328_ENETSW_TXDMA2_IRQ 0
652 #define BCM_6328_ENETSW_TXDMA3_IRQ 0
653 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
654 #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
655 
656 #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
657 #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
658 #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
659 #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
660 #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
661 #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
662 
663 /*
664  * 6338 irqs
665  */
666 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
667 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
668 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
669 #define BCM_6338_UART1_IRQ 0
670 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
671 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
672 #define BCM_6338_ENET1_IRQ 0
673 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
674 #define BCM_6338_OHCI0_IRQ 0
675 #define BCM_6338_EHCI0_IRQ 0
676 #define BCM_6338_USBD_IRQ 0
677 #define BCM_6338_USBD_RXDMA0_IRQ 0
678 #define BCM_6338_USBD_TXDMA0_IRQ 0
679 #define BCM_6338_USBD_RXDMA1_IRQ 0
680 #define BCM_6338_USBD_TXDMA1_IRQ 0
681 #define BCM_6338_USBD_RXDMA2_IRQ 0
682 #define BCM_6338_USBD_TXDMA2_IRQ 0
683 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
684 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
685 #define BCM_6338_ENET1_RXDMA_IRQ 0
686 #define BCM_6338_ENET1_TXDMA_IRQ 0
687 #define BCM_6338_PCI_IRQ 0
688 #define BCM_6338_PCMCIA_IRQ 0
689 #define BCM_6338_ATM_IRQ 0
690 #define BCM_6338_ENETSW_RXDMA0_IRQ 0
691 #define BCM_6338_ENETSW_RXDMA1_IRQ 0
692 #define BCM_6338_ENETSW_RXDMA2_IRQ 0
693 #define BCM_6338_ENETSW_RXDMA3_IRQ 0
694 #define BCM_6338_ENETSW_TXDMA0_IRQ 0
695 #define BCM_6338_ENETSW_TXDMA1_IRQ 0
696 #define BCM_6338_ENETSW_TXDMA2_IRQ 0
697 #define BCM_6338_ENETSW_TXDMA3_IRQ 0
698 #define BCM_6338_XTM_IRQ 0
699 #define BCM_6338_XTM_DMA0_IRQ 0
700 
701 /*
702  * 6345 irqs
703  */
704 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
705 #define BCM_6345_SPI_IRQ 0
706 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
707 #define BCM_6345_UART1_IRQ 0
708 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
709 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
710 #define BCM_6345_ENET1_IRQ 0
711 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
712 #define BCM_6345_OHCI0_IRQ 0
713 #define BCM_6345_EHCI0_IRQ 0
714 #define BCM_6345_USBD_IRQ 0
715 #define BCM_6345_USBD_RXDMA0_IRQ 0
716 #define BCM_6345_USBD_TXDMA0_IRQ 0
717 #define BCM_6345_USBD_RXDMA1_IRQ 0
718 #define BCM_6345_USBD_TXDMA1_IRQ 0
719 #define BCM_6345_USBD_RXDMA2_IRQ 0
720 #define BCM_6345_USBD_TXDMA2_IRQ 0
721 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
722 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
723 #define BCM_6345_ENET1_RXDMA_IRQ 0
724 #define BCM_6345_ENET1_TXDMA_IRQ 0
725 #define BCM_6345_PCI_IRQ 0
726 #define BCM_6345_PCMCIA_IRQ 0
727 #define BCM_6345_ATM_IRQ 0
728 #define BCM_6345_ENETSW_RXDMA0_IRQ 0
729 #define BCM_6345_ENETSW_RXDMA1_IRQ 0
730 #define BCM_6345_ENETSW_RXDMA2_IRQ 0
731 #define BCM_6345_ENETSW_RXDMA3_IRQ 0
732 #define BCM_6345_ENETSW_TXDMA0_IRQ 0
733 #define BCM_6345_ENETSW_TXDMA1_IRQ 0
734 #define BCM_6345_ENETSW_TXDMA2_IRQ 0
735 #define BCM_6345_ENETSW_TXDMA3_IRQ 0
736 #define BCM_6345_XTM_IRQ 0
737 #define BCM_6345_XTM_DMA0_IRQ 0
738 
739 /*
740  * 6348 irqs
741  */
742 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
743 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
744 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
745 #define BCM_6348_UART1_IRQ 0
746 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
747 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
748 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
749 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
750 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
751 #define BCM_6348_EHCI0_IRQ 0
752 #define BCM_6348_USBD_IRQ 0
753 #define BCM_6348_USBD_RXDMA0_IRQ 0
754 #define BCM_6348_USBD_TXDMA0_IRQ 0
755 #define BCM_6348_USBD_RXDMA1_IRQ 0
756 #define BCM_6348_USBD_TXDMA1_IRQ 0
757 #define BCM_6348_USBD_RXDMA2_IRQ 0
758 #define BCM_6348_USBD_TXDMA2_IRQ 0
759 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
760 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
761 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
762 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
763 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
764 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
765 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
766 #define BCM_6348_ENETSW_RXDMA0_IRQ 0
767 #define BCM_6348_ENETSW_RXDMA1_IRQ 0
768 #define BCM_6348_ENETSW_RXDMA2_IRQ 0
769 #define BCM_6348_ENETSW_RXDMA3_IRQ 0
770 #define BCM_6348_ENETSW_TXDMA0_IRQ 0
771 #define BCM_6348_ENETSW_TXDMA1_IRQ 0
772 #define BCM_6348_ENETSW_TXDMA2_IRQ 0
773 #define BCM_6348_ENETSW_TXDMA3_IRQ 0
774 #define BCM_6348_XTM_IRQ 0
775 #define BCM_6348_XTM_DMA0_IRQ 0
776 
777 /*
778  * 6358 irqs
779  */
780 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
781 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
782 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
783 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
784 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
785 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
786 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
787 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
788 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
789 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
790 #define BCM_6358_USBD_IRQ 0
791 #define BCM_6358_USBD_RXDMA0_IRQ 0
792 #define BCM_6358_USBD_TXDMA0_IRQ 0
793 #define BCM_6358_USBD_RXDMA1_IRQ 0
794 #define BCM_6358_USBD_TXDMA1_IRQ 0
795 #define BCM_6358_USBD_RXDMA2_IRQ 0
796 #define BCM_6358_USBD_TXDMA2_IRQ 0
797 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
798 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
799 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
800 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
801 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
802 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
803 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
804 #define BCM_6358_ENETSW_RXDMA0_IRQ 0
805 #define BCM_6358_ENETSW_RXDMA1_IRQ 0
806 #define BCM_6358_ENETSW_RXDMA2_IRQ 0
807 #define BCM_6358_ENETSW_RXDMA3_IRQ 0
808 #define BCM_6358_ENETSW_TXDMA0_IRQ 0
809 #define BCM_6358_ENETSW_TXDMA1_IRQ 0
810 #define BCM_6358_ENETSW_TXDMA2_IRQ 0
811 #define BCM_6358_ENETSW_TXDMA3_IRQ 0
812 #define BCM_6358_XTM_IRQ 0
813 #define BCM_6358_XTM_DMA0_IRQ 0
814 
815 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
816 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
817 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
818 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
819 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
820 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
821 
822 /*
823  * 6368 irqs
824  */
825 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
826 
827 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
828 #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
829 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
830 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
831 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
832 #define BCM_6368_ENET0_IRQ 0
833 #define BCM_6368_ENET1_IRQ 0
834 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
835 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
836 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
837 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
838 #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)
839 #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)
840 #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)
841 #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)
842 #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)
843 #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)
844 #define BCM_6368_PCMCIA_IRQ 0
845 #define BCM_6368_ENET0_RXDMA_IRQ 0
846 #define BCM_6368_ENET0_TXDMA_IRQ 0
847 #define BCM_6368_ENET1_RXDMA_IRQ 0
848 #define BCM_6368_ENET1_TXDMA_IRQ 0
849 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
850 #define BCM_6368_ATM_IRQ 0
851 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
852 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
853 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
854 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
855 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
856 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
857 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
858 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
859 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
860 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
861 
862 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
863 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
864 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
865 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
866 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
867 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
868 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
869 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
870 
871 extern const int *bcm63xx_irqs;
872 
873 #define __GEN_CPU_IRQ_TABLE(__cpu) \
874  [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
875  [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
876  [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
877  [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
878  [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
879  [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
880  [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
881  [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
882  [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
883  [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
884  [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
885  [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \
886  [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \
887  [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \
888  [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \
889  [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \
890  [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \
891  [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
892  [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
893  [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
894  [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
895  [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
896  [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
897  [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
898  [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
899  [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
900  [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
901  [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
902  [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
903  [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
904  [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
905  [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
906  [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
907  [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
908 
909 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
910 {
911  return bcm63xx_irqs[irq];
912 }
913 
914 /*
915  * return installed memory size
916  */
917 unsigned int bcm63xx_get_memory_size(void);
918 
919 void bcm63xx_machine_halt(void);
920 
921 void bcm63xx_machine_reboot(void);
922 
923 #endif /* !BCM63XX_CPU_H_ */
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