#include <linux/types.h>
#include <linux/init.h>

Macros
#define	BCM6328_CPU_ID 0x6328

#define	BCM6338_CPU_ID 0x6338

#define	BCM6345_CPU_ID 0x6345

#define	BCM6348_CPU_ID 0x6348

#define	BCM6358_CPU_ID 0x6358

#define	BCM6368_CPU_ID 0x6368

#define	BCMCPU_IS_6328() (0)

#define	BCMCPU_IS_6338() (0)

#define	BCMCPU_IS_6345() (0)

#define	BCMCPU_IS_6348() (0)

#define	BCMCPU_IS_6358() (0)

#define	BCMCPU_IS_6368() (0)

#define	RSET_DSL_LMEM_SIZE (64 * 1024 * 4)

#define	RSET_DSL_SIZE 4096

#define	RSET_WDT_SIZE 12

#define	BCM_6338_RSET_SPI_SIZE 64

#define	BCM_6348_RSET_SPI_SIZE 64

#define	BCM_6358_RSET_SPI_SIZE 1804

#define	BCM_6368_RSET_SPI_SIZE 1804

#define	RSET_ENET_SIZE 2048

#define	RSET_ENETDMA_SIZE 2048

#define	RSET_ENETSW_SIZE 65536

#define	RSET_UART_SIZE 24

#define	RSET_UDC_SIZE 256

#define	RSET_OHCI_SIZE 256

#define	RSET_EHCI_SIZE 256

#define	RSET_USBD_SIZE 256

#define	RSET_USBDMA_SIZE 1280

#define	RSET_PCMCIA_SIZE 12

#define	RSET_M2M_SIZE 256

#define	RSET_ATM_SIZE 4096

#define	RSET_XTM_SIZE 10240

#define	RSET_XTMDMA_SIZE 256

#define	RSET_XTMDMAC_SIZE(chans) (16 * (chans))

#define	RSET_XTMDMAS_SIZE(chans) (16 * (chans))

#define	RSET_RNG_SIZE 20

#define	BCM_6328_DSL_LMEM_BASE (0xdeadbeef)

#define	BCM_6328_PERF_BASE (0xb0000000)

#define	BCM_6328_TIMER_BASE (0xb0000040)

#define	BCM_6328_WDT_BASE (0xb000005c)

#define	BCM_6328_UART0_BASE (0xb0000100)

#define	BCM_6328_UART1_BASE (0xb0000120)

#define	BCM_6328_GPIO_BASE (0xb0000080)

#define	BCM_6328_SPI_BASE (0xdeadbeef)

#define	BCM_6328_UDC0_BASE (0xdeadbeef)

#define	BCM_6328_USBDMA_BASE (0xb000c000)

#define	BCM_6328_OHCI0_BASE (0xb0002600)

#define	BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)

#define	BCM_6328_USBH_PRIV_BASE (0xb0002700)

#define	BCM_6328_USBD_BASE (0xb0002400)

#define	BCM_6328_MPI_BASE (0xdeadbeef)

#define	BCM_6328_PCMCIA_BASE (0xdeadbeef)

#define	BCM_6328_PCIE_BASE (0xb0e40000)

#define	BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)

#define	BCM_6328_DSL_BASE (0xb0001900)

#define	BCM_6328_UBUS_BASE (0xdeadbeef)

#define	BCM_6328_ENET0_BASE (0xdeadbeef)

#define	BCM_6328_ENET1_BASE (0xdeadbeef)

#define	BCM_6328_ENETDMA_BASE (0xb000d800)

#define	BCM_6328_ENETDMAC_BASE (0xb000da00)

#define	BCM_6328_ENETDMAS_BASE (0xb000dc00)

#define	BCM_6328_ENETSW_BASE (0xb0e00000)

#define	BCM_6328_EHCI0_BASE (0xb0002500)

#define	BCM_6328_SDRAM_BASE (0xdeadbeef)

#define	BCM_6328_MEMC_BASE (0xdeadbeef)

#define	BCM_6328_DDR_BASE (0xb0003000)

#define	BCM_6328_M2M_BASE (0xdeadbeef)

#define	BCM_6328_ATM_BASE (0xdeadbeef)

#define	BCM_6328_XTM_BASE (0xdeadbeef)

#define	BCM_6328_XTMDMA_BASE (0xb000b800)

#define	BCM_6328_XTMDMAC_BASE (0xdeadbeef)

#define	BCM_6328_XTMDMAS_BASE (0xdeadbeef)

#define	BCM_6328_PCM_BASE (0xb000a800)

#define	BCM_6328_PCMDMA_BASE (0xdeadbeef)

#define	BCM_6328_PCMDMAC_BASE (0xdeadbeef)

#define	BCM_6328_PCMDMAS_BASE (0xdeadbeef)

#define	BCM_6328_RNG_BASE (0xdeadbeef)

#define	BCM_6328_MISC_BASE (0xb0001800)

#define	BCM_6338_DSL_LMEM_BASE (0xfff00000)

#define	BCM_6338_PERF_BASE (0xfffe0000)

#define	BCM_6338_BB_BASE (0xfffe0100)

#define	BCM_6338_TIMER_BASE (0xfffe0200)

#define	BCM_6338_WDT_BASE (0xfffe021c)

#define	BCM_6338_UART0_BASE (0xfffe0300)

#define	BCM_6338_UART1_BASE (0xdeadbeef)

#define	BCM_6338_GPIO_BASE (0xfffe0400)

#define	BCM_6338_SPI_BASE (0xfffe0c00)

#define	BCM_6338_UDC0_BASE (0xdeadbeef)

#define	BCM_6338_USBDMA_BASE (0xfffe2400)

#define	BCM_6338_OHCI0_BASE (0xdeadbeef)

#define	BCM_6338_OHCI_PRIV_BASE (0xfffe3000)

#define	BCM_6338_USBH_PRIV_BASE (0xdeadbeef)

#define	BCM_6338_USBD_BASE (0xdeadbeef)

#define	BCM_6338_MPI_BASE (0xfffe3160)

#define	BCM_6338_PCMCIA_BASE (0xdeadbeef)

#define	BCM_6338_PCIE_BASE (0xdeadbeef)

#define	BCM_6338_SDRAM_REGS_BASE (0xfffe3100)

#define	BCM_6338_DSL_BASE (0xfffe1000)

#define	BCM_6338_UBUS_BASE (0xdeadbeef)

#define	BCM_6338_ENET0_BASE (0xfffe2800)

#define	BCM_6338_ENET1_BASE (0xdeadbeef)

#define	BCM_6338_ENETDMA_BASE (0xfffe2400)

#define	BCM_6338_ENETDMAC_BASE (0xfffe2500)

#define	BCM_6338_ENETDMAS_BASE (0xfffe2600)

#define	BCM_6338_ENETSW_BASE (0xdeadbeef)

#define	BCM_6338_EHCI0_BASE (0xdeadbeef)

#define	BCM_6338_SDRAM_BASE (0xfffe3100)

#define	BCM_6338_MEMC_BASE (0xdeadbeef)

#define	BCM_6338_DDR_BASE (0xdeadbeef)

#define	BCM_6338_M2M_BASE (0xdeadbeef)

#define	BCM_6338_ATM_BASE (0xfffe2000)

#define	BCM_6338_XTM_BASE (0xdeadbeef)

#define	BCM_6338_XTMDMA_BASE (0xdeadbeef)

#define	BCM_6338_XTMDMAC_BASE (0xdeadbeef)

#define	BCM_6338_XTMDMAS_BASE (0xdeadbeef)

#define	BCM_6338_PCM_BASE (0xdeadbeef)

#define	BCM_6338_PCMDMA_BASE (0xdeadbeef)

#define	BCM_6338_PCMDMAC_BASE (0xdeadbeef)

#define	BCM_6338_PCMDMAS_BASE (0xdeadbeef)

#define	BCM_6338_RNG_BASE (0xdeadbeef)

#define	BCM_6338_MISC_BASE (0xdeadbeef)

#define	BCM_6345_DSL_LMEM_BASE (0xfff00000)

#define	BCM_6345_PERF_BASE (0xfffe0000)

#define	BCM_6345_BB_BASE (0xfffe0100)

#define	BCM_6345_TIMER_BASE (0xfffe0200)

#define	BCM_6345_WDT_BASE (0xfffe021c)

#define	BCM_6345_UART0_BASE (0xfffe0300)

#define	BCM_6345_UART1_BASE (0xdeadbeef)

#define	BCM_6345_GPIO_BASE (0xfffe0400)

#define	BCM_6345_SPI_BASE (0xdeadbeef)

#define	BCM_6345_UDC0_BASE (0xdeadbeef)

#define	BCM_6345_USBDMA_BASE (0xfffe2800)

#define	BCM_6345_ENET0_BASE (0xfffe1800)

#define	BCM_6345_ENETDMA_BASE (0xfffe2800)

#define	BCM_6345_ENETDMAC_BASE (0xfffe2900)

#define	BCM_6345_ENETDMAS_BASE (0xfffe2a00)

#define	BCM_6345_ENETSW_BASE (0xdeadbeef)

#define	BCM_6345_PCMCIA_BASE (0xfffe2028)

#define	BCM_6345_MPI_BASE (0xfffe2000)

#define	BCM_6345_PCIE_BASE (0xdeadbeef)

#define	BCM_6345_OHCI0_BASE (0xfffe2100)

#define	BCM_6345_OHCI_PRIV_BASE (0xfffe2200)

#define	BCM_6345_USBH_PRIV_BASE (0xdeadbeef)

#define	BCM_6345_USBD_BASE (0xdeadbeef)

#define	BCM_6345_SDRAM_REGS_BASE (0xfffe2300)

#define	BCM_6345_DSL_BASE (0xdeadbeef)

#define	BCM_6345_UBUS_BASE (0xdeadbeef)

#define	BCM_6345_ENET1_BASE (0xdeadbeef)

#define	BCM_6345_EHCI0_BASE (0xdeadbeef)

#define	BCM_6345_SDRAM_BASE (0xfffe2300)

#define	BCM_6345_MEMC_BASE (0xdeadbeef)

#define	BCM_6345_DDR_BASE (0xdeadbeef)

#define	BCM_6345_M2M_BASE (0xdeadbeef)

#define	BCM_6345_ATM_BASE (0xfffe4000)

#define	BCM_6345_XTM_BASE (0xdeadbeef)

#define	BCM_6345_XTMDMA_BASE (0xdeadbeef)

#define	BCM_6345_XTMDMAC_BASE (0xdeadbeef)

#define	BCM_6345_XTMDMAS_BASE (0xdeadbeef)

#define	BCM_6345_PCM_BASE (0xdeadbeef)

#define	BCM_6345_PCMDMA_BASE (0xdeadbeef)

#define	BCM_6345_PCMDMAC_BASE (0xdeadbeef)

#define	BCM_6345_PCMDMAS_BASE (0xdeadbeef)

#define	BCM_6345_RNG_BASE (0xdeadbeef)

#define	BCM_6345_MISC_BASE (0xdeadbeef)

#define	BCM_6348_DSL_LMEM_BASE (0xfff00000)

#define	BCM_6348_PERF_BASE (0xfffe0000)

#define	BCM_6348_TIMER_BASE (0xfffe0200)

#define	BCM_6348_WDT_BASE (0xfffe021c)

#define	BCM_6348_UART0_BASE (0xfffe0300)

#define	BCM_6348_UART1_BASE (0xdeadbeef)

#define	BCM_6348_GPIO_BASE (0xfffe0400)

#define	BCM_6348_SPI_BASE (0xfffe0c00)

#define	BCM_6348_UDC0_BASE (0xfffe1000)

#define	BCM_6348_USBDMA_BASE (0xdeadbeef)

#define	BCM_6348_OHCI0_BASE (0xfffe1b00)

#define	BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)

#define	BCM_6348_USBH_PRIV_BASE (0xdeadbeef)

#define	BCM_6348_USBD_BASE (0xdeadbeef)

#define	BCM_6348_MPI_BASE (0xfffe2000)

#define	BCM_6348_PCMCIA_BASE (0xfffe2054)

#define	BCM_6348_PCIE_BASE (0xdeadbeef)

#define	BCM_6348_SDRAM_REGS_BASE (0xfffe2300)

#define	BCM_6348_M2M_BASE (0xfffe2800)

#define	BCM_6348_DSL_BASE (0xfffe3000)

#define	BCM_6348_ENET0_BASE (0xfffe6000)

#define	BCM_6348_ENET1_BASE (0xfffe6800)

#define	BCM_6348_ENETDMA_BASE (0xfffe7000)

#define	BCM_6348_ENETDMAC_BASE (0xfffe7100)

#define	BCM_6348_ENETDMAS_BASE (0xfffe7200)

#define	BCM_6348_ENETSW_BASE (0xdeadbeef)

#define	BCM_6348_EHCI0_BASE (0xdeadbeef)

#define	BCM_6348_SDRAM_BASE (0xfffe2300)

#define	BCM_6348_MEMC_BASE (0xdeadbeef)

#define	BCM_6348_DDR_BASE (0xdeadbeef)

#define	BCM_6348_ATM_BASE (0xfffe4000)

#define	BCM_6348_XTM_BASE (0xdeadbeef)

#define	BCM_6348_XTMDMA_BASE (0xdeadbeef)

#define	BCM_6348_XTMDMAC_BASE (0xdeadbeef)

#define	BCM_6348_XTMDMAS_BASE (0xdeadbeef)

#define	BCM_6348_PCM_BASE (0xdeadbeef)

#define	BCM_6348_PCMDMA_BASE (0xdeadbeef)

#define	BCM_6348_PCMDMAC_BASE (0xdeadbeef)

#define	BCM_6348_PCMDMAS_BASE (0xdeadbeef)

#define	BCM_6348_RNG_BASE (0xdeadbeef)

#define	BCM_6348_MISC_BASE (0xdeadbeef)

#define	BCM_6358_DSL_LMEM_BASE (0xfff00000)

#define	BCM_6358_PERF_BASE (0xfffe0000)

#define	BCM_6358_TIMER_BASE (0xfffe0040)

#define	BCM_6358_WDT_BASE (0xfffe005c)

#define	BCM_6358_UART0_BASE (0xfffe0100)

#define	BCM_6358_UART1_BASE (0xfffe0120)

#define	BCM_6358_GPIO_BASE (0xfffe0080)

#define	BCM_6358_SPI_BASE (0xfffe0800)

#define	BCM_6358_UDC0_BASE (0xfffe0800)

#define	BCM_6358_USBDMA_BASE (0xdeadbeef)

#define	BCM_6358_OHCI0_BASE (0xfffe1400)

#define	BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)

#define	BCM_6358_USBH_PRIV_BASE (0xfffe1500)

#define	BCM_6358_USBD_BASE (0xdeadbeef)

#define	BCM_6358_MPI_BASE (0xfffe1000)

#define	BCM_6358_PCMCIA_BASE (0xfffe1054)

#define	BCM_6358_PCIE_BASE (0xdeadbeef)

#define	BCM_6358_SDRAM_REGS_BASE (0xfffe2300)

#define	BCM_6358_M2M_BASE (0xdeadbeef)

#define	BCM_6358_DSL_BASE (0xfffe3000)

#define	BCM_6358_ENET0_BASE (0xfffe4000)

#define	BCM_6358_ENET1_BASE (0xfffe4800)

#define	BCM_6358_ENETDMA_BASE (0xfffe5000)

#define	BCM_6358_ENETDMAC_BASE (0xfffe5100)

#define	BCM_6358_ENETDMAS_BASE (0xfffe5200)

#define	BCM_6358_ENETSW_BASE (0xdeadbeef)

#define	BCM_6358_EHCI0_BASE (0xfffe1300)

#define	BCM_6358_SDRAM_BASE (0xdeadbeef)

#define	BCM_6358_MEMC_BASE (0xfffe1200)

#define	BCM_6358_DDR_BASE (0xfffe12a0)

#define	BCM_6358_ATM_BASE (0xfffe2000)

#define	BCM_6358_XTM_BASE (0xdeadbeef)

#define	BCM_6358_XTMDMA_BASE (0xdeadbeef)

#define	BCM_6358_XTMDMAC_BASE (0xdeadbeef)

#define	BCM_6358_XTMDMAS_BASE (0xdeadbeef)

#define	BCM_6358_PCM_BASE (0xfffe1600)

#define	BCM_6358_PCMDMA_BASE (0xfffe1800)

#define	BCM_6358_PCMDMAC_BASE (0xfffe1900)

#define	BCM_6358_PCMDMAS_BASE (0xfffe1a00)

#define	BCM_6358_RNG_BASE (0xdeadbeef)

#define	BCM_6358_MISC_BASE (0xdeadbeef)

#define	BCM_6368_DSL_LMEM_BASE (0xdeadbeef)

#define	BCM_6368_PERF_BASE (0xb0000000)

#define	BCM_6368_TIMER_BASE (0xb0000040)

#define	BCM_6368_WDT_BASE (0xb000005c)

#define	BCM_6368_UART0_BASE (0xb0000100)

#define	BCM_6368_UART1_BASE (0xb0000120)

#define	BCM_6368_GPIO_BASE (0xb0000080)

#define	BCM_6368_SPI_BASE (0xb0000800)

#define	BCM_6368_UDC0_BASE (0xdeadbeef)

#define	BCM_6368_USBDMA_BASE (0xb0004800)

#define	BCM_6368_OHCI0_BASE (0xb0001600)

#define	BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)

#define	BCM_6368_USBH_PRIV_BASE (0xb0001700)

#define	BCM_6368_USBD_BASE (0xb0001400)

#define	BCM_6368_MPI_BASE (0xb0001000)

#define	BCM_6368_PCMCIA_BASE (0xb0001054)

#define	BCM_6368_PCIE_BASE (0xdeadbeef)

#define	BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)

#define	BCM_6368_M2M_BASE (0xdeadbeef)

#define	BCM_6368_DSL_BASE (0xdeadbeef)

#define	BCM_6368_ENET0_BASE (0xdeadbeef)

#define	BCM_6368_ENET1_BASE (0xdeadbeef)

#define	BCM_6368_ENETDMA_BASE (0xb0006800)

#define	BCM_6368_ENETDMAC_BASE (0xb0006a00)

#define	BCM_6368_ENETDMAS_BASE (0xb0006c00)

#define	BCM_6368_ENETSW_BASE (0xb0f00000)

#define	BCM_6368_EHCI0_BASE (0xb0001500)

#define	BCM_6368_SDRAM_BASE (0xdeadbeef)

#define	BCM_6368_MEMC_BASE (0xb0001200)

#define	BCM_6368_DDR_BASE (0xb0001280)

#define	BCM_6368_ATM_BASE (0xdeadbeef)

#define	BCM_6368_XTM_BASE (0xb0001800)

#define	BCM_6368_XTMDMA_BASE (0xb0005000)

#define	BCM_6368_XTMDMAC_BASE (0xb0005200)

#define	BCM_6368_XTMDMAS_BASE (0xb0005400)

#define	BCM_6368_PCM_BASE (0xb0004000)

#define	BCM_6368_PCMDMA_BASE (0xb0005800)

#define	BCM_6368_PCMDMAC_BASE (0xb0005a00)

#define	BCM_6368_PCMDMAS_BASE (0xb0005c00)

#define	BCM_6368_RNG_BASE (0xb0004180)

#define	BCM_6368_MISC_BASE (0xdeadbeef)

#define	__GEN_RSET_BASE(__cpu, __rset)

#define	__GEN_RSET(__cpu)

#define	__GEN_CPU_REGS_TABLE(__cpu)

#define	BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)

#define	BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)

#define	BCM_6328_SPI_IRQ 0

#define	BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)

#define	BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)

#define	BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

#define	BCM_6328_UDC0_IRQ 0

#define	BCM_6328_ENET0_IRQ 0

#define	BCM_6328_ENET1_IRQ 0

#define	BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)

#define	BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)

#define	BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)

#define	BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)

#define	BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)

#define	BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)

#define	BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)

#define	BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)

#define	BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)

#define	BCM_6328_PCMCIA_IRQ 0

#define	BCM_6328_ENET0_RXDMA_IRQ 0

#define	BCM_6328_ENET0_TXDMA_IRQ 0

#define	BCM_6328_ENET1_RXDMA_IRQ 0

#define	BCM_6328_ENET1_TXDMA_IRQ 0

#define	BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)

#define	BCM_6328_ATM_IRQ 0

#define	BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)

#define	BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)

#define	BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)

#define	BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)

#define	BCM_6328_ENETSW_TXDMA0_IRQ 0

#define	BCM_6328_ENETSW_TXDMA1_IRQ 0

#define	BCM_6328_ENETSW_TXDMA2_IRQ 0

#define	BCM_6328_ENETSW_TXDMA3_IRQ 0

#define	BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)

#define	BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)

#define	BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)

#define	BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)

#define	BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)

#define	BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)

#define	BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)

#define	BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

#define	BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

#define	BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6338_UART1_IRQ 0

#define	BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)

#define	BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6338_ENET1_IRQ 0

#define	BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

#define	BCM_6338_OHCI0_IRQ 0

#define	BCM_6338_EHCI0_IRQ 0

#define	BCM_6338_USBD_IRQ 0

#define	BCM_6338_USBD_RXDMA0_IRQ 0

#define	BCM_6338_USBD_TXDMA0_IRQ 0

#define	BCM_6338_USBD_RXDMA1_IRQ 0

#define	BCM_6338_USBD_TXDMA1_IRQ 0

#define	BCM_6338_USBD_RXDMA2_IRQ 0

#define	BCM_6338_USBD_TXDMA2_IRQ 0

#define	BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)

#define	BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)

#define	BCM_6338_ENET1_RXDMA_IRQ 0

#define	BCM_6338_ENET1_TXDMA_IRQ 0

#define	BCM_6338_PCI_IRQ 0

#define	BCM_6338_PCMCIA_IRQ 0

#define	BCM_6338_ATM_IRQ 0

#define	BCM_6338_ENETSW_RXDMA0_IRQ 0

#define	BCM_6338_ENETSW_RXDMA1_IRQ 0

#define	BCM_6338_ENETSW_RXDMA2_IRQ 0

#define	BCM_6338_ENETSW_RXDMA3_IRQ 0

#define	BCM_6338_ENETSW_TXDMA0_IRQ 0

#define	BCM_6338_ENETSW_TXDMA1_IRQ 0

#define	BCM_6338_ENETSW_TXDMA2_IRQ 0

#define	BCM_6338_ENETSW_TXDMA3_IRQ 0

#define	BCM_6338_XTM_IRQ 0

#define	BCM_6338_XTM_DMA0_IRQ 0

#define	BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

#define	BCM_6345_SPI_IRQ 0

#define	BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6345_UART1_IRQ 0

#define	BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)

#define	BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6345_ENET1_IRQ 0

#define	BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)

#define	BCM_6345_OHCI0_IRQ 0

#define	BCM_6345_EHCI0_IRQ 0

#define	BCM_6345_USBD_IRQ 0

#define	BCM_6345_USBD_RXDMA0_IRQ 0

#define	BCM_6345_USBD_TXDMA0_IRQ 0

#define	BCM_6345_USBD_RXDMA1_IRQ 0

#define	BCM_6345_USBD_TXDMA1_IRQ 0

#define	BCM_6345_USBD_RXDMA2_IRQ 0

#define	BCM_6345_USBD_TXDMA2_IRQ 0

#define	BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)

#define	BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)

#define	BCM_6345_ENET1_RXDMA_IRQ 0

#define	BCM_6345_ENET1_TXDMA_IRQ 0

#define	BCM_6345_PCI_IRQ 0

#define	BCM_6345_PCMCIA_IRQ 0

#define	BCM_6345_ATM_IRQ 0

#define	BCM_6345_ENETSW_RXDMA0_IRQ 0

#define	BCM_6345_ENETSW_RXDMA1_IRQ 0

#define	BCM_6345_ENETSW_RXDMA2_IRQ 0

#define	BCM_6345_ENETSW_RXDMA3_IRQ 0

#define	BCM_6345_ENETSW_TXDMA0_IRQ 0

#define	BCM_6345_ENETSW_TXDMA1_IRQ 0

#define	BCM_6345_ENETSW_TXDMA2_IRQ 0

#define	BCM_6345_ENETSW_TXDMA3_IRQ 0

#define	BCM_6345_XTM_IRQ 0

#define	BCM_6345_XTM_DMA0_IRQ 0

#define	BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

#define	BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

#define	BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6348_UART1_IRQ 0

#define	BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

#define	BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)

#define	BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

#define	BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)

#define	BCM_6348_EHCI0_IRQ 0

#define	BCM_6348_USBD_IRQ 0

#define	BCM_6348_USBD_RXDMA0_IRQ 0

#define	BCM_6348_USBD_TXDMA0_IRQ 0

#define	BCM_6348_USBD_RXDMA1_IRQ 0

#define	BCM_6348_USBD_TXDMA1_IRQ 0

#define	BCM_6348_USBD_RXDMA2_IRQ 0

#define	BCM_6348_USBD_TXDMA2_IRQ 0

#define	BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)

#define	BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)

#define	BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)

#define	BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)

#define	BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)

#define	BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)

#define	BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)

#define	BCM_6348_ENETSW_RXDMA0_IRQ 0

#define	BCM_6348_ENETSW_RXDMA1_IRQ 0

#define	BCM_6348_ENETSW_RXDMA2_IRQ 0

#define	BCM_6348_ENETSW_RXDMA3_IRQ 0

#define	BCM_6348_ENETSW_TXDMA0_IRQ 0

#define	BCM_6348_ENETSW_TXDMA1_IRQ 0

#define	BCM_6348_ENETSW_TXDMA2_IRQ 0

#define	BCM_6348_ENETSW_TXDMA3_IRQ 0

#define	BCM_6348_XTM_IRQ 0

#define	BCM_6348_XTM_DMA0_IRQ 0

#define	BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

#define	BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

#define	BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)

#define	BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)

#define	BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)

#define	BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

#define	BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)

#define	BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)

#define	BCM_6358_USBD_IRQ 0

#define	BCM_6358_USBD_RXDMA0_IRQ 0

#define	BCM_6358_USBD_TXDMA0_IRQ 0

#define	BCM_6358_USBD_RXDMA1_IRQ 0

#define	BCM_6358_USBD_TXDMA1_IRQ 0

#define	BCM_6358_USBD_RXDMA2_IRQ 0

#define	BCM_6358_USBD_TXDMA2_IRQ 0

#define	BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)

#define	BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)

#define	BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)

#define	BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)

#define	BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)

#define	BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)

#define	BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)

#define	BCM_6358_ENETSW_RXDMA0_IRQ 0

#define	BCM_6358_ENETSW_RXDMA1_IRQ 0

#define	BCM_6358_ENETSW_RXDMA2_IRQ 0

#define	BCM_6358_ENETSW_RXDMA3_IRQ 0

#define	BCM_6358_ENETSW_TXDMA0_IRQ 0

#define	BCM_6358_ENETSW_TXDMA1_IRQ 0

#define	BCM_6358_ENETSW_TXDMA2_IRQ 0

#define	BCM_6358_ENETSW_TXDMA3_IRQ 0

#define	BCM_6358_XTM_IRQ 0

#define	BCM_6358_XTM_DMA0_IRQ 0

#define	BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)

#define	BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)

#define	BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)

#define	BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)

#define	BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)

#define	BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)

#define	BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)

#define	BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

#define	BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

#define	BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

#define	BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)

#define	BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

#define	BCM_6368_ENET0_IRQ 0

#define	BCM_6368_ENET1_IRQ 0

#define	BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)

#define	BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)

#define	BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)

#define	BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)

#define	BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)

#define	BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)

#define	BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)

#define	BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)

#define	BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)

#define	BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)

#define	BCM_6368_PCMCIA_IRQ 0

#define	BCM_6368_ENET0_RXDMA_IRQ 0

#define	BCM_6368_ENET0_TXDMA_IRQ 0

#define	BCM_6368_ENET1_RXDMA_IRQ 0

#define	BCM_6368_ENET1_TXDMA_IRQ 0

#define	BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)

#define	BCM_6368_ATM_IRQ 0

#define	BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)

#define	BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)

#define	BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)

#define	BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)

#define	BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)

#define	BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)

#define	BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)

#define	BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)

#define	BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)

#define	BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)

#define	BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)

#define	BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)

#define	BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)

#define	BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)

#define	BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)

#define	BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)

#define	BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)

#define	BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)

#define	__GEN_CPU_IRQ_TABLE(__cpu)

Enumerations
enum	bcm63xx_regs_set { RSET_DSL_LMEM = 0, RSET_PERF, RSET_TIMER, RSET_WDT, RSET_UART0, RSET_UART1, RSET_GPIO, RSET_SPI, RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, RSET_USBH_PRIV, RSET_USBD, RSET_USBDMA, RSET_MPI, RSET_PCMCIA, RSET_PCIE, RSET_DSL, RSET_ENET0, RSET_ENET1, RSET_ENETDMA, RSET_ENETDMAC, RSET_ENETDMAS, RSET_ENETSW, RSET_EHCI0, RSET_SDRAM, RSET_MEMC, RSET_DDR, RSET_M2M, RSET_ATM, RSET_XTM, RSET_XTMDMA, RSET_XTMDMAC, RSET_XTMDMAS, RSET_PCM, RSET_PCMDMA, RSET_PCMDMAC, RSET_PCMDMAS, RSET_RNG, RSET_MISC }

enum	bcm63xx_irq { IRQ_TIMER = 0, IRQ_SPI, IRQ_UART0, IRQ_UART1, IRQ_DSL, IRQ_ENET0, IRQ_ENET1, IRQ_ENET_PHY, IRQ_OHCI0, IRQ_EHCI0, IRQ_USBD, IRQ_USBD_RXDMA0, IRQ_USBD_TXDMA0, IRQ_USBD_RXDMA1, IRQ_USBD_TXDMA1, IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2, IRQ_ENET0_RXDMA, IRQ_ENET0_TXDMA, IRQ_ENET1_RXDMA, IRQ_ENET1_TXDMA, IRQ_PCI, IRQ_PCMCIA, IRQ_ATM, IRQ_ENETSW_RXDMA0, IRQ_ENETSW_RXDMA1, IRQ_ENETSW_RXDMA2, IRQ_ENETSW_RXDMA3, IRQ_ENETSW_TXDMA0, IRQ_ENETSW_TXDMA1, IRQ_ENETSW_TXDMA2, IRQ_ENETSW_TXDMA3, IRQ_XTM, IRQ_XTM_DMA0 }

Functions
void __init	bcm63xx_cpu_init (void)

u16	__bcm63xx_get_cpu_id (void)

u16	bcm63xx_get_cpu_rev (void)

unsigned int	bcm63xx_get_cpu_freq (void)

unsigned int	bcm63xx_get_memory_size (void)

void	bcm63xx_machine_halt (void)

void	bcm63xx_machine_reboot (void)

Variables
const unsigned long *	bcm63xx_regs_base

const int *	bcm63xx_irqs

Macro Definition Documentation

#define __GEN_CPU_IRQ_TABLE ( __cpu )

Definition at line 873 of file bcm63xx_cpu.h.

#define __GEN_CPU_REGS_TABLE ( __cpu )

Definition at line 504 of file bcm63xx_cpu.h.

#define __GEN_RSET ( __cpu )

Definition at line 460 of file bcm63xx_cpu.h.

#define __GEN_RSET_BASE	(	__cpu,
		__rset
	)

Value:

case RSET_## __rset : \

return BCM_## __cpu ##_## __rset ##_BASE;

Definition at line 456 of file bcm63xx_cpu.h.

#define BCM6328_CPU_ID 0x6328

Definition at line 12 of file bcm63xx_cpu.h.

#define BCM6338_CPU_ID 0x6338

Definition at line 13 of file bcm63xx_cpu.h.

#define BCM6345_CPU_ID 0x6345

Definition at line 14 of file bcm63xx_cpu.h.

#define BCM6348_CPU_ID 0x6348

Definition at line 15 of file bcm63xx_cpu.h.

#define BCM6358_CPU_ID 0x6358

Definition at line 16 of file bcm63xx_cpu.h.

#define BCM6368_CPU_ID 0x6368

Definition at line 17 of file bcm63xx_cpu.h.

#define BCM_6328_ATM_BASE (0xdeadbeef)

Definition at line 212 of file bcm63xx_cpu.h.

#define BCM_6328_ATM_IRQ 0

Definition at line 644 of file bcm63xx_cpu.h.

#define BCM_6328_DDR_BASE (0xb0003000)

Definition at line 210 of file bcm63xx_cpu.h.

#define BCM_6328_DSL_BASE (0xb0001900)

Definition at line 199 of file bcm63xx_cpu.h.

#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

Definition at line 624 of file bcm63xx_cpu.h.

#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)

Definition at line 181 of file bcm63xx_cpu.h.

#define BCM_6328_EHCI0_BASE (0xb0002500)

Definition at line 207 of file bcm63xx_cpu.h.

#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)

Definition at line 630 of file bcm63xx_cpu.h.

#define BCM_6328_ENET0_BASE (0xdeadbeef)

Definition at line 201 of file bcm63xx_cpu.h.

#define BCM_6328_ENET0_IRQ 0

Definition at line 626 of file bcm63xx_cpu.h.

#define BCM_6328_ENET0_RXDMA_IRQ 0

Definition at line 639 of file bcm63xx_cpu.h.

#define BCM_6328_ENET0_TXDMA_IRQ 0

Definition at line 640 of file bcm63xx_cpu.h.

#define BCM_6328_ENET1_BASE (0xdeadbeef)

Definition at line 202 of file bcm63xx_cpu.h.

#define BCM_6328_ENET1_IRQ 0

Definition at line 627 of file bcm63xx_cpu.h.

#define BCM_6328_ENET1_RXDMA_IRQ 0

Definition at line 641 of file bcm63xx_cpu.h.

#define BCM_6328_ENET1_TXDMA_IRQ 0

Definition at line 642 of file bcm63xx_cpu.h.

#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)

Definition at line 628 of file bcm63xx_cpu.h.

#define BCM_6328_ENETDMA_BASE (0xb000d800)

Definition at line 203 of file bcm63xx_cpu.h.

#define BCM_6328_ENETDMAC_BASE (0xb000da00)

Definition at line 204 of file bcm63xx_cpu.h.

#define BCM_6328_ENETDMAS_BASE (0xb000dc00)

Definition at line 205 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_BASE (0xb0e00000)

Definition at line 206 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)

Definition at line 645 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)

Definition at line 646 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)

Definition at line 647 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)

Definition at line 648 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_TXDMA0_IRQ 0

Definition at line 649 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_TXDMA1_IRQ 0

Definition at line 650 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_TXDMA2_IRQ 0

Definition at line 651 of file bcm63xx_cpu.h.

#define BCM_6328_ENETSW_TXDMA3_IRQ 0

Definition at line 652 of file bcm63xx_cpu.h.

#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)

Definition at line 658 of file bcm63xx_cpu.h.

#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)

Definition at line 659 of file bcm63xx_cpu.h.

#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)

Definition at line 660 of file bcm63xx_cpu.h.

#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)

Definition at line 661 of file bcm63xx_cpu.h.

#define BCM_6328_GPIO_BASE (0xb0000080)

Definition at line 187 of file bcm63xx_cpu.h.

#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)

Definition at line 618 of file bcm63xx_cpu.h.

#define BCM_6328_M2M_BASE (0xdeadbeef)

Definition at line 211 of file bcm63xx_cpu.h.

#define BCM_6328_MEMC_BASE (0xdeadbeef)

Definition at line 209 of file bcm63xx_cpu.h.

#define BCM_6328_MISC_BASE (0xb0001800)

Definition at line 222 of file bcm63xx_cpu.h.

#define BCM_6328_MPI_BASE (0xdeadbeef)

Definition at line 195 of file bcm63xx_cpu.h.

#define BCM_6328_OHCI0_BASE (0xb0002600)

Definition at line 191 of file bcm63xx_cpu.h.

#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)

Definition at line 629 of file bcm63xx_cpu.h.

#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)

Definition at line 192 of file bcm63xx_cpu.h.

#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)

Definition at line 643 of file bcm63xx_cpu.h.

#define BCM_6328_PCIE_BASE (0xb0e40000)

Definition at line 197 of file bcm63xx_cpu.h.

#define BCM_6328_PCM_BASE (0xb000a800)

Definition at line 217 of file bcm63xx_cpu.h.

#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 656 of file bcm63xx_cpu.h.

#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)

Definition at line 657 of file bcm63xx_cpu.h.

#define BCM_6328_PCMCIA_BASE (0xdeadbeef)

Definition at line 196 of file bcm63xx_cpu.h.

#define BCM_6328_PCMCIA_IRQ 0

Definition at line 638 of file bcm63xx_cpu.h.

#define BCM_6328_PCMDMA_BASE (0xdeadbeef)

Definition at line 218 of file bcm63xx_cpu.h.

#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)

Definition at line 219 of file bcm63xx_cpu.h.

#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)

Definition at line 220 of file bcm63xx_cpu.h.

#define BCM_6328_PERF_BASE (0xb0000000)

Definition at line 182 of file bcm63xx_cpu.h.

#define BCM_6328_RNG_BASE (0xdeadbeef)

Definition at line 221 of file bcm63xx_cpu.h.

#define BCM_6328_SDRAM_BASE (0xdeadbeef)

Definition at line 208 of file bcm63xx_cpu.h.

#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)

Definition at line 198 of file bcm63xx_cpu.h.

#define BCM_6328_SPI_BASE (0xdeadbeef)

Definition at line 188 of file bcm63xx_cpu.h.

#define BCM_6328_SPI_IRQ 0

Definition at line 621 of file bcm63xx_cpu.h.

#define BCM_6328_TIMER_BASE (0xb0000040)

Definition at line 183 of file bcm63xx_cpu.h.

#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)

Definition at line 620 of file bcm63xx_cpu.h.

#define BCM_6328_UART0_BASE (0xb0000100)

Definition at line 185 of file bcm63xx_cpu.h.

#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)

Definition at line 622 of file bcm63xx_cpu.h.

#define BCM_6328_UART1_BASE (0xb0000120)

Definition at line 186 of file bcm63xx_cpu.h.

#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)

Definition at line 623 of file bcm63xx_cpu.h.

#define BCM_6328_UBUS_BASE (0xdeadbeef)

Definition at line 200 of file bcm63xx_cpu.h.

#define BCM_6328_UDC0_BASE (0xdeadbeef)

Definition at line 189 of file bcm63xx_cpu.h.

#define BCM_6328_UDC0_IRQ 0

Definition at line 625 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_BASE (0xb0002400)

Definition at line 194 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)

Definition at line 631 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)

Definition at line 632 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)

Definition at line 634 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)

Definition at line 636 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)

Definition at line 633 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 635 of file bcm63xx_cpu.h.

#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)

Definition at line 637 of file bcm63xx_cpu.h.

#define BCM_6328_USBDMA_BASE (0xb000c000)

Definition at line 190 of file bcm63xx_cpu.h.

#define BCM_6328_USBH_PRIV_BASE (0xb0002700)

Definition at line 193 of file bcm63xx_cpu.h.

#define BCM_6328_WDT_BASE (0xb000005c)

Definition at line 184 of file bcm63xx_cpu.h.

#define BCM_6328_XTM_BASE (0xdeadbeef)

Definition at line 213 of file bcm63xx_cpu.h.

#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)

Definition at line 654 of file bcm63xx_cpu.h.

#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)

Definition at line 653 of file bcm63xx_cpu.h.

#define BCM_6328_XTMDMA_BASE (0xb000b800)

Definition at line 214 of file bcm63xx_cpu.h.

#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)

Definition at line 215 of file bcm63xx_cpu.h.

#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)

Definition at line 216 of file bcm63xx_cpu.h.

#define BCM_6338_ATM_BASE (0xfffe2000)

Definition at line 258 of file bcm63xx_cpu.h.

#define BCM_6338_ATM_IRQ 0

Definition at line 689 of file bcm63xx_cpu.h.

#define BCM_6338_BB_BASE (0xfffe0100)

Definition at line 228 of file bcm63xx_cpu.h.

#define BCM_6338_DDR_BASE (0xdeadbeef)

Definition at line 256 of file bcm63xx_cpu.h.

#define BCM_6338_DSL_BASE (0xfffe1000)

Definition at line 245 of file bcm63xx_cpu.h.

#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)

Definition at line 670 of file bcm63xx_cpu.h.

#define BCM_6338_DSL_LMEM_BASE (0xfff00000)

Definition at line 226 of file bcm63xx_cpu.h.

#define BCM_6338_EHCI0_BASE (0xdeadbeef)

Definition at line 253 of file bcm63xx_cpu.h.

#define BCM_6338_EHCI0_IRQ 0

Definition at line 675 of file bcm63xx_cpu.h.

#define BCM_6338_ENET0_BASE (0xfffe2800)

Definition at line 247 of file bcm63xx_cpu.h.

#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 671 of file bcm63xx_cpu.h.

#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)

Definition at line 683 of file bcm63xx_cpu.h.

#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)

Definition at line 684 of file bcm63xx_cpu.h.

#define BCM_6338_ENET1_BASE (0xdeadbeef)

Definition at line 248 of file bcm63xx_cpu.h.

#define BCM_6338_ENET1_IRQ 0

Definition at line 672 of file bcm63xx_cpu.h.

#define BCM_6338_ENET1_RXDMA_IRQ 0

Definition at line 685 of file bcm63xx_cpu.h.

#define BCM_6338_ENET1_TXDMA_IRQ 0

Definition at line 686 of file bcm63xx_cpu.h.

#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

Definition at line 673 of file bcm63xx_cpu.h.

#define BCM_6338_ENETDMA_BASE (0xfffe2400)

Definition at line 249 of file bcm63xx_cpu.h.

#define BCM_6338_ENETDMAC_BASE (0xfffe2500)

Definition at line 250 of file bcm63xx_cpu.h.

#define BCM_6338_ENETDMAS_BASE (0xfffe2600)

Definition at line 251 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_BASE (0xdeadbeef)

Definition at line 252 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_RXDMA0_IRQ 0

Definition at line 690 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_RXDMA1_IRQ 0

Definition at line 691 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_RXDMA2_IRQ 0

Definition at line 692 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_RXDMA3_IRQ 0

Definition at line 693 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_TXDMA0_IRQ 0

Definition at line 694 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_TXDMA1_IRQ 0

Definition at line 695 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_TXDMA2_IRQ 0

Definition at line 696 of file bcm63xx_cpu.h.

#define BCM_6338_ENETSW_TXDMA3_IRQ 0

Definition at line 697 of file bcm63xx_cpu.h.

#define BCM_6338_GPIO_BASE (0xfffe0400)

Definition at line 233 of file bcm63xx_cpu.h.

#define BCM_6338_M2M_BASE (0xdeadbeef)

Definition at line 257 of file bcm63xx_cpu.h.

#define BCM_6338_MEMC_BASE (0xdeadbeef)

Definition at line 255 of file bcm63xx_cpu.h.

#define BCM_6338_MISC_BASE (0xdeadbeef)

Definition at line 268 of file bcm63xx_cpu.h.

#define BCM_6338_MPI_BASE (0xfffe3160)

Definition at line 241 of file bcm63xx_cpu.h.

#define BCM_6338_OHCI0_BASE (0xdeadbeef)

Definition at line 237 of file bcm63xx_cpu.h.

#define BCM_6338_OHCI0_IRQ 0

Definition at line 674 of file bcm63xx_cpu.h.

#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)

Definition at line 238 of file bcm63xx_cpu.h.

#define BCM_6338_PCI_IRQ 0

Definition at line 687 of file bcm63xx_cpu.h.

#define BCM_6338_PCIE_BASE (0xdeadbeef)

Definition at line 243 of file bcm63xx_cpu.h.

#define BCM_6338_PCM_BASE (0xdeadbeef)

Definition at line 263 of file bcm63xx_cpu.h.

#define BCM_6338_PCMCIA_BASE (0xdeadbeef)

Definition at line 242 of file bcm63xx_cpu.h.

#define BCM_6338_PCMCIA_IRQ 0

Definition at line 688 of file bcm63xx_cpu.h.

#define BCM_6338_PCMDMA_BASE (0xdeadbeef)

Definition at line 264 of file bcm63xx_cpu.h.

#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)

Definition at line 265 of file bcm63xx_cpu.h.

#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)

Definition at line 266 of file bcm63xx_cpu.h.

#define BCM_6338_PERF_BASE (0xfffe0000)

Definition at line 227 of file bcm63xx_cpu.h.

#define BCM_6338_RNG_BASE (0xdeadbeef)

Definition at line 267 of file bcm63xx_cpu.h.

#define BCM_6338_RSET_SPI_SIZE 64

Definition at line 156 of file bcm63xx_cpu.h.

#define BCM_6338_SDRAM_BASE (0xfffe3100)

Definition at line 254 of file bcm63xx_cpu.h.

#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)

Definition at line 244 of file bcm63xx_cpu.h.

#define BCM_6338_SPI_BASE (0xfffe0c00)

Definition at line 234 of file bcm63xx_cpu.h.

#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

Definition at line 667 of file bcm63xx_cpu.h.

#define BCM_6338_TIMER_BASE (0xfffe0200)

Definition at line 229 of file bcm63xx_cpu.h.

#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

Definition at line 666 of file bcm63xx_cpu.h.

#define BCM_6338_UART0_BASE (0xfffe0300)

Definition at line 231 of file bcm63xx_cpu.h.

#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 668 of file bcm63xx_cpu.h.

#define BCM_6338_UART1_BASE (0xdeadbeef)

Definition at line 232 of file bcm63xx_cpu.h.

#define BCM_6338_UART1_IRQ 0

Definition at line 669 of file bcm63xx_cpu.h.

#define BCM_6338_UBUS_BASE (0xdeadbeef)

Definition at line 246 of file bcm63xx_cpu.h.

#define BCM_6338_UDC0_BASE (0xdeadbeef)

Definition at line 235 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_BASE (0xdeadbeef)

Definition at line 240 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_IRQ 0

Definition at line 676 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_RXDMA0_IRQ 0

Definition at line 677 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_RXDMA1_IRQ 0

Definition at line 679 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_RXDMA2_IRQ 0

Definition at line 681 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_TXDMA0_IRQ 0

Definition at line 678 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_TXDMA1_IRQ 0

Definition at line 680 of file bcm63xx_cpu.h.

#define BCM_6338_USBD_TXDMA2_IRQ 0

Definition at line 682 of file bcm63xx_cpu.h.

#define BCM_6338_USBDMA_BASE (0xfffe2400)

Definition at line 236 of file bcm63xx_cpu.h.

#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)

Definition at line 239 of file bcm63xx_cpu.h.

#define BCM_6338_WDT_BASE (0xfffe021c)

Definition at line 230 of file bcm63xx_cpu.h.

#define BCM_6338_XTM_BASE (0xdeadbeef)

Definition at line 259 of file bcm63xx_cpu.h.

#define BCM_6338_XTM_DMA0_IRQ 0

Definition at line 699 of file bcm63xx_cpu.h.

#define BCM_6338_XTM_IRQ 0

Definition at line 698 of file bcm63xx_cpu.h.

#define BCM_6338_XTMDMA_BASE (0xdeadbeef)

Definition at line 260 of file bcm63xx_cpu.h.

#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)

Definition at line 261 of file bcm63xx_cpu.h.

#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)

Definition at line 262 of file bcm63xx_cpu.h.

#define BCM_6345_ATM_BASE (0xfffe4000)

Definition at line 305 of file bcm63xx_cpu.h.

#define BCM_6345_ATM_IRQ 0

Definition at line 727 of file bcm63xx_cpu.h.

#define BCM_6345_BB_BASE (0xfffe0100)

Definition at line 275 of file bcm63xx_cpu.h.

#define BCM_6345_DDR_BASE (0xdeadbeef)

Definition at line 303 of file bcm63xx_cpu.h.

#define BCM_6345_DSL_BASE (0xdeadbeef)

Definition at line 297 of file bcm63xx_cpu.h.

#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)

Definition at line 708 of file bcm63xx_cpu.h.

#define BCM_6345_DSL_LMEM_BASE (0xfff00000)

Definition at line 273 of file bcm63xx_cpu.h.

#define BCM_6345_EHCI0_BASE (0xdeadbeef)

Definition at line 300 of file bcm63xx_cpu.h.

#define BCM_6345_EHCI0_IRQ 0

Definition at line 713 of file bcm63xx_cpu.h.

#define BCM_6345_ENET0_BASE (0xfffe1800)

Definition at line 284 of file bcm63xx_cpu.h.

#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 709 of file bcm63xx_cpu.h.

#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)

Definition at line 721 of file bcm63xx_cpu.h.

#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)

Definition at line 722 of file bcm63xx_cpu.h.

#define BCM_6345_ENET1_BASE (0xdeadbeef)

Definition at line 299 of file bcm63xx_cpu.h.

#define BCM_6345_ENET1_IRQ 0

Definition at line 710 of file bcm63xx_cpu.h.

#define BCM_6345_ENET1_RXDMA_IRQ 0

Definition at line 723 of file bcm63xx_cpu.h.

#define BCM_6345_ENET1_TXDMA_IRQ 0

Definition at line 724 of file bcm63xx_cpu.h.

#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)

Definition at line 711 of file bcm63xx_cpu.h.

#define BCM_6345_ENETDMA_BASE (0xfffe2800)

Definition at line 285 of file bcm63xx_cpu.h.

#define BCM_6345_ENETDMAC_BASE (0xfffe2900)

Definition at line 286 of file bcm63xx_cpu.h.

#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)

Definition at line 287 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_BASE (0xdeadbeef)

Definition at line 288 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_RXDMA0_IRQ 0

Definition at line 728 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_RXDMA1_IRQ 0

Definition at line 729 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_RXDMA2_IRQ 0

Definition at line 730 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_RXDMA3_IRQ 0

Definition at line 731 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_TXDMA0_IRQ 0

Definition at line 732 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_TXDMA1_IRQ 0

Definition at line 733 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_TXDMA2_IRQ 0

Definition at line 734 of file bcm63xx_cpu.h.

#define BCM_6345_ENETSW_TXDMA3_IRQ 0

Definition at line 735 of file bcm63xx_cpu.h.

#define BCM_6345_GPIO_BASE (0xfffe0400)

Definition at line 280 of file bcm63xx_cpu.h.

#define BCM_6345_M2M_BASE (0xdeadbeef)

Definition at line 304 of file bcm63xx_cpu.h.

#define BCM_6345_MEMC_BASE (0xdeadbeef)

Definition at line 302 of file bcm63xx_cpu.h.

#define BCM_6345_MISC_BASE (0xdeadbeef)

Definition at line 315 of file bcm63xx_cpu.h.

#define BCM_6345_MPI_BASE (0xfffe2000)

Definition at line 290 of file bcm63xx_cpu.h.

#define BCM_6345_OHCI0_BASE (0xfffe2100)

Definition at line 292 of file bcm63xx_cpu.h.

#define BCM_6345_OHCI0_IRQ 0

Definition at line 712 of file bcm63xx_cpu.h.

#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)

Definition at line 293 of file bcm63xx_cpu.h.

#define BCM_6345_PCI_IRQ 0

Definition at line 725 of file bcm63xx_cpu.h.

#define BCM_6345_PCIE_BASE (0xdeadbeef)

Definition at line 291 of file bcm63xx_cpu.h.

#define BCM_6345_PCM_BASE (0xdeadbeef)

Definition at line 310 of file bcm63xx_cpu.h.

#define BCM_6345_PCMCIA_BASE (0xfffe2028)

Definition at line 289 of file bcm63xx_cpu.h.

#define BCM_6345_PCMCIA_IRQ 0

Definition at line 726 of file bcm63xx_cpu.h.

#define BCM_6345_PCMDMA_BASE (0xdeadbeef)

Definition at line 311 of file bcm63xx_cpu.h.

#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)

Definition at line 312 of file bcm63xx_cpu.h.

#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)

Definition at line 313 of file bcm63xx_cpu.h.

#define BCM_6345_PERF_BASE (0xfffe0000)

Definition at line 274 of file bcm63xx_cpu.h.

#define BCM_6345_RNG_BASE (0xdeadbeef)

Definition at line 314 of file bcm63xx_cpu.h.

#define BCM_6345_SDRAM_BASE (0xfffe2300)

Definition at line 301 of file bcm63xx_cpu.h.

#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)

Definition at line 296 of file bcm63xx_cpu.h.

#define BCM_6345_SPI_BASE (0xdeadbeef)

Definition at line 281 of file bcm63xx_cpu.h.

#define BCM_6345_SPI_IRQ 0

Definition at line 705 of file bcm63xx_cpu.h.

#define BCM_6345_TIMER_BASE (0xfffe0200)

Definition at line 276 of file bcm63xx_cpu.h.

#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

Definition at line 704 of file bcm63xx_cpu.h.

#define BCM_6345_UART0_BASE (0xfffe0300)

Definition at line 278 of file bcm63xx_cpu.h.

#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 706 of file bcm63xx_cpu.h.

#define BCM_6345_UART1_BASE (0xdeadbeef)

Definition at line 279 of file bcm63xx_cpu.h.

#define BCM_6345_UART1_IRQ 0

Definition at line 707 of file bcm63xx_cpu.h.

#define BCM_6345_UBUS_BASE (0xdeadbeef)

Definition at line 298 of file bcm63xx_cpu.h.

#define BCM_6345_UDC0_BASE (0xdeadbeef)

Definition at line 282 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_BASE (0xdeadbeef)

Definition at line 295 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_IRQ 0

Definition at line 714 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_RXDMA0_IRQ 0

Definition at line 715 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_RXDMA1_IRQ 0

Definition at line 717 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_RXDMA2_IRQ 0

Definition at line 719 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_TXDMA0_IRQ 0

Definition at line 716 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_TXDMA1_IRQ 0

Definition at line 718 of file bcm63xx_cpu.h.

#define BCM_6345_USBD_TXDMA2_IRQ 0

Definition at line 720 of file bcm63xx_cpu.h.

#define BCM_6345_USBDMA_BASE (0xfffe2800)

Definition at line 283 of file bcm63xx_cpu.h.

#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)

Definition at line 294 of file bcm63xx_cpu.h.

#define BCM_6345_WDT_BASE (0xfffe021c)

Definition at line 277 of file bcm63xx_cpu.h.

#define BCM_6345_XTM_BASE (0xdeadbeef)

Definition at line 306 of file bcm63xx_cpu.h.

#define BCM_6345_XTM_DMA0_IRQ 0

Definition at line 737 of file bcm63xx_cpu.h.

#define BCM_6345_XTM_IRQ 0

Definition at line 736 of file bcm63xx_cpu.h.

#define BCM_6345_XTMDMA_BASE (0xdeadbeef)

Definition at line 307 of file bcm63xx_cpu.h.

#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)

Definition at line 308 of file bcm63xx_cpu.h.

#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)

Definition at line 309 of file bcm63xx_cpu.h.

#define BCM_6348_ATM_BASE (0xfffe4000)

Definition at line 350 of file bcm63xx_cpu.h.

#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)

Definition at line 765 of file bcm63xx_cpu.h.

#define BCM_6348_DDR_BASE (0xdeadbeef)

Definition at line 349 of file bcm63xx_cpu.h.

#define BCM_6348_DSL_BASE (0xfffe3000)

Definition at line 339 of file bcm63xx_cpu.h.

#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

Definition at line 746 of file bcm63xx_cpu.h.

#define BCM_6348_DSL_LMEM_BASE (0xfff00000)

Definition at line 320 of file bcm63xx_cpu.h.

#define BCM_6348_EHCI0_BASE (0xdeadbeef)

Definition at line 346 of file bcm63xx_cpu.h.

#define BCM_6348_EHCI0_IRQ 0

Definition at line 751 of file bcm63xx_cpu.h.

#define BCM_6348_ENET0_BASE (0xfffe6000)

Definition at line 340 of file bcm63xx_cpu.h.

#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 747 of file bcm63xx_cpu.h.

#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)

Definition at line 759 of file bcm63xx_cpu.h.

#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)

Definition at line 760 of file bcm63xx_cpu.h.

#define BCM_6348_ENET1_BASE (0xfffe6800)

Definition at line 341 of file bcm63xx_cpu.h.

#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)

Definition at line 748 of file bcm63xx_cpu.h.

#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)

Definition at line 761 of file bcm63xx_cpu.h.

#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)

Definition at line 762 of file bcm63xx_cpu.h.

#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

Definition at line 749 of file bcm63xx_cpu.h.

#define BCM_6348_ENETDMA_BASE (0xfffe7000)

Definition at line 342 of file bcm63xx_cpu.h.

#define BCM_6348_ENETDMAC_BASE (0xfffe7100)

Definition at line 343 of file bcm63xx_cpu.h.

#define BCM_6348_ENETDMAS_BASE (0xfffe7200)

Definition at line 344 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_BASE (0xdeadbeef)

Definition at line 345 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_RXDMA0_IRQ 0

Definition at line 766 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_RXDMA1_IRQ 0

Definition at line 767 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_RXDMA2_IRQ 0

Definition at line 768 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_RXDMA3_IRQ 0

Definition at line 769 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_TXDMA0_IRQ 0

Definition at line 770 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_TXDMA1_IRQ 0

Definition at line 771 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_TXDMA2_IRQ 0

Definition at line 772 of file bcm63xx_cpu.h.

#define BCM_6348_ENETSW_TXDMA3_IRQ 0

Definition at line 773 of file bcm63xx_cpu.h.

#define BCM_6348_GPIO_BASE (0xfffe0400)

Definition at line 326 of file bcm63xx_cpu.h.

#define BCM_6348_M2M_BASE (0xfffe2800)

Definition at line 338 of file bcm63xx_cpu.h.

#define BCM_6348_MEMC_BASE (0xdeadbeef)

Definition at line 348 of file bcm63xx_cpu.h.

#define BCM_6348_MISC_BASE (0xdeadbeef)

Definition at line 360 of file bcm63xx_cpu.h.

#define BCM_6348_MPI_BASE (0xfffe2000)

Definition at line 334 of file bcm63xx_cpu.h.

#define BCM_6348_OHCI0_BASE (0xfffe1b00)

Definition at line 330 of file bcm63xx_cpu.h.

#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)

Definition at line 750 of file bcm63xx_cpu.h.

#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)

Definition at line 331 of file bcm63xx_cpu.h.

#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)

Definition at line 763 of file bcm63xx_cpu.h.

#define BCM_6348_PCIE_BASE (0xdeadbeef)

Definition at line 336 of file bcm63xx_cpu.h.

#define BCM_6348_PCM_BASE (0xdeadbeef)

Definition at line 355 of file bcm63xx_cpu.h.

#define BCM_6348_PCMCIA_BASE (0xfffe2054)

Definition at line 335 of file bcm63xx_cpu.h.

#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)

Definition at line 764 of file bcm63xx_cpu.h.

#define BCM_6348_PCMDMA_BASE (0xdeadbeef)

Definition at line 356 of file bcm63xx_cpu.h.

#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)

Definition at line 357 of file bcm63xx_cpu.h.

#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)

Definition at line 358 of file bcm63xx_cpu.h.

#define BCM_6348_PERF_BASE (0xfffe0000)

Definition at line 321 of file bcm63xx_cpu.h.

#define BCM_6348_RNG_BASE (0xdeadbeef)

Definition at line 359 of file bcm63xx_cpu.h.

#define BCM_6348_RSET_SPI_SIZE 64

Definition at line 157 of file bcm63xx_cpu.h.

#define BCM_6348_SDRAM_BASE (0xfffe2300)

Definition at line 347 of file bcm63xx_cpu.h.

#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)

Definition at line 337 of file bcm63xx_cpu.h.

#define BCM_6348_SPI_BASE (0xfffe0c00)

Definition at line 327 of file bcm63xx_cpu.h.

#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

Definition at line 743 of file bcm63xx_cpu.h.

#define BCM_6348_TIMER_BASE (0xfffe0200)

Definition at line 322 of file bcm63xx_cpu.h.

#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

Definition at line 742 of file bcm63xx_cpu.h.

#define BCM_6348_UART0_BASE (0xfffe0300)

Definition at line 324 of file bcm63xx_cpu.h.

#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 744 of file bcm63xx_cpu.h.

#define BCM_6348_UART1_BASE (0xdeadbeef)

Definition at line 325 of file bcm63xx_cpu.h.

#define BCM_6348_UART1_IRQ 0

Definition at line 745 of file bcm63xx_cpu.h.

#define BCM_6348_UDC0_BASE (0xfffe1000)

Definition at line 328 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_BASE (0xdeadbeef)

Definition at line 333 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_IRQ 0

Definition at line 752 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_RXDMA0_IRQ 0

Definition at line 753 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_RXDMA1_IRQ 0

Definition at line 755 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_RXDMA2_IRQ 0

Definition at line 757 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_TXDMA0_IRQ 0

Definition at line 754 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_TXDMA1_IRQ 0

Definition at line 756 of file bcm63xx_cpu.h.

#define BCM_6348_USBD_TXDMA2_IRQ 0

Definition at line 758 of file bcm63xx_cpu.h.

#define BCM_6348_USBDMA_BASE (0xdeadbeef)

Definition at line 329 of file bcm63xx_cpu.h.

#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)

Definition at line 332 of file bcm63xx_cpu.h.

#define BCM_6348_WDT_BASE (0xfffe021c)

Definition at line 323 of file bcm63xx_cpu.h.

#define BCM_6348_XTM_BASE (0xdeadbeef)

Definition at line 351 of file bcm63xx_cpu.h.

#define BCM_6348_XTM_DMA0_IRQ 0

Definition at line 775 of file bcm63xx_cpu.h.

#define BCM_6348_XTM_IRQ 0

Definition at line 774 of file bcm63xx_cpu.h.

#define BCM_6348_XTMDMA_BASE (0xdeadbeef)

Definition at line 352 of file bcm63xx_cpu.h.

#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)

Definition at line 353 of file bcm63xx_cpu.h.

#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)

Definition at line 354 of file bcm63xx_cpu.h.

#define BCM_6358_ATM_BASE (0xfffe2000)

Definition at line 395 of file bcm63xx_cpu.h.

#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)

Definition at line 803 of file bcm63xx_cpu.h.

#define BCM_6358_DDR_BASE (0xfffe12a0)

Definition at line 394 of file bcm63xx_cpu.h.

#define BCM_6358_DSL_BASE (0xfffe3000)

Definition at line 384 of file bcm63xx_cpu.h.

#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)

Definition at line 784 of file bcm63xx_cpu.h.

#define BCM_6358_DSL_LMEM_BASE (0xfff00000)

Definition at line 365 of file bcm63xx_cpu.h.

#define BCM_6358_EHCI0_BASE (0xfffe1300)

Definition at line 391 of file bcm63xx_cpu.h.

#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)

Definition at line 789 of file bcm63xx_cpu.h.

#define BCM_6358_ENET0_BASE (0xfffe4000)

Definition at line 385 of file bcm63xx_cpu.h.

#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 785 of file bcm63xx_cpu.h.

#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)

Definition at line 797 of file bcm63xx_cpu.h.

#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)

Definition at line 798 of file bcm63xx_cpu.h.

#define BCM_6358_ENET1_BASE (0xfffe4800)

Definition at line 386 of file bcm63xx_cpu.h.

#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)

Definition at line 786 of file bcm63xx_cpu.h.

#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)

Definition at line 799 of file bcm63xx_cpu.h.

#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)

Definition at line 800 of file bcm63xx_cpu.h.

#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)

Definition at line 787 of file bcm63xx_cpu.h.

#define BCM_6358_ENETDMA_BASE (0xfffe5000)

Definition at line 387 of file bcm63xx_cpu.h.

#define BCM_6358_ENETDMAC_BASE (0xfffe5100)

Definition at line 388 of file bcm63xx_cpu.h.

#define BCM_6358_ENETDMAS_BASE (0xfffe5200)

Definition at line 389 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_BASE (0xdeadbeef)

Definition at line 390 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_RXDMA0_IRQ 0

Definition at line 804 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_RXDMA1_IRQ 0

Definition at line 805 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_RXDMA2_IRQ 0

Definition at line 806 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_RXDMA3_IRQ 0

Definition at line 807 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_TXDMA0_IRQ 0

Definition at line 808 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_TXDMA1_IRQ 0

Definition at line 809 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_TXDMA2_IRQ 0

Definition at line 810 of file bcm63xx_cpu.h.

#define BCM_6358_ENETSW_TXDMA3_IRQ 0

Definition at line 811 of file bcm63xx_cpu.h.

#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)

Definition at line 817 of file bcm63xx_cpu.h.

#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)

Definition at line 818 of file bcm63xx_cpu.h.

#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)

Definition at line 819 of file bcm63xx_cpu.h.

#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)

Definition at line 820 of file bcm63xx_cpu.h.

#define BCM_6358_GPIO_BASE (0xfffe0080)

Definition at line 371 of file bcm63xx_cpu.h.

#define BCM_6358_M2M_BASE (0xdeadbeef)

Definition at line 383 of file bcm63xx_cpu.h.

#define BCM_6358_MEMC_BASE (0xfffe1200)

Definition at line 393 of file bcm63xx_cpu.h.

#define BCM_6358_MISC_BASE (0xdeadbeef)

Definition at line 405 of file bcm63xx_cpu.h.

#define BCM_6358_MPI_BASE (0xfffe1000)

Definition at line 379 of file bcm63xx_cpu.h.

#define BCM_6358_OHCI0_BASE (0xfffe1400)

Definition at line 375 of file bcm63xx_cpu.h.

#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)

Definition at line 788 of file bcm63xx_cpu.h.

#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)

Definition at line 376 of file bcm63xx_cpu.h.

#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)

Definition at line 801 of file bcm63xx_cpu.h.

#define BCM_6358_PCIE_BASE (0xdeadbeef)

Definition at line 381 of file bcm63xx_cpu.h.

#define BCM_6358_PCM_BASE (0xfffe1600)

Definition at line 400 of file bcm63xx_cpu.h.

#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)

Definition at line 815 of file bcm63xx_cpu.h.

#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)

Definition at line 816 of file bcm63xx_cpu.h.

#define BCM_6358_PCMCIA_BASE (0xfffe1054)

Definition at line 380 of file bcm63xx_cpu.h.

#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)

Definition at line 802 of file bcm63xx_cpu.h.

#define BCM_6358_PCMDMA_BASE (0xfffe1800)

Definition at line 401 of file bcm63xx_cpu.h.

#define BCM_6358_PCMDMAC_BASE (0xfffe1900)

Definition at line 402 of file bcm63xx_cpu.h.

#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)

Definition at line 403 of file bcm63xx_cpu.h.

#define BCM_6358_PERF_BASE (0xfffe0000)

Definition at line 366 of file bcm63xx_cpu.h.

#define BCM_6358_RNG_BASE (0xdeadbeef)

Definition at line 404 of file bcm63xx_cpu.h.

#define BCM_6358_RSET_SPI_SIZE 1804

Definition at line 158 of file bcm63xx_cpu.h.

#define BCM_6358_SDRAM_BASE (0xdeadbeef)

Definition at line 392 of file bcm63xx_cpu.h.

#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)

Definition at line 382 of file bcm63xx_cpu.h.

#define BCM_6358_SPI_BASE (0xfffe0800)

Definition at line 372 of file bcm63xx_cpu.h.

#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

Definition at line 781 of file bcm63xx_cpu.h.

#define BCM_6358_TIMER_BASE (0xfffe0040)

Definition at line 367 of file bcm63xx_cpu.h.

#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

Definition at line 780 of file bcm63xx_cpu.h.

#define BCM_6358_UART0_BASE (0xfffe0100)

Definition at line 369 of file bcm63xx_cpu.h.

#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 782 of file bcm63xx_cpu.h.

#define BCM_6358_UART1_BASE (0xfffe0120)

Definition at line 370 of file bcm63xx_cpu.h.

#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)

Definition at line 783 of file bcm63xx_cpu.h.

#define BCM_6358_UDC0_BASE (0xfffe0800)

Definition at line 373 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_BASE (0xdeadbeef)

Definition at line 378 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_IRQ 0

Definition at line 790 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_RXDMA0_IRQ 0

Definition at line 791 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_RXDMA1_IRQ 0

Definition at line 793 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_RXDMA2_IRQ 0

Definition at line 795 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_TXDMA0_IRQ 0

Definition at line 792 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_TXDMA1_IRQ 0

Definition at line 794 of file bcm63xx_cpu.h.

#define BCM_6358_USBD_TXDMA2_IRQ 0

Definition at line 796 of file bcm63xx_cpu.h.

#define BCM_6358_USBDMA_BASE (0xdeadbeef)

Definition at line 374 of file bcm63xx_cpu.h.

#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)

Definition at line 377 of file bcm63xx_cpu.h.

#define BCM_6358_WDT_BASE (0xfffe005c)

Definition at line 368 of file bcm63xx_cpu.h.

#define BCM_6358_XTM_BASE (0xdeadbeef)

Definition at line 396 of file bcm63xx_cpu.h.

#define BCM_6358_XTM_DMA0_IRQ 0

Definition at line 813 of file bcm63xx_cpu.h.

#define BCM_6358_XTM_IRQ 0

Definition at line 812 of file bcm63xx_cpu.h.

#define BCM_6358_XTMDMA_BASE (0xdeadbeef)

Definition at line 397 of file bcm63xx_cpu.h.

#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)

Definition at line 398 of file bcm63xx_cpu.h.

#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)

Definition at line 399 of file bcm63xx_cpu.h.

#define BCM_6368_ATM_BASE (0xdeadbeef)

Definition at line 441 of file bcm63xx_cpu.h.

#define BCM_6368_ATM_IRQ 0

Definition at line 850 of file bcm63xx_cpu.h.

#define BCM_6368_DDR_BASE (0xb0001280)

Definition at line 440 of file bcm63xx_cpu.h.

#define BCM_6368_DSL_BASE (0xdeadbeef)

Definition at line 430 of file bcm63xx_cpu.h.

#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)

Definition at line 831 of file bcm63xx_cpu.h.

#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)

Definition at line 411 of file bcm63xx_cpu.h.

#define BCM_6368_EHCI0_BASE (0xb0001500)

Definition at line 437 of file bcm63xx_cpu.h.

#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)

Definition at line 836 of file bcm63xx_cpu.h.

#define BCM_6368_ENET0_BASE (0xdeadbeef)

Definition at line 431 of file bcm63xx_cpu.h.

#define BCM_6368_ENET0_IRQ 0

Definition at line 832 of file bcm63xx_cpu.h.

#define BCM_6368_ENET0_RXDMA_IRQ 0

Definition at line 845 of file bcm63xx_cpu.h.

#define BCM_6368_ENET0_TXDMA_IRQ 0

Definition at line 846 of file bcm63xx_cpu.h.

#define BCM_6368_ENET1_BASE (0xdeadbeef)

Definition at line 432 of file bcm63xx_cpu.h.

#define BCM_6368_ENET1_IRQ 0

Definition at line 833 of file bcm63xx_cpu.h.

#define BCM_6368_ENET1_RXDMA_IRQ 0

Definition at line 847 of file bcm63xx_cpu.h.

#define BCM_6368_ENET1_TXDMA_IRQ 0

Definition at line 848 of file bcm63xx_cpu.h.

#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)

Definition at line 834 of file bcm63xx_cpu.h.

#define BCM_6368_ENETDMA_BASE (0xb0006800)

Definition at line 433 of file bcm63xx_cpu.h.

#define BCM_6368_ENETDMAC_BASE (0xb0006a00)

Definition at line 434 of file bcm63xx_cpu.h.

#define BCM_6368_ENETDMAS_BASE (0xb0006c00)

Definition at line 435 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_BASE (0xb0f00000)

Definition at line 436 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)

Definition at line 851 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)

Definition at line 852 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)

Definition at line 853 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)

Definition at line 854 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)

Definition at line 855 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)

Definition at line 856 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)

Definition at line 857 of file bcm63xx_cpu.h.

#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)

Definition at line 858 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)

Definition at line 864 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)

Definition at line 865 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)

Definition at line 866 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)

Definition at line 867 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)

Definition at line 868 of file bcm63xx_cpu.h.

#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)

Definition at line 869 of file bcm63xx_cpu.h.

#define BCM_6368_GPIO_BASE (0xb0000080)

Definition at line 417 of file bcm63xx_cpu.h.

#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)

Definition at line 825 of file bcm63xx_cpu.h.

#define BCM_6368_M2M_BASE (0xdeadbeef)

Definition at line 429 of file bcm63xx_cpu.h.

#define BCM_6368_MEMC_BASE (0xb0001200)

Definition at line 439 of file bcm63xx_cpu.h.

#define BCM_6368_MISC_BASE (0xdeadbeef)

Definition at line 451 of file bcm63xx_cpu.h.

#define BCM_6368_MPI_BASE (0xb0001000)

Definition at line 425 of file bcm63xx_cpu.h.

#define BCM_6368_OHCI0_BASE (0xb0001600)

Definition at line 421 of file bcm63xx_cpu.h.

#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)

Definition at line 835 of file bcm63xx_cpu.h.

#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)

Definition at line 422 of file bcm63xx_cpu.h.

#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)

Definition at line 849 of file bcm63xx_cpu.h.

#define BCM_6368_PCIE_BASE (0xdeadbeef)

Definition at line 427 of file bcm63xx_cpu.h.

#define BCM_6368_PCM_BASE (0xb0004000)

Definition at line 446 of file bcm63xx_cpu.h.

#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)

Definition at line 862 of file bcm63xx_cpu.h.

#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)

Definition at line 863 of file bcm63xx_cpu.h.

#define BCM_6368_PCMCIA_BASE (0xb0001054)

Definition at line 426 of file bcm63xx_cpu.h.

#define BCM_6368_PCMCIA_IRQ 0

Definition at line 844 of file bcm63xx_cpu.h.

#define BCM_6368_PCMDMA_BASE (0xb0005800)

Definition at line 447 of file bcm63xx_cpu.h.

#define BCM_6368_PCMDMAC_BASE (0xb0005a00)

Definition at line 448 of file bcm63xx_cpu.h.

#define BCM_6368_PCMDMAS_BASE (0xb0005c00)

Definition at line 449 of file bcm63xx_cpu.h.

#define BCM_6368_PERF_BASE (0xb0000000)

Definition at line 412 of file bcm63xx_cpu.h.

#define BCM_6368_RNG_BASE (0xb0004180)

Definition at line 450 of file bcm63xx_cpu.h.

#define BCM_6368_RSET_SPI_SIZE 1804

Definition at line 159 of file bcm63xx_cpu.h.

#define BCM_6368_SDRAM_BASE (0xdeadbeef)

Definition at line 438 of file bcm63xx_cpu.h.

#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)

Definition at line 428 of file bcm63xx_cpu.h.

#define BCM_6368_SPI_BASE (0xb0000800)

Definition at line 418 of file bcm63xx_cpu.h.

#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)

Definition at line 828 of file bcm63xx_cpu.h.

#define BCM_6368_TIMER_BASE (0xb0000040)

Definition at line 413 of file bcm63xx_cpu.h.

#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)

Definition at line 827 of file bcm63xx_cpu.h.

#define BCM_6368_UART0_BASE (0xb0000100)

Definition at line 415 of file bcm63xx_cpu.h.

#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)

Definition at line 829 of file bcm63xx_cpu.h.

#define BCM_6368_UART1_BASE (0xb0000120)

Definition at line 416 of file bcm63xx_cpu.h.

#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)

Definition at line 830 of file bcm63xx_cpu.h.

#define BCM_6368_UDC0_BASE (0xdeadbeef)

Definition at line 419 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_BASE (0xb0001400)

Definition at line 424 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)

Definition at line 837 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)

Definition at line 838 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)

Definition at line 840 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)

Definition at line 842 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)

Definition at line 839 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)

Definition at line 841 of file bcm63xx_cpu.h.

#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)

Definition at line 843 of file bcm63xx_cpu.h.

#define BCM_6368_USBDMA_BASE (0xb0004800)

Definition at line 420 of file bcm63xx_cpu.h.

#define BCM_6368_USBH_PRIV_BASE (0xb0001700)

Definition at line 423 of file bcm63xx_cpu.h.

#define BCM_6368_WDT_BASE (0xb000005c)

Definition at line 414 of file bcm63xx_cpu.h.

#define BCM_6368_XTM_BASE (0xb0001800)

Definition at line 442 of file bcm63xx_cpu.h.

#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)

Definition at line 860 of file bcm63xx_cpu.h.

#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)

Definition at line 859 of file bcm63xx_cpu.h.

#define BCM_6368_XTMDMA_BASE (0xb0005000)

Definition at line 443 of file bcm63xx_cpu.h.

#define BCM_6368_XTMDMAC_BASE (0xb0005200)

Definition at line 444 of file bcm63xx_cpu.h.

#define BCM_6368_XTMDMAS_BASE (0xb0005400)

Definition at line 445 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6328 ( ) (0)

Definition at line 34 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6338 ( ) (0)

Definition at line 47 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6345 ( ) (0)

Definition at line 60 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6348 ( ) (0)

Definition at line 73 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6358 ( ) (0)

Definition at line 86 of file bcm63xx_cpu.h.

#define BCMCPU_IS_6368 ( ) (0)

Definition at line 99 of file bcm63xx_cpu.h.

#define RSET_ATM_SIZE 4096

Definition at line 171 of file bcm63xx_cpu.h.

#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)

Definition at line 153 of file bcm63xx_cpu.h.

#define RSET_DSL_SIZE 4096

Definition at line 154 of file bcm63xx_cpu.h.

#define RSET_EHCI_SIZE 256

Definition at line 166 of file bcm63xx_cpu.h.

#define RSET_ENET_SIZE 2048

Definition at line 160 of file bcm63xx_cpu.h.

#define RSET_ENETDMA_SIZE 2048

Definition at line 161 of file bcm63xx_cpu.h.

#define RSET_ENETSW_SIZE 65536

Definition at line 162 of file bcm63xx_cpu.h.

#define RSET_M2M_SIZE 256

Definition at line 170 of file bcm63xx_cpu.h.

#define RSET_OHCI_SIZE 256

Definition at line 165 of file bcm63xx_cpu.h.

#define RSET_PCMCIA_SIZE 12

Definition at line 169 of file bcm63xx_cpu.h.

#define RSET_RNG_SIZE 20

Definition at line 176 of file bcm63xx_cpu.h.

#define RSET_UART_SIZE 24

Definition at line 163 of file bcm63xx_cpu.h.

#define RSET_UDC_SIZE 256

Definition at line 164 of file bcm63xx_cpu.h.

#define RSET_USBD_SIZE 256

Definition at line 167 of file bcm63xx_cpu.h.

#define RSET_USBDMA_SIZE 1280

Definition at line 168 of file bcm63xx_cpu.h.

#define RSET_WDT_SIZE 12

Definition at line 155 of file bcm63xx_cpu.h.

#define RSET_XTM_SIZE 10240

Definition at line 172 of file bcm63xx_cpu.h.

#define RSET_XTMDMA_SIZE 256

Definition at line 173 of file bcm63xx_cpu.h.

#define RSET_XTMDMAC_SIZE ( chans ) (16 * (chans))

Definition at line 174 of file bcm63xx_cpu.h.

#define RSET_XTMDMAS_SIZE ( chans ) (16 * (chans))

Definition at line 175 of file bcm63xx_cpu.h.

Enumeration Type Documentation

enum bcm63xx_irq

Enumerator:

IRQ_TIMER
IRQ_SPI
IRQ_UART0
IRQ_UART1
IRQ_DSL
IRQ_ENET0
IRQ_ENET1
IRQ_ENET_PHY
IRQ_OHCI0
IRQ_EHCI0
IRQ_USBD
IRQ_USBD_RXDMA0
IRQ_USBD_TXDMA0
IRQ_USBD_RXDMA1
IRQ_USBD_TXDMA1
IRQ_USBD_RXDMA2
IRQ_USBD_TXDMA2
IRQ_ENET0_RXDMA
IRQ_ENET0_TXDMA
IRQ_ENET1_RXDMA
IRQ_ENET1_TXDMA
IRQ_PCI
IRQ_PCMCIA
IRQ_ATM
IRQ_ENETSW_RXDMA0
IRQ_ENETSW_RXDMA1
IRQ_ENETSW_RXDMA2
IRQ_ENETSW_RXDMA3
IRQ_ENETSW_TXDMA0
IRQ_ENETSW_TXDMA1
IRQ_ENETSW_TXDMA2
IRQ_ENETSW_TXDMA3
IRQ_XTM
IRQ_XTM_DMA0

Definition at line 578 of file bcm63xx_cpu.h.

enum bcm63xx_regs_set

Enumerator:

RSET_DSL_LMEM
RSET_PERF
RSET_TIMER
RSET_WDT
RSET_UART0
RSET_UART1
RSET_GPIO
RSET_SPI
RSET_UDC0
RSET_OHCI0
RSET_OHCI_PRIV
RSET_USBH_PRIV
RSET_USBD
RSET_USBDMA
RSET_MPI
RSET_PCMCIA
RSET_PCIE
RSET_DSL
RSET_ENET0
RSET_ENET1
RSET_ENETDMA
RSET_ENETDMAC
RSET_ENETDMAS
RSET_ENETSW
RSET_EHCI0
RSET_SDRAM
RSET_MEMC
RSET_DDR
RSET_M2M
RSET_ATM
RSET_XTM
RSET_XTMDMA
RSET_XTMDMAC
RSET_XTMDMAS
RSET_PCM
RSET_PCMDMA
RSET_PCMDMAC
RSET_PCMDMAS
RSET_RNG
RSET_MISC

Definition at line 110 of file bcm63xx_cpu.h.

Function Documentation

u16 __bcm63xx_get_cpu_id ( void )

Definition at line 83 of file cpu.c.

void __init bcm63xx_cpu_init ( void )

Definition at line 241 of file cpu.c.

unsigned int bcm63xx_get_cpu_freq ( void )

Definition at line 97 of file cpu.c.

u16 bcm63xx_get_cpu_rev ( void )

Definition at line 90 of file cpu.c.

unsigned int bcm63xx_get_memory_size ( void )

Definition at line 102 of file cpu.c.

void bcm63xx_machine_halt ( void )

Definition at line 24 of file setup.c.

void bcm63xx_machine_reboot ( void )

Definition at line 64 of file setup.c.

Variable Documentation

const int* bcm63xx_irqs

Definition at line 24 of file cpu.c.

const unsigned long* bcm63xx_regs_base

Definition at line 21 of file cpu.c.

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation