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bcm63xx_regs.h
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1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
3 
4 /*************************************************************************
5  * _REG relative to RSET_PERF
6  *************************************************************************/
7 
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14 
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
17 
18 #define CKCTL_6328_PHYMIPS_EN (1 << 0)
19 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20 #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21 #define CKCTL_6328_ADSL_EN (1 << 3)
22 #define CKCTL_6328_MIPS_EN (1 << 4)
23 #define CKCTL_6328_SAR_EN (1 << 5)
24 #define CKCTL_6328_PCM_EN (1 << 6)
25 #define CKCTL_6328_USBD_EN (1 << 7)
26 #define CKCTL_6328_USBH_EN (1 << 8)
27 #define CKCTL_6328_HSSPI_EN (1 << 9)
28 #define CKCTL_6328_PCIE_EN (1 << 10)
29 #define CKCTL_6328_ROBOSW_EN (1 << 11)
30 
31 #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32  CKCTL_6328_ADSL_QPROC_EN | \
33  CKCTL_6328_ADSL_AFE_EN | \
34  CKCTL_6328_ADSL_EN | \
35  CKCTL_6328_SAR_EN | \
36  CKCTL_6328_PCM_EN | \
37  CKCTL_6328_USBD_EN | \
38  CKCTL_6328_USBH_EN | \
39  CKCTL_6328_ROBOSW_EN | \
40  CKCTL_6328_PCIE_EN)
41 
42 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
43 #define CKCTL_6338_MPI_EN (1 << 1)
44 #define CKCTL_6338_DRAM_EN (1 << 2)
45 #define CKCTL_6338_ENET_EN (1 << 4)
46 #define CKCTL_6338_USBS_EN (1 << 4)
47 #define CKCTL_6338_SAR_EN (1 << 5)
48 #define CKCTL_6338_SPI_EN (1 << 9)
49 
50 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
51  CKCTL_6338_MPI_EN | \
52  CKCTL_6338_ENET_EN | \
53  CKCTL_6338_SAR_EN | \
54  CKCTL_6338_SPI_EN)
55 
56 #define CKCTL_6345_CPU_EN (1 << 0)
57 #define CKCTL_6345_BUS_EN (1 << 1)
58 #define CKCTL_6345_EBI_EN (1 << 2)
59 #define CKCTL_6345_UART_EN (1 << 3)
60 #define CKCTL_6345_ADSLPHY_EN (1 << 4)
61 #define CKCTL_6345_ENET_EN (1 << 7)
62 #define CKCTL_6345_USBH_EN (1 << 8)
63 
64 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
65  CKCTL_6345_USBH_EN | \
66  CKCTL_6345_ADSLPHY_EN)
67 
68 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
69 #define CKCTL_6348_MPI_EN (1 << 1)
70 #define CKCTL_6348_SDRAM_EN (1 << 2)
71 #define CKCTL_6348_M2M_EN (1 << 3)
72 #define CKCTL_6348_ENET_EN (1 << 4)
73 #define CKCTL_6348_SAR_EN (1 << 5)
74 #define CKCTL_6348_USBS_EN (1 << 6)
75 #define CKCTL_6348_USBH_EN (1 << 8)
76 #define CKCTL_6348_SPI_EN (1 << 9)
77 
78 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
79  CKCTL_6348_M2M_EN | \
80  CKCTL_6348_ENET_EN | \
81  CKCTL_6348_SAR_EN | \
82  CKCTL_6348_USBS_EN | \
83  CKCTL_6348_USBH_EN | \
84  CKCTL_6348_SPI_EN)
85 
86 #define CKCTL_6358_ENET_EN (1 << 4)
87 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
88 #define CKCTL_6358_PCM_EN (1 << 8)
89 #define CKCTL_6358_SPI_EN (1 << 9)
90 #define CKCTL_6358_USBS_EN (1 << 10)
91 #define CKCTL_6358_SAR_EN (1 << 11)
92 #define CKCTL_6358_EMUSB_EN (1 << 17)
93 #define CKCTL_6358_ENET0_EN (1 << 18)
94 #define CKCTL_6358_ENET1_EN (1 << 19)
95 #define CKCTL_6358_USBSU_EN (1 << 20)
96 #define CKCTL_6358_EPHY_EN (1 << 21)
97 
98 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
99  CKCTL_6358_ADSLPHY_EN | \
100  CKCTL_6358_PCM_EN | \
101  CKCTL_6358_SPI_EN | \
102  CKCTL_6358_USBS_EN | \
103  CKCTL_6358_SAR_EN | \
104  CKCTL_6358_EMUSB_EN | \
105  CKCTL_6358_ENET0_EN | \
106  CKCTL_6358_ENET1_EN | \
107  CKCTL_6358_USBSU_EN | \
108  CKCTL_6358_EPHY_EN)
109 
110 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
111 #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
112 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
113 #define CKCTL_6368_VDSL_EN (1 << 5)
114 #define CKCTL_6368_PHYMIPS_EN (1 << 6)
115 #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
116 #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
117 #define CKCTL_6368_SPI_EN (1 << 9)
118 #define CKCTL_6368_USBD_EN (1 << 10)
119 #define CKCTL_6368_SAR_EN (1 << 11)
120 #define CKCTL_6368_ROBOSW_EN (1 << 12)
121 #define CKCTL_6368_UTOPIA_EN (1 << 13)
122 #define CKCTL_6368_PCM_EN (1 << 14)
123 #define CKCTL_6368_USBH_EN (1 << 15)
124 #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
125 #define CKCTL_6368_NAND_EN (1 << 17)
126 #define CKCTL_6368_IPSEC_EN (1 << 18)
127 
128 #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
129  CKCTL_6368_SWPKT_SAR_EN | \
130  CKCTL_6368_SPI_EN | \
131  CKCTL_6368_USBD_EN | \
132  CKCTL_6368_SAR_EN | \
133  CKCTL_6368_ROBOSW_EN | \
134  CKCTL_6368_UTOPIA_EN | \
135  CKCTL_6368_PCM_EN | \
136  CKCTL_6368_USBH_EN | \
137  CKCTL_6368_DISABLE_GLESS_EN | \
138  CKCTL_6368_NAND_EN | \
139  CKCTL_6368_IPSEC_EN)
140 
141 /* System PLL Control register */
142 #define PERF_SYS_PLL_CTL_REG 0x8
143 #define SYS_PLL_SOFT_RESET 0x1
144 
145 /* Interrupt Mask register */
146 #define PERF_IRQMASK_6328_REG 0x20
147 #define PERF_IRQMASK_6338_REG 0xc
148 #define PERF_IRQMASK_6345_REG 0xc
149 #define PERF_IRQMASK_6348_REG 0xc
150 #define PERF_IRQMASK_6358_REG 0xc
151 #define PERF_IRQMASK_6368_REG 0x20
152 
153 /* Interrupt Status register */
154 #define PERF_IRQSTAT_6328_REG 0x28
155 #define PERF_IRQSTAT_6338_REG 0x10
156 #define PERF_IRQSTAT_6345_REG 0x10
157 #define PERF_IRQSTAT_6348_REG 0x10
158 #define PERF_IRQSTAT_6358_REG 0x10
159 #define PERF_IRQSTAT_6368_REG 0x28
160 
161 /* External Interrupt Configuration register */
162 #define PERF_EXTIRQ_CFG_REG_6328 0x18
163 #define PERF_EXTIRQ_CFG_REG_6338 0x14
164 #define PERF_EXTIRQ_CFG_REG_6345 0x14
165 #define PERF_EXTIRQ_CFG_REG_6348 0x14
166 #define PERF_EXTIRQ_CFG_REG_6358 0x14
167 #define PERF_EXTIRQ_CFG_REG_6368 0x18
168 
169 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
170 
171 /* for 6348 only */
172 #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
173 #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
174 #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
175 #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
176 #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
177 #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
178 #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
179 #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
180 
181 /* for all others */
182 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
183 #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
184 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
185 #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
186 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
187 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
188 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
189 #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
190 
191 /* Soft Reset register */
192 #define PERF_SOFTRESET_REG 0x28
193 #define PERF_SOFTRESET_6328_REG 0x10
194 #define PERF_SOFTRESET_6368_REG 0x10
195 
196 #define SOFTRESET_6328_SPI_MASK (1 << 0)
197 #define SOFTRESET_6328_EPHY_MASK (1 << 1)
198 #define SOFTRESET_6328_SAR_MASK (1 << 2)
199 #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
200 #define SOFTRESET_6328_USBS_MASK (1 << 4)
201 #define SOFTRESET_6328_USBH_MASK (1 << 5)
202 #define SOFTRESET_6328_PCM_MASK (1 << 6)
203 #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
204 #define SOFTRESET_6328_PCIE_MASK (1 << 8)
205 #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
206 #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
207 
208 #define SOFTRESET_6338_SPI_MASK (1 << 0)
209 #define SOFTRESET_6338_ENET_MASK (1 << 2)
210 #define SOFTRESET_6338_USBH_MASK (1 << 3)
211 #define SOFTRESET_6338_USBS_MASK (1 << 4)
212 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
213 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
214 #define SOFTRESET_6338_SAR_MASK (1 << 7)
215 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
216 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
217 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
218  SOFTRESET_6338_ENET_MASK | \
219  SOFTRESET_6338_USBH_MASK | \
220  SOFTRESET_6338_USBS_MASK | \
221  SOFTRESET_6338_ADSL_MASK | \
222  SOFTRESET_6338_DMAMEM_MASK | \
223  SOFTRESET_6338_SAR_MASK | \
224  SOFTRESET_6338_ACLC_MASK | \
225  SOFTRESET_6338_ADSLMIPSPLL_MASK)
226 
227 #define SOFTRESET_6348_SPI_MASK (1 << 0)
228 #define SOFTRESET_6348_ENET_MASK (1 << 2)
229 #define SOFTRESET_6348_USBH_MASK (1 << 3)
230 #define SOFTRESET_6348_USBS_MASK (1 << 4)
231 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
232 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
233 #define SOFTRESET_6348_SAR_MASK (1 << 7)
234 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
235 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
236 
237 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
238  SOFTRESET_6348_ENET_MASK | \
239  SOFTRESET_6348_USBH_MASK | \
240  SOFTRESET_6348_USBS_MASK | \
241  SOFTRESET_6348_ADSL_MASK | \
242  SOFTRESET_6348_DMAMEM_MASK | \
243  SOFTRESET_6348_SAR_MASK | \
244  SOFTRESET_6348_ACLC_MASK | \
245  SOFTRESET_6348_ADSLMIPSPLL_MASK)
246 
247 #define SOFTRESET_6368_SPI_MASK (1 << 0)
248 #define SOFTRESET_6368_MPI_MASK (1 << 3)
249 #define SOFTRESET_6368_EPHY_MASK (1 << 6)
250 #define SOFTRESET_6368_SAR_MASK (1 << 7)
251 #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
252 #define SOFTRESET_6368_USBS_MASK (1 << 11)
253 #define SOFTRESET_6368_USBH_MASK (1 << 12)
254 #define SOFTRESET_6368_PCM_MASK (1 << 13)
255 
256 /* MIPS PLL control register */
257 #define PERF_MIPSPLLCTL_REG 0x34
258 #define MIPSPLLCTL_N1_SHIFT 20
259 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
260 #define MIPSPLLCTL_N2_SHIFT 15
261 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
262 #define MIPSPLLCTL_M1REF_SHIFT 12
263 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
264 #define MIPSPLLCTL_M2REF_SHIFT 9
265 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
266 #define MIPSPLLCTL_M1CPU_SHIFT 6
267 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
268 #define MIPSPLLCTL_M1BUS_SHIFT 3
269 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
270 #define MIPSPLLCTL_M2BUS_SHIFT 0
271 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
272 
273 /* ADSL PHY PLL Control register */
274 #define PERF_ADSLPLLCTL_REG 0x38
275 #define ADSLPLLCTL_N1_SHIFT 20
276 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
277 #define ADSLPLLCTL_N2_SHIFT 15
278 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
279 #define ADSLPLLCTL_M1REF_SHIFT 12
280 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
281 #define ADSLPLLCTL_M2REF_SHIFT 9
282 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
283 #define ADSLPLLCTL_M1CPU_SHIFT 6
284 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
285 #define ADSLPLLCTL_M1BUS_SHIFT 3
286 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
287 #define ADSLPLLCTL_M2BUS_SHIFT 0
288 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
289 
290 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
291  (((n1) << ADSLPLLCTL_N1_SHIFT) | \
292  ((n2) << ADSLPLLCTL_N2_SHIFT) | \
293  ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
294  ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
295  ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
296  ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
297  ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
298 
299 
300 /*************************************************************************
301  * _REG relative to RSET_TIMER
302  *************************************************************************/
303 
304 #define BCM63XX_TIMER_COUNT 4
305 #define TIMER_T0_ID 0
306 #define TIMER_T1_ID 1
307 #define TIMER_T2_ID 2
308 #define TIMER_WDT_ID 3
309 
310 /* Timer irqstat register */
311 #define TIMER_IRQSTAT_REG 0
312 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
313 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
314 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
315 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
316 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
317 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
318 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
319 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
320 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
321 
322 /* Timer control register */
323 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
324 #define TIMER_CTL0_REG 0x4
325 #define TIMER_CTL1_REG 0x8
326 #define TIMER_CTL2_REG 0xC
327 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
328 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
329 #define TIMER_CTL_ENABLE_MASK (1 << 31)
330 
331 
332 /*************************************************************************
333  * _REG relative to RSET_WDT
334  *************************************************************************/
335 
336 /* Watchdog default count register */
337 #define WDT_DEFVAL_REG 0x0
338 
339 /* Watchdog control register */
340 #define WDT_CTL_REG 0x4
341 
342 /* Watchdog control register constants */
343 #define WDT_START_1 (0xff00)
344 #define WDT_START_2 (0x00ff)
345 #define WDT_STOP_1 (0xee00)
346 #define WDT_STOP_2 (0x00ee)
347 
348 /* Watchdog reset length register */
349 #define WDT_RSTLEN_REG 0x8
350 
351 /* Watchdog soft reset register (BCM6328 only) */
352 #define WDT_SOFTRESET_REG 0xc
353 
354 /*************************************************************************
355  * _REG relative to RSET_UARTx
356  *************************************************************************/
357 
358 /* UART Control Register */
359 #define UART_CTL_REG 0x0
360 #define UART_CTL_RXTMOUTCNT_SHIFT 0
361 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
362 #define UART_CTL_RSTTXDN_SHIFT 5
363 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
364 #define UART_CTL_RSTRXFIFO_SHIFT 6
365 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
366 #define UART_CTL_RSTTXFIFO_SHIFT 7
367 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
368 #define UART_CTL_STOPBITS_SHIFT 8
369 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
370 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
371 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
372 #define UART_CTL_BITSPERSYM_SHIFT 12
373 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
374 #define UART_CTL_XMITBRK_SHIFT 14
375 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
376 #define UART_CTL_RSVD_SHIFT 15
377 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
378 #define UART_CTL_RXPAREVEN_SHIFT 16
379 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
380 #define UART_CTL_RXPAREN_SHIFT 17
381 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
382 #define UART_CTL_TXPAREVEN_SHIFT 18
383 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
384 #define UART_CTL_TXPAREN_SHIFT 18
385 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
386 #define UART_CTL_LOOPBACK_SHIFT 20
387 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
388 #define UART_CTL_RXEN_SHIFT 21
389 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
390 #define UART_CTL_TXEN_SHIFT 22
391 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
392 #define UART_CTL_BRGEN_SHIFT 23
393 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
394 
395 /* UART Baudword register */
396 #define UART_BAUD_REG 0x4
397 
398 /* UART Misc Control register */
399 #define UART_MCTL_REG 0x8
400 #define UART_MCTL_DTR_SHIFT 0
401 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
402 #define UART_MCTL_RTS_SHIFT 1
403 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
404 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
405 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
406 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
407 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
408 #define UART_MCTL_RXFIFOFILL_SHIFT 16
409 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
410 #define UART_MCTL_TXFIFOFILL_SHIFT 24
411 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
412 
413 /* UART External Input Configuration register */
414 #define UART_EXTINP_REG 0xc
415 #define UART_EXTINP_RI_SHIFT 0
416 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
417 #define UART_EXTINP_CTS_SHIFT 1
418 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
419 #define UART_EXTINP_DCD_SHIFT 2
420 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
421 #define UART_EXTINP_DSR_SHIFT 3
422 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
423 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
424 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
425 #define UART_EXTINP_IR_RI 0
426 #define UART_EXTINP_IR_CTS 1
427 #define UART_EXTINP_IR_DCD 2
428 #define UART_EXTINP_IR_DSR 3
429 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
430 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
431 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
432 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
433 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
434 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
435 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
436 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
437 
438 /* UART Interrupt register */
439 #define UART_IR_REG 0x10
440 #define UART_IR_MASK(x) (1 << (x + 16))
441 #define UART_IR_STAT(x) (1 << (x))
442 #define UART_IR_EXTIP 0
443 #define UART_IR_TXUNDER 1
444 #define UART_IR_TXOVER 2
445 #define UART_IR_TXTRESH 3
446 #define UART_IR_TXRDLATCH 4
447 #define UART_IR_TXEMPTY 5
448 #define UART_IR_RXUNDER 6
449 #define UART_IR_RXOVER 7
450 #define UART_IR_RXTIMEOUT 8
451 #define UART_IR_RXFULL 9
452 #define UART_IR_RXTHRESH 10
453 #define UART_IR_RXNOTEMPTY 11
454 #define UART_IR_RXFRAMEERR 12
455 #define UART_IR_RXPARERR 13
456 #define UART_IR_RXBRK 14
457 #define UART_IR_TXDONE 15
458 
459 /* UART Fifo register */
460 #define UART_FIFO_REG 0x14
461 #define UART_FIFO_VALID_SHIFT 0
462 #define UART_FIFO_VALID_MASK 0xff
463 #define UART_FIFO_FRAMEERR_SHIFT 8
464 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
465 #define UART_FIFO_PARERR_SHIFT 9
466 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
467 #define UART_FIFO_BRKDET_SHIFT 10
468 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
469 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
470  UART_FIFO_PARERR_MASK | \
471  UART_FIFO_BRKDET_MASK)
472 
473 
474 /*************************************************************************
475  * _REG relative to RSET_GPIO
476  *************************************************************************/
477 
478 /* GPIO registers */
479 #define GPIO_CTL_HI_REG 0x0
480 #define GPIO_CTL_LO_REG 0x4
481 #define GPIO_DATA_HI_REG 0x8
482 #define GPIO_DATA_LO_REG 0xC
483 #define GPIO_DATA_LO_REG_6345 0x8
484 
485 /* GPIO mux registers and constants */
486 #define GPIO_MODE_REG 0x18
487 
488 #define GPIO_MODE_6348_G4_DIAG 0x00090000
489 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
490 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
491 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
492 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
493 #define GPIO_MODE_6348_G3_DIAG 0x00009000
494 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
495 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
496 #define GPIO_MODE_6348_G2_DIAG 0x00000900
497 #define GPIO_MODE_6348_G2_PCI 0x00000500
498 #define GPIO_MODE_6348_G1_DIAG 0x00000090
499 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
500 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
501 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
502 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
503 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
504 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
505 #define GPIO_MODE_6348_G0_DIAG 0x00000009
506 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
507 
508 #define GPIO_MODE_6358_EXTRACS (1 << 5)
509 #define GPIO_MODE_6358_UART1 (1 << 6)
510 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
511 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
512 #define GPIO_MODE_6358_UTOPIA (1 << 12)
513 
514 #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
515 #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
516 #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
517 #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
518 #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
519 #define GPIO_MODE_6368_INET_LED (1 << 5)
520 #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
521 #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
522 #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
523 #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
524 #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
525 #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
526 #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
527 #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
528 #define GPIO_MODE_6368_USBD_LED (1 << 14)
529 #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
530 #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
531 #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
532 #define GPIO_MODE_6368_PCI_INTB (1 << 18)
533 #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
534 #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
535 #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
536 #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
537 #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
538 #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
539 #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
540 #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
541 #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
542 #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
543 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
544 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
545 
546 
547 #define GPIO_PINMUX_OTHR_REG 0x24
548 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
549 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
550 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
551 #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
552 
553 #define GPIO_BASEMODE_6368_REG 0x38
554 #define GPIO_BASEMODE_6368_UART2 0x1
555 #define GPIO_BASEMODE_6368_GPIO 0x0
556 #define GPIO_BASEMODE_6368_MASK 0x7
557 /* those bits must be kept as read in gpio basemode register*/
558 
559 #define GPIO_STRAPBUS_REG 0x40
560 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
561 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
562 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
563 #define STRAPBUS_6368_BOOT_SEL_NAND 0
564 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
565 #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
566 
567 
568 /*************************************************************************
569  * _REG relative to RSET_ENET
570  *************************************************************************/
571 
572 /* Receiver Configuration register */
573 #define ENET_RXCFG_REG 0x0
574 #define ENET_RXCFG_ALLMCAST_SHIFT 1
575 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
576 #define ENET_RXCFG_PROMISC_SHIFT 3
577 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
578 #define ENET_RXCFG_LOOPBACK_SHIFT 4
579 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
580 #define ENET_RXCFG_ENFLOW_SHIFT 5
581 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
582 
583 /* Receive Maximum Length register */
584 #define ENET_RXMAXLEN_REG 0x4
585 #define ENET_RXMAXLEN_SHIFT 0
586 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
587 
588 /* Transmit Maximum Length register */
589 #define ENET_TXMAXLEN_REG 0x8
590 #define ENET_TXMAXLEN_SHIFT 0
591 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
592 
593 /* MII Status/Control register */
594 #define ENET_MIISC_REG 0x10
595 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
596 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
597 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
598 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
599 
600 /* MII Data register */
601 #define ENET_MIIDATA_REG 0x14
602 #define ENET_MIIDATA_DATA_SHIFT 0
603 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
604 #define ENET_MIIDATA_TA_SHIFT 16
605 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
606 #define ENET_MIIDATA_REG_SHIFT 18
607 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
608 #define ENET_MIIDATA_PHYID_SHIFT 23
609 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
610 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
611 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
612 
613 /* Ethernet Interrupt Mask register */
614 #define ENET_IRMASK_REG 0x18
615 
616 /* Ethernet Interrupt register */
617 #define ENET_IR_REG 0x1c
618 #define ENET_IR_MII (1 << 0)
619 #define ENET_IR_MIB (1 << 1)
620 #define ENET_IR_FLOWC (1 << 2)
621 
622 /* Ethernet Control register */
623 #define ENET_CTL_REG 0x2c
624 #define ENET_CTL_ENABLE_SHIFT 0
625 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
626 #define ENET_CTL_DISABLE_SHIFT 1
627 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
628 #define ENET_CTL_SRESET_SHIFT 2
629 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
630 #define ENET_CTL_EPHYSEL_SHIFT 3
631 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
632 
633 /* Transmit Control register */
634 #define ENET_TXCTL_REG 0x30
635 #define ENET_TXCTL_FD_SHIFT 0
636 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
637 
638 /* Transmit Watermask register */
639 #define ENET_TXWMARK_REG 0x34
640 #define ENET_TXWMARK_WM_SHIFT 0
641 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
642 
643 /* MIB Control register */
644 #define ENET_MIBCTL_REG 0x38
645 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
646 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
647 
648 /* Perfect Match Data Low register */
649 #define ENET_PML_REG(x) (0x58 + (x) * 8)
650 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
651 #define ENET_PMH_DATAVALID_SHIFT 16
652 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
653 
654 /* MIB register */
655 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
656 #define ENET_MIB_REG_COUNT 55
657 
658 
659 /*************************************************************************
660  * _REG relative to RSET_ENETDMA
661  *************************************************************************/
662 
663 /* Controller Configuration Register */
664 #define ENETDMA_CFG_REG (0x0)
665 #define ENETDMA_CFG_EN_SHIFT 0
666 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
667 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
668 
669 /* Flow Control Descriptor Low Threshold register */
670 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
671 
672 /* Flow Control Descriptor High Threshold register */
673 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
674 
675 /* Flow Control Descriptor Buffer Alloca Threshold register */
676 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
677 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
678 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
679 
680 /* Global interrupt status */
681 #define ENETDMA_GLB_IRQSTAT_REG (0x40)
682 
683 /* Global interrupt mask */
684 #define ENETDMA_GLB_IRQMASK_REG (0x44)
685 
686 /* Channel Configuration register */
687 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
688 #define ENETDMA_CHANCFG_EN_SHIFT 0
689 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
690 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
691 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
692 
693 /* Interrupt Control/Status register */
694 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
695 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
696 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
697 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
698 
699 /* Interrupt Mask register */
700 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
701 
702 /* Maximum Burst Length */
703 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
704 
705 /* Ring Start Address register */
706 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
707 
708 /* State Ram Word 2 */
709 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
710 
711 /* State Ram Word 3 */
712 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
713 
714 /* State Ram Word 4 */
715 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
716 
717 
718 /*************************************************************************
719  * _REG relative to RSET_ENETDMAC
720  *************************************************************************/
721 
722 /* Channel Configuration register */
723 #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
724 #define ENETDMAC_CHANCFG_EN_SHIFT 0
725 #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
726 #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
727 #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
728 #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
729 #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
730 
731 /* Interrupt Control/Status register */
732 #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
733 #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
734 #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
735 #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
736 
737 /* Interrupt Mask register */
738 #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
739 
740 /* Maximum Burst Length */
741 #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
742 
743 
744 /*************************************************************************
745  * _REG relative to RSET_ENETDMAS
746  *************************************************************************/
747 
748 /* Ring Start Address register */
749 #define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
750 
751 /* State Ram Word 2 */
752 #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
753 
754 /* State Ram Word 3 */
755 #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
756 
757 /* State Ram Word 4 */
758 #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
759 
760 
761 /*************************************************************************
762  * _REG relative to RSET_ENETSW
763  *************************************************************************/
764 
765 /* MIB register */
766 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
767 #define ENETSW_MIB_REG_COUNT 47
768 
769 
770 /*************************************************************************
771  * _REG relative to RSET_OHCI_PRIV
772  *************************************************************************/
773 
774 #define OHCI_PRIV_REG 0x0
775 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
776 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
777 #define OHCI_PRIV_REG_SWAP_SHIFT 3
778 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
779 
780 
781 /*************************************************************************
782  * _REG relative to RSET_USBH_PRIV
783  *************************************************************************/
784 
785 #define USBH_PRIV_SWAP_6358_REG 0x0
786 #define USBH_PRIV_SWAP_6368_REG 0x1c
787 
788 #define USBH_PRIV_SWAP_USBD_SHIFT 6
789 #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
790 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
791 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
792 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
793 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
794 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
795 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
796 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
797 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
798 
799 #define USBH_PRIV_UTMI_CTL_6368_REG 0x10
800 #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
801 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
802 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
803 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
804 
805 #define USBH_PRIV_TEST_6358_REG 0x24
806 #define USBH_PRIV_TEST_6368_REG 0x14
807 
808 #define USBH_PRIV_SETUP_6368_REG 0x28
809 #define USBH_PRIV_SETUP_IOC_SHIFT 4
810 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
811 
812 
813 /*************************************************************************
814  * _REG relative to RSET_USBD
815  *************************************************************************/
816 
817 /* General control */
818 #define USBD_CONTROL_REG 0x00
819 #define USBD_CONTROL_TXZLENINS_SHIFT 14
820 #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
821 #define USBD_CONTROL_AUTO_CSRS_SHIFT 13
822 #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
823 #define USBD_CONTROL_RXZSCFG_SHIFT 12
824 #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
825 #define USBD_CONTROL_INIT_SEL_SHIFT 8
826 #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
827 #define USBD_CONTROL_FIFO_RESET_SHIFT 6
828 #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
829 #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
830 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
831 #define USBD_CONTROL_DONE_CSRS_SHIFT 0
832 #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
833 
834 /* Strap options */
835 #define USBD_STRAPS_REG 0x04
836 #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
837 #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
838 #define USBD_STRAPS_APP_DISCON_SHIFT 9
839 #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
840 #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
841 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
842 #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
843 #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
844 #define USBD_STRAPS_APP_RAM_IF_SHIFT 7
845 #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
846 #define USBD_STRAPS_APP_8BITPHY_SHIFT 2
847 #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
848 #define USBD_STRAPS_SPEED_SHIFT 0
849 #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
850 
851 /* Stall control */
852 #define USBD_STALL_REG 0x08
853 #define USBD_STALL_UPDATE_SHIFT 7
854 #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
855 #define USBD_STALL_ENABLE_SHIFT 6
856 #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
857 #define USBD_STALL_EPNUM_SHIFT 0
858 #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
859 
860 /* General status */
861 #define USBD_STATUS_REG 0x0c
862 #define USBD_STATUS_SOF_SHIFT 16
863 #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
864 #define USBD_STATUS_SPD_SHIFT 12
865 #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
866 #define USBD_STATUS_ALTINTF_SHIFT 8
867 #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
868 #define USBD_STATUS_INTF_SHIFT 4
869 #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
870 #define USBD_STATUS_CFG_SHIFT 0
871 #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
872 
873 /* Other events */
874 #define USBD_EVENTS_REG 0x10
875 #define USBD_EVENTS_USB_LINK_SHIFT 10
876 #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
877 
878 /* IRQ status */
879 #define USBD_EVENT_IRQ_STATUS_REG 0x14
880 
881 /* IRQ level (2 bits per IRQ event) */
882 #define USBD_EVENT_IRQ_CFG_HI_REG 0x18
883 
884 #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
885 
886 #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
887 #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
888 #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
889 #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
890 
891 /* IRQ mask (1=unmasked) */
892 #define USBD_EVENT_IRQ_MASK_REG 0x20
893 
894 /* IRQ bits */
895 #define USBD_EVENT_IRQ_USB_LINK 10
896 #define USBD_EVENT_IRQ_SETCFG 9
897 #define USBD_EVENT_IRQ_SETINTF 8
898 #define USBD_EVENT_IRQ_ERRATIC_ERR 7
899 #define USBD_EVENT_IRQ_SET_CSRS 6
900 #define USBD_EVENT_IRQ_SUSPEND 5
901 #define USBD_EVENT_IRQ_EARLY_SUSPEND 4
902 #define USBD_EVENT_IRQ_SOF 3
903 #define USBD_EVENT_IRQ_ENUM_ON 2
904 #define USBD_EVENT_IRQ_SETUP 1
905 #define USBD_EVENT_IRQ_USB_RESET 0
906 
907 /* TX FIFO partitioning */
908 #define USBD_TXFIFO_CONFIG_REG 0x40
909 #define USBD_TXFIFO_CONFIG_END_SHIFT 16
910 #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
911 #define USBD_TXFIFO_CONFIG_START_SHIFT 0
912 #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
913 
914 /* RX FIFO partitioning */
915 #define USBD_RXFIFO_CONFIG_REG 0x44
916 #define USBD_RXFIFO_CONFIG_END_SHIFT 16
917 #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
918 #define USBD_RXFIFO_CONFIG_START_SHIFT 0
919 #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
920 
921 /* TX FIFO/endpoint configuration */
922 #define USBD_TXFIFO_EPSIZE_REG 0x48
923 
924 /* RX FIFO/endpoint configuration */
925 #define USBD_RXFIFO_EPSIZE_REG 0x4c
926 
927 /* Endpoint<->DMA mappings */
928 #define USBD_EPNUM_TYPEMAP_REG 0x50
929 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
930 #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
931 #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
932 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
933 
934 /* Misc per-endpoint settings */
935 #define USBD_CSR_SETUPADDR_REG 0x80
936 #define USBD_CSR_SETUPADDR_DEF 0xb550
937 
938 #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
939 #define USBD_CSR_EP_MAXPKT_SHIFT 19
940 #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
941 #define USBD_CSR_EP_ALTIFACE_SHIFT 15
942 #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
943 #define USBD_CSR_EP_IFACE_SHIFT 11
944 #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
945 #define USBD_CSR_EP_CFG_SHIFT 7
946 #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
947 #define USBD_CSR_EP_TYPE_SHIFT 5
948 #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
949 #define USBD_CSR_EP_DIR_SHIFT 4
950 #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
951 #define USBD_CSR_EP_LOG_SHIFT 0
952 #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
953 
954 
955 /*************************************************************************
956  * _REG relative to RSET_MPI
957  *************************************************************************/
958 
959 /* well known (hard wired) chip select */
960 #define MPI_CS_PCMCIA_COMMON 4
961 #define MPI_CS_PCMCIA_ATTR 5
962 #define MPI_CS_PCMCIA_IO 6
963 
964 /* Chip select base register */
965 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
966 #define MPI_CSBASE_BASE_SHIFT 13
967 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
968 #define MPI_CSBASE_SIZE_SHIFT 0
969 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
970 
971 #define MPI_CSBASE_SIZE_8K 0
972 #define MPI_CSBASE_SIZE_16K 1
973 #define MPI_CSBASE_SIZE_32K 2
974 #define MPI_CSBASE_SIZE_64K 3
975 #define MPI_CSBASE_SIZE_128K 4
976 #define MPI_CSBASE_SIZE_256K 5
977 #define MPI_CSBASE_SIZE_512K 6
978 #define MPI_CSBASE_SIZE_1M 7
979 #define MPI_CSBASE_SIZE_2M 8
980 #define MPI_CSBASE_SIZE_4M 9
981 #define MPI_CSBASE_SIZE_8M 10
982 #define MPI_CSBASE_SIZE_16M 11
983 #define MPI_CSBASE_SIZE_32M 12
984 #define MPI_CSBASE_SIZE_64M 13
985 #define MPI_CSBASE_SIZE_128M 14
986 #define MPI_CSBASE_SIZE_256M 15
987 
988 /* Chip select control register */
989 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
990 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
991 #define MPI_CSCTL_WAIT_SHIFT 1
992 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
993 #define MPI_CSCTL_DATA16_MASK (1 << 4)
994 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
995 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
996 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
997 #define MPI_CSCTL_SETUP_SHIFT 16
998 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
999 #define MPI_CSCTL_HOLD_SHIFT 20
1000 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
1001 
1002 /* PCI registers */
1003 #define MPI_SP0_RANGE_REG 0x100
1004 #define MPI_SP0_REMAP_REG 0x104
1005 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
1006 #define MPI_SP1_RANGE_REG 0x10C
1007 #define MPI_SP1_REMAP_REG 0x110
1008 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
1009 
1010 #define MPI_L2PCFG_REG 0x11C
1011 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
1012 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
1013 #define MPI_L2PCFG_REG_SHIFT 2
1014 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
1015 #define MPI_L2PCFG_FUNC_SHIFT 8
1016 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
1017 #define MPI_L2PCFG_DEVNUM_SHIFT 11
1018 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
1019 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
1020 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
1021 
1022 #define MPI_L2PMEMRANGE1_REG 0x120
1023 #define MPI_L2PMEMBASE1_REG 0x124
1024 #define MPI_L2PMEMREMAP1_REG 0x128
1025 #define MPI_L2PMEMRANGE2_REG 0x12C
1026 #define MPI_L2PMEMBASE2_REG 0x130
1027 #define MPI_L2PMEMREMAP2_REG 0x134
1028 #define MPI_L2PIORANGE_REG 0x138
1029 #define MPI_L2PIOBASE_REG 0x13C
1030 #define MPI_L2PIOREMAP_REG 0x140
1031 #define MPI_L2P_BASE_MASK (0xffff8000)
1032 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
1033 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
1034 
1035 #define MPI_PCIMODESEL_REG 0x144
1036 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
1037 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
1038 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
1039 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
1040 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
1041 
1042 #define MPI_LOCBUSCTL_REG 0x14C
1043 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
1044 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
1045 
1046 #define MPI_LOCINT_REG 0x150
1047 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
1048 #define MPI_LOCINT_STAT(x) (1 << (x))
1049 #define MPI_LOCINT_DIR_FAILED 6
1050 #define MPI_LOCINT_EXT_PCI_INT 7
1051 #define MPI_LOCINT_SERR 8
1052 #define MPI_LOCINT_CSERR 9
1053 
1054 #define MPI_PCICFGCTL_REG 0x178
1055 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
1056 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
1057 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
1058 
1059 #define MPI_PCICFGDATA_REG 0x17C
1060 
1061 /* PCI host bridge custom register */
1062 #define BCMPCI_REG_TIMERS 0x40
1063 #define REG_TIMER_TRDY_SHIFT 0
1064 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
1065 #define REG_TIMER_RETRY_SHIFT 8
1066 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
1067 
1068 
1069 /*************************************************************************
1070  * _REG relative to RSET_PCMCIA
1071  *************************************************************************/
1072 
1073 #define PCMCIA_C1_REG 0x0
1074 #define PCMCIA_C1_CD1_MASK (1 << 0)
1075 #define PCMCIA_C1_CD2_MASK (1 << 1)
1076 #define PCMCIA_C1_VS1_MASK (1 << 2)
1077 #define PCMCIA_C1_VS2_MASK (1 << 3)
1078 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
1079 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
1080 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
1081 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
1082 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
1083 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
1084 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
1085 #define PCMCIA_C1_RESET_MASK (1 << 18)
1086 
1087 #define PCMCIA_C2_REG 0x8
1088 #define PCMCIA_C2_DATA16_MASK (1 << 0)
1089 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
1090 #define PCMCIA_C2_RWCOUNT_SHIFT 2
1091 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
1092 #define PCMCIA_C2_INACTIVE_SHIFT 8
1093 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
1094 #define PCMCIA_C2_SETUP_SHIFT 16
1095 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
1096 #define PCMCIA_C2_HOLD_SHIFT 24
1097 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
1098 
1099 
1100 /*************************************************************************
1101  * _REG relative to RSET_SDRAM
1102  *************************************************************************/
1103 
1104 #define SDRAM_CFG_REG 0x0
1105 #define SDRAM_CFG_ROW_SHIFT 4
1106 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
1107 #define SDRAM_CFG_COL_SHIFT 6
1108 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
1109 #define SDRAM_CFG_32B_SHIFT 10
1110 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
1111 #define SDRAM_CFG_BANK_SHIFT 13
1112 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
1113 
1114 #define SDRAM_MBASE_REG 0xc
1115 
1116 #define SDRAM_PRIO_REG 0x2C
1117 #define SDRAM_PRIO_MIPS_SHIFT 29
1118 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
1119 #define SDRAM_PRIO_ADSL_SHIFT 30
1120 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
1121 #define SDRAM_PRIO_EN_SHIFT 31
1122 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
1123 
1124 
1125 /*************************************************************************
1126  * _REG relative to RSET_MEMC
1127  *************************************************************************/
1128 
1129 #define MEMC_CFG_REG 0x4
1130 #define MEMC_CFG_32B_SHIFT 1
1131 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
1132 #define MEMC_CFG_COL_SHIFT 3
1133 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
1134 #define MEMC_CFG_ROW_SHIFT 6
1135 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
1136 
1137 
1138 /*************************************************************************
1139  * _REG relative to RSET_DDR
1140  *************************************************************************/
1141 
1142 #define DDR_CSEND_REG 0x8
1143 
1144 #define DDR_DMIPSPLLCFG_REG 0x18
1145 #define DMIPSPLLCFG_M1_SHIFT 0
1146 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
1147 #define DMIPSPLLCFG_N1_SHIFT 23
1148 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
1149 #define DMIPSPLLCFG_N2_SHIFT 29
1150 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
1151 
1152 #define DDR_DMIPSPLLCFG_6368_REG 0x20
1153 #define DMIPSPLLCFG_6368_P1_SHIFT 0
1154 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1155 #define DMIPSPLLCFG_6368_P2_SHIFT 4
1156 #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1157 #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
1158 #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1159 
1160 #define DDR_DMIPSPLLDIV_6368_REG 0x24
1161 #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
1162 #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1163 
1164 
1165 /*************************************************************************
1166  * _REG relative to RSET_M2M
1167  *************************************************************************/
1168 
1169 #define M2M_RX 0
1170 #define M2M_TX 1
1171 
1172 #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1173 #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1174 #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1175 
1176 #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1177 #define M2M_CTRL_ENABLE_MASK (1 << 0)
1178 #define M2M_CTRL_IRQEN_MASK (1 << 1)
1179 #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
1180 #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
1181 #define M2M_CTRL_NOINC_MASK (1 << 8)
1182 #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
1183 #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
1184 #define M2M_CTRL_ENDIAN_MASK (1 << 11)
1185 
1186 #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1187 #define M2M_STAT_DONE (1 << 0)
1188 #define M2M_STAT_ERROR (1 << 1)
1189 
1190 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1191 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1192 
1193 /*************************************************************************
1194  * _REG relative to RSET_RNG
1195  *************************************************************************/
1196 
1197 #define RNG_CTRL 0x00
1198 #define RNG_EN (1 << 0)
1199 
1200 #define RNG_STAT 0x04
1201 #define RNG_AVAIL_MASK (0xff000000)
1202 
1203 #define RNG_DATA 0x08
1204 #define RNG_THRES 0x0c
1205 #define RNG_MASK 0x10
1206 
1207 /*************************************************************************
1208  * _REG relative to RSET_SPI
1209  *************************************************************************/
1210 
1211 /* BCM 6338 SPI core */
1212 #define SPI_6338_CMD 0x00 /* 16-bits register */
1213 #define SPI_6338_INT_STATUS 0x02
1214 #define SPI_6338_INT_MASK_ST 0x03
1215 #define SPI_6338_INT_MASK 0x04
1216 #define SPI_6338_ST 0x05
1217 #define SPI_6338_CLK_CFG 0x06
1218 #define SPI_6338_FILL_BYTE 0x07
1219 #define SPI_6338_MSG_TAIL 0x09
1220 #define SPI_6338_RX_TAIL 0x0b
1221 #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1222 #define SPI_6338_MSG_CTL_WIDTH 8
1223 #define SPI_6338_MSG_DATA 0x41
1224 #define SPI_6338_MSG_DATA_SIZE 0x3f
1225 #define SPI_6338_RX_DATA 0x80
1226 #define SPI_6338_RX_DATA_SIZE 0x3f
1227 
1228 /* BCM 6348 SPI core */
1229 #define SPI_6348_CMD 0x00 /* 16-bits register */
1230 #define SPI_6348_INT_STATUS 0x02
1231 #define SPI_6348_INT_MASK_ST 0x03
1232 #define SPI_6348_INT_MASK 0x04
1233 #define SPI_6348_ST 0x05
1234 #define SPI_6348_CLK_CFG 0x06
1235 #define SPI_6348_FILL_BYTE 0x07
1236 #define SPI_6348_MSG_TAIL 0x09
1237 #define SPI_6348_RX_TAIL 0x0b
1238 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1239 #define SPI_6348_MSG_CTL_WIDTH 8
1240 #define SPI_6348_MSG_DATA 0x41
1241 #define SPI_6348_MSG_DATA_SIZE 0x3f
1242 #define SPI_6348_RX_DATA 0x80
1243 #define SPI_6348_RX_DATA_SIZE 0x3f
1244 
1245 /* BCM 6358 SPI core */
1246 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1247 #define SPI_6358_MSG_CTL_WIDTH 16
1248 #define SPI_6358_MSG_DATA 0x02
1249 #define SPI_6358_MSG_DATA_SIZE 0x21e
1250 #define SPI_6358_RX_DATA 0x400
1251 #define SPI_6358_RX_DATA_SIZE 0x220
1252 #define SPI_6358_CMD 0x700 /* 16-bits register */
1253 #define SPI_6358_INT_STATUS 0x702
1254 #define SPI_6358_INT_MASK_ST 0x703
1255 #define SPI_6358_INT_MASK 0x704
1256 #define SPI_6358_ST 0x705
1257 #define SPI_6358_CLK_CFG 0x706
1258 #define SPI_6358_FILL_BYTE 0x707
1259 #define SPI_6358_MSG_TAIL 0x709
1260 #define SPI_6358_RX_TAIL 0x70B
1261 
1262 /* BCM 6358 SPI core */
1263 #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1264 #define SPI_6368_MSG_CTL_WIDTH 16
1265 #define SPI_6368_MSG_DATA 0x02
1266 #define SPI_6368_MSG_DATA_SIZE 0x21e
1267 #define SPI_6368_RX_DATA 0x400
1268 #define SPI_6368_RX_DATA_SIZE 0x220
1269 #define SPI_6368_CMD 0x700 /* 16-bits register */
1270 #define SPI_6368_INT_STATUS 0x702
1271 #define SPI_6368_INT_MASK_ST 0x703
1272 #define SPI_6368_INT_MASK 0x704
1273 #define SPI_6368_ST 0x705
1274 #define SPI_6368_CLK_CFG 0x706
1275 #define SPI_6368_FILL_BYTE 0x707
1276 #define SPI_6368_MSG_TAIL 0x709
1277 #define SPI_6368_RX_TAIL 0x70B
1278 
1279 /* Shared SPI definitions */
1280 
1281 /* Message configuration */
1282 #define SPI_FD_RW 0x00
1283 #define SPI_HD_W 0x01
1284 #define SPI_HD_R 0x02
1285 #define SPI_BYTE_CNT_SHIFT 0
1286 #define SPI_6338_MSG_TYPE_SHIFT 6
1287 #define SPI_6348_MSG_TYPE_SHIFT 6
1288 #define SPI_6358_MSG_TYPE_SHIFT 14
1289 #define SPI_6368_MSG_TYPE_SHIFT 14
1290 
1291 /* Command */
1292 #define SPI_CMD_NOOP 0x00
1293 #define SPI_CMD_SOFT_RESET 0x01
1294 #define SPI_CMD_HARD_RESET 0x02
1295 #define SPI_CMD_START_IMMEDIATE 0x03
1296 #define SPI_CMD_COMMAND_SHIFT 0
1297 #define SPI_CMD_COMMAND_MASK 0x000f
1298 #define SPI_CMD_DEVICE_ID_SHIFT 4
1299 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1300 #define SPI_CMD_ONE_BYTE_SHIFT 11
1301 #define SPI_CMD_ONE_WIRE_SHIFT 12
1302 #define SPI_DEV_ID_0 0
1303 #define SPI_DEV_ID_1 1
1304 #define SPI_DEV_ID_2 2
1305 #define SPI_DEV_ID_3 3
1306 
1307 /* Interrupt mask */
1308 #define SPI_INTR_CMD_DONE 0x01
1309 #define SPI_INTR_RX_OVERFLOW 0x02
1310 #define SPI_INTR_TX_UNDERFLOW 0x04
1311 #define SPI_INTR_TX_OVERFLOW 0x08
1312 #define SPI_INTR_RX_UNDERFLOW 0x10
1313 #define SPI_INTR_CLEAR_ALL 0x1f
1314 
1315 /* Status */
1316 #define SPI_RX_EMPTY 0x02
1317 #define SPI_CMD_BUSY 0x04
1318 #define SPI_SERIAL_BUSY 0x08
1319 
1320 /* Clock configuration */
1321 #define SPI_CLK_20MHZ 0x00
1322 #define SPI_CLK_0_391MHZ 0x01
1323 #define SPI_CLK_0_781MHZ 0x02 /* default */
1324 #define SPI_CLK_1_563MHZ 0x03
1325 #define SPI_CLK_3_125MHZ 0x04
1326 #define SPI_CLK_6_250MHZ 0x05
1327 #define SPI_CLK_12_50MHZ 0x06
1328 #define SPI_CLK_MASK 0x07
1329 #define SPI_SSOFFTIME_MASK 0x38
1330 #define SPI_SSOFFTIME_SHIFT 3
1331 #define SPI_BYTE_SWAP 0x80
1332 
1333 /*************************************************************************
1334  * _REG relative to RSET_MISC
1335  *************************************************************************/
1336 #define MISC_SERDES_CTRL_REG 0x0
1337 #define SERDES_PCIE_EN (1 << 0)
1338 #define SERDES_PCIE_EXD_EN (1 << 15)
1339 
1340 #define MISC_STRAPBUS_6328_REG 0x240
1341 #define STRAPBUS_6328_FCVO_SHIFT 7
1342 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1343 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1344 #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1345 
1346 /*************************************************************************
1347  * _REG relative to RSET_PCIE
1348  *************************************************************************/
1349 
1350 #define PCIE_CONFIG2_REG 0x408
1351 #define CONFIG2_BAR1_SIZE_EN 1
1352 #define CONFIG2_BAR1_SIZE_MASK 0xf
1353 
1354 #define PCIE_IDVAL3_REG 0x43c
1355 #define IDVAL3_CLASS_CODE_MASK 0xffffff
1356 #define IDVAL3_SUBCLASS_SHIFT 8
1357 #define IDVAL3_CLASS_SHIFT 16
1358 
1359 #define PCIE_DLSTATUS_REG 0x1048
1360 #define DLSTATUS_PHYLINKUP (1 << 13)
1361 
1362 #define PCIE_BRIDGE_OPT1_REG 0x2820
1363 #define OPT1_RD_BE_OPT_EN (1 << 7)
1364 #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1365 #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1366 #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1367 
1368 #define PCIE_BRIDGE_OPT2_REG 0x2824
1369 #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1370 #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1371 #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1372 #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1373 #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1374 
1375 #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1376 #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1377 #define BASEMASK_REMAP_EN (1 << 0)
1378 #define BASEMASK_SWAP_EN (1 << 1)
1379 #define BASEMASK_MASK_SHIFT 4
1380 #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1381 #define BASEMASK_BASE_SHIFT 20
1382 #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1383 
1384 #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1385 #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1386 #define REBASE_ADDR_BASE_SHIFT 20
1387 #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1388 
1389 #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1390 #define PCIE_RC_INT_A (1 << 0)
1391 #define PCIE_RC_INT_B (1 << 1)
1392 #define PCIE_RC_INT_C (1 << 2)
1393 #define PCIE_RC_INT_D (1 << 3)
1394 
1395 #define PCIE_DEVICE_OFFSET 0x8000
1396 
1397 #endif /* BCM63XX_REGS_H_ */