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bcm63xx_regs.h File Reference

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Macros

#define PERF_REV_REG   0x0
 
#define REV_CHIPID_SHIFT   16
 
#define REV_CHIPID_MASK   (0xffff << REV_CHIPID_SHIFT)
 
#define REV_REVID_SHIFT   0
 
#define REV_REVID_MASK   (0xffff << REV_REVID_SHIFT)
 
#define PERF_CKCTL_REG   0x4
 
#define CKCTL_6328_PHYMIPS_EN   (1 << 0)
 
#define CKCTL_6328_ADSL_QPROC_EN   (1 << 1)
 
#define CKCTL_6328_ADSL_AFE_EN   (1 << 2)
 
#define CKCTL_6328_ADSL_EN   (1 << 3)
 
#define CKCTL_6328_MIPS_EN   (1 << 4)
 
#define CKCTL_6328_SAR_EN   (1 << 5)
 
#define CKCTL_6328_PCM_EN   (1 << 6)
 
#define CKCTL_6328_USBD_EN   (1 << 7)
 
#define CKCTL_6328_USBH_EN   (1 << 8)
 
#define CKCTL_6328_HSSPI_EN   (1 << 9)
 
#define CKCTL_6328_PCIE_EN   (1 << 10)
 
#define CKCTL_6328_ROBOSW_EN   (1 << 11)
 
#define CKCTL_6328_ALL_SAFE_EN
 
#define CKCTL_6338_ADSLPHY_EN   (1 << 0)
 
#define CKCTL_6338_MPI_EN   (1 << 1)
 
#define CKCTL_6338_DRAM_EN   (1 << 2)
 
#define CKCTL_6338_ENET_EN   (1 << 4)
 
#define CKCTL_6338_USBS_EN   (1 << 4)
 
#define CKCTL_6338_SAR_EN   (1 << 5)
 
#define CKCTL_6338_SPI_EN   (1 << 9)
 
#define CKCTL_6338_ALL_SAFE_EN
 
#define CKCTL_6345_CPU_EN   (1 << 0)
 
#define CKCTL_6345_BUS_EN   (1 << 1)
 
#define CKCTL_6345_EBI_EN   (1 << 2)
 
#define CKCTL_6345_UART_EN   (1 << 3)
 
#define CKCTL_6345_ADSLPHY_EN   (1 << 4)
 
#define CKCTL_6345_ENET_EN   (1 << 7)
 
#define CKCTL_6345_USBH_EN   (1 << 8)
 
#define CKCTL_6345_ALL_SAFE_EN
 
#define CKCTL_6348_ADSLPHY_EN   (1 << 0)
 
#define CKCTL_6348_MPI_EN   (1 << 1)
 
#define CKCTL_6348_SDRAM_EN   (1 << 2)
 
#define CKCTL_6348_M2M_EN   (1 << 3)
 
#define CKCTL_6348_ENET_EN   (1 << 4)
 
#define CKCTL_6348_SAR_EN   (1 << 5)
 
#define CKCTL_6348_USBS_EN   (1 << 6)
 
#define CKCTL_6348_USBH_EN   (1 << 8)
 
#define CKCTL_6348_SPI_EN   (1 << 9)
 
#define CKCTL_6348_ALL_SAFE_EN
 
#define CKCTL_6358_ENET_EN   (1 << 4)
 
#define CKCTL_6358_ADSLPHY_EN   (1 << 5)
 
#define CKCTL_6358_PCM_EN   (1 << 8)
 
#define CKCTL_6358_SPI_EN   (1 << 9)
 
#define CKCTL_6358_USBS_EN   (1 << 10)
 
#define CKCTL_6358_SAR_EN   (1 << 11)
 
#define CKCTL_6358_EMUSB_EN   (1 << 17)
 
#define CKCTL_6358_ENET0_EN   (1 << 18)
 
#define CKCTL_6358_ENET1_EN   (1 << 19)
 
#define CKCTL_6358_USBSU_EN   (1 << 20)
 
#define CKCTL_6358_EPHY_EN   (1 << 21)
 
#define CKCTL_6358_ALL_SAFE_EN
 
#define CKCTL_6368_VDSL_QPROC_EN   (1 << 2)
 
#define CKCTL_6368_VDSL_AFE_EN   (1 << 3)
 
#define CKCTL_6368_VDSL_BONDING_EN   (1 << 4)
 
#define CKCTL_6368_VDSL_EN   (1 << 5)
 
#define CKCTL_6368_PHYMIPS_EN   (1 << 6)
 
#define CKCTL_6368_SWPKT_USB_EN   (1 << 7)
 
#define CKCTL_6368_SWPKT_SAR_EN   (1 << 8)
 
#define CKCTL_6368_SPI_EN   (1 << 9)
 
#define CKCTL_6368_USBD_EN   (1 << 10)
 
#define CKCTL_6368_SAR_EN   (1 << 11)
 
#define CKCTL_6368_ROBOSW_EN   (1 << 12)
 
#define CKCTL_6368_UTOPIA_EN   (1 << 13)
 
#define CKCTL_6368_PCM_EN   (1 << 14)
 
#define CKCTL_6368_USBH_EN   (1 << 15)
 
#define CKCTL_6368_DISABLE_GLESS_EN   (1 << 16)
 
#define CKCTL_6368_NAND_EN   (1 << 17)
 
#define CKCTL_6368_IPSEC_EN   (1 << 18)
 
#define CKCTL_6368_ALL_SAFE_EN
 
#define PERF_SYS_PLL_CTL_REG   0x8
 
#define SYS_PLL_SOFT_RESET   0x1
 
#define PERF_IRQMASK_6328_REG   0x20
 
#define PERF_IRQMASK_6338_REG   0xc
 
#define PERF_IRQMASK_6345_REG   0xc
 
#define PERF_IRQMASK_6348_REG   0xc
 
#define PERF_IRQMASK_6358_REG   0xc
 
#define PERF_IRQMASK_6368_REG   0x20
 
#define PERF_IRQSTAT_6328_REG   0x28
 
#define PERF_IRQSTAT_6338_REG   0x10
 
#define PERF_IRQSTAT_6345_REG   0x10
 
#define PERF_IRQSTAT_6348_REG   0x10
 
#define PERF_IRQSTAT_6358_REG   0x10
 
#define PERF_IRQSTAT_6368_REG   0x28
 
#define PERF_EXTIRQ_CFG_REG_6328   0x18
 
#define PERF_EXTIRQ_CFG_REG_6338   0x14
 
#define PERF_EXTIRQ_CFG_REG_6345   0x14
 
#define PERF_EXTIRQ_CFG_REG_6348   0x14
 
#define PERF_EXTIRQ_CFG_REG_6358   0x14
 
#define PERF_EXTIRQ_CFG_REG_6368   0x18
 
#define PERF_EXTIRQ_CFG_REG2_6368   0x1c
 
#define EXTIRQ_CFG_SENSE_6348(x)   (1 << (x))
 
#define EXTIRQ_CFG_STAT_6348(x)   (1 << (x + 5))
 
#define EXTIRQ_CFG_CLEAR_6348(x)   (1 << (x + 10))
 
#define EXTIRQ_CFG_MASK_6348(x)   (1 << (x + 15))
 
#define EXTIRQ_CFG_BOTHEDGE_6348(x)   (1 << (x + 20))
 
#define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
 
#define EXTIRQ_CFG_CLEAR_ALL_6348   (0xf << 10)
 
#define EXTIRQ_CFG_MASK_ALL_6348   (0xf << 15)
 
#define EXTIRQ_CFG_SENSE(x)   (1 << (x))
 
#define EXTIRQ_CFG_STAT(x)   (1 << (x + 4))
 
#define EXTIRQ_CFG_CLEAR(x)   (1 << (x + 8))
 
#define EXTIRQ_CFG_MASK(x)   (1 << (x + 12))
 
#define EXTIRQ_CFG_BOTHEDGE(x)   (1 << (x + 16))
 
#define EXTIRQ_CFG_LEVELSENSE(x)   (1 << (x + 20))
 
#define EXTIRQ_CFG_CLEAR_ALL   (0xf << 8)
 
#define EXTIRQ_CFG_MASK_ALL   (0xf << 12)
 
#define PERF_SOFTRESET_REG   0x28
 
#define PERF_SOFTRESET_6328_REG   0x10
 
#define PERF_SOFTRESET_6368_REG   0x10
 
#define SOFTRESET_6328_SPI_MASK   (1 << 0)
 
#define SOFTRESET_6328_EPHY_MASK   (1 << 1)
 
#define SOFTRESET_6328_SAR_MASK   (1 << 2)
 
#define SOFTRESET_6328_ENETSW_MASK   (1 << 3)
 
#define SOFTRESET_6328_USBS_MASK   (1 << 4)
 
#define SOFTRESET_6328_USBH_MASK   (1 << 5)
 
#define SOFTRESET_6328_PCM_MASK   (1 << 6)
 
#define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)
 
#define SOFTRESET_6328_PCIE_MASK   (1 << 8)
 
#define SOFTRESET_6328_PCIE_EXT_MASK   (1 << 9)
 
#define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)
 
#define SOFTRESET_6338_SPI_MASK   (1 << 0)
 
#define SOFTRESET_6338_ENET_MASK   (1 << 2)
 
#define SOFTRESET_6338_USBH_MASK   (1 << 3)
 
#define SOFTRESET_6338_USBS_MASK   (1 << 4)
 
#define SOFTRESET_6338_ADSL_MASK   (1 << 5)
 
#define SOFTRESET_6338_DMAMEM_MASK   (1 << 6)
 
#define SOFTRESET_6338_SAR_MASK   (1 << 7)
 
#define SOFTRESET_6338_ACLC_MASK   (1 << 8)
 
#define SOFTRESET_6338_ADSLMIPSPLL_MASK   (1 << 10)
 
#define SOFTRESET_6338_ALL
 
#define SOFTRESET_6348_SPI_MASK   (1 << 0)
 
#define SOFTRESET_6348_ENET_MASK   (1 << 2)
 
#define SOFTRESET_6348_USBH_MASK   (1 << 3)
 
#define SOFTRESET_6348_USBS_MASK   (1 << 4)
 
#define SOFTRESET_6348_ADSL_MASK   (1 << 5)
 
#define SOFTRESET_6348_DMAMEM_MASK   (1 << 6)
 
#define SOFTRESET_6348_SAR_MASK   (1 << 7)
 
#define SOFTRESET_6348_ACLC_MASK   (1 << 8)
 
#define SOFTRESET_6348_ADSLMIPSPLL_MASK   (1 << 10)
 
#define SOFTRESET_6348_ALL
 
#define SOFTRESET_6368_SPI_MASK   (1 << 0)
 
#define SOFTRESET_6368_MPI_MASK   (1 << 3)
 
#define SOFTRESET_6368_EPHY_MASK   (1 << 6)
 
#define SOFTRESET_6368_SAR_MASK   (1 << 7)
 
#define SOFTRESET_6368_ENETSW_MASK   (1 << 10)
 
#define SOFTRESET_6368_USBS_MASK   (1 << 11)
 
#define SOFTRESET_6368_USBH_MASK   (1 << 12)
 
#define SOFTRESET_6368_PCM_MASK   (1 << 13)
 
#define PERF_MIPSPLLCTL_REG   0x34
 
#define MIPSPLLCTL_N1_SHIFT   20
 
#define MIPSPLLCTL_N1_MASK   (0x7 << MIPSPLLCTL_N1_SHIFT)
 
#define MIPSPLLCTL_N2_SHIFT   15
 
#define MIPSPLLCTL_N2_MASK   (0x1f << MIPSPLLCTL_N2_SHIFT)
 
#define MIPSPLLCTL_M1REF_SHIFT   12
 
#define MIPSPLLCTL_M1REF_MASK   (0x7 << MIPSPLLCTL_M1REF_SHIFT)
 
#define MIPSPLLCTL_M2REF_SHIFT   9
 
#define MIPSPLLCTL_M2REF_MASK   (0x7 << MIPSPLLCTL_M2REF_SHIFT)
 
#define MIPSPLLCTL_M1CPU_SHIFT   6
 
#define MIPSPLLCTL_M1CPU_MASK   (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
 
#define MIPSPLLCTL_M1BUS_SHIFT   3
 
#define MIPSPLLCTL_M1BUS_MASK   (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
 
#define MIPSPLLCTL_M2BUS_SHIFT   0
 
#define MIPSPLLCTL_M2BUS_MASK   (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
 
#define PERF_ADSLPLLCTL_REG   0x38
 
#define ADSLPLLCTL_N1_SHIFT   20
 
#define ADSLPLLCTL_N1_MASK   (0x7 << ADSLPLLCTL_N1_SHIFT)
 
#define ADSLPLLCTL_N2_SHIFT   15
 
#define ADSLPLLCTL_N2_MASK   (0x1f << ADSLPLLCTL_N2_SHIFT)
 
#define ADSLPLLCTL_M1REF_SHIFT   12
 
#define ADSLPLLCTL_M1REF_MASK   (0x7 << ADSLPLLCTL_M1REF_SHIFT)
 
#define ADSLPLLCTL_M2REF_SHIFT   9
 
#define ADSLPLLCTL_M2REF_MASK   (0x7 << ADSLPLLCTL_M2REF_SHIFT)
 
#define ADSLPLLCTL_M1CPU_SHIFT   6
 
#define ADSLPLLCTL_M1CPU_MASK   (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
 
#define ADSLPLLCTL_M1BUS_SHIFT   3
 
#define ADSLPLLCTL_M1BUS_MASK   (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
 
#define ADSLPLLCTL_M2BUS_SHIFT   0
 
#define ADSLPLLCTL_M2BUS_MASK   (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
 
#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus)
 
#define BCM63XX_TIMER_COUNT   4
 
#define TIMER_T0_ID   0
 
#define TIMER_T1_ID   1
 
#define TIMER_T2_ID   2
 
#define TIMER_WDT_ID   3
 
#define TIMER_IRQSTAT_REG   0
 
#define TIMER_IRQSTAT_TIMER_CAUSE(x)   (1 << (x))
 
#define TIMER_IRQSTAT_TIMER0_CAUSE   (1 << 0)
 
#define TIMER_IRQSTAT_TIMER1_CAUSE   (1 << 1)
 
#define TIMER_IRQSTAT_TIMER2_CAUSE   (1 << 2)
 
#define TIMER_IRQSTAT_WDT_CAUSE   (1 << 3)
 
#define TIMER_IRQSTAT_TIMER_IR_EN(x)   (1 << ((x) + 8))
 
#define TIMER_IRQSTAT_TIMER0_IR_EN   (1 << 8)
 
#define TIMER_IRQSTAT_TIMER1_IR_EN   (1 << 9)
 
#define TIMER_IRQSTAT_TIMER2_IR_EN   (1 << 10)
 
#define TIMER_CTLx_REG(x)   (0x4 + (x * 4))
 
#define TIMER_CTL0_REG   0x4
 
#define TIMER_CTL1_REG   0x8
 
#define TIMER_CTL2_REG   0xC
 
#define TIMER_CTL_COUNTDOWN_MASK   (0x3fffffff)
 
#define TIMER_CTL_MONOTONIC_MASK   (1 << 30)
 
#define TIMER_CTL_ENABLE_MASK   (1 << 31)
 
#define WDT_DEFVAL_REG   0x0
 
#define WDT_CTL_REG   0x4
 
#define WDT_START_1   (0xff00)
 
#define WDT_START_2   (0x00ff)
 
#define WDT_STOP_1   (0xee00)
 
#define WDT_STOP_2   (0x00ee)
 
#define WDT_RSTLEN_REG   0x8
 
#define WDT_SOFTRESET_REG   0xc
 
#define UART_CTL_REG   0x0
 
#define UART_CTL_RXTMOUTCNT_SHIFT   0
 
#define UART_CTL_RXTMOUTCNT_MASK   (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
 
#define UART_CTL_RSTTXDN_SHIFT   5
 
#define UART_CTL_RSTTXDN_MASK   (1 << UART_CTL_RSTTXDN_SHIFT)
 
#define UART_CTL_RSTRXFIFO_SHIFT   6
 
#define UART_CTL_RSTRXFIFO_MASK   (1 << UART_CTL_RSTRXFIFO_SHIFT)
 
#define UART_CTL_RSTTXFIFO_SHIFT   7
 
#define UART_CTL_RSTTXFIFO_MASK   (1 << UART_CTL_RSTTXFIFO_SHIFT)
 
#define UART_CTL_STOPBITS_SHIFT   8
 
#define UART_CTL_STOPBITS_MASK   (0xf << UART_CTL_STOPBITS_SHIFT)
 
#define UART_CTL_STOPBITS_1   (0x7 << UART_CTL_STOPBITS_SHIFT)
 
#define UART_CTL_STOPBITS_2   (0xf << UART_CTL_STOPBITS_SHIFT)
 
#define UART_CTL_BITSPERSYM_SHIFT   12
 
#define UART_CTL_BITSPERSYM_MASK   (0x3 << UART_CTL_BITSPERSYM_SHIFT)
 
#define UART_CTL_XMITBRK_SHIFT   14
 
#define UART_CTL_XMITBRK_MASK   (1 << UART_CTL_XMITBRK_SHIFT)
 
#define UART_CTL_RSVD_SHIFT   15
 
#define UART_CTL_RSVD_MASK   (1 << UART_CTL_RSVD_SHIFT)
 
#define UART_CTL_RXPAREVEN_SHIFT   16
 
#define UART_CTL_RXPAREVEN_MASK   (1 << UART_CTL_RXPAREVEN_SHIFT)
 
#define UART_CTL_RXPAREN_SHIFT   17
 
#define UART_CTL_RXPAREN_MASK   (1 << UART_CTL_RXPAREN_SHIFT)
 
#define UART_CTL_TXPAREVEN_SHIFT   18
 
#define UART_CTL_TXPAREVEN_MASK   (1 << UART_CTL_TXPAREVEN_SHIFT)
 
#define UART_CTL_TXPAREN_SHIFT   18
 
#define UART_CTL_TXPAREN_MASK   (1 << UART_CTL_TXPAREN_SHIFT)
 
#define UART_CTL_LOOPBACK_SHIFT   20
 
#define UART_CTL_LOOPBACK_MASK   (1 << UART_CTL_LOOPBACK_SHIFT)
 
#define UART_CTL_RXEN_SHIFT   21
 
#define UART_CTL_RXEN_MASK   (1 << UART_CTL_RXEN_SHIFT)
 
#define UART_CTL_TXEN_SHIFT   22
 
#define UART_CTL_TXEN_MASK   (1 << UART_CTL_TXEN_SHIFT)
 
#define UART_CTL_BRGEN_SHIFT   23
 
#define UART_CTL_BRGEN_MASK   (1 << UART_CTL_BRGEN_SHIFT)
 
#define UART_BAUD_REG   0x4
 
#define UART_MCTL_REG   0x8
 
#define UART_MCTL_DTR_SHIFT   0
 
#define UART_MCTL_DTR_MASK   (1 << UART_MCTL_DTR_SHIFT)
 
#define UART_MCTL_RTS_SHIFT   1
 
#define UART_MCTL_RTS_MASK   (1 << UART_MCTL_RTS_SHIFT)
 
#define UART_MCTL_RXFIFOTHRESH_SHIFT   8
 
#define UART_MCTL_RXFIFOTHRESH_MASK   (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
 
#define UART_MCTL_TXFIFOTHRESH_SHIFT   12
 
#define UART_MCTL_TXFIFOTHRESH_MASK   (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
 
#define UART_MCTL_RXFIFOFILL_SHIFT   16
 
#define UART_MCTL_RXFIFOFILL_MASK   (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
 
#define UART_MCTL_TXFIFOFILL_SHIFT   24
 
#define UART_MCTL_TXFIFOFILL_MASK   (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
 
#define UART_EXTINP_REG   0xc
 
#define UART_EXTINP_RI_SHIFT   0
 
#define UART_EXTINP_RI_MASK   (1 << UART_EXTINP_RI_SHIFT)
 
#define UART_EXTINP_CTS_SHIFT   1
 
#define UART_EXTINP_CTS_MASK   (1 << UART_EXTINP_CTS_SHIFT)
 
#define UART_EXTINP_DCD_SHIFT   2
 
#define UART_EXTINP_DCD_MASK   (1 << UART_EXTINP_DCD_SHIFT)
 
#define UART_EXTINP_DSR_SHIFT   3
 
#define UART_EXTINP_DSR_MASK   (1 << UART_EXTINP_DSR_SHIFT)
 
#define UART_EXTINP_IRSTAT(x)   (1 << (x + 4))
 
#define UART_EXTINP_IRMASK(x)   (1 << (x + 8))
 
#define UART_EXTINP_IR_RI   0
 
#define UART_EXTINP_IR_CTS   1
 
#define UART_EXTINP_IR_DCD   2
 
#define UART_EXTINP_IR_DSR   3
 
#define UART_EXTINP_RI_NOSENSE_SHIFT   16
 
#define UART_EXTINP_RI_NOSENSE_MASK   (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
 
#define UART_EXTINP_CTS_NOSENSE_SHIFT   17
 
#define UART_EXTINP_CTS_NOSENSE_MASK   (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
 
#define UART_EXTINP_DCD_NOSENSE_SHIFT   18
 
#define UART_EXTINP_DCD_NOSENSE_MASK   (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
 
#define UART_EXTINP_DSR_NOSENSE_SHIFT   19
 
#define UART_EXTINP_DSR_NOSENSE_MASK   (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
 
#define UART_IR_REG   0x10
 
#define UART_IR_MASK(x)   (1 << (x + 16))
 
#define UART_IR_STAT(x)   (1 << (x))
 
#define UART_IR_EXTIP   0
 
#define UART_IR_TXUNDER   1
 
#define UART_IR_TXOVER   2
 
#define UART_IR_TXTRESH   3
 
#define UART_IR_TXRDLATCH   4
 
#define UART_IR_TXEMPTY   5
 
#define UART_IR_RXUNDER   6
 
#define UART_IR_RXOVER   7
 
#define UART_IR_RXTIMEOUT   8
 
#define UART_IR_RXFULL   9
 
#define UART_IR_RXTHRESH   10
 
#define UART_IR_RXNOTEMPTY   11
 
#define UART_IR_RXFRAMEERR   12
 
#define UART_IR_RXPARERR   13
 
#define UART_IR_RXBRK   14
 
#define UART_IR_TXDONE   15
 
#define UART_FIFO_REG   0x14
 
#define UART_FIFO_VALID_SHIFT   0
 
#define UART_FIFO_VALID_MASK   0xff
 
#define UART_FIFO_FRAMEERR_SHIFT   8
 
#define UART_FIFO_FRAMEERR_MASK   (1 << UART_FIFO_FRAMEERR_SHIFT)
 
#define UART_FIFO_PARERR_SHIFT   9
 
#define UART_FIFO_PARERR_MASK   (1 << UART_FIFO_PARERR_SHIFT)
 
#define UART_FIFO_BRKDET_SHIFT   10
 
#define UART_FIFO_BRKDET_MASK   (1 << UART_FIFO_BRKDET_SHIFT)
 
#define UART_FIFO_ANYERR_MASK
 
#define GPIO_CTL_HI_REG   0x0
 
#define GPIO_CTL_LO_REG   0x4
 
#define GPIO_DATA_HI_REG   0x8
 
#define GPIO_DATA_LO_REG   0xC
 
#define GPIO_DATA_LO_REG_6345   0x8
 
#define GPIO_MODE_REG   0x18
 
#define GPIO_MODE_6348_G4_DIAG   0x00090000
 
#define GPIO_MODE_6348_G4_UTOPIA   0x00080000
 
#define GPIO_MODE_6348_G4_LEGACY_LED   0x00030000
 
#define GPIO_MODE_6348_G4_MII_SNOOP   0x00020000
 
#define GPIO_MODE_6348_G4_EXT_EPHY   0x00010000
 
#define GPIO_MODE_6348_G3_DIAG   0x00009000
 
#define GPIO_MODE_6348_G3_UTOPIA   0x00008000
 
#define GPIO_MODE_6348_G3_EXT_MII   0x00007000
 
#define GPIO_MODE_6348_G2_DIAG   0x00000900
 
#define GPIO_MODE_6348_G2_PCI   0x00000500
 
#define GPIO_MODE_6348_G1_DIAG   0x00000090
 
#define GPIO_MODE_6348_G1_UTOPIA   0x00000080
 
#define GPIO_MODE_6348_G1_SPI_UART   0x00000060
 
#define GPIO_MODE_6348_G1_SPI_MASTER   0x00000060
 
#define GPIO_MODE_6348_G1_MII_PCCARD   0x00000040
 
#define GPIO_MODE_6348_G1_MII_SNOOP   0x00000020
 
#define GPIO_MODE_6348_G1_EXT_EPHY   0x00000010
 
#define GPIO_MODE_6348_G0_DIAG   0x00000009
 
#define GPIO_MODE_6348_G0_EXT_MII   0x00000007
 
#define GPIO_MODE_6358_EXTRACS   (1 << 5)
 
#define GPIO_MODE_6358_UART1   (1 << 6)
 
#define GPIO_MODE_6358_EXTRA_SPI_SS   (1 << 7)
 
#define GPIO_MODE_6358_SERIAL_LED   (1 << 10)
 
#define GPIO_MODE_6358_UTOPIA   (1 << 12)
 
#define GPIO_MODE_6368_ANALOG_AFE_0   (1 << 0)
 
#define GPIO_MODE_6368_ANALOG_AFE_1   (1 << 1)
 
#define GPIO_MODE_6368_SYS_IRQ   (1 << 2)
 
#define GPIO_MODE_6368_SERIAL_LED_DATA   (1 << 3)
 
#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
 
#define GPIO_MODE_6368_INET_LED   (1 << 5)
 
#define GPIO_MODE_6368_EPHY0_LED   (1 << 6)
 
#define GPIO_MODE_6368_EPHY1_LED   (1 << 7)
 
#define GPIO_MODE_6368_EPHY2_LED   (1 << 8)
 
#define GPIO_MODE_6368_EPHY3_LED   (1 << 9)
 
#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
 
#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
 
#define GPIO_MODE_6368_ROBOSW_LED0   (1 << 12)
 
#define GPIO_MODE_6368_ROBOSW_LED1   (1 << 13)
 
#define GPIO_MODE_6368_USBD_LED   (1 << 14)
 
#define GPIO_MODE_6368_NTR_PULSE   (1 << 15)
 
#define GPIO_MODE_6368_PCI_REQ1   (1 << 16)
 
#define GPIO_MODE_6368_PCI_GNT1   (1 << 17)
 
#define GPIO_MODE_6368_PCI_INTB   (1 << 18)
 
#define GPIO_MODE_6368_PCI_REQ0   (1 << 19)
 
#define GPIO_MODE_6368_PCI_GNT0   (1 << 20)
 
#define GPIO_MODE_6368_PCMCIA_CD1   (1 << 22)
 
#define GPIO_MODE_6368_PCMCIA_CD2   (1 << 23)
 
#define GPIO_MODE_6368_PCMCIA_VS1   (1 << 24)
 
#define GPIO_MODE_6368_PCMCIA_VS2   (1 << 25)
 
#define GPIO_MODE_6368_EBI_CS2   (1 << 26)
 
#define GPIO_MODE_6368_EBI_CS3   (1 << 27)
 
#define GPIO_MODE_6368_SPI_SSN2   (1 << 28)
 
#define GPIO_MODE_6368_SPI_SSN3   (1 << 29)
 
#define GPIO_MODE_6368_SPI_SSN4   (1 << 30)
 
#define GPIO_MODE_6368_SPI_SSN5   (1 << 31)
 
#define GPIO_PINMUX_OTHR_REG   0x24
 
#define GPIO_PINMUX_OTHR_6328_USB_SHIFT   12
 
#define GPIO_PINMUX_OTHR_6328_USB_MASK   (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 
#define GPIO_PINMUX_OTHR_6328_USB_HOST   (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 
#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 
#define GPIO_BASEMODE_6368_REG   0x38
 
#define GPIO_BASEMODE_6368_UART2   0x1
 
#define GPIO_BASEMODE_6368_GPIO   0x0
 
#define GPIO_BASEMODE_6368_MASK   0x7
 
#define GPIO_STRAPBUS_REG   0x40
 
#define STRAPBUS_6358_BOOT_SEL_PARALLEL   (1 << 1)
 
#define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)
 
#define STRAPBUS_6368_BOOT_SEL_MASK   0x3
 
#define STRAPBUS_6368_BOOT_SEL_NAND   0
 
#define STRAPBUS_6368_BOOT_SEL_SERIAL   1
 
#define STRAPBUS_6368_BOOT_SEL_PARALLEL   3
 
#define ENET_RXCFG_REG   0x0
 
#define ENET_RXCFG_ALLMCAST_SHIFT   1
 
#define ENET_RXCFG_ALLMCAST_MASK   (1 << ENET_RXCFG_ALLMCAST_SHIFT)
 
#define ENET_RXCFG_PROMISC_SHIFT   3
 
#define ENET_RXCFG_PROMISC_MASK   (1 << ENET_RXCFG_PROMISC_SHIFT)
 
#define ENET_RXCFG_LOOPBACK_SHIFT   4
 
#define ENET_RXCFG_LOOPBACK_MASK   (1 << ENET_RXCFG_LOOPBACK_SHIFT)
 
#define ENET_RXCFG_ENFLOW_SHIFT   5
 
#define ENET_RXCFG_ENFLOW_MASK   (1 << ENET_RXCFG_ENFLOW_SHIFT)
 
#define ENET_RXMAXLEN_REG   0x4
 
#define ENET_RXMAXLEN_SHIFT   0
 
#define ENET_RXMAXLEN_MASK   (0x7ff << ENET_RXMAXLEN_SHIFT)
 
#define ENET_TXMAXLEN_REG   0x8
 
#define ENET_TXMAXLEN_SHIFT   0
 
#define ENET_TXMAXLEN_MASK   (0x7ff << ENET_TXMAXLEN_SHIFT)
 
#define ENET_MIISC_REG   0x10
 
#define ENET_MIISC_MDCFREQDIV_SHIFT   0
 
#define ENET_MIISC_MDCFREQDIV_MASK   (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
 
#define ENET_MIISC_PREAMBLEEN_SHIFT   7
 
#define ENET_MIISC_PREAMBLEEN_MASK   (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
 
#define ENET_MIIDATA_REG   0x14
 
#define ENET_MIIDATA_DATA_SHIFT   0
 
#define ENET_MIIDATA_DATA_MASK   (0xffff << ENET_MIIDATA_DATA_SHIFT)
 
#define ENET_MIIDATA_TA_SHIFT   16
 
#define ENET_MIIDATA_TA_MASK   (0x3 << ENET_MIIDATA_TA_SHIFT)
 
#define ENET_MIIDATA_REG_SHIFT   18
 
#define ENET_MIIDATA_REG_MASK   (0x1f << ENET_MIIDATA_REG_SHIFT)
 
#define ENET_MIIDATA_PHYID_SHIFT   23
 
#define ENET_MIIDATA_PHYID_MASK   (0x1f << ENET_MIIDATA_PHYID_SHIFT)
 
#define ENET_MIIDATA_OP_READ_MASK   (0x6 << 28)
 
#define ENET_MIIDATA_OP_WRITE_MASK   (0x5 << 28)
 
#define ENET_IRMASK_REG   0x18
 
#define ENET_IR_REG   0x1c
 
#define ENET_IR_MII   (1 << 0)
 
#define ENET_IR_MIB   (1 << 1)
 
#define ENET_IR_FLOWC   (1 << 2)
 
#define ENET_CTL_REG   0x2c
 
#define ENET_CTL_ENABLE_SHIFT   0
 
#define ENET_CTL_ENABLE_MASK   (1 << ENET_CTL_ENABLE_SHIFT)
 
#define ENET_CTL_DISABLE_SHIFT   1
 
#define ENET_CTL_DISABLE_MASK   (1 << ENET_CTL_DISABLE_SHIFT)
 
#define ENET_CTL_SRESET_SHIFT   2
 
#define ENET_CTL_SRESET_MASK   (1 << ENET_CTL_SRESET_SHIFT)
 
#define ENET_CTL_EPHYSEL_SHIFT   3
 
#define ENET_CTL_EPHYSEL_MASK   (1 << ENET_CTL_EPHYSEL_SHIFT)
 
#define ENET_TXCTL_REG   0x30
 
#define ENET_TXCTL_FD_SHIFT   0
 
#define ENET_TXCTL_FD_MASK   (1 << ENET_TXCTL_FD_SHIFT)
 
#define ENET_TXWMARK_REG   0x34
 
#define ENET_TXWMARK_WM_SHIFT   0
 
#define ENET_TXWMARK_WM_MASK   (0x3f << ENET_TXWMARK_WM_SHIFT)
 
#define ENET_MIBCTL_REG   0x38
 
#define ENET_MIBCTL_RDCLEAR_SHIFT   0
 
#define ENET_MIBCTL_RDCLEAR_MASK   (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
 
#define ENET_PML_REG(x)   (0x58 + (x) * 8)
 
#define ENET_PMH_REG(x)   (0x5c + (x) * 8)
 
#define ENET_PMH_DATAVALID_SHIFT   16
 
#define ENET_PMH_DATAVALID_MASK   (1 << ENET_PMH_DATAVALID_SHIFT)
 
#define ENET_MIB_REG(x)   (0x200 + (x) * 4)
 
#define ENET_MIB_REG_COUNT   55
 
#define ENETDMA_CFG_REG   (0x0)
 
#define ENETDMA_CFG_EN_SHIFT   0
 
#define ENETDMA_CFG_EN_MASK   (1 << ENETDMA_CFG_EN_SHIFT)
 
#define ENETDMA_CFG_FLOWCH_MASK(x)   (1 << ((x >> 1) + 1))
 
#define ENETDMA_FLOWCL_REG(x)   (0x4 + (x) * 6)
 
#define ENETDMA_FLOWCH_REG(x)   (0x8 + (x) * 6)
 
#define ENETDMA_BUFALLOC_REG(x)   (0xc + (x) * 6)
 
#define ENETDMA_BUFALLOC_FORCE_SHIFT   31
 
#define ENETDMA_BUFALLOC_FORCE_MASK   (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
 
#define ENETDMA_GLB_IRQSTAT_REG   (0x40)
 
#define ENETDMA_GLB_IRQMASK_REG   (0x44)
 
#define ENETDMA_CHANCFG_REG(x)   (0x100 + (x) * 0x10)
 
#define ENETDMA_CHANCFG_EN_SHIFT   0
 
#define ENETDMA_CHANCFG_EN_MASK   (1 << ENETDMA_CHANCFG_EN_SHIFT)
 
#define ENETDMA_CHANCFG_PKTHALT_SHIFT   1
 
#define ENETDMA_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
 
#define ENETDMA_IR_REG(x)   (0x104 + (x) * 0x10)
 
#define ENETDMA_IR_BUFDONE_MASK   (1 << 0)
 
#define ENETDMA_IR_PKTDONE_MASK   (1 << 1)
 
#define ENETDMA_IR_NOTOWNER_MASK   (1 << 2)
 
#define ENETDMA_IRMASK_REG(x)   (0x108 + (x) * 0x10)
 
#define ENETDMA_MAXBURST_REG(x)   (0x10C + (x) * 0x10)
 
#define ENETDMA_RSTART_REG(x)   (0x200 + (x) * 0x10)
 
#define ENETDMA_SRAM2_REG(x)   (0x204 + (x) * 0x10)
 
#define ENETDMA_SRAM3_REG(x)   (0x208 + (x) * 0x10)
 
#define ENETDMA_SRAM4_REG(x)   (0x20c + (x) * 0x10)
 
#define ENETDMAC_CHANCFG_REG(x)   ((x) * 0x10)
 
#define ENETDMAC_CHANCFG_EN_SHIFT   0
 
#define ENETDMAC_CHANCFG_EN_MASK   (1 << ENETDMAC_CHANCFG_EN_SHIFT)
 
#define ENETDMAC_CHANCFG_PKTHALT_SHIFT   1
 
#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
 
#define ENETDMAC_CHANCFG_BUFHALT_SHIFT   2
 
#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
 
#define ENETDMAC_IR_REG(x)   (0x4 + (x) * 0x10)
 
#define ENETDMAC_IR_BUFDONE_MASK   (1 << 0)
 
#define ENETDMAC_IR_PKTDONE_MASK   (1 << 1)
 
#define ENETDMAC_IR_NOTOWNER_MASK   (1 << 2)
 
#define ENETDMAC_IRMASK_REG(x)   (0x8 + (x) * 0x10)
 
#define ENETDMAC_MAXBURST_REG(x)   (0xc + (x) * 0x10)
 
#define ENETDMAS_RSTART_REG(x)   ((x) * 0x10)
 
#define ENETDMAS_SRAM2_REG(x)   (0x4 + (x) * 0x10)
 
#define ENETDMAS_SRAM3_REG(x)   (0x8 + (x) * 0x10)
 
#define ENETDMAS_SRAM4_REG(x)   (0xc + (x) * 0x10)
 
#define ENETSW_MIB_REG(x)   (0x2800 + (x) * 4)
 
#define ENETSW_MIB_REG_COUNT   47
 
#define OHCI_PRIV_REG   0x0
 
#define OHCI_PRIV_PORT1_HOST_SHIFT   0
 
#define OHCI_PRIV_PORT1_HOST_MASK   (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
 
#define OHCI_PRIV_REG_SWAP_SHIFT   3
 
#define OHCI_PRIV_REG_SWAP_MASK   (1 << OHCI_PRIV_REG_SWAP_SHIFT)
 
#define USBH_PRIV_SWAP_6358_REG   0x0
 
#define USBH_PRIV_SWAP_6368_REG   0x1c
 
#define USBH_PRIV_SWAP_USBD_SHIFT   6
 
#define USBH_PRIV_SWAP_USBD_MASK   (1 << USBH_PRIV_SWAP_USBD_SHIFT)
 
#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT   4
 
#define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 
#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT   3
 
#define USBH_PRIV_SWAP_EHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
 
#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT   1
 
#define USBH_PRIV_SWAP_OHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
 
#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT   0
 
#define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
#define USBH_PRIV_UTMI_CTL_6368_REG   0x10
 
#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT   12
 
#define USBH_PRIV_UTMI_CTL_NODRIV_MASK   (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
 
#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT   0
 
#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
 
#define USBH_PRIV_TEST_6358_REG   0x24
 
#define USBH_PRIV_TEST_6368_REG   0x14
 
#define USBH_PRIV_SETUP_6368_REG   0x28
 
#define USBH_PRIV_SETUP_IOC_SHIFT   4
 
#define USBH_PRIV_SETUP_IOC_MASK   (1 << USBH_PRIV_SETUP_IOC_SHIFT)
 
#define USBD_CONTROL_REG   0x00
 
#define USBD_CONTROL_TXZLENINS_SHIFT   14
 
#define USBD_CONTROL_TXZLENINS_MASK   (1 << USBD_CONTROL_TXZLENINS_SHIFT)
 
#define USBD_CONTROL_AUTO_CSRS_SHIFT   13
 
#define USBD_CONTROL_AUTO_CSRS_MASK   (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
 
#define USBD_CONTROL_RXZSCFG_SHIFT   12
 
#define USBD_CONTROL_RXZSCFG_MASK   (1 << USBD_CONTROL_RXZSCFG_SHIFT)
 
#define USBD_CONTROL_INIT_SEL_SHIFT   8
 
#define USBD_CONTROL_INIT_SEL_MASK   (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
 
#define USBD_CONTROL_FIFO_RESET_SHIFT   6
 
#define USBD_CONTROL_FIFO_RESET_MASK   (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
 
#define USBD_CONTROL_SETUPERRLOCK_SHIFT   5
 
#define USBD_CONTROL_SETUPERRLOCK_MASK   (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
 
#define USBD_CONTROL_DONE_CSRS_SHIFT   0
 
#define USBD_CONTROL_DONE_CSRS_MASK   (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
 
#define USBD_STRAPS_REG   0x04
 
#define USBD_STRAPS_APP_SELF_PWR_SHIFT   10
 
#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
 
#define USBD_STRAPS_APP_DISCON_SHIFT   9
 
#define USBD_STRAPS_APP_DISCON_MASK   (1 << USBD_STRAPS_APP_DISCON_SHIFT)
 
#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT   8
 
#define USBD_STRAPS_APP_CSRPRGSUP_MASK   (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
 
#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
 
#define USBD_STRAPS_APP_RMTWKUP_MASK   (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
 
#define USBD_STRAPS_APP_RAM_IF_SHIFT   7
 
#define USBD_STRAPS_APP_RAM_IF_MASK   (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
 
#define USBD_STRAPS_APP_8BITPHY_SHIFT   2
 
#define USBD_STRAPS_APP_8BITPHY_MASK   (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
 
#define USBD_STRAPS_SPEED_SHIFT   0
 
#define USBD_STRAPS_SPEED_MASK   (3 << USBD_STRAPS_SPEED_SHIFT)
 
#define USBD_STALL_REG   0x08
 
#define USBD_STALL_UPDATE_SHIFT   7
 
#define USBD_STALL_UPDATE_MASK   (1 << USBD_STALL_UPDATE_SHIFT)
 
#define USBD_STALL_ENABLE_SHIFT   6
 
#define USBD_STALL_ENABLE_MASK   (1 << USBD_STALL_ENABLE_SHIFT)
 
#define USBD_STALL_EPNUM_SHIFT   0
 
#define USBD_STALL_EPNUM_MASK   (0xf << USBD_STALL_EPNUM_SHIFT)
 
#define USBD_STATUS_REG   0x0c
 
#define USBD_STATUS_SOF_SHIFT   16
 
#define USBD_STATUS_SOF_MASK   (0x7ff << USBD_STATUS_SOF_SHIFT)
 
#define USBD_STATUS_SPD_SHIFT   12
 
#define USBD_STATUS_SPD_MASK   (3 << USBD_STATUS_SPD_SHIFT)
 
#define USBD_STATUS_ALTINTF_SHIFT   8
 
#define USBD_STATUS_ALTINTF_MASK   (0xf << USBD_STATUS_ALTINTF_SHIFT)
 
#define USBD_STATUS_INTF_SHIFT   4
 
#define USBD_STATUS_INTF_MASK   (0xf << USBD_STATUS_INTF_SHIFT)
 
#define USBD_STATUS_CFG_SHIFT   0
 
#define USBD_STATUS_CFG_MASK   (0xf << USBD_STATUS_CFG_SHIFT)
 
#define USBD_EVENTS_REG   0x10
 
#define USBD_EVENTS_USB_LINK_SHIFT   10
 
#define USBD_EVENTS_USB_LINK_MASK   (1 << USBD_EVENTS_USB_LINK_SHIFT)
 
#define USBD_EVENT_IRQ_STATUS_REG   0x14
 
#define USBD_EVENT_IRQ_CFG_HI_REG   0x18
 
#define USBD_EVENT_IRQ_CFG_LO_REG   0x1c
 
#define USBD_EVENT_IRQ_CFG_SHIFT(x)   ((x & 0xf) << 1)
 
#define USBD_EVENT_IRQ_CFG_MASK(x)   (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
 
#define USBD_EVENT_IRQ_CFG_RISING(x)   (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
 
#define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
 
#define USBD_EVENT_IRQ_MASK_REG   0x20
 
#define USBD_EVENT_IRQ_USB_LINK   10
 
#define USBD_EVENT_IRQ_SETCFG   9
 
#define USBD_EVENT_IRQ_SETINTF   8
 
#define USBD_EVENT_IRQ_ERRATIC_ERR   7
 
#define USBD_EVENT_IRQ_SET_CSRS   6
 
#define USBD_EVENT_IRQ_SUSPEND   5
 
#define USBD_EVENT_IRQ_EARLY_SUSPEND   4
 
#define USBD_EVENT_IRQ_SOF   3
 
#define USBD_EVENT_IRQ_ENUM_ON   2
 
#define USBD_EVENT_IRQ_SETUP   1
 
#define USBD_EVENT_IRQ_USB_RESET   0
 
#define USBD_TXFIFO_CONFIG_REG   0x40
 
#define USBD_TXFIFO_CONFIG_END_SHIFT   16
 
#define USBD_TXFIFO_CONFIG_END_MASK   (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
 
#define USBD_TXFIFO_CONFIG_START_SHIFT   0
 
#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
 
#define USBD_RXFIFO_CONFIG_REG   0x44
 
#define USBD_RXFIFO_CONFIG_END_SHIFT   16
 
#define USBD_RXFIFO_CONFIG_END_MASK   (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
 
#define USBD_RXFIFO_CONFIG_START_SHIFT   0
 
#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
 
#define USBD_TXFIFO_EPSIZE_REG   0x48
 
#define USBD_RXFIFO_EPSIZE_REG   0x4c
 
#define USBD_EPNUM_TYPEMAP_REG   0x50
 
#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
 
#define USBD_EPNUM_TYPEMAP_TYPE_MASK   (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
 
#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT   0
 
#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK   (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
 
#define USBD_CSR_SETUPADDR_REG   0x80
 
#define USBD_CSR_SETUPADDR_DEF   0xb550
 
#define USBD_CSR_EP_REG(x)   (0x84 + (x) * 4)
 
#define USBD_CSR_EP_MAXPKT_SHIFT   19
 
#define USBD_CSR_EP_MAXPKT_MASK   (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
 
#define USBD_CSR_EP_ALTIFACE_SHIFT   15
 
#define USBD_CSR_EP_ALTIFACE_MASK   (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
 
#define USBD_CSR_EP_IFACE_SHIFT   11
 
#define USBD_CSR_EP_IFACE_MASK   (0xf << USBD_CSR_EP_IFACE_SHIFT)
 
#define USBD_CSR_EP_CFG_SHIFT   7
 
#define USBD_CSR_EP_CFG_MASK   (0xf << USBD_CSR_EP_CFG_SHIFT)
 
#define USBD_CSR_EP_TYPE_SHIFT   5
 
#define USBD_CSR_EP_TYPE_MASK   (3 << USBD_CSR_EP_TYPE_SHIFT)
 
#define USBD_CSR_EP_DIR_SHIFT   4
 
#define USBD_CSR_EP_DIR_MASK   (1 << USBD_CSR_EP_DIR_SHIFT)
 
#define USBD_CSR_EP_LOG_SHIFT   0
 
#define USBD_CSR_EP_LOG_MASK   (0xf << USBD_CSR_EP_LOG_SHIFT)
 
#define MPI_CS_PCMCIA_COMMON   4
 
#define MPI_CS_PCMCIA_ATTR   5
 
#define MPI_CS_PCMCIA_IO   6
 
#define MPI_CSBASE_REG(x)   (0x0 + (x) * 8)
 
#define MPI_CSBASE_BASE_SHIFT   13
 
#define MPI_CSBASE_BASE_MASK   (0x1ffff << MPI_CSBASE_BASE_SHIFT)
 
#define MPI_CSBASE_SIZE_SHIFT   0
 
#define MPI_CSBASE_SIZE_MASK   (0xf << MPI_CSBASE_SIZE_SHIFT)
 
#define MPI_CSBASE_SIZE_8K   0
 
#define MPI_CSBASE_SIZE_16K   1
 
#define MPI_CSBASE_SIZE_32K   2
 
#define MPI_CSBASE_SIZE_64K   3
 
#define MPI_CSBASE_SIZE_128K   4
 
#define MPI_CSBASE_SIZE_256K   5
 
#define MPI_CSBASE_SIZE_512K   6
 
#define MPI_CSBASE_SIZE_1M   7
 
#define MPI_CSBASE_SIZE_2M   8
 
#define MPI_CSBASE_SIZE_4M   9
 
#define MPI_CSBASE_SIZE_8M   10
 
#define MPI_CSBASE_SIZE_16M   11
 
#define MPI_CSBASE_SIZE_32M   12
 
#define MPI_CSBASE_SIZE_64M   13
 
#define MPI_CSBASE_SIZE_128M   14
 
#define MPI_CSBASE_SIZE_256M   15
 
#define MPI_CSCTL_REG(x)   (0x4 + (x) * 8)
 
#define MPI_CSCTL_ENABLE_MASK   (1 << 0)
 
#define MPI_CSCTL_WAIT_SHIFT   1
 
#define MPI_CSCTL_WAIT_MASK   (0x7 << MPI_CSCTL_WAIT_SHIFT)
 
#define MPI_CSCTL_DATA16_MASK   (1 << 4)
 
#define MPI_CSCTL_SYNCMODE_MASK   (1 << 7)
 
#define MPI_CSCTL_TSIZE_MASK   (1 << 8)
 
#define MPI_CSCTL_ENDIANSWAP_MASK   (1 << 10)
 
#define MPI_CSCTL_SETUP_SHIFT   16
 
#define MPI_CSCTL_SETUP_MASK   (0xf << MPI_CSCTL_SETUP_SHIFT)
 
#define MPI_CSCTL_HOLD_SHIFT   20
 
#define MPI_CSCTL_HOLD_MASK   (0xf << MPI_CSCTL_HOLD_SHIFT)
 
#define MPI_SP0_RANGE_REG   0x100
 
#define MPI_SP0_REMAP_REG   0x104
 
#define MPI_SP0_REMAP_ENABLE_MASK   (1 << 0)
 
#define MPI_SP1_RANGE_REG   0x10C
 
#define MPI_SP1_REMAP_REG   0x110
 
#define MPI_SP1_REMAP_ENABLE_MASK   (1 << 0)
 
#define MPI_L2PCFG_REG   0x11C
 
#define MPI_L2PCFG_CFG_TYPE_SHIFT   0
 
#define MPI_L2PCFG_CFG_TYPE_MASK   (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
 
#define MPI_L2PCFG_REG_SHIFT   2
 
#define MPI_L2PCFG_REG_MASK   (0x3f << MPI_L2PCFG_REG_SHIFT)
 
#define MPI_L2PCFG_FUNC_SHIFT   8
 
#define MPI_L2PCFG_FUNC_MASK   (0x7 << MPI_L2PCFG_FUNC_SHIFT)
 
#define MPI_L2PCFG_DEVNUM_SHIFT   11
 
#define MPI_L2PCFG_DEVNUM_MASK   (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
 
#define MPI_L2PCFG_CFG_USEREG_MASK   (1 << 30)
 
#define MPI_L2PCFG_CFG_SEL_MASK   (1 << 31)
 
#define MPI_L2PMEMRANGE1_REG   0x120
 
#define MPI_L2PMEMBASE1_REG   0x124
 
#define MPI_L2PMEMREMAP1_REG   0x128
 
#define MPI_L2PMEMRANGE2_REG   0x12C
 
#define MPI_L2PMEMBASE2_REG   0x130
 
#define MPI_L2PMEMREMAP2_REG   0x134
 
#define MPI_L2PIORANGE_REG   0x138
 
#define MPI_L2PIOBASE_REG   0x13C
 
#define MPI_L2PIOREMAP_REG   0x140
 
#define MPI_L2P_BASE_MASK   (0xffff8000)
 
#define MPI_L2PREMAP_ENABLED_MASK   (1 << 0)
 
#define MPI_L2PREMAP_IS_CARDBUS_MASK   (1 << 2)
 
#define MPI_PCIMODESEL_REG   0x144
 
#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK   (1 << 0)
 
#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK   (1 << 1)
 
#define MPI_PCIMODESEL_EXT_ARB_MASK   (1 << 2)
 
#define MPI_PCIMODESEL_PREFETCH_SHIFT   4
 
#define MPI_PCIMODESEL_PREFETCH_MASK   (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
 
#define MPI_LOCBUSCTL_REG   0x14C
 
#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK   (1 << 0)
 
#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
 
#define MPI_LOCINT_REG   0x150
 
#define MPI_LOCINT_MASK(x)   (1 << (x + 16))
 
#define MPI_LOCINT_STAT(x)   (1 << (x))
 
#define MPI_LOCINT_DIR_FAILED   6
 
#define MPI_LOCINT_EXT_PCI_INT   7
 
#define MPI_LOCINT_SERR   8
 
#define MPI_LOCINT_CSERR   9
 
#define MPI_PCICFGCTL_REG   0x178
 
#define MPI_PCICFGCTL_CFGADDR_SHIFT   2
 
#define MPI_PCICFGCTL_CFGADDR_MASK   (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
 
#define MPI_PCICFGCTL_WRITEEN_MASK   (1 << 7)
 
#define MPI_PCICFGDATA_REG   0x17C
 
#define BCMPCI_REG_TIMERS   0x40
 
#define REG_TIMER_TRDY_SHIFT   0
 
#define REG_TIMER_TRDY_MASK   (0xff << REG_TIMER_TRDY_SHIFT)
 
#define REG_TIMER_RETRY_SHIFT   8
 
#define REG_TIMER_RETRY_MASK   (0xff << REG_TIMER_RETRY_SHIFT)
 
#define PCMCIA_C1_REG   0x0
 
#define PCMCIA_C1_CD1_MASK   (1 << 0)
 
#define PCMCIA_C1_CD2_MASK   (1 << 1)
 
#define PCMCIA_C1_VS1_MASK   (1 << 2)
 
#define PCMCIA_C1_VS2_MASK   (1 << 3)
 
#define PCMCIA_C1_VS1OE_MASK   (1 << 6)
 
#define PCMCIA_C1_VS2OE_MASK   (1 << 7)
 
#define PCMCIA_C1_CBIDSEL_SHIFT   (8)
 
#define PCMCIA_C1_CBIDSEL_MASK   (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
 
#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
 
#define PCMCIA_C1_EN_PCMCIA_MASK   (1 << 14)
 
#define PCMCIA_C1_EN_CARDBUS_MASK   (1 << 15)
 
#define PCMCIA_C1_RESET_MASK   (1 << 18)
 
#define PCMCIA_C2_REG   0x8
 
#define PCMCIA_C2_DATA16_MASK   (1 << 0)
 
#define PCMCIA_C2_BYTESWAP_MASK   (1 << 1)
 
#define PCMCIA_C2_RWCOUNT_SHIFT   2
 
#define PCMCIA_C2_RWCOUNT_MASK   (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
 
#define PCMCIA_C2_INACTIVE_SHIFT   8
 
#define PCMCIA_C2_INACTIVE_MASK   (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
 
#define PCMCIA_C2_SETUP_SHIFT   16
 
#define PCMCIA_C2_SETUP_MASK   (0x3f << PCMCIA_C2_SETUP_SHIFT)
 
#define PCMCIA_C2_HOLD_SHIFT   24
 
#define PCMCIA_C2_HOLD_MASK   (0x3f << PCMCIA_C2_HOLD_SHIFT)
 
#define SDRAM_CFG_REG   0x0
 
#define SDRAM_CFG_ROW_SHIFT   4
 
#define SDRAM_CFG_ROW_MASK   (0x3 << SDRAM_CFG_ROW_SHIFT)
 
#define SDRAM_CFG_COL_SHIFT   6
 
#define SDRAM_CFG_COL_MASK   (0x3 << SDRAM_CFG_COL_SHIFT)
 
#define SDRAM_CFG_32B_SHIFT   10
 
#define SDRAM_CFG_32B_MASK   (1 << SDRAM_CFG_32B_SHIFT)
 
#define SDRAM_CFG_BANK_SHIFT   13
 
#define SDRAM_CFG_BANK_MASK   (1 << SDRAM_CFG_BANK_SHIFT)
 
#define SDRAM_MBASE_REG   0xc
 
#define SDRAM_PRIO_REG   0x2C
 
#define SDRAM_PRIO_MIPS_SHIFT   29
 
#define SDRAM_PRIO_MIPS_MASK   (1 << SDRAM_PRIO_MIPS_SHIFT)
 
#define SDRAM_PRIO_ADSL_SHIFT   30
 
#define SDRAM_PRIO_ADSL_MASK   (1 << SDRAM_PRIO_ADSL_SHIFT)
 
#define SDRAM_PRIO_EN_SHIFT   31
 
#define SDRAM_PRIO_EN_MASK   (1 << SDRAM_PRIO_EN_SHIFT)
 
#define MEMC_CFG_REG   0x4
 
#define MEMC_CFG_32B_SHIFT   1
 
#define MEMC_CFG_32B_MASK   (1 << MEMC_CFG_32B_SHIFT)
 
#define MEMC_CFG_COL_SHIFT   3
 
#define MEMC_CFG_COL_MASK   (0x3 << MEMC_CFG_COL_SHIFT)
 
#define MEMC_CFG_ROW_SHIFT   6
 
#define MEMC_CFG_ROW_MASK   (0x3 << MEMC_CFG_ROW_SHIFT)
 
#define DDR_CSEND_REG   0x8
 
#define DDR_DMIPSPLLCFG_REG   0x18
 
#define DMIPSPLLCFG_M1_SHIFT   0
 
#define DMIPSPLLCFG_M1_MASK   (0xff << DMIPSPLLCFG_M1_SHIFT)
 
#define DMIPSPLLCFG_N1_SHIFT   23
 
#define DMIPSPLLCFG_N1_MASK   (0x3f << DMIPSPLLCFG_N1_SHIFT)
 
#define DMIPSPLLCFG_N2_SHIFT   29
 
#define DMIPSPLLCFG_N2_MASK   (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
#define DDR_DMIPSPLLCFG_6368_REG   0x20
 
#define DMIPSPLLCFG_6368_P1_SHIFT   0
 
#define DMIPSPLLCFG_6368_P1_MASK   (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
 
#define DMIPSPLLCFG_6368_P2_SHIFT   4
 
#define DMIPSPLLCFG_6368_P2_MASK   (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
 
#define DMIPSPLLCFG_6368_NDIV_SHIFT   16
 
#define DMIPSPLLCFG_6368_NDIV_MASK   (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
 
#define DDR_DMIPSPLLDIV_6368_REG   0x24
 
#define DMIPSPLLDIV_6368_MDIV_SHIFT   0
 
#define DMIPSPLLDIV_6368_MDIV_MASK   (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
 
#define M2M_RX   0
 
#define M2M_TX   1
 
#define M2M_SRC_REG(x)   ((x) * 0x40 + 0x00)
 
#define M2M_DST_REG(x)   ((x) * 0x40 + 0x04)
 
#define M2M_SIZE_REG(x)   ((x) * 0x40 + 0x08)
 
#define M2M_CTRL_REG(x)   ((x) * 0x40 + 0x0c)
 
#define M2M_CTRL_ENABLE_MASK   (1 << 0)
 
#define M2M_CTRL_IRQEN_MASK   (1 << 1)
 
#define M2M_CTRL_ERROR_CLR_MASK   (1 << 6)
 
#define M2M_CTRL_DONE_CLR_MASK   (1 << 7)
 
#define M2M_CTRL_NOINC_MASK   (1 << 8)
 
#define M2M_CTRL_PCMCIASWAP_MASK   (1 << 9)
 
#define M2M_CTRL_SWAPBYTE_MASK   (1 << 10)
 
#define M2M_CTRL_ENDIAN_MASK   (1 << 11)
 
#define M2M_STAT_REG(x)   ((x) * 0x40 + 0x10)
 
#define M2M_STAT_DONE   (1 << 0)
 
#define M2M_STAT_ERROR   (1 << 1)
 
#define M2M_SRCID_REG(x)   ((x) * 0x40 + 0x14)
 
#define M2M_DSTID_REG(x)   ((x) * 0x40 + 0x18)
 
#define RNG_CTRL   0x00
 
#define RNG_EN   (1 << 0)
 
#define RNG_STAT   0x04
 
#define RNG_AVAIL_MASK   (0xff000000)
 
#define RNG_DATA   0x08
 
#define RNG_THRES   0x0c
 
#define RNG_MASK   0x10
 
#define SPI_6338_CMD   0x00 /* 16-bits register */
 
#define SPI_6338_INT_STATUS   0x02
 
#define SPI_6338_INT_MASK_ST   0x03
 
#define SPI_6338_INT_MASK   0x04
 
#define SPI_6338_ST   0x05
 
#define SPI_6338_CLK_CFG   0x06
 
#define SPI_6338_FILL_BYTE   0x07
 
#define SPI_6338_MSG_TAIL   0x09
 
#define SPI_6338_RX_TAIL   0x0b
 
#define SPI_6338_MSG_CTL   0x40 /* 8-bits register */
 
#define SPI_6338_MSG_CTL_WIDTH   8
 
#define SPI_6338_MSG_DATA   0x41
 
#define SPI_6338_MSG_DATA_SIZE   0x3f
 
#define SPI_6338_RX_DATA   0x80
 
#define SPI_6338_RX_DATA_SIZE   0x3f
 
#define SPI_6348_CMD   0x00 /* 16-bits register */
 
#define SPI_6348_INT_STATUS   0x02
 
#define SPI_6348_INT_MASK_ST   0x03
 
#define SPI_6348_INT_MASK   0x04
 
#define SPI_6348_ST   0x05
 
#define SPI_6348_CLK_CFG   0x06
 
#define SPI_6348_FILL_BYTE   0x07
 
#define SPI_6348_MSG_TAIL   0x09
 
#define SPI_6348_RX_TAIL   0x0b
 
#define SPI_6348_MSG_CTL   0x40 /* 8-bits register */
 
#define SPI_6348_MSG_CTL_WIDTH   8
 
#define SPI_6348_MSG_DATA   0x41
 
#define SPI_6348_MSG_DATA_SIZE   0x3f
 
#define SPI_6348_RX_DATA   0x80
 
#define SPI_6348_RX_DATA_SIZE   0x3f
 
#define SPI_6358_MSG_CTL   0x00 /* 16-bits register */
 
#define SPI_6358_MSG_CTL_WIDTH   16
 
#define SPI_6358_MSG_DATA   0x02
 
#define SPI_6358_MSG_DATA_SIZE   0x21e
 
#define SPI_6358_RX_DATA   0x400
 
#define SPI_6358_RX_DATA_SIZE   0x220
 
#define SPI_6358_CMD   0x700 /* 16-bits register */
 
#define SPI_6358_INT_STATUS   0x702
 
#define SPI_6358_INT_MASK_ST   0x703
 
#define SPI_6358_INT_MASK   0x704
 
#define SPI_6358_ST   0x705
 
#define SPI_6358_CLK_CFG   0x706
 
#define SPI_6358_FILL_BYTE   0x707
 
#define SPI_6358_MSG_TAIL   0x709
 
#define SPI_6358_RX_TAIL   0x70B
 
#define SPI_6368_MSG_CTL   0x00 /* 16-bits register */
 
#define SPI_6368_MSG_CTL_WIDTH   16
 
#define SPI_6368_MSG_DATA   0x02
 
#define SPI_6368_MSG_DATA_SIZE   0x21e
 
#define SPI_6368_RX_DATA   0x400
 
#define SPI_6368_RX_DATA_SIZE   0x220
 
#define SPI_6368_CMD   0x700 /* 16-bits register */
 
#define SPI_6368_INT_STATUS   0x702
 
#define SPI_6368_INT_MASK_ST   0x703
 
#define SPI_6368_INT_MASK   0x704
 
#define SPI_6368_ST   0x705
 
#define SPI_6368_CLK_CFG   0x706
 
#define SPI_6368_FILL_BYTE   0x707
 
#define SPI_6368_MSG_TAIL   0x709
 
#define SPI_6368_RX_TAIL   0x70B
 
#define SPI_FD_RW   0x00
 
#define SPI_HD_W   0x01
 
#define SPI_HD_R   0x02
 
#define SPI_BYTE_CNT_SHIFT   0
 
#define SPI_6338_MSG_TYPE_SHIFT   6
 
#define SPI_6348_MSG_TYPE_SHIFT   6
 
#define SPI_6358_MSG_TYPE_SHIFT   14
 
#define SPI_6368_MSG_TYPE_SHIFT   14
 
#define SPI_CMD_NOOP   0x00
 
#define SPI_CMD_SOFT_RESET   0x01
 
#define SPI_CMD_HARD_RESET   0x02
 
#define SPI_CMD_START_IMMEDIATE   0x03
 
#define SPI_CMD_COMMAND_SHIFT   0
 
#define SPI_CMD_COMMAND_MASK   0x000f
 
#define SPI_CMD_DEVICE_ID_SHIFT   4
 
#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT   8
 
#define SPI_CMD_ONE_BYTE_SHIFT   11
 
#define SPI_CMD_ONE_WIRE_SHIFT   12
 
#define SPI_DEV_ID_0   0
 
#define SPI_DEV_ID_1   1
 
#define SPI_DEV_ID_2   2
 
#define SPI_DEV_ID_3   3
 
#define SPI_INTR_CMD_DONE   0x01
 
#define SPI_INTR_RX_OVERFLOW   0x02
 
#define SPI_INTR_TX_UNDERFLOW   0x04
 
#define SPI_INTR_TX_OVERFLOW   0x08
 
#define SPI_INTR_RX_UNDERFLOW   0x10
 
#define SPI_INTR_CLEAR_ALL   0x1f
 
#define SPI_RX_EMPTY   0x02
 
#define SPI_CMD_BUSY   0x04
 
#define SPI_SERIAL_BUSY   0x08
 
#define SPI_CLK_20MHZ   0x00
 
#define SPI_CLK_0_391MHZ   0x01
 
#define SPI_CLK_0_781MHZ   0x02 /* default */
 
#define SPI_CLK_1_563MHZ   0x03
 
#define SPI_CLK_3_125MHZ   0x04
 
#define SPI_CLK_6_250MHZ   0x05
 
#define SPI_CLK_12_50MHZ   0x06
 
#define SPI_CLK_MASK   0x07
 
#define SPI_SSOFFTIME_MASK   0x38
 
#define SPI_SSOFFTIME_SHIFT   3
 
#define SPI_BYTE_SWAP   0x80
 
#define MISC_SERDES_CTRL_REG   0x0
 
#define SERDES_PCIE_EN   (1 << 0)
 
#define SERDES_PCIE_EXD_EN   (1 << 15)
 
#define MISC_STRAPBUS_6328_REG   0x240
 
#define STRAPBUS_6328_FCVO_SHIFT   7
 
#define STRAPBUS_6328_FCVO_MASK   (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 
#define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 28)
 
#define STRAPBUS_6328_BOOT_SEL_NAND   (0 << 28)
 
#define PCIE_CONFIG2_REG   0x408
 
#define CONFIG2_BAR1_SIZE_EN   1
 
#define CONFIG2_BAR1_SIZE_MASK   0xf
 
#define PCIE_IDVAL3_REG   0x43c
 
#define IDVAL3_CLASS_CODE_MASK   0xffffff
 
#define IDVAL3_SUBCLASS_SHIFT   8
 
#define IDVAL3_CLASS_SHIFT   16
 
#define PCIE_DLSTATUS_REG   0x1048
 
#define DLSTATUS_PHYLINKUP   (1 << 13)
 
#define PCIE_BRIDGE_OPT1_REG   0x2820
 
#define OPT1_RD_BE_OPT_EN   (1 << 7)
 
#define OPT1_RD_REPLY_BE_FIX_EN   (1 << 9)
 
#define OPT1_PCIE_BRIDGE_HOLE_DET_EN   (1 << 11)
 
#define OPT1_L1_INT_STATUS_MASK_POL   (1 << 12)
 
#define PCIE_BRIDGE_OPT2_REG   0x2824
 
#define OPT2_UBUS_UR_DECODE_DIS   (1 << 2)
 
#define OPT2_TX_CREDIT_CHK_EN   (1 << 4)
 
#define OPT2_CFG_TYPE1_BD_SEL   (1 << 7)
 
#define OPT2_CFG_TYPE1_BUS_NO_SHIFT   16
 
#define OPT2_CFG_TYPE1_BUS_NO_MASK   (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
 
#define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828
 
#define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830
 
#define BASEMASK_REMAP_EN   (1 << 0)
 
#define BASEMASK_SWAP_EN   (1 << 1)
 
#define BASEMASK_MASK_SHIFT   4
 
#define BASEMASK_MASK_MASK   (0xfff << BASEMASK_MASK_SHIFT)
 
#define BASEMASK_BASE_SHIFT   20
 
#define BASEMASK_BASE_MASK   (0xfff << BASEMASK_BASE_SHIFT)
 
#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG   0x282c
 
#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG   0x2834
 
#define REBASE_ADDR_BASE_SHIFT   20
 
#define REBASE_ADDR_BASE_MASK   (0xfff << REBASE_ADDR_BASE_SHIFT)
 
#define PCIE_BRIDGE_RC_INT_MASK_REG   0x2854
 
#define PCIE_RC_INT_A   (1 << 0)
 
#define PCIE_RC_INT_B   (1 << 1)
 
#define PCIE_RC_INT_C   (1 << 2)
 
#define PCIE_RC_INT_D   (1 << 3)
 
#define PCIE_DEVICE_OFFSET   0x8000
 

Macro Definition Documentation

#define ADSLPLLCTL_M1BUS_MASK   (0x7 << ADSLPLLCTL_M1BUS_SHIFT)

Definition at line 286 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M1BUS_SHIFT   3

Definition at line 285 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M1CPU_MASK   (0x7 << ADSLPLLCTL_M1CPU_SHIFT)

Definition at line 284 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M1CPU_SHIFT   6

Definition at line 283 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M1REF_MASK   (0x7 << ADSLPLLCTL_M1REF_SHIFT)

Definition at line 280 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M1REF_SHIFT   12

Definition at line 279 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M2BUS_MASK   (0x7 << ADSLPLLCTL_M2BUS_SHIFT)

Definition at line 288 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M2BUS_SHIFT   0

Definition at line 287 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M2REF_MASK   (0x7 << ADSLPLLCTL_M2REF_SHIFT)

Definition at line 282 of file bcm63xx_regs.h.

#define ADSLPLLCTL_M2REF_SHIFT   9

Definition at line 281 of file bcm63xx_regs.h.

#define ADSLPLLCTL_N1_MASK   (0x7 << ADSLPLLCTL_N1_SHIFT)

Definition at line 276 of file bcm63xx_regs.h.

#define ADSLPLLCTL_N1_SHIFT   20

Definition at line 275 of file bcm63xx_regs.h.

#define ADSLPLLCTL_N2_MASK   (0x1f << ADSLPLLCTL_N2_SHIFT)

Definition at line 278 of file bcm63xx_regs.h.

#define ADSLPLLCTL_N2_SHIFT   15

Definition at line 277 of file bcm63xx_regs.h.

#define ADSLPLLCTL_VAL (   n1,
  n2,
  m1ref,
  m2ref,
  m1cpu,
  m1bus,
  m2bus 
)
Value:
(((n1) << ADSLPLLCTL_N1_SHIFT) | \
((n2) << ADSLPLLCTL_N2_SHIFT) | \
((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))

Definition at line 290 of file bcm63xx_regs.h.

#define BASEMASK_BASE_MASK   (0xfff << BASEMASK_BASE_SHIFT)

Definition at line 1382 of file bcm63xx_regs.h.

#define BASEMASK_BASE_SHIFT   20

Definition at line 1381 of file bcm63xx_regs.h.

#define BASEMASK_MASK_MASK   (0xfff << BASEMASK_MASK_SHIFT)

Definition at line 1380 of file bcm63xx_regs.h.

#define BASEMASK_MASK_SHIFT   4

Definition at line 1379 of file bcm63xx_regs.h.

#define BASEMASK_REMAP_EN   (1 << 0)

Definition at line 1377 of file bcm63xx_regs.h.

#define BASEMASK_SWAP_EN   (1 << 1)

Definition at line 1378 of file bcm63xx_regs.h.

#define BCM63XX_TIMER_COUNT   4

Definition at line 304 of file bcm63xx_regs.h.

#define BCMPCI_REG_TIMERS   0x40

Definition at line 1062 of file bcm63xx_regs.h.

#define CKCTL_6328_ADSL_AFE_EN   (1 << 2)

Definition at line 20 of file bcm63xx_regs.h.

#define CKCTL_6328_ADSL_EN   (1 << 3)

Definition at line 21 of file bcm63xx_regs.h.

#define CKCTL_6328_ADSL_QPROC_EN   (1 << 1)

Definition at line 19 of file bcm63xx_regs.h.

#define CKCTL_6328_ALL_SAFE_EN
Value:
(CKCTL_6328_PHYMIPS_EN | \
CKCTL_6328_ADSL_QPROC_EN | \
CKCTL_6328_ADSL_AFE_EN | \
CKCTL_6328_ADSL_EN | \
CKCTL_6328_SAR_EN | \
CKCTL_6328_PCM_EN | \
CKCTL_6328_USBD_EN | \
CKCTL_6328_USBH_EN | \
CKCTL_6328_ROBOSW_EN | \
CKCTL_6328_PCIE_EN)

Definition at line 31 of file bcm63xx_regs.h.

#define CKCTL_6328_HSSPI_EN   (1 << 9)

Definition at line 27 of file bcm63xx_regs.h.

#define CKCTL_6328_MIPS_EN   (1 << 4)

Definition at line 22 of file bcm63xx_regs.h.

#define CKCTL_6328_PCIE_EN   (1 << 10)

Definition at line 28 of file bcm63xx_regs.h.

#define CKCTL_6328_PCM_EN   (1 << 6)

Definition at line 24 of file bcm63xx_regs.h.

#define CKCTL_6328_PHYMIPS_EN   (1 << 0)

Definition at line 18 of file bcm63xx_regs.h.

#define CKCTL_6328_ROBOSW_EN   (1 << 11)

Definition at line 29 of file bcm63xx_regs.h.

#define CKCTL_6328_SAR_EN   (1 << 5)

Definition at line 23 of file bcm63xx_regs.h.

#define CKCTL_6328_USBD_EN   (1 << 7)

Definition at line 25 of file bcm63xx_regs.h.

#define CKCTL_6328_USBH_EN   (1 << 8)

Definition at line 26 of file bcm63xx_regs.h.

#define CKCTL_6338_ADSLPHY_EN   (1 << 0)

Definition at line 42 of file bcm63xx_regs.h.

#define CKCTL_6338_ALL_SAFE_EN
Value:
(CKCTL_6338_ADSLPHY_EN | \
CKCTL_6338_MPI_EN | \
CKCTL_6338_ENET_EN | \
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)

Definition at line 50 of file bcm63xx_regs.h.

#define CKCTL_6338_DRAM_EN   (1 << 2)

Definition at line 44 of file bcm63xx_regs.h.

#define CKCTL_6338_ENET_EN   (1 << 4)

Definition at line 45 of file bcm63xx_regs.h.

#define CKCTL_6338_MPI_EN   (1 << 1)

Definition at line 43 of file bcm63xx_regs.h.

#define CKCTL_6338_SAR_EN   (1 << 5)

Definition at line 47 of file bcm63xx_regs.h.

#define CKCTL_6338_SPI_EN   (1 << 9)

Definition at line 48 of file bcm63xx_regs.h.

#define CKCTL_6338_USBS_EN   (1 << 4)

Definition at line 46 of file bcm63xx_regs.h.

#define CKCTL_6345_ADSLPHY_EN   (1 << 4)

Definition at line 60 of file bcm63xx_regs.h.

#define CKCTL_6345_ALL_SAFE_EN
Value:
(CKCTL_6345_ENET_EN | \
CKCTL_6345_USBH_EN | \
CKCTL_6345_ADSLPHY_EN)

Definition at line 64 of file bcm63xx_regs.h.

#define CKCTL_6345_BUS_EN   (1 << 1)

Definition at line 57 of file bcm63xx_regs.h.

#define CKCTL_6345_CPU_EN   (1 << 0)

Definition at line 56 of file bcm63xx_regs.h.

#define CKCTL_6345_EBI_EN   (1 << 2)

Definition at line 58 of file bcm63xx_regs.h.

#define CKCTL_6345_ENET_EN   (1 << 7)

Definition at line 61 of file bcm63xx_regs.h.

#define CKCTL_6345_UART_EN   (1 << 3)

Definition at line 59 of file bcm63xx_regs.h.

#define CKCTL_6345_USBH_EN   (1 << 8)

Definition at line 62 of file bcm63xx_regs.h.

#define CKCTL_6348_ADSLPHY_EN   (1 << 0)

Definition at line 68 of file bcm63xx_regs.h.

#define CKCTL_6348_ALL_SAFE_EN
Value:
(CKCTL_6348_ADSLPHY_EN | \
CKCTL_6348_M2M_EN | \
CKCTL_6348_ENET_EN | \
CKCTL_6348_SAR_EN | \
CKCTL_6348_USBS_EN | \
CKCTL_6348_USBH_EN | \
CKCTL_6348_SPI_EN)

Definition at line 78 of file bcm63xx_regs.h.

#define CKCTL_6348_ENET_EN   (1 << 4)

Definition at line 72 of file bcm63xx_regs.h.

#define CKCTL_6348_M2M_EN   (1 << 3)

Definition at line 71 of file bcm63xx_regs.h.

#define CKCTL_6348_MPI_EN   (1 << 1)

Definition at line 69 of file bcm63xx_regs.h.

#define CKCTL_6348_SAR_EN   (1 << 5)

Definition at line 73 of file bcm63xx_regs.h.

#define CKCTL_6348_SDRAM_EN   (1 << 2)

Definition at line 70 of file bcm63xx_regs.h.

#define CKCTL_6348_SPI_EN   (1 << 9)

Definition at line 76 of file bcm63xx_regs.h.

#define CKCTL_6348_USBH_EN   (1 << 8)

Definition at line 75 of file bcm63xx_regs.h.

#define CKCTL_6348_USBS_EN   (1 << 6)

Definition at line 74 of file bcm63xx_regs.h.

#define CKCTL_6358_ADSLPHY_EN   (1 << 5)

Definition at line 87 of file bcm63xx_regs.h.

#define CKCTL_6358_ALL_SAFE_EN
Value:
(CKCTL_6358_ENET_EN | \
CKCTL_6358_ADSLPHY_EN | \
CKCTL_6358_PCM_EN | \
CKCTL_6358_SPI_EN | \
CKCTL_6358_USBS_EN | \
CKCTL_6358_SAR_EN | \
CKCTL_6358_EMUSB_EN | \
CKCTL_6358_ENET0_EN | \
CKCTL_6358_ENET1_EN | \
CKCTL_6358_USBSU_EN | \
CKCTL_6358_EPHY_EN)

Definition at line 98 of file bcm63xx_regs.h.

#define CKCTL_6358_EMUSB_EN   (1 << 17)

Definition at line 92 of file bcm63xx_regs.h.

#define CKCTL_6358_ENET0_EN   (1 << 18)

Definition at line 93 of file bcm63xx_regs.h.

#define CKCTL_6358_ENET1_EN   (1 << 19)

Definition at line 94 of file bcm63xx_regs.h.

#define CKCTL_6358_ENET_EN   (1 << 4)

Definition at line 86 of file bcm63xx_regs.h.

#define CKCTL_6358_EPHY_EN   (1 << 21)

Definition at line 96 of file bcm63xx_regs.h.

#define CKCTL_6358_PCM_EN   (1 << 8)

Definition at line 88 of file bcm63xx_regs.h.

#define CKCTL_6358_SAR_EN   (1 << 11)

Definition at line 91 of file bcm63xx_regs.h.

#define CKCTL_6358_SPI_EN   (1 << 9)

Definition at line 89 of file bcm63xx_regs.h.

#define CKCTL_6358_USBS_EN   (1 << 10)

Definition at line 90 of file bcm63xx_regs.h.

#define CKCTL_6358_USBSU_EN   (1 << 20)

Definition at line 95 of file bcm63xx_regs.h.

#define CKCTL_6368_ALL_SAFE_EN
Value:
(CKCTL_6368_SWPKT_USB_EN | \
CKCTL_6368_SWPKT_SAR_EN | \
CKCTL_6368_SPI_EN | \
CKCTL_6368_USBD_EN | \
CKCTL_6368_SAR_EN | \
CKCTL_6368_ROBOSW_EN | \
CKCTL_6368_UTOPIA_EN | \
CKCTL_6368_PCM_EN | \
CKCTL_6368_USBH_EN | \
CKCTL_6368_DISABLE_GLESS_EN | \
CKCTL_6368_NAND_EN | \
CKCTL_6368_IPSEC_EN)

Definition at line 128 of file bcm63xx_regs.h.

#define CKCTL_6368_DISABLE_GLESS_EN   (1 << 16)

Definition at line 124 of file bcm63xx_regs.h.

#define CKCTL_6368_IPSEC_EN   (1 << 18)

Definition at line 126 of file bcm63xx_regs.h.

#define CKCTL_6368_NAND_EN   (1 << 17)

Definition at line 125 of file bcm63xx_regs.h.

#define CKCTL_6368_PCM_EN   (1 << 14)

Definition at line 122 of file bcm63xx_regs.h.

#define CKCTL_6368_PHYMIPS_EN   (1 << 6)

Definition at line 114 of file bcm63xx_regs.h.

#define CKCTL_6368_ROBOSW_EN   (1 << 12)

Definition at line 120 of file bcm63xx_regs.h.

#define CKCTL_6368_SAR_EN   (1 << 11)

Definition at line 119 of file bcm63xx_regs.h.

#define CKCTL_6368_SPI_EN   (1 << 9)

Definition at line 117 of file bcm63xx_regs.h.

#define CKCTL_6368_SWPKT_SAR_EN   (1 << 8)

Definition at line 116 of file bcm63xx_regs.h.

#define CKCTL_6368_SWPKT_USB_EN   (1 << 7)

Definition at line 115 of file bcm63xx_regs.h.

#define CKCTL_6368_USBD_EN   (1 << 10)

Definition at line 118 of file bcm63xx_regs.h.

#define CKCTL_6368_USBH_EN   (1 << 15)

Definition at line 123 of file bcm63xx_regs.h.

#define CKCTL_6368_UTOPIA_EN   (1 << 13)

Definition at line 121 of file bcm63xx_regs.h.

#define CKCTL_6368_VDSL_AFE_EN   (1 << 3)

Definition at line 111 of file bcm63xx_regs.h.

#define CKCTL_6368_VDSL_BONDING_EN   (1 << 4)

Definition at line 112 of file bcm63xx_regs.h.

#define CKCTL_6368_VDSL_EN   (1 << 5)

Definition at line 113 of file bcm63xx_regs.h.

#define CKCTL_6368_VDSL_QPROC_EN   (1 << 2)

Definition at line 110 of file bcm63xx_regs.h.

#define CONFIG2_BAR1_SIZE_EN   1

Definition at line 1351 of file bcm63xx_regs.h.

#define CONFIG2_BAR1_SIZE_MASK   0xf

Definition at line 1352 of file bcm63xx_regs.h.

#define DDR_CSEND_REG   0x8

Definition at line 1142 of file bcm63xx_regs.h.

#define DDR_DMIPSPLLCFG_6368_REG   0x20

Definition at line 1152 of file bcm63xx_regs.h.

#define DDR_DMIPSPLLCFG_REG   0x18

Definition at line 1144 of file bcm63xx_regs.h.

#define DDR_DMIPSPLLDIV_6368_REG   0x24

Definition at line 1160 of file bcm63xx_regs.h.

#define DLSTATUS_PHYLINKUP   (1 << 13)

Definition at line 1360 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_NDIV_MASK   (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)

Definition at line 1158 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_NDIV_SHIFT   16

Definition at line 1157 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_P1_MASK   (0xf << DMIPSPLLCFG_6368_P1_SHIFT)

Definition at line 1154 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_P1_SHIFT   0

Definition at line 1153 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_P2_MASK   (0xf << DMIPSPLLCFG_6368_P2_SHIFT)

Definition at line 1156 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_6368_P2_SHIFT   4

Definition at line 1155 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_M1_MASK   (0xff << DMIPSPLLCFG_M1_SHIFT)

Definition at line 1146 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_M1_SHIFT   0

Definition at line 1145 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_N1_MASK   (0x3f << DMIPSPLLCFG_N1_SHIFT)

Definition at line 1148 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_N1_SHIFT   23

Definition at line 1147 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_N2_MASK   (0x7 << DMIPSPLLCFG_N2_SHIFT)

Definition at line 1150 of file bcm63xx_regs.h.

#define DMIPSPLLCFG_N2_SHIFT   29

Definition at line 1149 of file bcm63xx_regs.h.

#define DMIPSPLLDIV_6368_MDIV_MASK   (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)

Definition at line 1162 of file bcm63xx_regs.h.

#define DMIPSPLLDIV_6368_MDIV_SHIFT   0

Definition at line 1161 of file bcm63xx_regs.h.

#define ENET_CTL_DISABLE_MASK   (1 << ENET_CTL_DISABLE_SHIFT)

Definition at line 627 of file bcm63xx_regs.h.

#define ENET_CTL_DISABLE_SHIFT   1

Definition at line 626 of file bcm63xx_regs.h.

#define ENET_CTL_ENABLE_MASK   (1 << ENET_CTL_ENABLE_SHIFT)

Definition at line 625 of file bcm63xx_regs.h.

#define ENET_CTL_ENABLE_SHIFT   0

Definition at line 624 of file bcm63xx_regs.h.

#define ENET_CTL_EPHYSEL_MASK   (1 << ENET_CTL_EPHYSEL_SHIFT)

Definition at line 631 of file bcm63xx_regs.h.

#define ENET_CTL_EPHYSEL_SHIFT   3

Definition at line 630 of file bcm63xx_regs.h.

#define ENET_CTL_REG   0x2c

Definition at line 623 of file bcm63xx_regs.h.

#define ENET_CTL_SRESET_MASK   (1 << ENET_CTL_SRESET_SHIFT)

Definition at line 629 of file bcm63xx_regs.h.

#define ENET_CTL_SRESET_SHIFT   2

Definition at line 628 of file bcm63xx_regs.h.

#define ENET_IR_FLOWC   (1 << 2)

Definition at line 620 of file bcm63xx_regs.h.

#define ENET_IR_MIB   (1 << 1)

Definition at line 619 of file bcm63xx_regs.h.

#define ENET_IR_MII   (1 << 0)

Definition at line 618 of file bcm63xx_regs.h.

#define ENET_IR_REG   0x1c

Definition at line 617 of file bcm63xx_regs.h.

#define ENET_IRMASK_REG   0x18

Definition at line 614 of file bcm63xx_regs.h.

#define ENET_MIB_REG (   x)    (0x200 + (x) * 4)

Definition at line 655 of file bcm63xx_regs.h.

#define ENET_MIB_REG_COUNT   55

Definition at line 656 of file bcm63xx_regs.h.

#define ENET_MIBCTL_RDCLEAR_MASK   (1 << ENET_MIBCTL_RDCLEAR_SHIFT)

Definition at line 646 of file bcm63xx_regs.h.

#define ENET_MIBCTL_RDCLEAR_SHIFT   0

Definition at line 645 of file bcm63xx_regs.h.

#define ENET_MIBCTL_REG   0x38

Definition at line 644 of file bcm63xx_regs.h.

#define ENET_MIIDATA_DATA_MASK   (0xffff << ENET_MIIDATA_DATA_SHIFT)

Definition at line 603 of file bcm63xx_regs.h.

#define ENET_MIIDATA_DATA_SHIFT   0

Definition at line 602 of file bcm63xx_regs.h.

#define ENET_MIIDATA_OP_READ_MASK   (0x6 << 28)

Definition at line 610 of file bcm63xx_regs.h.

#define ENET_MIIDATA_OP_WRITE_MASK   (0x5 << 28)

Definition at line 611 of file bcm63xx_regs.h.

#define ENET_MIIDATA_PHYID_MASK   (0x1f << ENET_MIIDATA_PHYID_SHIFT)

Definition at line 609 of file bcm63xx_regs.h.

#define ENET_MIIDATA_PHYID_SHIFT   23

Definition at line 608 of file bcm63xx_regs.h.

#define ENET_MIIDATA_REG   0x14

Definition at line 601 of file bcm63xx_regs.h.

#define ENET_MIIDATA_REG_MASK   (0x1f << ENET_MIIDATA_REG_SHIFT)

Definition at line 607 of file bcm63xx_regs.h.

#define ENET_MIIDATA_REG_SHIFT   18

Definition at line 606 of file bcm63xx_regs.h.

#define ENET_MIIDATA_TA_MASK   (0x3 << ENET_MIIDATA_TA_SHIFT)

Definition at line 605 of file bcm63xx_regs.h.

#define ENET_MIIDATA_TA_SHIFT   16

Definition at line 604 of file bcm63xx_regs.h.

#define ENET_MIISC_MDCFREQDIV_MASK   (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)

Definition at line 596 of file bcm63xx_regs.h.

#define ENET_MIISC_MDCFREQDIV_SHIFT   0

Definition at line 595 of file bcm63xx_regs.h.

#define ENET_MIISC_PREAMBLEEN_MASK   (1 << ENET_MIISC_PREAMBLEEN_SHIFT)

Definition at line 598 of file bcm63xx_regs.h.

#define ENET_MIISC_PREAMBLEEN_SHIFT   7

Definition at line 597 of file bcm63xx_regs.h.

#define ENET_MIISC_REG   0x10

Definition at line 594 of file bcm63xx_regs.h.

#define ENET_PMH_DATAVALID_MASK   (1 << ENET_PMH_DATAVALID_SHIFT)

Definition at line 652 of file bcm63xx_regs.h.

#define ENET_PMH_DATAVALID_SHIFT   16

Definition at line 651 of file bcm63xx_regs.h.

#define ENET_PMH_REG (   x)    (0x5c + (x) * 8)

Definition at line 650 of file bcm63xx_regs.h.

#define ENET_PML_REG (   x)    (0x58 + (x) * 8)

Definition at line 649 of file bcm63xx_regs.h.

#define ENET_RXCFG_ALLMCAST_MASK   (1 << ENET_RXCFG_ALLMCAST_SHIFT)

Definition at line 575 of file bcm63xx_regs.h.

#define ENET_RXCFG_ALLMCAST_SHIFT   1

Definition at line 574 of file bcm63xx_regs.h.

#define ENET_RXCFG_ENFLOW_MASK   (1 << ENET_RXCFG_ENFLOW_SHIFT)

Definition at line 581 of file bcm63xx_regs.h.

#define ENET_RXCFG_ENFLOW_SHIFT   5

Definition at line 580 of file bcm63xx_regs.h.

#define ENET_RXCFG_LOOPBACK_MASK   (1 << ENET_RXCFG_LOOPBACK_SHIFT)

Definition at line 579 of file bcm63xx_regs.h.

#define ENET_RXCFG_LOOPBACK_SHIFT   4

Definition at line 578 of file bcm63xx_regs.h.

#define ENET_RXCFG_PROMISC_MASK   (1 << ENET_RXCFG_PROMISC_SHIFT)

Definition at line 577 of file bcm63xx_regs.h.

#define ENET_RXCFG_PROMISC_SHIFT   3

Definition at line 576 of file bcm63xx_regs.h.

#define ENET_RXCFG_REG   0x0

Definition at line 573 of file bcm63xx_regs.h.

#define ENET_RXMAXLEN_MASK   (0x7ff << ENET_RXMAXLEN_SHIFT)

Definition at line 586 of file bcm63xx_regs.h.

#define ENET_RXMAXLEN_REG   0x4

Definition at line 584 of file bcm63xx_regs.h.

#define ENET_RXMAXLEN_SHIFT   0

Definition at line 585 of file bcm63xx_regs.h.

#define ENET_TXCTL_FD_MASK   (1 << ENET_TXCTL_FD_SHIFT)

Definition at line 636 of file bcm63xx_regs.h.

#define ENET_TXCTL_FD_SHIFT   0

Definition at line 635 of file bcm63xx_regs.h.

#define ENET_TXCTL_REG   0x30

Definition at line 634 of file bcm63xx_regs.h.

#define ENET_TXMAXLEN_MASK   (0x7ff << ENET_TXMAXLEN_SHIFT)

Definition at line 591 of file bcm63xx_regs.h.

#define ENET_TXMAXLEN_REG   0x8

Definition at line 589 of file bcm63xx_regs.h.

#define ENET_TXMAXLEN_SHIFT   0

Definition at line 590 of file bcm63xx_regs.h.

#define ENET_TXWMARK_REG   0x34

Definition at line 639 of file bcm63xx_regs.h.

#define ENET_TXWMARK_WM_MASK   (0x3f << ENET_TXWMARK_WM_SHIFT)

Definition at line 641 of file bcm63xx_regs.h.

#define ENET_TXWMARK_WM_SHIFT   0

Definition at line 640 of file bcm63xx_regs.h.

#define ENETDMA_BUFALLOC_FORCE_MASK   (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)

Definition at line 678 of file bcm63xx_regs.h.

#define ENETDMA_BUFALLOC_FORCE_SHIFT   31

Definition at line 677 of file bcm63xx_regs.h.

#define ENETDMA_BUFALLOC_REG (   x)    (0xc + (x) * 6)

Definition at line 676 of file bcm63xx_regs.h.

#define ENETDMA_CFG_EN_MASK   (1 << ENETDMA_CFG_EN_SHIFT)

Definition at line 666 of file bcm63xx_regs.h.

#define ENETDMA_CFG_EN_SHIFT   0

Definition at line 665 of file bcm63xx_regs.h.

#define ENETDMA_CFG_FLOWCH_MASK (   x)    (1 << ((x >> 1) + 1))

Definition at line 667 of file bcm63xx_regs.h.

#define ENETDMA_CFG_REG   (0x0)

Definition at line 664 of file bcm63xx_regs.h.

#define ENETDMA_CHANCFG_EN_MASK   (1 << ENETDMA_CHANCFG_EN_SHIFT)

Definition at line 689 of file bcm63xx_regs.h.

#define ENETDMA_CHANCFG_EN_SHIFT   0

Definition at line 688 of file bcm63xx_regs.h.

#define ENETDMA_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)

Definition at line 691 of file bcm63xx_regs.h.

#define ENETDMA_CHANCFG_PKTHALT_SHIFT   1

Definition at line 690 of file bcm63xx_regs.h.

#define ENETDMA_CHANCFG_REG (   x)    (0x100 + (x) * 0x10)

Definition at line 687 of file bcm63xx_regs.h.

#define ENETDMA_FLOWCH_REG (   x)    (0x8 + (x) * 6)

Definition at line 673 of file bcm63xx_regs.h.

#define ENETDMA_FLOWCL_REG (   x)    (0x4 + (x) * 6)

Definition at line 670 of file bcm63xx_regs.h.

#define ENETDMA_GLB_IRQMASK_REG   (0x44)

Definition at line 684 of file bcm63xx_regs.h.

#define ENETDMA_GLB_IRQSTAT_REG   (0x40)

Definition at line 681 of file bcm63xx_regs.h.

#define ENETDMA_IR_BUFDONE_MASK   (1 << 0)

Definition at line 695 of file bcm63xx_regs.h.

#define ENETDMA_IR_NOTOWNER_MASK   (1 << 2)

Definition at line 697 of file bcm63xx_regs.h.

#define ENETDMA_IR_PKTDONE_MASK   (1 << 1)

Definition at line 696 of file bcm63xx_regs.h.

#define ENETDMA_IR_REG (   x)    (0x104 + (x) * 0x10)

Definition at line 694 of file bcm63xx_regs.h.

#define ENETDMA_IRMASK_REG (   x)    (0x108 + (x) * 0x10)

Definition at line 700 of file bcm63xx_regs.h.

#define ENETDMA_MAXBURST_REG (   x)    (0x10C + (x) * 0x10)

Definition at line 703 of file bcm63xx_regs.h.

#define ENETDMA_RSTART_REG (   x)    (0x200 + (x) * 0x10)

Definition at line 706 of file bcm63xx_regs.h.

#define ENETDMA_SRAM2_REG (   x)    (0x204 + (x) * 0x10)

Definition at line 709 of file bcm63xx_regs.h.

#define ENETDMA_SRAM3_REG (   x)    (0x208 + (x) * 0x10)

Definition at line 712 of file bcm63xx_regs.h.

#define ENETDMA_SRAM4_REG (   x)    (0x20c + (x) * 0x10)

Definition at line 715 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)

Definition at line 729 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_BUFHALT_SHIFT   2

Definition at line 728 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_EN_MASK   (1 << ENETDMAC_CHANCFG_EN_SHIFT)

Definition at line 725 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_EN_SHIFT   0

Definition at line 724 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)

Definition at line 727 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_PKTHALT_SHIFT   1

Definition at line 726 of file bcm63xx_regs.h.

#define ENETDMAC_CHANCFG_REG (   x)    ((x) * 0x10)

Definition at line 723 of file bcm63xx_regs.h.

#define ENETDMAC_IR_BUFDONE_MASK   (1 << 0)

Definition at line 733 of file bcm63xx_regs.h.

#define ENETDMAC_IR_NOTOWNER_MASK   (1 << 2)

Definition at line 735 of file bcm63xx_regs.h.

#define ENETDMAC_IR_PKTDONE_MASK   (1 << 1)

Definition at line 734 of file bcm63xx_regs.h.

#define ENETDMAC_IR_REG (   x)    (0x4 + (x) * 0x10)

Definition at line 732 of file bcm63xx_regs.h.

#define ENETDMAC_IRMASK_REG (   x)    (0x8 + (x) * 0x10)

Definition at line 738 of file bcm63xx_regs.h.

#define ENETDMAC_MAXBURST_REG (   x)    (0xc + (x) * 0x10)

Definition at line 741 of file bcm63xx_regs.h.

#define ENETDMAS_RSTART_REG (   x)    ((x) * 0x10)

Definition at line 749 of file bcm63xx_regs.h.

#define ENETDMAS_SRAM2_REG (   x)    (0x4 + (x) * 0x10)

Definition at line 752 of file bcm63xx_regs.h.

#define ENETDMAS_SRAM3_REG (   x)    (0x8 + (x) * 0x10)

Definition at line 755 of file bcm63xx_regs.h.

#define ENETDMAS_SRAM4_REG (   x)    (0xc + (x) * 0x10)

Definition at line 758 of file bcm63xx_regs.h.

#define ENETSW_MIB_REG (   x)    (0x2800 + (x) * 4)

Definition at line 766 of file bcm63xx_regs.h.

#define ENETSW_MIB_REG_COUNT   47

Definition at line 767 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_BOTHEDGE (   x)    (1 << (x + 16))

Definition at line 186 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_BOTHEDGE_6348 (   x)    (1 << (x + 20))

Definition at line 176 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_CLEAR (   x)    (1 << (x + 8))

Definition at line 184 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_CLEAR_6348 (   x)    (1 << (x + 10))

Definition at line 174 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_CLEAR_ALL   (0xf << 8)

Definition at line 188 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_CLEAR_ALL_6348   (0xf << 10)

Definition at line 178 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_LEVELSENSE (   x)    (1 << (x + 20))

Definition at line 187 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_LEVELSENSE_6348 (   x)    (1 << (x + 25))

Definition at line 177 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_MASK (   x)    (1 << (x + 12))

Definition at line 185 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_MASK_6348 (   x)    (1 << (x + 15))

Definition at line 175 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_MASK_ALL   (0xf << 12)

Definition at line 189 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_MASK_ALL_6348   (0xf << 15)

Definition at line 179 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_SENSE (   x)    (1 << (x))

Definition at line 182 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_SENSE_6348 (   x)    (1 << (x))

Definition at line 172 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_STAT (   x)    (1 << (x + 4))

Definition at line 183 of file bcm63xx_regs.h.

#define EXTIRQ_CFG_STAT_6348 (   x)    (1 << (x + 5))

Definition at line 173 of file bcm63xx_regs.h.

#define GPIO_BASEMODE_6368_GPIO   0x0

Definition at line 555 of file bcm63xx_regs.h.

#define GPIO_BASEMODE_6368_MASK   0x7

Definition at line 556 of file bcm63xx_regs.h.

#define GPIO_BASEMODE_6368_REG   0x38

Definition at line 553 of file bcm63xx_regs.h.

#define GPIO_BASEMODE_6368_UART2   0x1

Definition at line 554 of file bcm63xx_regs.h.

#define GPIO_CTL_HI_REG   0x0

Definition at line 479 of file bcm63xx_regs.h.

#define GPIO_CTL_LO_REG   0x4

Definition at line 480 of file bcm63xx_regs.h.

#define GPIO_DATA_HI_REG   0x8

Definition at line 481 of file bcm63xx_regs.h.

#define GPIO_DATA_LO_REG   0xC

Definition at line 482 of file bcm63xx_regs.h.

#define GPIO_DATA_LO_REG_6345   0x8

Definition at line 483 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G0_DIAG   0x00000009

Definition at line 505 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G0_EXT_MII   0x00000007

Definition at line 506 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_DIAG   0x00000090

Definition at line 498 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_EXT_EPHY   0x00000010

Definition at line 504 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_MII_PCCARD   0x00000040

Definition at line 502 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_MII_SNOOP   0x00000020

Definition at line 503 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_SPI_MASTER   0x00000060

Definition at line 501 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_SPI_UART   0x00000060

Definition at line 500 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G1_UTOPIA   0x00000080

Definition at line 499 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G2_DIAG   0x00000900

Definition at line 496 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G2_PCI   0x00000500

Definition at line 497 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G3_DIAG   0x00009000

Definition at line 493 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G3_EXT_MII   0x00007000

Definition at line 495 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G3_UTOPIA   0x00008000

Definition at line 494 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G4_DIAG   0x00090000

Definition at line 488 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G4_EXT_EPHY   0x00010000

Definition at line 492 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G4_LEGACY_LED   0x00030000

Definition at line 490 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G4_MII_SNOOP   0x00020000

Definition at line 491 of file bcm63xx_regs.h.

#define GPIO_MODE_6348_G4_UTOPIA   0x00080000

Definition at line 489 of file bcm63xx_regs.h.

#define GPIO_MODE_6358_EXTRA_SPI_SS   (1 << 7)

Definition at line 510 of file bcm63xx_regs.h.

#define GPIO_MODE_6358_EXTRACS   (1 << 5)

Definition at line 508 of file bcm63xx_regs.h.

#define GPIO_MODE_6358_SERIAL_LED   (1 << 10)

Definition at line 511 of file bcm63xx_regs.h.

#define GPIO_MODE_6358_UART1   (1 << 6)

Definition at line 509 of file bcm63xx_regs.h.

#define GPIO_MODE_6358_UTOPIA   (1 << 12)

Definition at line 512 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ANALOG_AFE_0   (1 << 0)

Definition at line 514 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ANALOG_AFE_1   (1 << 1)

Definition at line 515 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EBI_CS2   (1 << 26)

Definition at line 539 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EBI_CS3   (1 << 27)

Definition at line 540 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EPHY0_LED   (1 << 6)

Definition at line 520 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EPHY1_LED   (1 << 7)

Definition at line 521 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EPHY2_LED   (1 << 8)

Definition at line 522 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_EPHY3_LED   (1 << 9)

Definition at line 523 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_INET_LED   (1 << 5)

Definition at line 519 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_NTR_PULSE   (1 << 15)

Definition at line 529 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCI_GNT0   (1 << 20)

Definition at line 534 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCI_GNT1   (1 << 17)

Definition at line 531 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCI_INTB   (1 << 18)

Definition at line 532 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCI_REQ0   (1 << 19)

Definition at line 533 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCI_REQ1   (1 << 16)

Definition at line 530 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCMCIA_CD1   (1 << 22)

Definition at line 535 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCMCIA_CD2   (1 << 23)

Definition at line 536 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCMCIA_VS1   (1 << 24)

Definition at line 537 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_PCMCIA_VS2   (1 << 25)

Definition at line 538 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ROBOSW_LED0   (1 << 12)

Definition at line 526 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ROBOSW_LED1   (1 << 13)

Definition at line 527 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)

Definition at line 525 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)

Definition at line 524 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)

Definition at line 518 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SERIAL_LED_DATA   (1 << 3)

Definition at line 517 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SPI_SSN2   (1 << 28)

Definition at line 541 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SPI_SSN3   (1 << 29)

Definition at line 542 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SPI_SSN4   (1 << 30)

Definition at line 543 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SPI_SSN5   (1 << 31)

Definition at line 544 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_SYS_IRQ   (1 << 2)

Definition at line 516 of file bcm63xx_regs.h.

#define GPIO_MODE_6368_USBD_LED   (1 << 14)

Definition at line 528 of file bcm63xx_regs.h.

#define GPIO_MODE_REG   0x18

Definition at line 486 of file bcm63xx_regs.h.

#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)

Definition at line 551 of file bcm63xx_regs.h.

#define GPIO_PINMUX_OTHR_6328_USB_HOST   (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)

Definition at line 550 of file bcm63xx_regs.h.

#define GPIO_PINMUX_OTHR_6328_USB_MASK   (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)

Definition at line 549 of file bcm63xx_regs.h.

#define GPIO_PINMUX_OTHR_6328_USB_SHIFT   12

Definition at line 548 of file bcm63xx_regs.h.

#define GPIO_PINMUX_OTHR_REG   0x24

Definition at line 547 of file bcm63xx_regs.h.

#define GPIO_STRAPBUS_REG   0x40

Definition at line 559 of file bcm63xx_regs.h.

#define IDVAL3_CLASS_CODE_MASK   0xffffff

Definition at line 1355 of file bcm63xx_regs.h.

#define IDVAL3_CLASS_SHIFT   16

Definition at line 1357 of file bcm63xx_regs.h.

#define IDVAL3_SUBCLASS_SHIFT   8

Definition at line 1356 of file bcm63xx_regs.h.

#define M2M_CTRL_DONE_CLR_MASK   (1 << 7)

Definition at line 1180 of file bcm63xx_regs.h.

#define M2M_CTRL_ENABLE_MASK   (1 << 0)

Definition at line 1177 of file bcm63xx_regs.h.

#define M2M_CTRL_ENDIAN_MASK   (1 << 11)

Definition at line 1184 of file bcm63xx_regs.h.

#define M2M_CTRL_ERROR_CLR_MASK   (1 << 6)

Definition at line 1179 of file bcm63xx_regs.h.

#define M2M_CTRL_IRQEN_MASK   (1 << 1)

Definition at line 1178 of file bcm63xx_regs.h.

#define M2M_CTRL_NOINC_MASK   (1 << 8)

Definition at line 1181 of file bcm63xx_regs.h.

#define M2M_CTRL_PCMCIASWAP_MASK   (1 << 9)

Definition at line 1182 of file bcm63xx_regs.h.

#define M2M_CTRL_REG (   x)    ((x) * 0x40 + 0x0c)

Definition at line 1176 of file bcm63xx_regs.h.

#define M2M_CTRL_SWAPBYTE_MASK   (1 << 10)

Definition at line 1183 of file bcm63xx_regs.h.

#define M2M_DST_REG (   x)    ((x) * 0x40 + 0x04)

Definition at line 1173 of file bcm63xx_regs.h.

#define M2M_DSTID_REG (   x)    ((x) * 0x40 + 0x18)

Definition at line 1191 of file bcm63xx_regs.h.

#define M2M_RX   0

Definition at line 1169 of file bcm63xx_regs.h.

#define M2M_SIZE_REG (   x)    ((x) * 0x40 + 0x08)

Definition at line 1174 of file bcm63xx_regs.h.

#define M2M_SRC_REG (   x)    ((x) * 0x40 + 0x00)

Definition at line 1172 of file bcm63xx_regs.h.

#define M2M_SRCID_REG (   x)    ((x) * 0x40 + 0x14)

Definition at line 1190 of file bcm63xx_regs.h.

#define M2M_STAT_DONE   (1 << 0)

Definition at line 1187 of file bcm63xx_regs.h.

#define M2M_STAT_ERROR   (1 << 1)

Definition at line 1188 of file bcm63xx_regs.h.

#define M2M_STAT_REG (   x)    ((x) * 0x40 + 0x10)

Definition at line 1186 of file bcm63xx_regs.h.

#define M2M_TX   1

Definition at line 1170 of file bcm63xx_regs.h.

#define MEMC_CFG_32B_MASK   (1 << MEMC_CFG_32B_SHIFT)

Definition at line 1131 of file bcm63xx_regs.h.

#define MEMC_CFG_32B_SHIFT   1

Definition at line 1130 of file bcm63xx_regs.h.

#define MEMC_CFG_COL_MASK   (0x3 << MEMC_CFG_COL_SHIFT)

Definition at line 1133 of file bcm63xx_regs.h.

#define MEMC_CFG_COL_SHIFT   3

Definition at line 1132 of file bcm63xx_regs.h.

#define MEMC_CFG_REG   0x4

Definition at line 1129 of file bcm63xx_regs.h.

#define MEMC_CFG_ROW_MASK   (0x3 << MEMC_CFG_ROW_SHIFT)

Definition at line 1135 of file bcm63xx_regs.h.

#define MEMC_CFG_ROW_SHIFT   6

Definition at line 1134 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1BUS_MASK   (0x7 << MIPSPLLCTL_M1BUS_SHIFT)

Definition at line 269 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1BUS_SHIFT   3

Definition at line 268 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1CPU_MASK   (0x7 << MIPSPLLCTL_M1CPU_SHIFT)

Definition at line 267 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1CPU_SHIFT   6

Definition at line 266 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1REF_MASK   (0x7 << MIPSPLLCTL_M1REF_SHIFT)

Definition at line 263 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M1REF_SHIFT   12

Definition at line 262 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M2BUS_MASK   (0x7 << MIPSPLLCTL_M2BUS_SHIFT)

Definition at line 271 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M2BUS_SHIFT   0

Definition at line 270 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M2REF_MASK   (0x7 << MIPSPLLCTL_M2REF_SHIFT)

Definition at line 265 of file bcm63xx_regs.h.

#define MIPSPLLCTL_M2REF_SHIFT   9

Definition at line 264 of file bcm63xx_regs.h.

#define MIPSPLLCTL_N1_MASK   (0x7 << MIPSPLLCTL_N1_SHIFT)

Definition at line 259 of file bcm63xx_regs.h.

#define MIPSPLLCTL_N1_SHIFT   20

Definition at line 258 of file bcm63xx_regs.h.

#define MIPSPLLCTL_N2_MASK   (0x1f << MIPSPLLCTL_N2_SHIFT)

Definition at line 261 of file bcm63xx_regs.h.

#define MIPSPLLCTL_N2_SHIFT   15

Definition at line 260 of file bcm63xx_regs.h.

#define MISC_SERDES_CTRL_REG   0x0

Definition at line 1336 of file bcm63xx_regs.h.

#define MISC_STRAPBUS_6328_REG   0x240

Definition at line 1340 of file bcm63xx_regs.h.

#define MPI_CS_PCMCIA_ATTR   5

Definition at line 961 of file bcm63xx_regs.h.

#define MPI_CS_PCMCIA_COMMON   4

Definition at line 960 of file bcm63xx_regs.h.

#define MPI_CS_PCMCIA_IO   6

Definition at line 962 of file bcm63xx_regs.h.

#define MPI_CSBASE_BASE_MASK   (0x1ffff << MPI_CSBASE_BASE_SHIFT)

Definition at line 967 of file bcm63xx_regs.h.

#define MPI_CSBASE_BASE_SHIFT   13

Definition at line 966 of file bcm63xx_regs.h.

#define MPI_CSBASE_REG (   x)    (0x0 + (x) * 8)

Definition at line 965 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_128K   4

Definition at line 975 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_128M   14

Definition at line 985 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_16K   1

Definition at line 972 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_16M   11

Definition at line 982 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_1M   7

Definition at line 978 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_256K   5

Definition at line 976 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_256M   15

Definition at line 986 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_2M   8

Definition at line 979 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_32K   2

Definition at line 973 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_32M   12

Definition at line 983 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_4M   9

Definition at line 980 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_512K   6

Definition at line 977 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_64K   3

Definition at line 974 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_64M   13

Definition at line 984 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_8K   0

Definition at line 971 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_8M   10

Definition at line 981 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_MASK   (0xf << MPI_CSBASE_SIZE_SHIFT)

Definition at line 969 of file bcm63xx_regs.h.

#define MPI_CSBASE_SIZE_SHIFT   0

Definition at line 968 of file bcm63xx_regs.h.

#define MPI_CSCTL_DATA16_MASK   (1 << 4)

Definition at line 993 of file bcm63xx_regs.h.

#define MPI_CSCTL_ENABLE_MASK   (1 << 0)

Definition at line 990 of file bcm63xx_regs.h.

#define MPI_CSCTL_ENDIANSWAP_MASK   (1 << 10)

Definition at line 996 of file bcm63xx_regs.h.

#define MPI_CSCTL_HOLD_MASK   (0xf << MPI_CSCTL_HOLD_SHIFT)

Definition at line 1000 of file bcm63xx_regs.h.

#define MPI_CSCTL_HOLD_SHIFT   20

Definition at line 999 of file bcm63xx_regs.h.

#define MPI_CSCTL_REG (   x)    (0x4 + (x) * 8)

Definition at line 989 of file bcm63xx_regs.h.

#define MPI_CSCTL_SETUP_MASK   (0xf << MPI_CSCTL_SETUP_SHIFT)

Definition at line 998 of file bcm63xx_regs.h.

#define MPI_CSCTL_SETUP_SHIFT   16

Definition at line 997 of file bcm63xx_regs.h.

#define MPI_CSCTL_SYNCMODE_MASK   (1 << 7)

Definition at line 994 of file bcm63xx_regs.h.

#define MPI_CSCTL_TSIZE_MASK   (1 << 8)

Definition at line 995 of file bcm63xx_regs.h.

#define MPI_CSCTL_WAIT_MASK   (0x7 << MPI_CSCTL_WAIT_SHIFT)

Definition at line 992 of file bcm63xx_regs.h.

#define MPI_CSCTL_WAIT_SHIFT   1

Definition at line 991 of file bcm63xx_regs.h.

#define MPI_L2P_BASE_MASK   (0xffff8000)

Definition at line 1031 of file bcm63xx_regs.h.

#define MPI_L2PCFG_CFG_SEL_MASK   (1 << 31)

Definition at line 1020 of file bcm63xx_regs.h.

#define MPI_L2PCFG_CFG_TYPE_MASK   (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)

Definition at line 1012 of file bcm63xx_regs.h.

#define MPI_L2PCFG_CFG_TYPE_SHIFT   0

Definition at line 1011 of file bcm63xx_regs.h.

#define MPI_L2PCFG_CFG_USEREG_MASK   (1 << 30)

Definition at line 1019 of file bcm63xx_regs.h.

#define MPI_L2PCFG_DEVNUM_MASK   (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)

Definition at line 1018 of file bcm63xx_regs.h.

#define MPI_L2PCFG_DEVNUM_SHIFT   11

Definition at line 1017 of file bcm63xx_regs.h.

#define MPI_L2PCFG_FUNC_MASK   (0x7 << MPI_L2PCFG_FUNC_SHIFT)

Definition at line 1016 of file bcm63xx_regs.h.

#define MPI_L2PCFG_FUNC_SHIFT   8

Definition at line 1015 of file bcm63xx_regs.h.

#define MPI_L2PCFG_REG   0x11C

Definition at line 1010 of file bcm63xx_regs.h.

#define MPI_L2PCFG_REG_MASK   (0x3f << MPI_L2PCFG_REG_SHIFT)

Definition at line 1014 of file bcm63xx_regs.h.

#define MPI_L2PCFG_REG_SHIFT   2

Definition at line 1013 of file bcm63xx_regs.h.

#define MPI_L2PIOBASE_REG   0x13C

Definition at line 1029 of file bcm63xx_regs.h.

#define MPI_L2PIORANGE_REG   0x138

Definition at line 1028 of file bcm63xx_regs.h.

#define MPI_L2PIOREMAP_REG   0x140

Definition at line 1030 of file bcm63xx_regs.h.

#define MPI_L2PMEMBASE1_REG   0x124

Definition at line 1023 of file bcm63xx_regs.h.

#define MPI_L2PMEMBASE2_REG   0x130

Definition at line 1026 of file bcm63xx_regs.h.

#define MPI_L2PMEMRANGE1_REG   0x120

Definition at line 1022 of file bcm63xx_regs.h.

#define MPI_L2PMEMRANGE2_REG   0x12C

Definition at line 1025 of file bcm63xx_regs.h.

#define MPI_L2PMEMREMAP1_REG   0x128

Definition at line 1024 of file bcm63xx_regs.h.

#define MPI_L2PMEMREMAP2_REG   0x134

Definition at line 1027 of file bcm63xx_regs.h.

#define MPI_L2PREMAP_ENABLED_MASK   (1 << 0)

Definition at line 1032 of file bcm63xx_regs.h.

#define MPI_L2PREMAP_IS_CARDBUS_MASK   (1 << 2)

Definition at line 1033 of file bcm63xx_regs.h.

#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK   (1 << 0)

Definition at line 1043 of file bcm63xx_regs.h.

#define MPI_LOCBUSCTL_REG   0x14C

Definition at line 1042 of file bcm63xx_regs.h.

#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)

Definition at line 1044 of file bcm63xx_regs.h.

#define MPI_LOCINT_CSERR   9

Definition at line 1052 of file bcm63xx_regs.h.

#define MPI_LOCINT_DIR_FAILED   6

Definition at line 1049 of file bcm63xx_regs.h.

#define MPI_LOCINT_EXT_PCI_INT   7

Definition at line 1050 of file bcm63xx_regs.h.

#define MPI_LOCINT_MASK (   x)    (1 << (x + 16))

Definition at line 1047 of file bcm63xx_regs.h.

#define MPI_LOCINT_REG   0x150

Definition at line 1046 of file bcm63xx_regs.h.

#define MPI_LOCINT_SERR   8

Definition at line 1051 of file bcm63xx_regs.h.

#define MPI_LOCINT_STAT (   x)    (1 << (x))

Definition at line 1048 of file bcm63xx_regs.h.

#define MPI_PCICFGCTL_CFGADDR_MASK   (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)

Definition at line 1056 of file bcm63xx_regs.h.

#define MPI_PCICFGCTL_CFGADDR_SHIFT   2

Definition at line 1055 of file bcm63xx_regs.h.

#define MPI_PCICFGCTL_REG   0x178

Definition at line 1054 of file bcm63xx_regs.h.

#define MPI_PCICFGCTL_WRITEEN_MASK   (1 << 7)

Definition at line 1057 of file bcm63xx_regs.h.

#define MPI_PCICFGDATA_REG   0x17C

Definition at line 1059 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK   (1 << 0)

Definition at line 1036 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK   (1 << 1)

Definition at line 1037 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_EXT_ARB_MASK   (1 << 2)

Definition at line 1038 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_PREFETCH_MASK   (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)

Definition at line 1040 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_PREFETCH_SHIFT   4

Definition at line 1039 of file bcm63xx_regs.h.

#define MPI_PCIMODESEL_REG   0x144

Definition at line 1035 of file bcm63xx_regs.h.

#define MPI_SP0_RANGE_REG   0x100

Definition at line 1003 of file bcm63xx_regs.h.

#define MPI_SP0_REMAP_ENABLE_MASK   (1 << 0)

Definition at line 1005 of file bcm63xx_regs.h.

#define MPI_SP0_REMAP_REG   0x104

Definition at line 1004 of file bcm63xx_regs.h.

#define MPI_SP1_RANGE_REG   0x10C

Definition at line 1006 of file bcm63xx_regs.h.

#define MPI_SP1_REMAP_ENABLE_MASK   (1 << 0)

Definition at line 1008 of file bcm63xx_regs.h.

#define MPI_SP1_REMAP_REG   0x110

Definition at line 1007 of file bcm63xx_regs.h.

#define OHCI_PRIV_PORT1_HOST_MASK   (1 << OHCI_PRIV_PORT1_HOST_SHIFT)

Definition at line 776 of file bcm63xx_regs.h.

#define OHCI_PRIV_PORT1_HOST_SHIFT   0

Definition at line 775 of file bcm63xx_regs.h.

#define OHCI_PRIV_REG   0x0

Definition at line 774 of file bcm63xx_regs.h.

#define OHCI_PRIV_REG_SWAP_MASK   (1 << OHCI_PRIV_REG_SWAP_SHIFT)

Definition at line 778 of file bcm63xx_regs.h.

#define OHCI_PRIV_REG_SWAP_SHIFT   3

Definition at line 777 of file bcm63xx_regs.h.

#define OPT1_L1_INT_STATUS_MASK_POL   (1 << 12)

Definition at line 1366 of file bcm63xx_regs.h.

#define OPT1_PCIE_BRIDGE_HOLE_DET_EN   (1 << 11)

Definition at line 1365 of file bcm63xx_regs.h.

#define OPT1_RD_BE_OPT_EN   (1 << 7)

Definition at line 1363 of file bcm63xx_regs.h.

#define OPT1_RD_REPLY_BE_FIX_EN   (1 << 9)

Definition at line 1364 of file bcm63xx_regs.h.

#define OPT2_CFG_TYPE1_BD_SEL   (1 << 7)

Definition at line 1371 of file bcm63xx_regs.h.

#define OPT2_CFG_TYPE1_BUS_NO_MASK   (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)

Definition at line 1373 of file bcm63xx_regs.h.

#define OPT2_CFG_TYPE1_BUS_NO_SHIFT   16

Definition at line 1372 of file bcm63xx_regs.h.

#define OPT2_TX_CREDIT_CHK_EN   (1 << 4)

Definition at line 1370 of file bcm63xx_regs.h.

#define OPT2_UBUS_UR_DECODE_DIS   (1 << 2)

Definition at line 1369 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828

Definition at line 1375 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG   0x282c

Definition at line 1384 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830

Definition at line 1376 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG   0x2834

Definition at line 1385 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_OPT1_REG   0x2820

Definition at line 1362 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_OPT2_REG   0x2824

Definition at line 1368 of file bcm63xx_regs.h.

#define PCIE_BRIDGE_RC_INT_MASK_REG   0x2854

Definition at line 1389 of file bcm63xx_regs.h.

#define PCIE_CONFIG2_REG   0x408

Definition at line 1350 of file bcm63xx_regs.h.

#define PCIE_DEVICE_OFFSET   0x8000

Definition at line 1395 of file bcm63xx_regs.h.

#define PCIE_DLSTATUS_REG   0x1048

Definition at line 1359 of file bcm63xx_regs.h.

#define PCIE_IDVAL3_REG   0x43c

Definition at line 1354 of file bcm63xx_regs.h.

#define PCIE_RC_INT_A   (1 << 0)

Definition at line 1390 of file bcm63xx_regs.h.

#define PCIE_RC_INT_B   (1 << 1)

Definition at line 1391 of file bcm63xx_regs.h.

#define PCIE_RC_INT_C   (1 << 2)

Definition at line 1392 of file bcm63xx_regs.h.

#define PCIE_RC_INT_D   (1 << 3)

Definition at line 1393 of file bcm63xx_regs.h.

#define PCMCIA_C1_CBIDSEL_MASK   (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)

Definition at line 1081 of file bcm63xx_regs.h.

#define PCMCIA_C1_CBIDSEL_SHIFT   (8)

Definition at line 1080 of file bcm63xx_regs.h.

#define PCMCIA_C1_CD1_MASK   (1 << 0)

Definition at line 1074 of file bcm63xx_regs.h.

#define PCMCIA_C1_CD2_MASK   (1 << 1)

Definition at line 1075 of file bcm63xx_regs.h.

#define PCMCIA_C1_EN_CARDBUS_MASK   (1 << 15)

Definition at line 1084 of file bcm63xx_regs.h.

#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)

Definition at line 1082 of file bcm63xx_regs.h.

#define PCMCIA_C1_EN_PCMCIA_MASK   (1 << 14)

Definition at line 1083 of file bcm63xx_regs.h.

#define PCMCIA_C1_REG   0x0

Definition at line 1073 of file bcm63xx_regs.h.

#define PCMCIA_C1_RESET_MASK   (1 << 18)

Definition at line 1085 of file bcm63xx_regs.h.

#define PCMCIA_C1_VS1_MASK   (1 << 2)

Definition at line 1076 of file bcm63xx_regs.h.

#define PCMCIA_C1_VS1OE_MASK   (1 << 6)

Definition at line 1078 of file bcm63xx_regs.h.

#define PCMCIA_C1_VS2_MASK   (1 << 3)

Definition at line 1077 of file bcm63xx_regs.h.

#define PCMCIA_C1_VS2OE_MASK   (1 << 7)

Definition at line 1079 of file bcm63xx_regs.h.

#define PCMCIA_C2_BYTESWAP_MASK   (1 << 1)

Definition at line 1089 of file bcm63xx_regs.h.

#define PCMCIA_C2_DATA16_MASK   (1 << 0)

Definition at line 1088 of file bcm63xx_regs.h.

#define PCMCIA_C2_HOLD_MASK   (0x3f << PCMCIA_C2_HOLD_SHIFT)

Definition at line 1097 of file bcm63xx_regs.h.

#define PCMCIA_C2_HOLD_SHIFT   24

Definition at line 1096 of file bcm63xx_regs.h.

#define PCMCIA_C2_INACTIVE_MASK   (0x3f << PCMCIA_C2_INACTIVE_SHIFT)

Definition at line 1093 of file bcm63xx_regs.h.

#define PCMCIA_C2_INACTIVE_SHIFT   8

Definition at line 1092 of file bcm63xx_regs.h.

#define PCMCIA_C2_REG   0x8

Definition at line 1087 of file bcm63xx_regs.h.

#define PCMCIA_C2_RWCOUNT_MASK   (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)

Definition at line 1091 of file bcm63xx_regs.h.

#define PCMCIA_C2_RWCOUNT_SHIFT   2

Definition at line 1090 of file bcm63xx_regs.h.

#define PCMCIA_C2_SETUP_MASK   (0x3f << PCMCIA_C2_SETUP_SHIFT)

Definition at line 1095 of file bcm63xx_regs.h.

#define PCMCIA_C2_SETUP_SHIFT   16

Definition at line 1094 of file bcm63xx_regs.h.

#define PERF_ADSLPLLCTL_REG   0x38

Definition at line 274 of file bcm63xx_regs.h.

#define PERF_CKCTL_REG   0x4

Definition at line 16 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG2_6368   0x1c

Definition at line 169 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6328   0x18

Definition at line 162 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6338   0x14

Definition at line 163 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6345   0x14

Definition at line 164 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6348   0x14

Definition at line 165 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6358   0x14

Definition at line 166 of file bcm63xx_regs.h.

#define PERF_EXTIRQ_CFG_REG_6368   0x18

Definition at line 167 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6328_REG   0x20

Definition at line 146 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6338_REG   0xc

Definition at line 147 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6345_REG   0xc

Definition at line 148 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6348_REG   0xc

Definition at line 149 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6358_REG   0xc

Definition at line 150 of file bcm63xx_regs.h.

#define PERF_IRQMASK_6368_REG   0x20

Definition at line 151 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6328_REG   0x28

Definition at line 154 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6338_REG   0x10

Definition at line 155 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6345_REG   0x10

Definition at line 156 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6348_REG   0x10

Definition at line 157 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6358_REG   0x10

Definition at line 158 of file bcm63xx_regs.h.

#define PERF_IRQSTAT_6368_REG   0x28

Definition at line 159 of file bcm63xx_regs.h.

#define PERF_MIPSPLLCTL_REG   0x34

Definition at line 257 of file bcm63xx_regs.h.

#define PERF_REV_REG   0x0

Definition at line 9 of file bcm63xx_regs.h.

#define PERF_SOFTRESET_6328_REG   0x10

Definition at line 193 of file bcm63xx_regs.h.

#define PERF_SOFTRESET_6368_REG   0x10

Definition at line 194 of file bcm63xx_regs.h.

#define PERF_SOFTRESET_REG   0x28

Definition at line 192 of file bcm63xx_regs.h.

#define PERF_SYS_PLL_CTL_REG   0x8

Definition at line 142 of file bcm63xx_regs.h.

#define REBASE_ADDR_BASE_MASK   (0xfff << REBASE_ADDR_BASE_SHIFT)

Definition at line 1387 of file bcm63xx_regs.h.

#define REBASE_ADDR_BASE_SHIFT   20

Definition at line 1386 of file bcm63xx_regs.h.

#define REG_TIMER_RETRY_MASK   (0xff << REG_TIMER_RETRY_SHIFT)

Definition at line 1066 of file bcm63xx_regs.h.

#define REG_TIMER_RETRY_SHIFT   8

Definition at line 1065 of file bcm63xx_regs.h.

#define REG_TIMER_TRDY_MASK   (0xff << REG_TIMER_TRDY_SHIFT)

Definition at line 1064 of file bcm63xx_regs.h.

#define REG_TIMER_TRDY_SHIFT   0

Definition at line 1063 of file bcm63xx_regs.h.

#define REV_CHIPID_MASK   (0xffff << REV_CHIPID_SHIFT)

Definition at line 11 of file bcm63xx_regs.h.

#define REV_CHIPID_SHIFT   16

Definition at line 10 of file bcm63xx_regs.h.

#define REV_REVID_MASK   (0xffff << REV_REVID_SHIFT)

Definition at line 13 of file bcm63xx_regs.h.

#define REV_REVID_SHIFT   0

Definition at line 12 of file bcm63xx_regs.h.

#define RNG_AVAIL_MASK   (0xff000000)

Definition at line 1201 of file bcm63xx_regs.h.

#define RNG_CTRL   0x00

Definition at line 1197 of file bcm63xx_regs.h.

#define RNG_DATA   0x08

Definition at line 1203 of file bcm63xx_regs.h.

#define RNG_EN   (1 << 0)

Definition at line 1198 of file bcm63xx_regs.h.

#define RNG_MASK   0x10

Definition at line 1205 of file bcm63xx_regs.h.

#define RNG_STAT   0x04

Definition at line 1200 of file bcm63xx_regs.h.

#define RNG_THRES   0x0c

Definition at line 1204 of file bcm63xx_regs.h.

#define SDRAM_CFG_32B_MASK   (1 << SDRAM_CFG_32B_SHIFT)

Definition at line 1110 of file bcm63xx_regs.h.

#define SDRAM_CFG_32B_SHIFT   10

Definition at line 1109 of file bcm63xx_regs.h.

#define SDRAM_CFG_BANK_MASK   (1 << SDRAM_CFG_BANK_SHIFT)

Definition at line 1112 of file bcm63xx_regs.h.

#define SDRAM_CFG_BANK_SHIFT   13

Definition at line 1111 of file bcm63xx_regs.h.

#define SDRAM_CFG_COL_MASK   (0x3 << SDRAM_CFG_COL_SHIFT)

Definition at line 1108 of file bcm63xx_regs.h.

#define SDRAM_CFG_COL_SHIFT   6

Definition at line 1107 of file bcm63xx_regs.h.

#define SDRAM_CFG_REG   0x0

Definition at line 1104 of file bcm63xx_regs.h.

#define SDRAM_CFG_ROW_MASK   (0x3 << SDRAM_CFG_ROW_SHIFT)

Definition at line 1106 of file bcm63xx_regs.h.

#define SDRAM_CFG_ROW_SHIFT   4

Definition at line 1105 of file bcm63xx_regs.h.

#define SDRAM_MBASE_REG   0xc

Definition at line 1114 of file bcm63xx_regs.h.

#define SDRAM_PRIO_ADSL_MASK   (1 << SDRAM_PRIO_ADSL_SHIFT)

Definition at line 1120 of file bcm63xx_regs.h.

#define SDRAM_PRIO_ADSL_SHIFT   30

Definition at line 1119 of file bcm63xx_regs.h.

#define SDRAM_PRIO_EN_MASK   (1 << SDRAM_PRIO_EN_SHIFT)

Definition at line 1122 of file bcm63xx_regs.h.

#define SDRAM_PRIO_EN_SHIFT   31

Definition at line 1121 of file bcm63xx_regs.h.

#define SDRAM_PRIO_MIPS_MASK   (1 << SDRAM_PRIO_MIPS_SHIFT)

Definition at line 1118 of file bcm63xx_regs.h.

#define SDRAM_PRIO_MIPS_SHIFT   29

Definition at line 1117 of file bcm63xx_regs.h.

#define SDRAM_PRIO_REG   0x2C

Definition at line 1116 of file bcm63xx_regs.h.

#define SERDES_PCIE_EN   (1 << 0)

Definition at line 1337 of file bcm63xx_regs.h.

#define SERDES_PCIE_EXD_EN   (1 << 15)

Definition at line 1338 of file bcm63xx_regs.h.

#define SOFTRESET_6328_ENETSW_MASK   (1 << 3)

Definition at line 199 of file bcm63xx_regs.h.

#define SOFTRESET_6328_EPHY_MASK   (1 << 1)

Definition at line 197 of file bcm63xx_regs.h.

#define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)

Definition at line 203 of file bcm63xx_regs.h.

#define SOFTRESET_6328_PCIE_EXT_MASK   (1 << 9)

Definition at line 205 of file bcm63xx_regs.h.

#define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)

Definition at line 206 of file bcm63xx_regs.h.

#define SOFTRESET_6328_PCIE_MASK   (1 << 8)

Definition at line 204 of file bcm63xx_regs.h.

#define SOFTRESET_6328_PCM_MASK   (1 << 6)

Definition at line 202 of file bcm63xx_regs.h.

#define SOFTRESET_6328_SAR_MASK   (1 << 2)

Definition at line 198 of file bcm63xx_regs.h.

#define SOFTRESET_6328_SPI_MASK   (1 << 0)

Definition at line 196 of file bcm63xx_regs.h.

#define SOFTRESET_6328_USBH_MASK   (1 << 5)

Definition at line 201 of file bcm63xx_regs.h.

#define SOFTRESET_6328_USBS_MASK   (1 << 4)

Definition at line 200 of file bcm63xx_regs.h.

#define SOFTRESET_6338_ACLC_MASK   (1 << 8)

Definition at line 215 of file bcm63xx_regs.h.

#define SOFTRESET_6338_ADSL_MASK   (1 << 5)

Definition at line 212 of file bcm63xx_regs.h.

#define SOFTRESET_6338_ADSLMIPSPLL_MASK   (1 << 10)

Definition at line 216 of file bcm63xx_regs.h.

#define SOFTRESET_6338_ALL
Value:
(SOFTRESET_6338_SPI_MASK | \
SOFTRESET_6338_ENET_MASK | \
SOFTRESET_6338_USBH_MASK | \
SOFTRESET_6338_USBS_MASK | \
SOFTRESET_6338_ADSL_MASK | \
SOFTRESET_6338_DMAMEM_MASK | \
SOFTRESET_6338_SAR_MASK | \
SOFTRESET_6338_ACLC_MASK | \
SOFTRESET_6338_ADSLMIPSPLL_MASK)

Definition at line 217 of file bcm63xx_regs.h.

#define SOFTRESET_6338_DMAMEM_MASK   (1 << 6)

Definition at line 213 of file bcm63xx_regs.h.

#define SOFTRESET_6338_ENET_MASK   (1 << 2)

Definition at line 209 of file bcm63xx_regs.h.

#define SOFTRESET_6338_SAR_MASK   (1 << 7)

Definition at line 214 of file bcm63xx_regs.h.

#define SOFTRESET_6338_SPI_MASK   (1 << 0)

Definition at line 208 of file bcm63xx_regs.h.

#define SOFTRESET_6338_USBH_MASK   (1 << 3)

Definition at line 210 of file bcm63xx_regs.h.

#define SOFTRESET_6338_USBS_MASK   (1 << 4)

Definition at line 211 of file bcm63xx_regs.h.

#define SOFTRESET_6348_ACLC_MASK   (1 << 8)

Definition at line 234 of file bcm63xx_regs.h.

#define SOFTRESET_6348_ADSL_MASK   (1 << 5)

Definition at line 231 of file bcm63xx_regs.h.

#define SOFTRESET_6348_ADSLMIPSPLL_MASK   (1 << 10)

Definition at line 235 of file bcm63xx_regs.h.

#define SOFTRESET_6348_ALL
Value:
(SOFTRESET_6348_SPI_MASK | \
SOFTRESET_6348_ENET_MASK | \
SOFTRESET_6348_USBH_MASK | \
SOFTRESET_6348_USBS_MASK | \
SOFTRESET_6348_ADSL_MASK | \
SOFTRESET_6348_DMAMEM_MASK | \
SOFTRESET_6348_SAR_MASK | \
SOFTRESET_6348_ACLC_MASK | \
SOFTRESET_6348_ADSLMIPSPLL_MASK)

Definition at line 237 of file bcm63xx_regs.h.

#define SOFTRESET_6348_DMAMEM_MASK   (1 << 6)

Definition at line 232 of file bcm63xx_regs.h.

#define SOFTRESET_6348_ENET_MASK   (1 << 2)

Definition at line 228 of file bcm63xx_regs.h.

#define SOFTRESET_6348_SAR_MASK   (1 << 7)

Definition at line 233 of file bcm63xx_regs.h.

#define SOFTRESET_6348_SPI_MASK   (1 << 0)

Definition at line 227 of file bcm63xx_regs.h.

#define SOFTRESET_6348_USBH_MASK   (1 << 3)

Definition at line 229 of file bcm63xx_regs.h.

#define SOFTRESET_6348_USBS_MASK   (1 << 4)

Definition at line 230 of file bcm63xx_regs.h.

#define SOFTRESET_6368_ENETSW_MASK   (1 << 10)

Definition at line 251 of file bcm63xx_regs.h.

#define SOFTRESET_6368_EPHY_MASK   (1 << 6)

Definition at line 249 of file bcm63xx_regs.h.

#define SOFTRESET_6368_MPI_MASK   (1 << 3)

Definition at line 248 of file bcm63xx_regs.h.

#define SOFTRESET_6368_PCM_MASK   (1 << 13)

Definition at line 254 of file bcm63xx_regs.h.

#define SOFTRESET_6368_SAR_MASK   (1 << 7)

Definition at line 250 of file bcm63xx_regs.h.

#define SOFTRESET_6368_SPI_MASK   (1 << 0)

Definition at line 247 of file bcm63xx_regs.h.

#define SOFTRESET_6368_USBH_MASK   (1 << 12)

Definition at line 253 of file bcm63xx_regs.h.

#define SOFTRESET_6368_USBS_MASK   (1 << 11)

Definition at line 252 of file bcm63xx_regs.h.

#define SPI_6338_CLK_CFG   0x06

Definition at line 1217 of file bcm63xx_regs.h.

#define SPI_6338_CMD   0x00 /* 16-bits register */

Definition at line 1212 of file bcm63xx_regs.h.

#define SPI_6338_FILL_BYTE   0x07

Definition at line 1218 of file bcm63xx_regs.h.

#define SPI_6338_INT_MASK   0x04

Definition at line 1215 of file bcm63xx_regs.h.

#define SPI_6338_INT_MASK_ST   0x03

Definition at line 1214 of file bcm63xx_regs.h.

#define SPI_6338_INT_STATUS   0x02

Definition at line 1213 of file bcm63xx_regs.h.

#define SPI_6338_MSG_CTL   0x40 /* 8-bits register */

Definition at line 1221 of file bcm63xx_regs.h.

#define SPI_6338_MSG_CTL_WIDTH   8

Definition at line 1222 of file bcm63xx_regs.h.

#define SPI_6338_MSG_DATA   0x41

Definition at line 1223 of file bcm63xx_regs.h.

#define SPI_6338_MSG_DATA_SIZE   0x3f

Definition at line 1224 of file bcm63xx_regs.h.

#define SPI_6338_MSG_TAIL   0x09

Definition at line 1219 of file bcm63xx_regs.h.

#define SPI_6338_MSG_TYPE_SHIFT   6

Definition at line 1286 of file bcm63xx_regs.h.

#define SPI_6338_RX_DATA   0x80

Definition at line 1225 of file bcm63xx_regs.h.

#define SPI_6338_RX_DATA_SIZE   0x3f

Definition at line 1226 of file bcm63xx_regs.h.

#define SPI_6338_RX_TAIL   0x0b

Definition at line 1220 of file bcm63xx_regs.h.

#define SPI_6338_ST   0x05

Definition at line 1216 of file bcm63xx_regs.h.

#define SPI_6348_CLK_CFG   0x06

Definition at line 1234 of file bcm63xx_regs.h.

#define SPI_6348_CMD   0x00 /* 16-bits register */

Definition at line 1229 of file bcm63xx_regs.h.

#define SPI_6348_FILL_BYTE   0x07

Definition at line 1235 of file bcm63xx_regs.h.

#define SPI_6348_INT_MASK   0x04

Definition at line 1232 of file bcm63xx_regs.h.

#define SPI_6348_INT_MASK_ST   0x03

Definition at line 1231 of file bcm63xx_regs.h.

#define SPI_6348_INT_STATUS   0x02

Definition at line 1230 of file bcm63xx_regs.h.

#define SPI_6348_MSG_CTL   0x40 /* 8-bits register */

Definition at line 1238 of file bcm63xx_regs.h.

#define SPI_6348_MSG_CTL_WIDTH   8

Definition at line 1239 of file bcm63xx_regs.h.

#define SPI_6348_MSG_DATA   0x41

Definition at line 1240 of file bcm63xx_regs.h.

#define SPI_6348_MSG_DATA_SIZE   0x3f

Definition at line 1241 of file bcm63xx_regs.h.

#define SPI_6348_MSG_TAIL   0x09

Definition at line 1236 of file bcm63xx_regs.h.

#define SPI_6348_MSG_TYPE_SHIFT   6

Definition at line 1287 of file bcm63xx_regs.h.

#define SPI_6348_RX_DATA   0x80

Definition at line 1242 of file bcm63xx_regs.h.

#define SPI_6348_RX_DATA_SIZE   0x3f

Definition at line 1243 of file bcm63xx_regs.h.

#define SPI_6348_RX_TAIL   0x0b

Definition at line 1237 of file bcm63xx_regs.h.

#define SPI_6348_ST   0x05

Definition at line 1233 of file bcm63xx_regs.h.

#define SPI_6358_CLK_CFG   0x706

Definition at line 1257 of file bcm63xx_regs.h.

#define SPI_6358_CMD   0x700 /* 16-bits register */

Definition at line 1252 of file bcm63xx_regs.h.

#define SPI_6358_FILL_BYTE   0x707

Definition at line 1258 of file bcm63xx_regs.h.

#define SPI_6358_INT_MASK   0x704

Definition at line 1255 of file bcm63xx_regs.h.

#define SPI_6358_INT_MASK_ST   0x703

Definition at line 1254 of file bcm63xx_regs.h.

#define SPI_6358_INT_STATUS   0x702

Definition at line 1253 of file bcm63xx_regs.h.

#define SPI_6358_MSG_CTL   0x00 /* 16-bits register */

Definition at line 1246 of file bcm63xx_regs.h.

#define SPI_6358_MSG_CTL_WIDTH   16

Definition at line 1247 of file bcm63xx_regs.h.

#define SPI_6358_MSG_DATA   0x02

Definition at line 1248 of file bcm63xx_regs.h.

#define SPI_6358_MSG_DATA_SIZE   0x21e

Definition at line 1249 of file bcm63xx_regs.h.

#define SPI_6358_MSG_TAIL   0x709

Definition at line 1259 of file bcm63xx_regs.h.

#define SPI_6358_MSG_TYPE_SHIFT   14

Definition at line 1288 of file bcm63xx_regs.h.

#define SPI_6358_RX_DATA   0x400

Definition at line 1250 of file bcm63xx_regs.h.

#define SPI_6358_RX_DATA_SIZE   0x220

Definition at line 1251 of file bcm63xx_regs.h.

#define SPI_6358_RX_TAIL   0x70B

Definition at line 1260 of file bcm63xx_regs.h.

#define SPI_6358_ST   0x705

Definition at line 1256 of file bcm63xx_regs.h.

#define SPI_6368_CLK_CFG   0x706

Definition at line 1274 of file bcm63xx_regs.h.

#define SPI_6368_CMD   0x700 /* 16-bits register */

Definition at line 1269 of file bcm63xx_regs.h.

#define SPI_6368_FILL_BYTE   0x707

Definition at line 1275 of file bcm63xx_regs.h.

#define SPI_6368_INT_MASK   0x704

Definition at line 1272 of file bcm63xx_regs.h.

#define SPI_6368_INT_MASK_ST   0x703

Definition at line 1271 of file bcm63xx_regs.h.

#define SPI_6368_INT_STATUS   0x702

Definition at line 1270 of file bcm63xx_regs.h.

#define SPI_6368_MSG_CTL   0x00 /* 16-bits register */

Definition at line 1263 of file bcm63xx_regs.h.

#define SPI_6368_MSG_CTL_WIDTH   16

Definition at line 1264 of file bcm63xx_regs.h.

#define SPI_6368_MSG_DATA   0x02

Definition at line 1265 of file bcm63xx_regs.h.

#define SPI_6368_MSG_DATA_SIZE   0x21e

Definition at line 1266 of file bcm63xx_regs.h.

#define SPI_6368_MSG_TAIL   0x709

Definition at line 1276 of file bcm63xx_regs.h.

#define SPI_6368_MSG_TYPE_SHIFT   14

Definition at line 1289 of file bcm63xx_regs.h.

#define SPI_6368_RX_DATA   0x400

Definition at line 1267 of file bcm63xx_regs.h.

#define SPI_6368_RX_DATA_SIZE   0x220

Definition at line 1268 of file bcm63xx_regs.h.

#define SPI_6368_RX_TAIL   0x70B

Definition at line 1277 of file bcm63xx_regs.h.

#define SPI_6368_ST   0x705

Definition at line 1273 of file bcm63xx_regs.h.

#define SPI_BYTE_CNT_SHIFT   0

Definition at line 1285 of file bcm63xx_regs.h.

#define SPI_BYTE_SWAP   0x80

Definition at line 1331 of file bcm63xx_regs.h.

#define SPI_CLK_0_391MHZ   0x01

Definition at line 1322 of file bcm63xx_regs.h.

#define SPI_CLK_0_781MHZ   0x02 /* default */

Definition at line 1323 of file bcm63xx_regs.h.

#define SPI_CLK_12_50MHZ   0x06

Definition at line 1327 of file bcm63xx_regs.h.

#define SPI_CLK_1_563MHZ   0x03

Definition at line 1324 of file bcm63xx_regs.h.

#define SPI_CLK_20MHZ   0x00

Definition at line 1321 of file bcm63xx_regs.h.

#define SPI_CLK_3_125MHZ   0x04

Definition at line 1325 of file bcm63xx_regs.h.

#define SPI_CLK_6_250MHZ   0x05

Definition at line 1326 of file bcm63xx_regs.h.

#define SPI_CLK_MASK   0x07

Definition at line 1328 of file bcm63xx_regs.h.

#define SPI_CMD_BUSY   0x04

Definition at line 1317 of file bcm63xx_regs.h.

#define SPI_CMD_COMMAND_MASK   0x000f

Definition at line 1297 of file bcm63xx_regs.h.

#define SPI_CMD_COMMAND_SHIFT   0

Definition at line 1296 of file bcm63xx_regs.h.

#define SPI_CMD_DEVICE_ID_SHIFT   4

Definition at line 1298 of file bcm63xx_regs.h.

#define SPI_CMD_HARD_RESET   0x02

Definition at line 1294 of file bcm63xx_regs.h.

#define SPI_CMD_NOOP   0x00

Definition at line 1292 of file bcm63xx_regs.h.

#define SPI_CMD_ONE_BYTE_SHIFT   11

Definition at line 1300 of file bcm63xx_regs.h.

#define SPI_CMD_ONE_WIRE_SHIFT   12

Definition at line 1301 of file bcm63xx_regs.h.

#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT   8

Definition at line 1299 of file bcm63xx_regs.h.

#define SPI_CMD_SOFT_RESET   0x01

Definition at line 1293 of file bcm63xx_regs.h.

#define SPI_CMD_START_IMMEDIATE   0x03

Definition at line 1295 of file bcm63xx_regs.h.

#define SPI_DEV_ID_0   0

Definition at line 1302 of file bcm63xx_regs.h.

#define SPI_DEV_ID_1   1

Definition at line 1303 of file bcm63xx_regs.h.

#define SPI_DEV_ID_2   2

Definition at line 1304 of file bcm63xx_regs.h.

#define SPI_DEV_ID_3   3

Definition at line 1305 of file bcm63xx_regs.h.

#define SPI_FD_RW   0x00

Definition at line 1282 of file bcm63xx_regs.h.

#define SPI_HD_R   0x02

Definition at line 1284 of file bcm63xx_regs.h.

#define SPI_HD_W   0x01

Definition at line 1283 of file bcm63xx_regs.h.

#define SPI_INTR_CLEAR_ALL   0x1f

Definition at line 1313 of file bcm63xx_regs.h.

#define SPI_INTR_CMD_DONE   0x01

Definition at line 1308 of file bcm63xx_regs.h.

#define SPI_INTR_RX_OVERFLOW   0x02

Definition at line 1309 of file bcm63xx_regs.h.

#define SPI_INTR_RX_UNDERFLOW   0x10

Definition at line 1312 of file bcm63xx_regs.h.

#define SPI_INTR_TX_OVERFLOW   0x08

Definition at line 1311 of file bcm63xx_regs.h.

#define SPI_INTR_TX_UNDERFLOW   0x04

Definition at line 1310 of file bcm63xx_regs.h.

#define SPI_RX_EMPTY   0x02

Definition at line 1316 of file bcm63xx_regs.h.

#define SPI_SERIAL_BUSY   0x08

Definition at line 1318 of file bcm63xx_regs.h.

#define SPI_SSOFFTIME_MASK   0x38

Definition at line 1329 of file bcm63xx_regs.h.

#define SPI_SSOFFTIME_SHIFT   3

Definition at line 1330 of file bcm63xx_regs.h.

#define STRAPBUS_6328_BOOT_SEL_NAND   (0 << 28)

Definition at line 1344 of file bcm63xx_regs.h.

#define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 28)

Definition at line 1343 of file bcm63xx_regs.h.

#define STRAPBUS_6328_FCVO_MASK   (0x1f << STRAPBUS_6328_FCVO_SHIFT)

Definition at line 1342 of file bcm63xx_regs.h.

#define STRAPBUS_6328_FCVO_SHIFT   7

Definition at line 1341 of file bcm63xx_regs.h.

#define STRAPBUS_6358_BOOT_SEL_PARALLEL   (1 << 1)

Definition at line 560 of file bcm63xx_regs.h.

#define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)

Definition at line 561 of file bcm63xx_regs.h.

#define STRAPBUS_6368_BOOT_SEL_MASK   0x3

Definition at line 562 of file bcm63xx_regs.h.

#define STRAPBUS_6368_BOOT_SEL_NAND   0

Definition at line 563 of file bcm63xx_regs.h.

#define STRAPBUS_6368_BOOT_SEL_PARALLEL   3

Definition at line 565 of file bcm63xx_regs.h.

#define STRAPBUS_6368_BOOT_SEL_SERIAL   1

Definition at line 564 of file bcm63xx_regs.h.

#define SYS_PLL_SOFT_RESET   0x1

Definition at line 143 of file bcm63xx_regs.h.

#define TIMER_CTL0_REG   0x4

Definition at line 324 of file bcm63xx_regs.h.

#define TIMER_CTL1_REG   0x8

Definition at line 325 of file bcm63xx_regs.h.

#define TIMER_CTL2_REG   0xC

Definition at line 326 of file bcm63xx_regs.h.

#define TIMER_CTL_COUNTDOWN_MASK   (0x3fffffff)

Definition at line 327 of file bcm63xx_regs.h.

#define TIMER_CTL_ENABLE_MASK   (1 << 31)

Definition at line 329 of file bcm63xx_regs.h.

#define TIMER_CTL_MONOTONIC_MASK   (1 << 30)

Definition at line 328 of file bcm63xx_regs.h.

#define TIMER_CTLx_REG (   x)    (0x4 + (x * 4))

Definition at line 323 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_REG   0

Definition at line 311 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER0_CAUSE   (1 << 0)

Definition at line 313 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER0_IR_EN   (1 << 8)

Definition at line 318 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER1_CAUSE   (1 << 1)

Definition at line 314 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER1_IR_EN   (1 << 9)

Definition at line 319 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER2_CAUSE   (1 << 2)

Definition at line 315 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER2_IR_EN   (1 << 10)

Definition at line 320 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER_CAUSE (   x)    (1 << (x))

Definition at line 312 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_TIMER_IR_EN (   x)    (1 << ((x) + 8))

Definition at line 317 of file bcm63xx_regs.h.

#define TIMER_IRQSTAT_WDT_CAUSE   (1 << 3)

Definition at line 316 of file bcm63xx_regs.h.

#define TIMER_T0_ID   0

Definition at line 305 of file bcm63xx_regs.h.

#define TIMER_T1_ID   1

Definition at line 306 of file bcm63xx_regs.h.

#define TIMER_T2_ID   2

Definition at line 307 of file bcm63xx_regs.h.

#define TIMER_WDT_ID   3

Definition at line 308 of file bcm63xx_regs.h.

#define UART_BAUD_REG   0x4

Definition at line 396 of file bcm63xx_regs.h.

#define UART_CTL_BITSPERSYM_MASK   (0x3 << UART_CTL_BITSPERSYM_SHIFT)

Definition at line 373 of file bcm63xx_regs.h.

#define UART_CTL_BITSPERSYM_SHIFT   12

Definition at line 372 of file bcm63xx_regs.h.

#define UART_CTL_BRGEN_MASK   (1 << UART_CTL_BRGEN_SHIFT)

Definition at line 393 of file bcm63xx_regs.h.

#define UART_CTL_BRGEN_SHIFT   23

Definition at line 392 of file bcm63xx_regs.h.

#define UART_CTL_LOOPBACK_MASK   (1 << UART_CTL_LOOPBACK_SHIFT)

Definition at line 387 of file bcm63xx_regs.h.

#define UART_CTL_LOOPBACK_SHIFT   20

Definition at line 386 of file bcm63xx_regs.h.

#define UART_CTL_REG   0x0

Definition at line 359 of file bcm63xx_regs.h.

#define UART_CTL_RSTRXFIFO_MASK   (1 << UART_CTL_RSTRXFIFO_SHIFT)

Definition at line 365 of file bcm63xx_regs.h.

#define UART_CTL_RSTRXFIFO_SHIFT   6

Definition at line 364 of file bcm63xx_regs.h.

#define UART_CTL_RSTTXDN_MASK   (1 << UART_CTL_RSTTXDN_SHIFT)

Definition at line 363 of file bcm63xx_regs.h.

#define UART_CTL_RSTTXDN_SHIFT   5

Definition at line 362 of file bcm63xx_regs.h.

#define UART_CTL_RSTTXFIFO_MASK   (1 << UART_CTL_RSTTXFIFO_SHIFT)

Definition at line 367 of file bcm63xx_regs.h.

#define UART_CTL_RSTTXFIFO_SHIFT   7

Definition at line 366 of file bcm63xx_regs.h.

#define UART_CTL_RSVD_MASK   (1 << UART_CTL_RSVD_SHIFT)

Definition at line 377 of file bcm63xx_regs.h.

#define UART_CTL_RSVD_SHIFT   15

Definition at line 376 of file bcm63xx_regs.h.

#define UART_CTL_RXEN_MASK   (1 << UART_CTL_RXEN_SHIFT)

Definition at line 389 of file bcm63xx_regs.h.

#define UART_CTL_RXEN_SHIFT   21

Definition at line 388 of file bcm63xx_regs.h.

#define UART_CTL_RXPAREN_MASK   (1 << UART_CTL_RXPAREN_SHIFT)

Definition at line 381 of file bcm63xx_regs.h.

#define UART_CTL_RXPAREN_SHIFT   17

Definition at line 380 of file bcm63xx_regs.h.

#define UART_CTL_RXPAREVEN_MASK   (1 << UART_CTL_RXPAREVEN_SHIFT)

Definition at line 379 of file bcm63xx_regs.h.

#define UART_CTL_RXPAREVEN_SHIFT   16

Definition at line 378 of file bcm63xx_regs.h.

#define UART_CTL_RXTMOUTCNT_MASK   (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)

Definition at line 361 of file bcm63xx_regs.h.

#define UART_CTL_RXTMOUTCNT_SHIFT   0

Definition at line 360 of file bcm63xx_regs.h.

#define UART_CTL_STOPBITS_1   (0x7 << UART_CTL_STOPBITS_SHIFT)

Definition at line 370 of file bcm63xx_regs.h.

#define UART_CTL_STOPBITS_2   (0xf << UART_CTL_STOPBITS_SHIFT)

Definition at line 371 of file bcm63xx_regs.h.

#define UART_CTL_STOPBITS_MASK   (0xf << UART_CTL_STOPBITS_SHIFT)

Definition at line 369 of file bcm63xx_regs.h.

#define UART_CTL_STOPBITS_SHIFT   8

Definition at line 368 of file bcm63xx_regs.h.

#define UART_CTL_TXEN_MASK   (1 << UART_CTL_TXEN_SHIFT)

Definition at line 391 of file bcm63xx_regs.h.

#define UART_CTL_TXEN_SHIFT   22

Definition at line 390 of file bcm63xx_regs.h.

#define UART_CTL_TXPAREN_MASK   (1 << UART_CTL_TXPAREN_SHIFT)

Definition at line 385 of file bcm63xx_regs.h.

#define UART_CTL_TXPAREN_SHIFT   18

Definition at line 384 of file bcm63xx_regs.h.

#define UART_CTL_TXPAREVEN_MASK   (1 << UART_CTL_TXPAREVEN_SHIFT)

Definition at line 383 of file bcm63xx_regs.h.

#define UART_CTL_TXPAREVEN_SHIFT   18

Definition at line 382 of file bcm63xx_regs.h.

#define UART_CTL_XMITBRK_MASK   (1 << UART_CTL_XMITBRK_SHIFT)

Definition at line 375 of file bcm63xx_regs.h.

#define UART_CTL_XMITBRK_SHIFT   14

Definition at line 374 of file bcm63xx_regs.h.

#define UART_EXTINP_CTS_MASK   (1 << UART_EXTINP_CTS_SHIFT)

Definition at line 418 of file bcm63xx_regs.h.

#define UART_EXTINP_CTS_NOSENSE_MASK   (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)

Definition at line 432 of file bcm63xx_regs.h.

#define UART_EXTINP_CTS_NOSENSE_SHIFT   17

Definition at line 431 of file bcm63xx_regs.h.

#define UART_EXTINP_CTS_SHIFT   1

Definition at line 417 of file bcm63xx_regs.h.

#define UART_EXTINP_DCD_MASK   (1 << UART_EXTINP_DCD_SHIFT)

Definition at line 420 of file bcm63xx_regs.h.

#define UART_EXTINP_DCD_NOSENSE_MASK   (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)

Definition at line 434 of file bcm63xx_regs.h.

#define UART_EXTINP_DCD_NOSENSE_SHIFT   18

Definition at line 433 of file bcm63xx_regs.h.

#define UART_EXTINP_DCD_SHIFT   2

Definition at line 419 of file bcm63xx_regs.h.

#define UART_EXTINP_DSR_MASK   (1 << UART_EXTINP_DSR_SHIFT)

Definition at line 422 of file bcm63xx_regs.h.

#define UART_EXTINP_DSR_NOSENSE_MASK   (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)

Definition at line 436 of file bcm63xx_regs.h.

#define UART_EXTINP_DSR_NOSENSE_SHIFT   19

Definition at line 435 of file bcm63xx_regs.h.

#define UART_EXTINP_DSR_SHIFT   3

Definition at line 421 of file bcm63xx_regs.h.

#define UART_EXTINP_IR_CTS   1

Definition at line 426 of file bcm63xx_regs.h.

#define UART_EXTINP_IR_DCD   2

Definition at line 427 of file bcm63xx_regs.h.

#define UART_EXTINP_IR_DSR   3

Definition at line 428 of file bcm63xx_regs.h.

#define UART_EXTINP_IR_RI   0

Definition at line 425 of file bcm63xx_regs.h.

#define UART_EXTINP_IRMASK (   x)    (1 << (x + 8))

Definition at line 424 of file bcm63xx_regs.h.

#define UART_EXTINP_IRSTAT (   x)    (1 << (x + 4))

Definition at line 423 of file bcm63xx_regs.h.

#define UART_EXTINP_REG   0xc

Definition at line 414 of file bcm63xx_regs.h.

#define UART_EXTINP_RI_MASK   (1 << UART_EXTINP_RI_SHIFT)

Definition at line 416 of file bcm63xx_regs.h.

#define UART_EXTINP_RI_NOSENSE_MASK   (1 << UART_EXTINP_RI_NOSENSE_SHIFT)

Definition at line 430 of file bcm63xx_regs.h.

#define UART_EXTINP_RI_NOSENSE_SHIFT   16

Definition at line 429 of file bcm63xx_regs.h.

#define UART_EXTINP_RI_SHIFT   0

Definition at line 415 of file bcm63xx_regs.h.

#define UART_FIFO_ANYERR_MASK
Value:
(UART_FIFO_FRAMEERR_MASK | \
UART_FIFO_PARERR_MASK | \
UART_FIFO_BRKDET_MASK)

Definition at line 469 of file bcm63xx_regs.h.

#define UART_FIFO_BRKDET_MASK   (1 << UART_FIFO_BRKDET_SHIFT)

Definition at line 468 of file bcm63xx_regs.h.

#define UART_FIFO_BRKDET_SHIFT   10

Definition at line 467 of file bcm63xx_regs.h.

#define UART_FIFO_FRAMEERR_MASK   (1 << UART_FIFO_FRAMEERR_SHIFT)

Definition at line 464 of file bcm63xx_regs.h.

#define UART_FIFO_FRAMEERR_SHIFT   8

Definition at line 463 of file bcm63xx_regs.h.

#define UART_FIFO_PARERR_MASK   (1 << UART_FIFO_PARERR_SHIFT)

Definition at line 466 of file bcm63xx_regs.h.

#define UART_FIFO_PARERR_SHIFT   9

Definition at line 465 of file bcm63xx_regs.h.

#define UART_FIFO_REG   0x14

Definition at line 460 of file bcm63xx_regs.h.

#define UART_FIFO_VALID_MASK   0xff

Definition at line 462 of file bcm63xx_regs.h.

#define UART_FIFO_VALID_SHIFT   0

Definition at line 461 of file bcm63xx_regs.h.

#define UART_IR_EXTIP   0

Definition at line 442 of file bcm63xx_regs.h.

#define UART_IR_MASK (   x)    (1 << (x + 16))

Definition at line 440 of file bcm63xx_regs.h.

#define UART_IR_REG   0x10

Definition at line 439 of file bcm63xx_regs.h.

#define UART_IR_RXBRK   14

Definition at line 456 of file bcm63xx_regs.h.

#define UART_IR_RXFRAMEERR   12

Definition at line 454 of file bcm63xx_regs.h.

#define UART_IR_RXFULL   9

Definition at line 451 of file bcm63xx_regs.h.

#define UART_IR_RXNOTEMPTY   11

Definition at line 453 of file bcm63xx_regs.h.

#define UART_IR_RXOVER   7

Definition at line 449 of file bcm63xx_regs.h.

#define UART_IR_RXPARERR   13

Definition at line 455 of file bcm63xx_regs.h.

#define UART_IR_RXTHRESH   10

Definition at line 452 of file bcm63xx_regs.h.

#define UART_IR_RXTIMEOUT   8

Definition at line 450 of file bcm63xx_regs.h.

#define UART_IR_RXUNDER   6

Definition at line 448 of file bcm63xx_regs.h.

#define UART_IR_STAT (   x)    (1 << (x))

Definition at line 441 of file bcm63xx_regs.h.

#define UART_IR_TXDONE   15

Definition at line 457 of file bcm63xx_regs.h.

#define UART_IR_TXEMPTY   5

Definition at line 447 of file bcm63xx_regs.h.

#define UART_IR_TXOVER   2

Definition at line 444 of file bcm63xx_regs.h.

#define UART_IR_TXRDLATCH   4

Definition at line 446 of file bcm63xx_regs.h.

#define UART_IR_TXTRESH   3

Definition at line 445 of file bcm63xx_regs.h.

#define UART_IR_TXUNDER   1

Definition at line 443 of file bcm63xx_regs.h.

#define UART_MCTL_DTR_MASK   (1 << UART_MCTL_DTR_SHIFT)

Definition at line 401 of file bcm63xx_regs.h.

#define UART_MCTL_DTR_SHIFT   0

Definition at line 400 of file bcm63xx_regs.h.

#define UART_MCTL_REG   0x8

Definition at line 399 of file bcm63xx_regs.h.

#define UART_MCTL_RTS_MASK   (1 << UART_MCTL_RTS_SHIFT)

Definition at line 403 of file bcm63xx_regs.h.

#define UART_MCTL_RTS_SHIFT   1

Definition at line 402 of file bcm63xx_regs.h.

#define UART_MCTL_RXFIFOFILL_MASK   (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)

Definition at line 409 of file bcm63xx_regs.h.

#define UART_MCTL_RXFIFOFILL_SHIFT   16

Definition at line 408 of file bcm63xx_regs.h.

#define UART_MCTL_RXFIFOTHRESH_MASK   (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)

Definition at line 405 of file bcm63xx_regs.h.

#define UART_MCTL_RXFIFOTHRESH_SHIFT   8

Definition at line 404 of file bcm63xx_regs.h.

#define UART_MCTL_TXFIFOFILL_MASK   (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)

Definition at line 411 of file bcm63xx_regs.h.

#define UART_MCTL_TXFIFOFILL_SHIFT   24

Definition at line 410 of file bcm63xx_regs.h.

#define UART_MCTL_TXFIFOTHRESH_MASK   (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)

Definition at line 407 of file bcm63xx_regs.h.

#define UART_MCTL_TXFIFOTHRESH_SHIFT   12

Definition at line 406 of file bcm63xx_regs.h.

#define USBD_CONTROL_AUTO_CSRS_MASK   (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)

Definition at line 822 of file bcm63xx_regs.h.

#define USBD_CONTROL_AUTO_CSRS_SHIFT   13

Definition at line 821 of file bcm63xx_regs.h.

#define USBD_CONTROL_DONE_CSRS_MASK   (1 << USBD_CONTROL_DONE_CSRS_SHIFT)

Definition at line 832 of file bcm63xx_regs.h.

#define USBD_CONTROL_DONE_CSRS_SHIFT   0

Definition at line 831 of file bcm63xx_regs.h.

#define USBD_CONTROL_FIFO_RESET_MASK   (3 << USBD_CONTROL_FIFO_RESET_SHIFT)

Definition at line 828 of file bcm63xx_regs.h.

#define USBD_CONTROL_FIFO_RESET_SHIFT   6

Definition at line 827 of file bcm63xx_regs.h.

#define USBD_CONTROL_INIT_SEL_MASK   (0xf << USBD_CONTROL_INIT_SEL_SHIFT)

Definition at line 826 of file bcm63xx_regs.h.

#define USBD_CONTROL_INIT_SEL_SHIFT   8

Definition at line 825 of file bcm63xx_regs.h.

#define USBD_CONTROL_REG   0x00

Definition at line 818 of file bcm63xx_regs.h.

#define USBD_CONTROL_RXZSCFG_MASK   (1 << USBD_CONTROL_RXZSCFG_SHIFT)

Definition at line 824 of file bcm63xx_regs.h.

#define USBD_CONTROL_RXZSCFG_SHIFT   12

Definition at line 823 of file bcm63xx_regs.h.

#define USBD_CONTROL_SETUPERRLOCK_MASK   (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)

Definition at line 830 of file bcm63xx_regs.h.

#define USBD_CONTROL_SETUPERRLOCK_SHIFT   5

Definition at line 829 of file bcm63xx_regs.h.

#define USBD_CONTROL_TXZLENINS_MASK   (1 << USBD_CONTROL_TXZLENINS_SHIFT)

Definition at line 820 of file bcm63xx_regs.h.

#define USBD_CONTROL_TXZLENINS_SHIFT   14

Definition at line 819 of file bcm63xx_regs.h.

#define USBD_CSR_EP_ALTIFACE_MASK   (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)

Definition at line 942 of file bcm63xx_regs.h.

#define USBD_CSR_EP_ALTIFACE_SHIFT   15

Definition at line 941 of file bcm63xx_regs.h.

#define USBD_CSR_EP_CFG_MASK   (0xf << USBD_CSR_EP_CFG_SHIFT)

Definition at line 946 of file bcm63xx_regs.h.

#define USBD_CSR_EP_CFG_SHIFT   7

Definition at line 945 of file bcm63xx_regs.h.

#define USBD_CSR_EP_DIR_MASK   (1 << USBD_CSR_EP_DIR_SHIFT)

Definition at line 950 of file bcm63xx_regs.h.

#define USBD_CSR_EP_DIR_SHIFT   4

Definition at line 949 of file bcm63xx_regs.h.

#define USBD_CSR_EP_IFACE_MASK   (0xf << USBD_CSR_EP_IFACE_SHIFT)

Definition at line 944 of file bcm63xx_regs.h.

#define USBD_CSR_EP_IFACE_SHIFT   11

Definition at line 943 of file bcm63xx_regs.h.

#define USBD_CSR_EP_LOG_MASK   (0xf << USBD_CSR_EP_LOG_SHIFT)

Definition at line 952 of file bcm63xx_regs.h.

#define USBD_CSR_EP_LOG_SHIFT   0

Definition at line 951 of file bcm63xx_regs.h.

#define USBD_CSR_EP_MAXPKT_MASK   (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)

Definition at line 940 of file bcm63xx_regs.h.

#define USBD_CSR_EP_MAXPKT_SHIFT   19

Definition at line 939 of file bcm63xx_regs.h.

#define USBD_CSR_EP_REG (   x)    (0x84 + (x) * 4)

Definition at line 938 of file bcm63xx_regs.h.

#define USBD_CSR_EP_TYPE_MASK   (3 << USBD_CSR_EP_TYPE_SHIFT)

Definition at line 948 of file bcm63xx_regs.h.

#define USBD_CSR_EP_TYPE_SHIFT   5

Definition at line 947 of file bcm63xx_regs.h.

#define USBD_CSR_SETUPADDR_DEF   0xb550

Definition at line 936 of file bcm63xx_regs.h.

#define USBD_CSR_SETUPADDR_REG   0x80

Definition at line 935 of file bcm63xx_regs.h.

#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK   (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)

Definition at line 932 of file bcm63xx_regs.h.

#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT   0

Definition at line 931 of file bcm63xx_regs.h.

#define USBD_EPNUM_TYPEMAP_REG   0x50

Definition at line 928 of file bcm63xx_regs.h.

#define USBD_EPNUM_TYPEMAP_TYPE_MASK   (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)

Definition at line 930 of file bcm63xx_regs.h.

#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8

Definition at line 929 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_FALLING (   x)    (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))

Definition at line 889 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_HI_REG   0x18

Definition at line 882 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_LO_REG   0x1c

Definition at line 884 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_MASK (   x)    (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))

Definition at line 887 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_RISING (   x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))

Definition at line 888 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_CFG_SHIFT (   x)    ((x & 0xf) << 1)

Definition at line 886 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_EARLY_SUSPEND   4

Definition at line 901 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_ENUM_ON   2

Definition at line 903 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_ERRATIC_ERR   7

Definition at line 898 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_MASK_REG   0x20

Definition at line 892 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SET_CSRS   6

Definition at line 899 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SETCFG   9

Definition at line 896 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SETINTF   8

Definition at line 897 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SETUP   1

Definition at line 904 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SOF   3

Definition at line 902 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_STATUS_REG   0x14

Definition at line 879 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_SUSPEND   5

Definition at line 900 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_USB_LINK   10

Definition at line 895 of file bcm63xx_regs.h.

#define USBD_EVENT_IRQ_USB_RESET   0

Definition at line 905 of file bcm63xx_regs.h.

#define USBD_EVENTS_REG   0x10

Definition at line 874 of file bcm63xx_regs.h.

#define USBD_EVENTS_USB_LINK_MASK   (1 << USBD_EVENTS_USB_LINK_SHIFT)

Definition at line 876 of file bcm63xx_regs.h.

#define USBD_EVENTS_USB_LINK_SHIFT   10

Definition at line 875 of file bcm63xx_regs.h.

#define USBD_RXFIFO_CONFIG_END_MASK   (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)

Definition at line 917 of file bcm63xx_regs.h.

#define USBD_RXFIFO_CONFIG_END_SHIFT   16

Definition at line 916 of file bcm63xx_regs.h.

#define USBD_RXFIFO_CONFIG_REG   0x44

Definition at line 915 of file bcm63xx_regs.h.

#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)

Definition at line 919 of file bcm63xx_regs.h.

#define USBD_RXFIFO_CONFIG_START_SHIFT   0

Definition at line 918 of file bcm63xx_regs.h.

#define USBD_RXFIFO_EPSIZE_REG   0x4c

Definition at line 925 of file bcm63xx_regs.h.

#define USBD_STALL_ENABLE_MASK   (1 << USBD_STALL_ENABLE_SHIFT)

Definition at line 856 of file bcm63xx_regs.h.

#define USBD_STALL_ENABLE_SHIFT   6

Definition at line 855 of file bcm63xx_regs.h.

#define USBD_STALL_EPNUM_MASK   (0xf << USBD_STALL_EPNUM_SHIFT)

Definition at line 858 of file bcm63xx_regs.h.

#define USBD_STALL_EPNUM_SHIFT   0

Definition at line 857 of file bcm63xx_regs.h.

#define USBD_STALL_REG   0x08

Definition at line 852 of file bcm63xx_regs.h.

#define USBD_STALL_UPDATE_MASK   (1 << USBD_STALL_UPDATE_SHIFT)

Definition at line 854 of file bcm63xx_regs.h.

#define USBD_STALL_UPDATE_SHIFT   7

Definition at line 853 of file bcm63xx_regs.h.

#define USBD_STATUS_ALTINTF_MASK   (0xf << USBD_STATUS_ALTINTF_SHIFT)

Definition at line 867 of file bcm63xx_regs.h.

#define USBD_STATUS_ALTINTF_SHIFT   8

Definition at line 866 of file bcm63xx_regs.h.

#define USBD_STATUS_CFG_MASK   (0xf << USBD_STATUS_CFG_SHIFT)

Definition at line 871 of file bcm63xx_regs.h.

#define USBD_STATUS_CFG_SHIFT   0

Definition at line 870 of file bcm63xx_regs.h.

#define USBD_STATUS_INTF_MASK   (0xf << USBD_STATUS_INTF_SHIFT)

Definition at line 869 of file bcm63xx_regs.h.

#define USBD_STATUS_INTF_SHIFT   4

Definition at line 868 of file bcm63xx_regs.h.

#define USBD_STATUS_REG   0x0c

Definition at line 861 of file bcm63xx_regs.h.

#define USBD_STATUS_SOF_MASK   (0x7ff << USBD_STATUS_SOF_SHIFT)

Definition at line 863 of file bcm63xx_regs.h.

#define USBD_STATUS_SOF_SHIFT   16

Definition at line 862 of file bcm63xx_regs.h.

#define USBD_STATUS_SPD_MASK   (3 << USBD_STATUS_SPD_SHIFT)

Definition at line 865 of file bcm63xx_regs.h.

#define USBD_STATUS_SPD_SHIFT   12

Definition at line 864 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_8BITPHY_MASK   (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)

Definition at line 847 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_8BITPHY_SHIFT   2

Definition at line 846 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_CSRPRGSUP_MASK   (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)

Definition at line 841 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT   8

Definition at line 840 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_DISCON_MASK   (1 << USBD_STRAPS_APP_DISCON_SHIFT)

Definition at line 839 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_DISCON_SHIFT   9

Definition at line 838 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_RAM_IF_MASK   (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)

Definition at line 845 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_RAM_IF_SHIFT   7

Definition at line 844 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_RMTWKUP_MASK   (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)

Definition at line 843 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6

Definition at line 842 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)

Definition at line 837 of file bcm63xx_regs.h.

#define USBD_STRAPS_APP_SELF_PWR_SHIFT   10

Definition at line 836 of file bcm63xx_regs.h.

#define USBD_STRAPS_REG   0x04

Definition at line 835 of file bcm63xx_regs.h.

#define USBD_STRAPS_SPEED_MASK   (3 << USBD_STRAPS_SPEED_SHIFT)

Definition at line 849 of file bcm63xx_regs.h.

#define USBD_STRAPS_SPEED_SHIFT   0

Definition at line 848 of file bcm63xx_regs.h.

#define USBD_TXFIFO_CONFIG_END_MASK   (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)

Definition at line 910 of file bcm63xx_regs.h.

#define USBD_TXFIFO_CONFIG_END_SHIFT   16

Definition at line 909 of file bcm63xx_regs.h.

#define USBD_TXFIFO_CONFIG_REG   0x40

Definition at line 908 of file bcm63xx_regs.h.

#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)

Definition at line 912 of file bcm63xx_regs.h.

#define USBD_TXFIFO_CONFIG_START_SHIFT   0

Definition at line 911 of file bcm63xx_regs.h.

#define USBD_TXFIFO_EPSIZE_REG   0x48

Definition at line 922 of file bcm63xx_regs.h.

#define USBH_PRIV_SETUP_6368_REG   0x28

Definition at line 808 of file bcm63xx_regs.h.

#define USBH_PRIV_SETUP_IOC_MASK   (1 << USBH_PRIV_SETUP_IOC_SHIFT)

Definition at line 810 of file bcm63xx_regs.h.

#define USBH_PRIV_SETUP_IOC_SHIFT   4

Definition at line 809 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_6358_REG   0x0

Definition at line 785 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_6368_REG   0x1c

Definition at line 786 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_EHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)

Definition at line 793 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT   3

Definition at line 792 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)

Definition at line 791 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT   4

Definition at line 790 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)

Definition at line 797 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT   0

Definition at line 796 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_OHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)

Definition at line 795 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT   1

Definition at line 794 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_USBD_MASK   (1 << USBH_PRIV_SWAP_USBD_SHIFT)

Definition at line 789 of file bcm63xx_regs.h.

#define USBH_PRIV_SWAP_USBD_SHIFT   6

Definition at line 788 of file bcm63xx_regs.h.

#define USBH_PRIV_TEST_6358_REG   0x24

Definition at line 805 of file bcm63xx_regs.h.

#define USBH_PRIV_TEST_6368_REG   0x14

Definition at line 806 of file bcm63xx_regs.h.

#define USBH_PRIV_UTMI_CTL_6368_REG   0x10

Definition at line 799 of file bcm63xx_regs.h.

#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)

Definition at line 803 of file bcm63xx_regs.h.

#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT   0

Definition at line 802 of file bcm63xx_regs.h.

#define USBH_PRIV_UTMI_CTL_NODRIV_MASK   (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)

Definition at line 801 of file bcm63xx_regs.h.

#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT   12

Definition at line 800 of file bcm63xx_regs.h.

#define WDT_CTL_REG   0x4

Definition at line 340 of file bcm63xx_regs.h.

#define WDT_DEFVAL_REG   0x0

Definition at line 337 of file bcm63xx_regs.h.

#define WDT_RSTLEN_REG   0x8

Definition at line 349 of file bcm63xx_regs.h.

#define WDT_SOFTRESET_REG   0xc

Definition at line 352 of file bcm63xx_regs.h.

#define WDT_START_1   (0xff00)

Definition at line 343 of file bcm63xx_regs.h.

#define WDT_START_2   (0x00ff)

Definition at line 344 of file bcm63xx_regs.h.

#define WDT_STOP_1   (0xee00)

Definition at line 345 of file bcm63xx_regs.h.

#define WDT_STOP_2   (0x00ee)

Definition at line 346 of file bcm63xx_regs.h.

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