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bcm_70012_regs.h File Reference

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Macros

#define BRCM_ALIGN(c, r, f)   c##_##r##_##f##_ALIGN
 
#define BRCM_BITS(c, r, f)   c##_##r##_##f##_BITS
 
#define BRCM_MASK(c, r, f)   c##_##r##_##f##_MASK
 
#define BRCM_SHIFT(c, r, f)   c##_##r##_##f##_SHIFT
 
#define GET_FIELD(m, c, r, f)   ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f))
 
#define SET_FIELD(m, c, r, f, d)
 
#define SET_TYPE_FIELD(m, c, r, f, d)   SET_FIELD(m, c, r, f, c##_##d)
 
#define SET_NAME_FIELD(m, c, r, f, d)   SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)
 
#define SET_VALUE_FIELD(m, c, r, f, d)   SET_FIELD(m, c, r, f, d)
 
#define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define AES_RGR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT   0
 
#define GISB_ARBITER_DEASSERT_ASSERT_ASSERT   1
 
#define GISB_ARBITER_UNMASK_MASK_UNMASK   0
 
#define GISB_ARBITER_UNMASK_MASK_MASK   1
 
#define GISB_ARBITER_DISABLE_ENABLE_DISABLE   0
 
#define GISB_ARBITER_DISABLE_ENABLE_ENABLE   1
 
#define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define I2C_GR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define MISC_GR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT   0
 
#define OTP_GR_BRIDGE_RESET_CTRL_ASSERT   1
 
#define PCIE_CFG_DEVICE_VENDOR_ID   0x00000000 /* DEVICE_VENDOR_ID Register */
 
#define PCIE_CFG_STATUS_COMMAND   0x00000004 /* STATUS_COMMAND Register */
 
#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID   0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */
 
#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE   0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */
 
#define PCIE_CFG_BASE_ADDRESS_1   0x00000010 /* BASE_ADDRESS_1 Register */
 
#define PCIE_CFG_BASE_ADDRESS_2   0x00000014 /* BASE_ADDRESS_2 Register */
 
#define PCIE_CFG_BASE_ADDRESS_3   0x00000018 /* BASE_ADDRESS_3 Register */
 
#define PCIE_CFG_BASE_ADDRESS_4   0x0000001c /* BASE_ADDRESS_4 Register */
 
#define PCIE_CFG_CARDBUS_CIS_POINTER   0x00000028 /* CARDBUS_CIS_POINTER Register */
 
#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID   0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */
 
#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS   0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */
 
#define PCIE_CFG_CAPABILITIES_POINTER   0x00000034 /* CAPABILITIES_POINTER Register */
 
#define PCIE_CFG_INTERRUPT   0x0000003c /* INTERRUPT Register */
 
#define PCIE_CFG_VPD_CAPABILITIES   0x00000040 /* VPD_CAPABILITIES Register */
 
#define PCIE_CFG_VPD_DATA   0x00000044 /* VPD_DATA Register */
 
#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY   0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */
 
#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS   0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */
 
#define PCIE_CFG_MSI_CAPABILITY_HEADER   0x00000050 /* MSI_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_MSI_LOWER_ADDRESS   0x00000054 /* MSI_LOWER_ADDRESS Register */
 
#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER   0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */
 
#define PCIE_CFG_MSI_DATA   0x0000005c /* MSI_DATA Register */
 
#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER   0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES   0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */
 
#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL   0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */
 
#define PCIE_CFG_SPARE   0x0000006c /* SPARE Register */
 
#define PCIE_CFG_PCI_STATE   0x00000070 /* PCI_STATE Register */
 
#define PCIE_CFG_CLOCK_CONTROL   0x00000074 /* CLOCK_CONTROL Register */
 
#define PCIE_CFG_REGISTER_BASE   0x00000078 /* REGISTER_BASE Register */
 
#define PCIE_CFG_MEMORY_BASE   0x0000007c /* MEMORY_BASE Register */
 
#define PCIE_CFG_REGISTER_DATA   0x00000080 /* REGISTER_DATA Register */
 
#define PCIE_CFG_MEMORY_DATA   0x00000084 /* MEMORY_DATA Register */
 
#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE   0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */
 
#define PCIE_CFG_EXPANSION_ROM_ADDRESS   0x0000008c /* EXPANSION_ROM_ADDRESS Register */
 
#define PCIE_CFG_EXPANSION_ROM_DATA   0x00000090 /* EXPANSION_ROM_DATA Register */
 
#define PCIE_CFG_VPD_INTERFACE   0x00000094 /* VPD_INTERFACE Register */
 
#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER   0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */
 
#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER   0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */
 
#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER   0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */
 
#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER   0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */
 
#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER   0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */
 
#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER   0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */
 
#define PCIE_CFG_INT_MAILBOX_UPPER   0x000000b0 /* INT_MAILBOX_UPPER Register */
 
#define PCIE_CFG_INT_MAILBOX_LOWER   0x000000b4 /* INT_MAILBOX_LOWER Register */
 
#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION   0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */
 
#define PCIE_CFG_FUNCTION_EVENT   0x000000c0 /* FUNCTION_EVENT Register */
 
#define PCIE_CFG_FUNCTION_EVENT_MASK   0x000000c4 /* FUNCTION_EVENT_MASK Register */
 
#define PCIE_CFG_FUNCTION_PRESENT   0x000000c8 /* FUNCTION_PRESENT Register */
 
#define PCIE_CFG_PCIE_CAPABILITIES   0x000000cc /* PCIE_CAPABILITIES Register */
 
#define PCIE_CFG_DEVICE_CAPABILITIES   0x000000d0 /* DEVICE_CAPABILITIES Register */
 
#define PCIE_CFG_DEVICE_STATUS_CONTROL   0x000000d4 /* DEVICE_STATUS_CONTROL Register */
 
#define PCIE_CFG_LINK_CAPABILITY   0x000000d8 /* LINK_CAPABILITY Register */
 
#define PCIE_CFG_LINK_STATUS_CONTROL   0x000000dc /* LINK_STATUS_CONTROL Register */
 
#define PCIE_CFG_DEVICE_CAPABILITIES_2   0x000000f0 /* DEVICE_CAPABILITIES_2 Register */
 
#define PCIE_CFG_DEVICE_STATUS_CONTROL_2   0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */
 
#define PCIE_CFG_LINK_CAPABILITIES_2   0x000000f8 /* LINK_CAPABILITIES_2 Register */
 
#define PCIE_CFG_LINK_STATUS_CONTROL_2   0x000000fc /* LINK_STATUS_CONTROL_2 Register */
 
#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER   0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS   0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */
 
#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK   0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */
 
#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY   0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */
 
#define PCIE_CFG_CORRECTABLE_ERROR_STATUS   0x00000110 /* CORRECTABLE_ERROR_STATUS Register */
 
#define PCIE_CFG_CORRECTABLE_ERROR_MASK   0x00000114 /* CORRECTABLE_ERROR_MASK Register */
 
#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL   0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */
 
#define PCIE_CFG_HEADER_LOG_1   0x0000011c /* HEADER_LOG_1 Register */
 
#define PCIE_CFG_HEADER_LOG_2   0x00000120 /* HEADER_LOG_2 Register */
 
#define PCIE_CFG_HEADER_LOG_3   0x00000124 /* HEADER_LOG_3 Register */
 
#define PCIE_CFG_HEADER_LOG_4   0x00000128 /* HEADER_LOG_4 Register */
 
#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER   0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_PORT_VC_CAPABILITY   0x00000140 /* PORT_VC_CAPABILITY Register */
 
#define PCIE_CFG_PORT_VC_CAPABILITY_2   0x00000144 /* PORT_VC_CAPABILITY_2 Register */
 
#define PCIE_CFG_PORT_VC_STATUS_CONTROL   0x00000148 /* PORT_VC_STATUS_CONTROL Register */
 
#define PCIE_CFG_VC_RESOURCE_CAPABILITY   0x0000014c /* VC_RESOURCE_CAPABILITY Register */
 
#define PCIE_CFG_VC_RESOURCE_CONTROL   0x00000150 /* VC_RESOURCE_CONTROL Register */
 
#define PCIE_CFG_VC_RESOURCE_STATUS   0x00000154 /* VC_RESOURCE_STATUS Register */
 
#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER   0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW   0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */
 
#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW   0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */
 
#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER   0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */
 
#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT   0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */
 
#define PCIE_CFG_POWER_BUDGETING_DATA   0x00000174 /* POWER_BUDGETING_DATA Register */
 
#define PCIE_CFG_POWER_BUDGETING_CAPABILITY   0x00000178 /* POWER_BUDGETING_CAPABILITY Register */
 
#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1   0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */
 
#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3   0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */
 
#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5   0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */
 
#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7   0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */
 
#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING   0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */
 
#define PCIE_TL_TL_CONTROL   0x00000400 /* TL_CONTROL Register */
 
#define PCIE_TL_TRANSACTION_CONFIGURATION   0x00000404 /* TRANSACTION_CONFIGURATION Register */
 
#define PCIE_DLL_DATA_LINK_CONTROL   0x00000500 /* DATA_LINK_CONTROL Register */
 
#define PCIE_DLL_DATA_LINK_STATUS   0x00000504 /* DATA_LINK_STATUS Register */
 
#define INTR_INTR_STATUS   0x00000700 /* Interrupt Status Register */
 
#define INTR_INTR_SET   0x00000704 /* Interrupt Set Register */
 
#define INTR_INTR_CLR_REG   0x00000708 /* Interrupt Clear Register */
 
#define INTR_INTR_MSK_STS_REG   0x0000070c /* Interrupt Mask Status Register */
 
#define INTR_INTR_MSK_SET_REG   0x00000710 /* Interrupt Mask Set Register */
 
#define INTR_INTR_MSK_CLR_REG   0x00000714 /* Interrupt Mask Clear Register */
 
#define INTR_EOI_CTRL   0x00000720 /* End of interrupt control register */
 
#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0   0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */
 
#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0   0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */
 
#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1   0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */
 
#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1   0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS   0x00000c10 /* Tx DMA Software Descriptor List Control and Status */
 
#define MISC1_TX_DMA_ERROR_STATUS   0x00000c18 /* Tx DMA Engine Error Status */
 
#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR   0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */
 
#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR   0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */
 
#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM   0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */
 
#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR   0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */
 
#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR   0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */
 
#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM   0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */
 
#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0   0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */
 
#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0   0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */
 
#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1   0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */
 
#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1   0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */
 
#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS   0x00000c44 /* Y Rx Software Descriptor List Control and Status */
 
#define MISC1_Y_RX_ERROR_STATUS   0x00000c4c /* Y Rx Engine Error Status */
 
#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR   0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */
 
#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR   0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */
 
#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT   0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */
 
#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR   0x00000c5c /* Y Rx List1 Current Descriptor Lower address */
 
#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR   0x00000c60 /* Y Rx List1 Current Descriptor Upper address */
 
#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT   0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */
 
#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0   0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */
 
#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0   0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */
 
#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1   0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */
 
#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1   0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */
 
#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS   0x00000c78 /* UV Rx Software Descriptor List Control and Status */
 
#define MISC1_UV_RX_ERROR_STATUS   0x00000c7c /* UV Rx Engine Error Status */
 
#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR   0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */
 
#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR   0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */
 
#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT   0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */
 
#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR   0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */
 
#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR   0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */
 
#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT   0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */
 
#define MISC1_DMA_DEBUG_OPTIONS_REG   0x00000c98 /* DMA Debug Options Register */
 
#define MISC1_READ_CHANNEL_ERROR_STATUS   0x00000c9c /* Read Channel Error Status */
 
#define MISC1_PCIE_DMA_CTRL   0x00000ca0 /* PCIE DMA Control Register */
 
#define MISC2_GLOBAL_CTRL   0x00000d00 /* Global Control Register */
 
#define MISC2_INTERNAL_STATUS   0x00000d04 /* Internal Status Register */
 
#define MISC2_INTERNAL_STATUS_MUX_CTRL   0x00000d08 /* Internal Debug Mux Control */
 
#define MISC2_DEBUG_FIFO_LENGTH   0x00000d0c /* Debug FIFO Length */
 
#define MISC3_RESET_CTRL   0x00000e00 /* Reset Control Register */
 
#define MISC3_BIST_CTRL   0x00000e04 /* BIST Control Register */
 
#define MISC3_BIST_STATUS   0x00000e08 /* BIST Status Register */
 
#define MISC3_RX_CHECKSUM   0x00000e0c /* Receive Checksum */
 
#define MISC3_TX_CHECKSUM   0x00000e10 /* Transmit Checksum */
 
#define MISC3_ECO_CTRL_CORE   0x00000e14 /* ECO Core Reset Control Register */
 
#define MISC3_CSI_TEST_CTRL   0x00000e18 /* CSI Test Control Register */
 
#define MISC3_HD_DVI_TEST_CTRL   0x00000e1c /* HD DVI Test Control Register */
 
#define MISC_PERST_ECO_CTRL_PERST   0x00000e80 /* ECO PCIE Reset Control Register */
 
#define MISC_PERST_DECODER_CTRL   0x00000e84 /* Decoder Control Register */
 
#define MISC_PERST_CCE_STATUS   0x00000e88 /* Config Copy Engine Status */
 
#define MISC_PERST_PCIE_DEBUG   0x00000e8c /* PCIE Debug Control Register */
 
#define MISC_PERST_PCIE_DEBUG_STATUS   0x00000e90 /* PCIE Debug Status Register */
 
#define MISC_PERST_VREG_CTRL   0x00000e94 /* Voltage Regulator Control Register */
 
#define MISC_PERST_MEM_CTRL   0x00000e98 /* Memory Control Register */
 
#define MISC_PERST_CLOCK_CTRL   0x00000e9c /* Clock Control Register */
 
#define GISB_ARBITER_REVISION   0x00000f00 /* GISB ARBITER REVISION */
 
#define GISB_ARBITER_SCRATCH   0x00000f04 /* GISB ARBITER Scratch Register */
 
#define GISB_ARBITER_REQ_MASK   0x00000f08 /* GISB ARBITER Master Request Mask Register */
 
#define GISB_ARBITER_TIMER   0x00000f0c /* GISB ARBITER Timer Value Register */
 
#define OTP_CONFIG_INFO   0x00001400 /* OTP Configuration Register */
 
#define OTP_CMD   0x00001404 /* OTP Command Register */
 
#define OTP_STATUS   0x00001408 /* OTP Status Register */
 
#define OTP_CONTENT_MISC   0x0000140c /* Content : Miscellaneous Register */
 
#define OTP_CONTENT_AES_0   0x00001410 /* Content : AES Key 0 Register */
 
#define OTP_CONTENT_AES_1   0x00001414 /* Content : AES Key 1 Register */
 
#define OTP_CONTENT_AES_2   0x00001418 /* Content : AES Key 2 Register */
 
#define OTP_CONTENT_AES_3   0x0000141c /* Content : AES Key 3 Register */
 
#define OTP_CONTENT_SHA_0   0x00001420 /* Content : SHA Key 0 Register */
 
#define OTP_CONTENT_SHA_1   0x00001424 /* Content : SHA Key 1 Register */
 
#define OTP_CONTENT_SHA_2   0x00001428 /* Content : SHA Key 2 Register */
 
#define OTP_CONTENT_SHA_3   0x0000142c /* Content : SHA Key 3 Register */
 
#define OTP_CONTENT_SHA_4   0x00001430 /* Content : SHA Key 4 Register */
 
#define OTP_CONTENT_SHA_5   0x00001434 /* Content : SHA Key 5 Register */
 
#define OTP_CONTENT_SHA_6   0x00001438 /* Content : SHA Key 6 Register */
 
#define OTP_CONTENT_SHA_7   0x0000143c /* Content : SHA Key 7 Register */
 
#define OTP_CONTENT_CHECKSUM   0x00001440 /* Content : Checksum Register */
 
#define OTP_PROG_CTRL   0x00001444 /* Programming Control Register */
 
#define OTP_PROG_STATUS   0x00001448 /* Programming Status Register */
 
#define OTP_PROG_PULSE   0x0000144c /* Program Pulse Width Register */
 
#define OTP_VERIFY_PULSE   0x00001450 /* Verify Pulse Width Register */
 
#define OTP_PROG_MASK   0x00001454 /* Program Mask Register */
 
#define OTP_DATA_INPUT   0x00001458 /* Data Input Register */
 
#define OTP_DATA_OUTPUT   0x0000145c /* Data Output Register */
 
#define AES_CONFIG_INFO   0x00001800 /* AES Configuration Information Register */
 
#define AES_CMD   0x00001804 /* AES Command Register */
 
#define AES_STATUS   0x00001808 /* AES Status Register */
 
#define AES_EEPROM_CONFIG   0x0000180c /* AES EEPROM Configuration Register */
 
#define AES_EEPROM_DATA_0   0x00001810 /* AES EEPROM Data Register 0 */
 
#define AES_EEPROM_DATA_1   0x00001814 /* AES EEPROM Data Register 1 */
 
#define AES_EEPROM_DATA_2   0x00001818 /* AES EEPROM Data Register 2 */
 
#define AES_EEPROM_DATA_3   0x0000181c /* AES EEPROM Data Register 3 */
 
#define DCI_CMD   0x00001c00 /* DCI Command Register */
 
#define DCI_STATUS   0x00001c04 /* DCI Status Register */
 
#define DCI_DRAM_BASE_ADDR   0x00001c08 /* DRAM Base Address Register */
 
#define DCI_FIRMWARE_ADDR   0x00001c0c /* Firmware Address Register */
 
#define DCI_FIRMWARE_DATA   0x00001c10 /* Firmware Data Register */
 
#define DCI_SIGNATURE_DATA_0   0x00001c14 /* Signature Data Register 0 */
 
#define DCI_SIGNATURE_DATA_1   0x00001c18 /* Signature Data Register 1 */
 
#define DCI_SIGNATURE_DATA_2   0x00001c1c /* Signature Data Register 2 */
 
#define DCI_SIGNATURE_DATA_3   0x00001c20 /* Signature Data Register 3 */
 
#define DCI_SIGNATURE_DATA_4   0x00001c24 /* Signature Data Register 4 */
 
#define DCI_SIGNATURE_DATA_5   0x00001c28 /* Signature Data Register 5 */
 
#define DCI_SIGNATURE_DATA_6   0x00001c2c /* Signature Data Register 6 */
 
#define DCI_SIGNATURE_DATA_7   0x00001c30 /* Signature Data Register 7 */
 
#define INTR_INTR_STATUS_reserved0_MASK   0xfc000000
 
#define INTR_INTR_STATUS_reserved0_ALIGN   0
 
#define INTR_INTR_STATUS_reserved0_BITS   6
 
#define INTR_INTR_STATUS_reserved0_SHIFT   26
 
#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK   0x02000000
 
#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN   0
 
#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS   1
 
#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT   25
 
#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK   0x01000000
 
#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN   0
 
#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS   1
 
#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT   24
 
#define INTR_INTR_STATUS_reserved1_MASK   0x00ffc000
 
#define INTR_INTR_STATUS_reserved1_ALIGN   0
 
#define INTR_INTR_STATUS_reserved1_BITS   10
 
#define INTR_INTR_STATUS_reserved1_SHIFT   14
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK   0x00002000
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT   13
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK   0x00001000
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT   12
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK   0x00000800
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT   11
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK   0x00000400
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT   10
 
#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK   0x00000200
 
#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   9
 
#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000100
 
#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT   8
 
#define INTR_INTR_STATUS_reserved2_MASK   0x000000c0
 
#define INTR_INTR_STATUS_reserved2_ALIGN   0
 
#define INTR_INTR_STATUS_reserved2_BITS   2
 
#define INTR_INTR_STATUS_reserved2_SHIFT   6
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK   0x00000020
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT   5
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK   0x00000010
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT   4
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK   0x00000008
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT   3
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK   0x00000004
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT   2
 
#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK   0x00000002
 
#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1
 
#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001
 
#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN   0
 
#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS   1
 
#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK   0xfffffff0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS   28
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT   4
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK   0x00000008
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS   1
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT   3
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK   0x00000004
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS   1
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT   2
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK   0x00000002
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS   1
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT   1
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK   0x00000001
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN   0
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS   1
 
#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK   0xfffffc00
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS   22
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT   10
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK   0x00000100
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT   8
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK   0x00000040
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT   6
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK   0x00000020
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT   5
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK   0x00000010
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT   4
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK   0x00000008
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT   3
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK   0x00000004
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT   2
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK   0x00000002
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT   1
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK   0x00000001
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN   0
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS   1
 
#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK   0xffffc000
 
#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS   18
 
#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT   14
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK   0x00002000
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT   13
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK   0x00001000
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT   12
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK   0x00000800
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT   11
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK   0x00000400
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT   10
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9
 
#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK   0x00000100
 
#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT   8
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7
 
#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK   0x00000060
 
#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS   2
 
#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT   5
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK   0x00000010
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT   4
 
#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK   0x0000000c
 
#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS   2
 
#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT   2
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK   0x00000002
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT   1
 
#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK   0x00000001
 
#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN   0
 
#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS   1
 
#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK   0xffffc000
 
#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS   18
 
#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT   14
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK   0x00002000
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT   13
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK   0x00001000
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT   12
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK   0x00000800
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT   11
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK   0x00000400
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT   10
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9
 
#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK   0x00000100
 
#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT   8
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7
 
#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK   0x00000060
 
#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS   2
 
#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT   5
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK   0x00000010
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT   4
 
#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK   0x0000000c
 
#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS   2
 
#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT   2
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK   0x00000002
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT   1
 
#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK   0x00000001
 
#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN   0
 
#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS   1
 
#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT   0
 

Macro Definition Documentation

#define AES_CMD   0x00001804 /* AES Command Register */

Definition at line 348 of file bcm_70012_regs.h.

#define AES_CONFIG_INFO   0x00001800 /* AES Configuration Information Register */

Definition at line 347 of file bcm_70012_regs.h.

#define AES_EEPROM_CONFIG   0x0000180c /* AES EEPROM Configuration Register */

Definition at line 350 of file bcm_70012_regs.h.

#define AES_EEPROM_DATA_0   0x00001810 /* AES EEPROM Data Register 0 */

Definition at line 351 of file bcm_70012_regs.h.

#define AES_EEPROM_DATA_1   0x00001814 /* AES EEPROM Data Register 1 */

Definition at line 352 of file bcm_70012_regs.h.

#define AES_EEPROM_DATA_2   0x00001818 /* AES EEPROM Data Register 2 */

Definition at line 353 of file bcm_70012_regs.h.

#define AES_EEPROM_DATA_3   0x0000181c /* AES EEPROM Data Register 3 */

Definition at line 354 of file bcm_70012_regs.h.

#define AES_RGR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 54 of file bcm_70012_regs.h.

#define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 53 of file bcm_70012_regs.h.

#define AES_STATUS   0x00001808 /* AES Status Register */

Definition at line 349 of file bcm_70012_regs.h.

#define BRCM_ALIGN (   c,
  r,
  f 
)    c##_##r##_##f##_ALIGN

m = memory, c = core, r = register, f = field, d = data.

Definition at line 28 of file bcm_70012_regs.h.

#define BRCM_BITS (   c,
  r,
  f 
)    c##_##r##_##f##_BITS

Definition at line 29 of file bcm_70012_regs.h.

#define BRCM_MASK (   c,
  r,
  f 
)    c##_##r##_##f##_MASK

Definition at line 30 of file bcm_70012_regs.h.

#define BRCM_SHIFT (   c,
  r,
  f 
)    c##_##r##_##f##_SHIFT

Definition at line 31 of file bcm_70012_regs.h.

#define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 60 of file bcm_70012_regs.h.

#define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 59 of file bcm_70012_regs.h.

#define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 66 of file bcm_70012_regs.h.

#define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 65 of file bcm_70012_regs.h.

#define DCI_CMD   0x00001c00 /* DCI Command Register */

Definition at line 360 of file bcm_70012_regs.h.

#define DCI_DRAM_BASE_ADDR   0x00001c08 /* DRAM Base Address Register */

Definition at line 362 of file bcm_70012_regs.h.

#define DCI_FIRMWARE_ADDR   0x00001c0c /* Firmware Address Register */

Definition at line 363 of file bcm_70012_regs.h.

#define DCI_FIRMWARE_DATA   0x00001c10 /* Firmware Data Register */

Definition at line 364 of file bcm_70012_regs.h.

#define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 72 of file bcm_70012_regs.h.

#define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 71 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_0   0x00001c14 /* Signature Data Register 0 */

Definition at line 365 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_1   0x00001c18 /* Signature Data Register 1 */

Definition at line 366 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_2   0x00001c1c /* Signature Data Register 2 */

Definition at line 367 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_3   0x00001c20 /* Signature Data Register 3 */

Definition at line 368 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_4   0x00001c24 /* Signature Data Register 4 */

Definition at line 369 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_5   0x00001c28 /* Signature Data Register 5 */

Definition at line 370 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_6   0x00001c2c /* Signature Data Register 6 */

Definition at line 371 of file bcm_70012_regs.h.

#define DCI_SIGNATURE_DATA_7   0x00001c30 /* Signature Data Register 7 */

Definition at line 372 of file bcm_70012_regs.h.

#define DCI_STATUS   0x00001c04 /* DCI Status Register */

Definition at line 361 of file bcm_70012_regs.h.

#define GET_FIELD (   m,
  c,
  r,
  f 
)    ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f))

Definition at line 33 of file bcm_70012_regs.h.

#define GISB_ARBITER_DEASSERT_ASSERT_ASSERT   1

Definition at line 78 of file bcm_70012_regs.h.

#define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT   0

Definition at line 77 of file bcm_70012_regs.h.

#define GISB_ARBITER_DISABLE_ENABLE_DISABLE   0

Definition at line 89 of file bcm_70012_regs.h.

#define GISB_ARBITER_DISABLE_ENABLE_ENABLE   1

Definition at line 90 of file bcm_70012_regs.h.

#define GISB_ARBITER_REQ_MASK   0x00000f08 /* GISB ARBITER Master Request Mask Register */

Definition at line 311 of file bcm_70012_regs.h.

#define GISB_ARBITER_REVISION   0x00000f00 /* GISB ARBITER REVISION */

Definition at line 309 of file bcm_70012_regs.h.

#define GISB_ARBITER_SCRATCH   0x00000f04 /* GISB ARBITER Scratch Register */

Definition at line 310 of file bcm_70012_regs.h.

#define GISB_ARBITER_TIMER   0x00000f0c /* GISB ARBITER Timer Value Register */

Definition at line 312 of file bcm_70012_regs.h.

#define GISB_ARBITER_UNMASK_MASK_MASK   1

Definition at line 84 of file bcm_70012_regs.h.

#define GISB_ARBITER_UNMASK_MASK_UNMASK   0

Definition at line 83 of file bcm_70012_regs.h.

#define I2C_GR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 96 of file bcm_70012_regs.h.

#define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 95 of file bcm_70012_regs.h.

#define INTR_EOI_CTRL   0x00000720 /* End of interrupt control register */

Definition at line 224 of file bcm_70012_regs.h.

#define INTR_INTR_CLR_REG   0x00000708 /* Interrupt Clear Register */

Definition at line 220 of file bcm_70012_regs.h.

#define INTR_INTR_MSK_CLR_REG   0x00000714 /* Interrupt Mask Clear Register */

Definition at line 223 of file bcm_70012_regs.h.

#define INTR_INTR_MSK_SET_REG   0x00000710 /* Interrupt Mask Set Register */

Definition at line 222 of file bcm_70012_regs.h.

#define INTR_INTR_MSK_STS_REG   0x0000070c /* Interrupt Mask Status Register */

Definition at line 221 of file bcm_70012_regs.h.

#define INTR_INTR_SET   0x00000704 /* Interrupt Set Register */

Definition at line 219 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS   0x00000700 /* Interrupt Status Register */

Definition at line 218 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN   0

Definition at line 479 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS   1

Definition at line 480 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK   0x00000001

Definition at line 478 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT   0

Definition at line 481 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN   0

Definition at line 473 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS   1

Definition at line 474 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK   0x00000002

Definition at line 472 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT   1

Definition at line 475 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN   0

Definition at line 455 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS   1

Definition at line 456 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK   0x00000010

Definition at line 454 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT   4

Definition at line 457 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN   0

Definition at line 449 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS   1

Definition at line 450 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK   0x00000020

Definition at line 448 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT   5

Definition at line 451 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN   0

Definition at line 467 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS   1

Definition at line 468 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK   0x00000004

Definition at line 466 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT   2

Definition at line 469 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN   0

Definition at line 461 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS   1

Definition at line 462 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK   0x00000008

Definition at line 460 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT   3

Definition at line 463 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN   0

Definition at line 437 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS   1

Definition at line 438 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK   0x00000100

Definition at line 436 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT   8

Definition at line 439 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN   0

Definition at line 431 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS   1

Definition at line 432 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK   0x00000200

Definition at line 430 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT   9

Definition at line 433 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN   0

Definition at line 413 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS   1

Definition at line 414 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK   0x00001000

Definition at line 412 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT   12

Definition at line 415 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN   0

Definition at line 407 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS   1

Definition at line 408 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK   0x00002000

Definition at line 406 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT   13

Definition at line 409 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN   0

Definition at line 425 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS   1

Definition at line 426 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK   0x00000400

Definition at line 424 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT   10

Definition at line 427 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN   0

Definition at line 419 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS   1

Definition at line 420 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK   0x00000800

Definition at line 418 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT   11

Definition at line 421 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN   0

Definition at line 389 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS   1

Definition at line 390 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK   0x02000000

Definition at line 388 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT   25

Definition at line 391 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN   0

Definition at line 395 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS   1

Definition at line 396 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK   0x01000000

Definition at line 394 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT   24

Definition at line 397 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved0_ALIGN   0

Definition at line 383 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved0_BITS   6

Definition at line 384 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved0_MASK   0xfc000000

Definition at line 382 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved0_SHIFT   26

Definition at line 385 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved1_ALIGN   0

Definition at line 401 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved1_BITS   10

Definition at line 402 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved1_MASK   0x00ffc000

Definition at line 400 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved1_SHIFT   14

Definition at line 403 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved2_ALIGN   0

Definition at line 443 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved2_BITS   2

Definition at line 444 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved2_MASK   0x000000c0

Definition at line 442 of file bcm_70012_regs.h.

#define INTR_INTR_STATUS_reserved2_SHIFT   6

Definition at line 445 of file bcm_70012_regs.h.

#define MISC1_DMA_DEBUG_OPTIONS_REG   0x00000c98 /* DMA Debug Options Register */

Definition at line 266 of file bcm_70012_regs.h.

#define MISC1_PCIE_DMA_CTRL   0x00000ca0 /* PCIE DMA Control Register */

Definition at line 268 of file bcm_70012_regs.h.

#define MISC1_READ_CHANNEL_ERROR_STATUS   0x00000c9c /* Read Channel Error Status */

Definition at line 267 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS   0x00000c18 /* Tx DMA Engine Error Status */

Definition at line 235 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN   0

Definition at line 523 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS   22

Definition at line 524 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK   0xfffffc00

Definition at line 522 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT   10

Definition at line 525 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN   0

Definition at line 535 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS   1

Definition at line 536 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK   0x00000100

Definition at line 534 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT   8

Definition at line 537 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN   0

Definition at line 547 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS   1

Definition at line 548 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK   0x00000040

Definition at line 546 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT   6

Definition at line 549 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN   0

Definition at line 565 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS   1

Definition at line 566 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK   0x00000008

Definition at line 564 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT   3

Definition at line 567 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN   0

Definition at line 583 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS   1

Definition at line 584 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK   0x00000001

Definition at line 582 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT   0

Definition at line 585 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 541 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 542 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080

Definition at line 540 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7

Definition at line 543 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN   0

Definition at line 571 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS   1

Definition at line 572 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK   0x00000004

Definition at line 570 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT   2

Definition at line 573 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 577 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS   1

Definition at line 578 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK   0x00000002

Definition at line 576 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT   1

Definition at line 579 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 529 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 530 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200

Definition at line 528 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9

Definition at line 531 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN   0

Definition at line 553 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS   1

Definition at line 554 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK   0x00000020

Definition at line 552 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT   5

Definition at line 555 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 559 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS   1

Definition at line 560 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK   0x00000010

Definition at line 558 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT   4

Definition at line 561 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM   0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */

Definition at line 238 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR   0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */

Definition at line 236 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR   0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */

Definition at line 237 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM   0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */

Definition at line 241 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR   0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */

Definition at line 239 of file bcm_70012_regs.h.

#define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR   0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */

Definition at line 240 of file bcm_70012_regs.h.

#define MISC1_TX_FIRST_DESC_L_ADDR_LIST0   0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */

Definition at line 230 of file bcm_70012_regs.h.

#define MISC1_TX_FIRST_DESC_L_ADDR_LIST1   0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */

Definition at line 232 of file bcm_70012_regs.h.

#define MISC1_TX_FIRST_DESC_U_ADDR_LIST0   0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */

Definition at line 231 of file bcm_70012_regs.h.

#define MISC1_TX_FIRST_DESC_U_ADDR_LIST1   0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */

Definition at line 233 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS   0x00000c10 /* Tx DMA Software Descriptor List Control and Status */

Definition at line 234 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN   0

Definition at line 501 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS   1

Definition at line 502 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK   0x00000004

Definition at line 500 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT   2

Definition at line 503 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN   0

Definition at line 495 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS   1

Definition at line 496 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK   0x00000008

Definition at line 494 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT   3

Definition at line 497 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN   0

Definition at line 489 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS   28

Definition at line 490 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK   0xfffffff0

Definition at line 488 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT   4

Definition at line 491 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN   0

Definition at line 507 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS   1

Definition at line 508 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK   0x00000002

Definition at line 506 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT   1

Definition at line 509 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN   0

Definition at line 513 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS   1

Definition at line 514 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK   0x00000001

Definition at line 512 of file bcm_70012_regs.h.

#define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT   0

Definition at line 515 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS   0x00000c7c /* UV Rx Engine Error Status */

Definition at line 259 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN   0

Definition at line 675 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS   18

Definition at line 676 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK   0xffffc000

Definition at line 674 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT   14

Definition at line 677 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN   0

Definition at line 711 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS   1

Definition at line 712 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK   0x00000100

Definition at line 710 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT   8

Definition at line 713 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN   0

Definition at line 723 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS   2

Definition at line 724 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK   0x00000060

Definition at line 722 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT   5

Definition at line 725 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN   0

Definition at line 735 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS   2

Definition at line 736 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK   0x0000000c

Definition at line 734 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT   2

Definition at line 737 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN   0

Definition at line 747 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS   1

Definition at line 748 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK   0x00000001

Definition at line 746 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT   0

Definition at line 749 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 717 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 718 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080

Definition at line 716 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7

Definition at line 719 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 741 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS   1

Definition at line 742 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK   0x00000002

Definition at line 740 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT   1

Definition at line 743 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN   0

Definition at line 699 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS   1

Definition at line 700 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK   0x00000400

Definition at line 698 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT   10

Definition at line 701 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN   0

Definition at line 693 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS   1

Definition at line 694 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK   0x00000800

Definition at line 692 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT   11

Definition at line 695 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 705 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 706 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200

Definition at line 704 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9

Definition at line 707 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 729 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS   1

Definition at line 730 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK   0x00000010

Definition at line 728 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT   4

Definition at line 731 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN   0

Definition at line 687 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS   1

Definition at line 688 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK   0x00001000

Definition at line 686 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT   12

Definition at line 689 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN   0

Definition at line 681 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS   1

Definition at line 682 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK   0x00002000

Definition at line 680 of file bcm_70012_regs.h.

#define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT   13

Definition at line 683 of file bcm_70012_regs.h.

#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0   0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */

Definition at line 254 of file bcm_70012_regs.h.

#define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1   0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */

Definition at line 256 of file bcm_70012_regs.h.

#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0   0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */

Definition at line 255 of file bcm_70012_regs.h.

#define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1   0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */

Definition at line 257 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST0_CUR_BYTE_CNT   0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */

Definition at line 262 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR   0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */

Definition at line 260 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR   0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */

Definition at line 261 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST1_CUR_BYTE_CNT   0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */

Definition at line 265 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR   0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */

Definition at line 263 of file bcm_70012_regs.h.

#define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR   0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */

Definition at line 264 of file bcm_70012_regs.h.

#define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS   0x00000c78 /* UV Rx Software Descriptor List Control and Status */

Definition at line 258 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS   0x00000c4c /* Y Rx Engine Error Status */

Definition at line 247 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN   0

Definition at line 593 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS   18

Definition at line 594 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK   0xffffc000

Definition at line 592 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT   14

Definition at line 595 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN   0

Definition at line 629 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS   1

Definition at line 630 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK   0x00000100

Definition at line 628 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT   8

Definition at line 631 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN   0

Definition at line 641 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS   2

Definition at line 642 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK   0x00000060

Definition at line 640 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT   5

Definition at line 643 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN   0

Definition at line 653 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS   2

Definition at line 654 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK   0x0000000c

Definition at line 652 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT   2

Definition at line 655 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN   0

Definition at line 665 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS   1

Definition at line 666 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK   0x00000001

Definition at line 664 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT   0

Definition at line 667 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 635 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 636 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK   0x00000080

Definition at line 634 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT   7

Definition at line 637 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 659 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS   1

Definition at line 660 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK   0x00000002

Definition at line 658 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT   1

Definition at line 661 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN   0

Definition at line 617 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS   1

Definition at line 618 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK   0x00000400

Definition at line 616 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT   10

Definition at line 619 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN   0

Definition at line 611 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS   1

Definition at line 612 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK   0x00000800

Definition at line 610 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT   11

Definition at line 613 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN   0

Definition at line 623 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS   1

Definition at line 624 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK   0x00000200

Definition at line 622 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT   9

Definition at line 625 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN   0

Definition at line 647 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS   1

Definition at line 648 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK   0x00000010

Definition at line 646 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT   4

Definition at line 649 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN   0

Definition at line 605 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS   1

Definition at line 606 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK   0x00001000

Definition at line 604 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT   12

Definition at line 607 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN   0

Definition at line 599 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS   1

Definition at line 600 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK   0x00002000

Definition at line 598 of file bcm_70012_regs.h.

#define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT   13

Definition at line 601 of file bcm_70012_regs.h.

#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0   0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */

Definition at line 242 of file bcm_70012_regs.h.

#define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1   0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */

Definition at line 244 of file bcm_70012_regs.h.

#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0   0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */

Definition at line 243 of file bcm_70012_regs.h.

#define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1   0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */

Definition at line 245 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST0_CUR_BYTE_CNT   0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */

Definition at line 250 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR   0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */

Definition at line 248 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR   0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */

Definition at line 249 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST1_CUR_BYTE_CNT   0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */

Definition at line 253 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR   0x00000c5c /* Y Rx List1 Current Descriptor Lower address */

Definition at line 251 of file bcm_70012_regs.h.

#define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR   0x00000c60 /* Y Rx List1 Current Descriptor Upper address */

Definition at line 252 of file bcm_70012_regs.h.

#define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS   0x00000c44 /* Y Rx Software Descriptor List Control and Status */

Definition at line 246 of file bcm_70012_regs.h.

#define MISC2_DEBUG_FIFO_LENGTH   0x00000d0c /* Debug FIFO Length */

Definition at line 277 of file bcm_70012_regs.h.

#define MISC2_GLOBAL_CTRL   0x00000d00 /* Global Control Register */

Definition at line 274 of file bcm_70012_regs.h.

#define MISC2_INTERNAL_STATUS   0x00000d04 /* Internal Status Register */

Definition at line 275 of file bcm_70012_regs.h.

#define MISC2_INTERNAL_STATUS_MUX_CTRL   0x00000d08 /* Internal Debug Mux Control */

Definition at line 276 of file bcm_70012_regs.h.

#define MISC3_BIST_CTRL   0x00000e04 /* BIST Control Register */

Definition at line 284 of file bcm_70012_regs.h.

#define MISC3_BIST_STATUS   0x00000e08 /* BIST Status Register */

Definition at line 285 of file bcm_70012_regs.h.

#define MISC3_CSI_TEST_CTRL   0x00000e18 /* CSI Test Control Register */

Definition at line 289 of file bcm_70012_regs.h.

#define MISC3_ECO_CTRL_CORE   0x00000e14 /* ECO Core Reset Control Register */

Definition at line 288 of file bcm_70012_regs.h.

#define MISC3_HD_DVI_TEST_CTRL   0x00000e1c /* HD DVI Test Control Register */

Definition at line 290 of file bcm_70012_regs.h.

#define MISC3_RESET_CTRL   0x00000e00 /* Reset Control Register */

Definition at line 283 of file bcm_70012_regs.h.

#define MISC3_RX_CHECKSUM   0x00000e0c /* Receive Checksum */

Definition at line 286 of file bcm_70012_regs.h.

#define MISC3_TX_CHECKSUM   0x00000e10 /* Transmit Checksum */

Definition at line 287 of file bcm_70012_regs.h.

#define MISC_GR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 102 of file bcm_70012_regs.h.

#define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 101 of file bcm_70012_regs.h.

#define MISC_PERST_CCE_STATUS   0x00000e88 /* Config Copy Engine Status */

Definition at line 298 of file bcm_70012_regs.h.

#define MISC_PERST_CLOCK_CTRL   0x00000e9c /* Clock Control Register */

Definition at line 303 of file bcm_70012_regs.h.

#define MISC_PERST_DECODER_CTRL   0x00000e84 /* Decoder Control Register */

Definition at line 297 of file bcm_70012_regs.h.

#define MISC_PERST_ECO_CTRL_PERST   0x00000e80 /* ECO PCIE Reset Control Register */

Definition at line 296 of file bcm_70012_regs.h.

#define MISC_PERST_MEM_CTRL   0x00000e98 /* Memory Control Register */

Definition at line 302 of file bcm_70012_regs.h.

#define MISC_PERST_PCIE_DEBUG   0x00000e8c /* PCIE Debug Control Register */

Definition at line 299 of file bcm_70012_regs.h.

#define MISC_PERST_PCIE_DEBUG_STATUS   0x00000e90 /* PCIE Debug Status Register */

Definition at line 300 of file bcm_70012_regs.h.

#define MISC_PERST_VREG_CTRL   0x00000e94 /* Voltage Regulator Control Register */

Definition at line 301 of file bcm_70012_regs.h.

#define OTP_CMD   0x00001404 /* OTP Command Register */

Definition at line 319 of file bcm_70012_regs.h.

#define OTP_CONFIG_INFO   0x00001400 /* OTP Configuration Register */

Definition at line 318 of file bcm_70012_regs.h.

#define OTP_CONTENT_AES_0   0x00001410 /* Content : AES Key 0 Register */

Definition at line 322 of file bcm_70012_regs.h.

#define OTP_CONTENT_AES_1   0x00001414 /* Content : AES Key 1 Register */

Definition at line 323 of file bcm_70012_regs.h.

#define OTP_CONTENT_AES_2   0x00001418 /* Content : AES Key 2 Register */

Definition at line 324 of file bcm_70012_regs.h.

#define OTP_CONTENT_AES_3   0x0000141c /* Content : AES Key 3 Register */

Definition at line 325 of file bcm_70012_regs.h.

#define OTP_CONTENT_CHECKSUM   0x00001440 /* Content : Checksum Register */

Definition at line 334 of file bcm_70012_regs.h.

#define OTP_CONTENT_MISC   0x0000140c /* Content : Miscellaneous Register */

Definition at line 321 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_0   0x00001420 /* Content : SHA Key 0 Register */

Definition at line 326 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_1   0x00001424 /* Content : SHA Key 1 Register */

Definition at line 327 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_2   0x00001428 /* Content : SHA Key 2 Register */

Definition at line 328 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_3   0x0000142c /* Content : SHA Key 3 Register */

Definition at line 329 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_4   0x00001430 /* Content : SHA Key 4 Register */

Definition at line 330 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_5   0x00001434 /* Content : SHA Key 5 Register */

Definition at line 331 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_6   0x00001438 /* Content : SHA Key 6 Register */

Definition at line 332 of file bcm_70012_regs.h.

#define OTP_CONTENT_SHA_7   0x0000143c /* Content : SHA Key 7 Register */

Definition at line 333 of file bcm_70012_regs.h.

#define OTP_DATA_INPUT   0x00001458 /* Data Input Register */

Definition at line 340 of file bcm_70012_regs.h.

#define OTP_DATA_OUTPUT   0x0000145c /* Data Output Register */

Definition at line 341 of file bcm_70012_regs.h.

#define OTP_GR_BRIDGE_RESET_CTRL_ASSERT   1

Definition at line 108 of file bcm_70012_regs.h.

#define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT   0

Definition at line 107 of file bcm_70012_regs.h.

#define OTP_PROG_CTRL   0x00001444 /* Programming Control Register */

Definition at line 335 of file bcm_70012_regs.h.

#define OTP_PROG_MASK   0x00001454 /* Program Mask Register */

Definition at line 339 of file bcm_70012_regs.h.

#define OTP_PROG_PULSE   0x0000144c /* Program Pulse Width Register */

Definition at line 337 of file bcm_70012_regs.h.

#define OTP_PROG_STATUS   0x00001448 /* Programming Status Register */

Definition at line 336 of file bcm_70012_regs.h.

#define OTP_STATUS   0x00001408 /* OTP Status Register */

Definition at line 320 of file bcm_70012_regs.h.

#define OTP_VERIFY_PULSE   0x00001450 /* Verify Pulse Width Register */

Definition at line 338 of file bcm_70012_regs.h.

#define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL   0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */

Definition at line 175 of file bcm_70012_regs.h.

#define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER   0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */

Definition at line 169 of file bcm_70012_regs.h.

#define PCIE_CFG_BASE_ADDRESS_1   0x00000010 /* BASE_ADDRESS_1 Register */

Definition at line 117 of file bcm_70012_regs.h.

#define PCIE_CFG_BASE_ADDRESS_2   0x00000014 /* BASE_ADDRESS_2 Register */

Definition at line 118 of file bcm_70012_regs.h.

#define PCIE_CFG_BASE_ADDRESS_3   0x00000018 /* BASE_ADDRESS_3 Register */

Definition at line 119 of file bcm_70012_regs.h.

#define PCIE_CFG_BASE_ADDRESS_4   0x0000001c /* BASE_ADDRESS_4 Register */

Definition at line 120 of file bcm_70012_regs.h.

#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE   0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */

Definition at line 116 of file bcm_70012_regs.h.

#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER   0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */

Definition at line 134 of file bcm_70012_regs.h.

#define PCIE_CFG_CAPABILITIES_POINTER   0x00000034 /* CAPABILITIES_POINTER Register */

Definition at line 124 of file bcm_70012_regs.h.

#define PCIE_CFG_CARDBUS_CIS_POINTER   0x00000028 /* CARDBUS_CIS_POINTER Register */

Definition at line 121 of file bcm_70012_regs.h.

#define PCIE_CFG_CLOCK_CONTROL   0x00000074 /* CLOCK_CONTROL Register */

Definition at line 139 of file bcm_70012_regs.h.

#define PCIE_CFG_CORRECTABLE_ERROR_MASK   0x00000114 /* CORRECTABLE_ERROR_MASK Register */

Definition at line 174 of file bcm_70012_regs.h.

#define PCIE_CFG_CORRECTABLE_ERROR_STATUS   0x00000110 /* CORRECTABLE_ERROR_STATUS Register */

Definition at line 173 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_CAPABILITIES   0x000000d0 /* DEVICE_CAPABILITIES Register */

Definition at line 161 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_CAPABILITIES_2   0x000000f0 /* DEVICE_CAPABILITIES_2 Register */

Definition at line 165 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER   0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */

Definition at line 187 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW   0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */

Definition at line 188 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW   0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */

Definition at line 189 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_STATUS_CONTROL   0x000000d4 /* DEVICE_STATUS_CONTROL Register */

Definition at line 162 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_STATUS_CONTROL_2   0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */

Definition at line 166 of file bcm_70012_regs.h.

#define PCIE_CFG_DEVICE_VENDOR_ID   0x00000000 /* DEVICE_VENDOR_ID Register */

Definition at line 113 of file bcm_70012_regs.h.

#define PCIE_CFG_EXPANSION_ROM_ADDRESS   0x0000008c /* EXPANSION_ROM_ADDRESS Register */

Definition at line 145 of file bcm_70012_regs.h.

#define PCIE_CFG_EXPANSION_ROM_BAR_SIZE   0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */

Definition at line 144 of file bcm_70012_regs.h.

#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS   0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */

Definition at line 123 of file bcm_70012_regs.h.

#define PCIE_CFG_EXPANSION_ROM_DATA   0x00000090 /* EXPANSION_ROM_DATA Register */

Definition at line 146 of file bcm_70012_regs.h.

#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1   0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */

Definition at line 194 of file bcm_70012_regs.h.

#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3   0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */

Definition at line 195 of file bcm_70012_regs.h.

#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5   0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */

Definition at line 196 of file bcm_70012_regs.h.

#define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7   0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */

Definition at line 197 of file bcm_70012_regs.h.

#define PCIE_CFG_FUNCTION_EVENT   0x000000c0 /* FUNCTION_EVENT Register */

Definition at line 157 of file bcm_70012_regs.h.

#define PCIE_CFG_FUNCTION_EVENT_MASK   0x000000c4 /* FUNCTION_EVENT_MASK Register */

Definition at line 158 of file bcm_70012_regs.h.

#define PCIE_CFG_FUNCTION_PRESENT   0x000000c8 /* FUNCTION_PRESENT Register */

Definition at line 159 of file bcm_70012_regs.h.

#define PCIE_CFG_HEADER_LOG_1   0x0000011c /* HEADER_LOG_1 Register */

Definition at line 176 of file bcm_70012_regs.h.

#define PCIE_CFG_HEADER_LOG_2   0x00000120 /* HEADER_LOG_2 Register */

Definition at line 177 of file bcm_70012_regs.h.

#define PCIE_CFG_HEADER_LOG_3   0x00000124 /* HEADER_LOG_3 Register */

Definition at line 178 of file bcm_70012_regs.h.

#define PCIE_CFG_HEADER_LOG_4   0x00000128 /* HEADER_LOG_4 Register */

Definition at line 179 of file bcm_70012_regs.h.

#define PCIE_CFG_INT_MAILBOX_LOWER   0x000000b4 /* INT_MAILBOX_LOWER Register */

Definition at line 155 of file bcm_70012_regs.h.

#define PCIE_CFG_INT_MAILBOX_UPPER   0x000000b0 /* INT_MAILBOX_UPPER Register */

Definition at line 154 of file bcm_70012_regs.h.

#define PCIE_CFG_INTERRUPT   0x0000003c /* INTERRUPT Register */

Definition at line 125 of file bcm_70012_regs.h.

#define PCIE_CFG_LINK_CAPABILITIES_2   0x000000f8 /* LINK_CAPABILITIES_2 Register */

Definition at line 167 of file bcm_70012_regs.h.

#define PCIE_CFG_LINK_CAPABILITY   0x000000d8 /* LINK_CAPABILITY Register */

Definition at line 163 of file bcm_70012_regs.h.

#define PCIE_CFG_LINK_STATUS_CONTROL   0x000000dc /* LINK_STATUS_CONTROL Register */

Definition at line 164 of file bcm_70012_regs.h.

#define PCIE_CFG_LINK_STATUS_CONTROL_2   0x000000fc /* LINK_STATUS_CONTROL_2 Register */

Definition at line 168 of file bcm_70012_regs.h.

#define PCIE_CFG_MEMORY_BASE   0x0000007c /* MEMORY_BASE Register */

Definition at line 141 of file bcm_70012_regs.h.

#define PCIE_CFG_MEMORY_DATA   0x00000084 /* MEMORY_DATA Register */

Definition at line 143 of file bcm_70012_regs.h.

#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL   0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */

Definition at line 136 of file bcm_70012_regs.h.

#define PCIE_CFG_MSI_CAPABILITY_HEADER   0x00000050 /* MSI_CAPABILITY_HEADER Register */

Definition at line 130 of file bcm_70012_regs.h.

#define PCIE_CFG_MSI_DATA   0x0000005c /* MSI_DATA Register */

Definition at line 133 of file bcm_70012_regs.h.

#define PCIE_CFG_MSI_LOWER_ADDRESS   0x00000054 /* MSI_LOWER_ADDRESS Register */

Definition at line 131 of file bcm_70012_regs.h.

#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER   0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */

Definition at line 132 of file bcm_70012_regs.h.

#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID   0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */

Definition at line 115 of file bcm_70012_regs.h.

#define PCIE_CFG_PCI_STATE   0x00000070 /* PCI_STATE Register */

Definition at line 138 of file bcm_70012_regs.h.

#define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING   0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */

Definition at line 198 of file bcm_70012_regs.h.

#define PCIE_CFG_PCIE_CAPABILITIES   0x000000cc /* PCIE_CAPABILITIES Register */

Definition at line 160 of file bcm_70012_regs.h.

#define PCIE_CFG_PORT_VC_CAPABILITY   0x00000140 /* PORT_VC_CAPABILITY Register */

Definition at line 181 of file bcm_70012_regs.h.

#define PCIE_CFG_PORT_VC_CAPABILITY_2   0x00000144 /* PORT_VC_CAPABILITY_2 Register */

Definition at line 182 of file bcm_70012_regs.h.

#define PCIE_CFG_PORT_VC_STATUS_CONTROL   0x00000148 /* PORT_VC_STATUS_CONTROL Register */

Definition at line 183 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_BUDGETING_CAPABILITY   0x00000178 /* POWER_BUDGETING_CAPABILITY Register */

Definition at line 193 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_BUDGETING_DATA   0x00000174 /* POWER_BUDGETING_DATA Register */

Definition at line 192 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_BUDGETING_DATA_SELECT   0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */

Definition at line 191 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER   0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */

Definition at line 190 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY   0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */

Definition at line 128 of file bcm_70012_regs.h.

#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS   0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */

Definition at line 129 of file bcm_70012_regs.h.

#define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION   0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */

Definition at line 156 of file bcm_70012_regs.h.

#define PCIE_CFG_REGISTER_BASE   0x00000078 /* REGISTER_BASE Register */

Definition at line 140 of file bcm_70012_regs.h.

#define PCIE_CFG_REGISTER_DATA   0x00000080 /* REGISTER_DATA Register */

Definition at line 142 of file bcm_70012_regs.h.

#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES   0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */

Definition at line 135 of file bcm_70012_regs.h.

#define PCIE_CFG_SPARE   0x0000006c /* SPARE Register */

Definition at line 137 of file bcm_70012_regs.h.

#define PCIE_CFG_STATUS_COMMAND   0x00000004 /* STATUS_COMMAND Register */

Definition at line 114 of file bcm_70012_regs.h.

#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID   0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */

Definition at line 122 of file bcm_70012_regs.h.

#define PCIE_CFG_UNCORRECTABLE_ERROR_MASK   0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */

Definition at line 171 of file bcm_70012_regs.h.

#define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY   0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */

Definition at line 172 of file bcm_70012_regs.h.

#define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS   0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */

Definition at line 170 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER   0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */

Definition at line 149 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER   0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */

Definition at line 148 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER   0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */

Definition at line 151 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER   0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */

Definition at line 150 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER   0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */

Definition at line 153 of file bcm_70012_regs.h.

#define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER   0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */

Definition at line 152 of file bcm_70012_regs.h.

#define PCIE_CFG_VC_RESOURCE_CAPABILITY   0x0000014c /* VC_RESOURCE_CAPABILITY Register */

Definition at line 184 of file bcm_70012_regs.h.

#define PCIE_CFG_VC_RESOURCE_CONTROL   0x00000150 /* VC_RESOURCE_CONTROL Register */

Definition at line 185 of file bcm_70012_regs.h.

#define PCIE_CFG_VC_RESOURCE_STATUS   0x00000154 /* VC_RESOURCE_STATUS Register */

Definition at line 186 of file bcm_70012_regs.h.

#define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER   0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */

Definition at line 180 of file bcm_70012_regs.h.

#define PCIE_CFG_VPD_CAPABILITIES   0x00000040 /* VPD_CAPABILITIES Register */

Definition at line 126 of file bcm_70012_regs.h.

#define PCIE_CFG_VPD_DATA   0x00000044 /* VPD_DATA Register */

Definition at line 127 of file bcm_70012_regs.h.

#define PCIE_CFG_VPD_INTERFACE   0x00000094 /* VPD_INTERFACE Register */

Definition at line 147 of file bcm_70012_regs.h.

#define PCIE_DLL_DATA_LINK_CONTROL   0x00000500 /* DATA_LINK_CONTROL Register */

Definition at line 211 of file bcm_70012_regs.h.

#define PCIE_DLL_DATA_LINK_STATUS   0x00000504 /* DATA_LINK_STATUS Register */

Definition at line 212 of file bcm_70012_regs.h.

#define PCIE_TL_TL_CONTROL   0x00000400 /* TL_CONTROL Register */

Definition at line 204 of file bcm_70012_regs.h.

#define PCIE_TL_TRANSACTION_CONFIGURATION   0x00000404 /* TRANSACTION_CONFIGURATION Register */

Definition at line 205 of file bcm_70012_regs.h.

#define SET_FIELD (   m,
  c,
  r,
  f,
  d 
)
Value:
((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \
BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \
)

Definition at line 36 of file bcm_70012_regs.h.

#define SET_NAME_FIELD (   m,
  c,
  r,
  f,
  d 
)    SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)

Definition at line 42 of file bcm_70012_regs.h.

#define SET_TYPE_FIELD (   m,
  c,
  r,
  f,
  d 
)    SET_FIELD(m, c, r, f, c##_##d)

Definition at line 41 of file bcm_70012_regs.h.

#define SET_VALUE_FIELD (   m,
  c,
  r,
  f,
  d 
)    SET_FIELD(m, c, r, f, d)

Definition at line 43 of file bcm_70012_regs.h.

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