Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
be_hw.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2005 - 2011 Emulex
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation. The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Contact Information:
11  * [email protected]
12  *
13  * Emulex
14  * 3333 Susan Street
15  * Costa Mesa, CA 92626
16  */
17 
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20  * The software must write this register twice to post any command. First,
21  * it writes the register with hi=1 and the upper bits of the physical address
22  * for the MAILBOX structure. Software must poll the ready bit until this
23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24  * bits in the address. It must poll the ready bit until the command is
25  * complete. Upon completion, the MAILBOX will contain a valid completion
26  * queue entry.
27  */
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
31 
32 #define MPU_EP_CONTROL 0
33 
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400
37 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
38 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
39 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
40 
41 /* MPU semphore POST stage values */
42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
46 
47 
48 /* Lancer SLIPORT registers */
49 #define SLIPORT_STATUS_OFFSET 0x404
50 #define SLIPORT_CONTROL_OFFSET 0x408
51 #define SLIPORT_ERROR1_OFFSET 0x40C
52 #define SLIPORT_ERROR2_OFFSET 0x410
53 #define PHYSDEV_CONTROL_OFFSET 0x414
54 
55 #define SLIPORT_STATUS_ERR_MASK 0x80000000
56 #define SLIPORT_STATUS_RN_MASK 0x01000000
57 #define SLIPORT_STATUS_RDY_MASK 0x00800000
58 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
59 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
60 #define PHYSDEV_CONTROL_INP_MASK 0x40000000
61 
62 /********* Memory BAR register ************/
63 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
64 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
65  * Disable" may still globally block interrupts in addition to individual
66  * interrupt masks; a mechanism for the device driver to block all interrupts
67  * atomically without having to arbitrate for the PCI Interrupt Disable bit
68  * with the OS.
69  */
70 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
71 
72 /********* Power management (WOL) **********/
73 #define PCICFG_PM_CONTROL_OFFSET 0x44
74 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
75 
76 /********* Online Control Registers *******/
77 #define PCICFG_ONLINE0 0xB0
78 #define PCICFG_ONLINE1 0xB4
79 
80 /********* UE Status and Mask Registers ***/
81 #define PCICFG_UE_STATUS_LOW 0xA0
82 #define PCICFG_UE_STATUS_HIGH 0xA4
83 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
84 #define PCICFG_UE_STATUS_HI_MASK 0xAC
85 
86 /******** SLI_INTF ***********************/
87 #define SLI_INTF_REG_OFFSET 0x58
88 #define SLI_INTF_VALID_MASK 0xE0000000
89 #define SLI_INTF_VALID 0xC0000000
90 #define SLI_INTF_HINT2_MASK 0x1F000000
91 #define SLI_INTF_HINT2_SHIFT 24
92 #define SLI_INTF_HINT1_MASK 0x00FF0000
93 #define SLI_INTF_HINT1_SHIFT 16
94 #define SLI_INTF_FAMILY_MASK 0x00000F00
95 #define SLI_INTF_FAMILY_SHIFT 8
96 #define SLI_INTF_IF_TYPE_MASK 0x0000F000
97 #define SLI_INTF_IF_TYPE_SHIFT 12
98 #define SLI_INTF_REV_MASK 0x000000F0
99 #define SLI_INTF_REV_SHIFT 4
100 #define SLI_INTF_FT_MASK 0x00000001
101 
102 #define SLI_INTF_TYPE_2 2
103 #define SLI_INTF_TYPE_3 3
104 
105 /* SLI family */
106 #define BE_SLI_FAMILY 0x0
107 #define LANCER_A0_SLI_FAMILY 0xA
108 #define SKYHAWK_SLI_FAMILY 0x2
109 
110 /********* ISR0 Register offset **********/
111 #define CEV_ISR0_OFFSET 0xC18
112 #define CEV_ISR_SIZE 4
113 
114 /********* Event Q door bell *************/
115 #define DB_EQ_OFFSET DB_CQ_OFFSET
116 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
117 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
118 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
119 
120 /* Clear the interrupt for this eq */
121 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
122 /* Must be 1 */
123 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
124 /* Number of event entries processed */
125 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
126 /* Rearm bit */
127 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
128 
129 /********* Compl Q door bell *************/
130 #define DB_CQ_OFFSET 0x120
131 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
132 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
133 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
134  placing at 11-15 */
135 
136 /* Number of event entries processed */
137 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
138 /* Rearm bit */
139 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
140 
141 /********** TX ULP door bell *************/
142 #define DB_TXULP1_OFFSET 0x60
143 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
144 /* Number of tx entries posted */
145 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
146 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
147 
148 /********** RQ(erx) door bell ************/
149 #define DB_RQ_OFFSET 0x100
150 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
151 /* Number of rx frags posted */
152 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
153 
154 /********** MCC door bell ************/
155 #define DB_MCCQ_OFFSET 0x140
156 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
157 /* Number of entries posted */
158 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
159 
160 /********** SRIOV VF PCICFG OFFSET ********/
161 #define SRIOV_VF_PCICFG_OFFSET (4096)
162 
163 /********** FAT TABLE ********/
164 #define RETRIEVE_FAT 0
165 #define QUERY_FAT 1
166 
167 /* Flashrom related descriptors */
168 #define MAX_FLASH_COMP 32
169 #define IMAGE_TYPE_FIRMWARE 160
170 #define IMAGE_TYPE_BOOTCODE 224
171 #define IMAGE_TYPE_OPTIONROM 32
172 
173 #define NUM_FLASHDIR_ENTRIES 32
174 
175 #define OPTYPE_ISCSI_ACTIVE 0
176 #define OPTYPE_REDBOOT 1
177 #define OPTYPE_BIOS 2
178 #define OPTYPE_PXE_BIOS 3
179 #define OPTYPE_FCOE_BIOS 8
180 #define OPTYPE_ISCSI_BACKUP 9
181 #define OPTYPE_FCOE_FW_ACTIVE 10
182 #define OPTYPE_FCOE_FW_BACKUP 11
183 #define OPTYPE_NCSI_FW 13
184 #define OPTYPE_PHY_FW 99
185 #define TN_8022 13
186 
187 #define ILLEGAL_IOCTL_REQ 2
188 #define FLASHROM_OPER_PHY_FLASH 9
189 #define FLASHROM_OPER_PHY_SAVE 10
190 #define FLASHROM_OPER_FLASH 1
191 #define FLASHROM_OPER_SAVE 2
192 #define FLASHROM_OPER_REPORT 4
193 
194 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */
195 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */
196 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
197 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */
198 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */
199 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
200 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144)
201 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
202 
203 #define FLASH_NCSI_MAGIC (0x16032009)
204 #define FLASH_NCSI_DISABLED (0)
205 #define FLASH_NCSI_ENABLED (1)
206 
207 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
208 
209 /* Offsets for components on Flash. */
210 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
211 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
212 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
213 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
214 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
215 #define FLASH_PXE_BIOS_START_g2 (7864320)
216 #define FLASH_FCoE_BIOS_START_g2 (524288)
217 #define FLASH_REDBOOT_START_g2 (0)
218 
219 #define FLASH_NCSI_START_g3 (15990784)
220 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
221 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
222 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
223 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
224 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
225 #define FLASH_PXE_BIOS_START_g3 (13107200)
226 #define FLASH_FCoE_BIOS_START_g3 (13631488)
227 #define FLASH_REDBOOT_START_g3 (262144)
228 #define FLASH_PHY_FW_START_g3 1310720
229 
230 #define IMAGE_NCSI 16
231 #define IMAGE_OPTION_ROM_PXE 32
232 #define IMAGE_OPTION_ROM_FCoE 33
233 #define IMAGE_OPTION_ROM_ISCSI 34
234 #define IMAGE_FLASHISM_JUMPVECTOR 48
235 #define IMAGE_FLASH_ISM 49
236 #define IMAGE_JUMP_VECTOR 50
237 #define IMAGE_FIRMWARE_iSCSI 160
238 #define IMAGE_FIRMWARE_COMP_iSCSI 161
239 #define IMAGE_FIRMWARE_FCoE 162
240 #define IMAGE_FIRMWARE_COMP_FCoE 163
241 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176
242 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
243 #define IMAGE_FIRMWARE_BACKUP_FCoE 178
244 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
245 #define IMAGE_FIRMWARE_PHY 192
246 #define IMAGE_BOOT_CODE 224
247 
248 /************* Rx Packet Type Encoding **************/
249 #define BE_UNICAST_PACKET 0
250 #define BE_MULTICAST_PACKET 1
251 #define BE_BROADCAST_PACKET 2
252 #define BE_RSVD_PACKET 3
253 
254 /*
255  * BE descriptors: host memory data structures whose formats
256  * are hardwired in BE silicon.
257  */
258 /* Event Queue Descriptor */
259 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
260 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
261 #define EQ_ENTRY_RES_ID_SHIFT 16
262 
263 struct be_eq_entry {
264  u32 evt;
265 };
266 
267 /* TX Queue Descriptor */
268 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
269 struct be_eth_wrb {
270  u32 frag_pa_hi; /* dword 0 */
271  u32 frag_pa_lo; /* dword 1 */
272  u32 rsvd0; /* dword 2 */
273  u32 frag_len; /* dword 3: bits 0 - 15 */
274 } __packed;
275 
276 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
277  * actual structure is defined as a byte : used to calculate
278  * offset/shift/mask of each field */
279 struct amap_eth_hdr_wrb {
280  u8 rsvd0[32]; /* dword 0 */
281  u8 rsvd1[32]; /* dword 1 */
282  u8 complete; /* dword 2 */
283  u8 event;
284  u8 crc;
285  u8 forward;
286  u8 lso6;
287  u8 mgmt;
288  u8 ipcs;
289  u8 udpcs;
290  u8 tcpcs;
291  u8 lso;
292  u8 vlan;
293  u8 gso[2];
294  u8 num_wrb[5];
295  u8 lso_mss[14];
296  u8 len[16]; /* dword 3 */
297  u8 vlan_tag[16];
298 } __packed;
299 
300 struct be_eth_hdr_wrb {
301  u32 dw[4];
302 };
303 
304 /* TX Compl Queue Descriptor */
305 
306 /* Pseudo amap definition for eth_tx_compl in which each bit of the
307  * actual structure is defined as a byte: used to calculate
308  * offset/shift/mask of each field */
309 struct amap_eth_tx_compl {
310  u8 wrb_index[16]; /* dword 0 */
311  u8 ct[2]; /* dword 0 */
312  u8 port[2]; /* dword 0 */
313  u8 rsvd0[8]; /* dword 0 */
314  u8 status[4]; /* dword 0 */
315  u8 user_bytes[16]; /* dword 1 */
316  u8 nwh_bytes[8]; /* dword 1 */
317  u8 lso; /* dword 1 */
318  u8 cast_enc[2]; /* dword 1 */
319  u8 rsvd1[5]; /* dword 1 */
320  u8 rsvd2[32]; /* dword 2 */
321  u8 pkts[16]; /* dword 3 */
322  u8 ringid[11]; /* dword 3 */
323  u8 hash_val[4]; /* dword 3 */
324  u8 valid; /* dword 3 */
325 } __packed;
326 
327 struct be_eth_tx_compl {
328  u32 dw[4];
329 };
330 
331 /* RX Queue Descriptor */
332 struct be_eth_rx_d {
333  u32 fragpa_hi;
334  u32 fragpa_lo;
335 };
336 
337 /* RX Compl Queue Descriptor */
338 
339 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
340  * each bit of the actual structure is defined as a byte: used to calculate
341  * offset/shift/mask of each field */
342 struct amap_eth_rx_compl_v0 {
343  u8 vlan_tag[16]; /* dword 0 */
344  u8 pktsize[14]; /* dword 0 */
345  u8 port; /* dword 0 */
346  u8 ip_opt; /* dword 0 */
347  u8 err; /* dword 1 */
348  u8 rsshp; /* dword 1 */
349  u8 ipf; /* dword 1 */
350  u8 tcpf; /* dword 1 */
351  u8 udpf; /* dword 1 */
352  u8 ipcksm; /* dword 1 */
353  u8 l4_cksm; /* dword 1 */
354  u8 ip_version; /* dword 1 */
355  u8 macdst[6]; /* dword 1 */
356  u8 vtp; /* dword 1 */
357  u8 rsvd0; /* dword 1 */
358  u8 fragndx[10]; /* dword 1 */
359  u8 ct[2]; /* dword 1 */
360  u8 sw; /* dword 1 */
361  u8 numfrags[3]; /* dword 1 */
362  u8 rss_flush; /* dword 2 */
363  u8 cast_enc[2]; /* dword 2 */
364  u8 vtm; /* dword 2 */
365  u8 rss_bank; /* dword 2 */
366  u8 rsvd1[23]; /* dword 2 */
367  u8 lro_pkt; /* dword 2 */
368  u8 rsvd2[2]; /* dword 2 */
369  u8 valid; /* dword 2 */
370  u8 rsshash[32]; /* dword 3 */
371 } __packed;
372 
373 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
374  * each bit of the actual structure is defined as a byte: used to calculate
375  * offset/shift/mask of each field */
376 struct amap_eth_rx_compl_v1 {
377  u8 vlan_tag[16]; /* dword 0 */
378  u8 pktsize[14]; /* dword 0 */
379  u8 vtp; /* dword 0 */
380  u8 ip_opt; /* dword 0 */
381  u8 err; /* dword 1 */
382  u8 rsshp; /* dword 1 */
383  u8 ipf; /* dword 1 */
384  u8 tcpf; /* dword 1 */
385  u8 udpf; /* dword 1 */
386  u8 ipcksm; /* dword 1 */
387  u8 l4_cksm; /* dword 1 */
388  u8 ip_version; /* dword 1 */
389  u8 macdst[7]; /* dword 1 */
390  u8 rsvd0; /* dword 1 */
391  u8 fragndx[10]; /* dword 1 */
392  u8 ct[2]; /* dword 1 */
393  u8 sw; /* dword 1 */
394  u8 numfrags[3]; /* dword 1 */
395  u8 rss_flush; /* dword 2 */
396  u8 cast_enc[2]; /* dword 2 */
397  u8 vtm; /* dword 2 */
398  u8 rss_bank; /* dword 2 */
399  u8 port[2]; /* dword 2 */
400  u8 vntagp; /* dword 2 */
401  u8 header_len[8]; /* dword 2 */
402  u8 header_split[2]; /* dword 2 */
403  u8 rsvd1[13]; /* dword 2 */
404  u8 valid; /* dword 2 */
405  u8 rsshash[32]; /* dword 3 */
406 } __packed;
407 
408 struct be_eth_rx_compl {
409  u32 dw[4];
410 };
411 
412 struct mgmt_hba_attribs {
413  u8 flashrom_version_string[32];
414  u8 manufacturer_name[32];
415  u32 supported_modes;
416  u32 rsvd0[3];
417  u8 ncsi_ver_string[12];
418  u32 default_extended_timeout;
419  u8 controller_model_number[32];
420  u8 controller_description[64];
421  u8 controller_serial_number[32];
422  u8 ip_version_string[32];
423  u8 firmware_version_string[32];
424  u8 bios_version_string[32];
425  u8 redboot_version_string[32];
426  u8 driver_version_string[32];
427  u8 fw_on_flash_version_string[32];
428  u32 functionalities_supported;
429  u16 max_cdblength;
430  u8 asic_revision;
431  u8 generational_guid[16];
432  u8 hba_port_count;
433  u16 default_link_down_timeout;
434  u8 iscsi_ver_min_max;
435  u8 multifunction_device;
436  u8 cache_valid;
437  u8 hba_status;
438  u8 max_domains_supported;
439  u8 phy_port;
440  u32 firmware_post_status;
441  u32 hba_mtu[8];
442  u32 rsvd1[4];
443 };
444 
445 struct mgmt_controller_attrib {
446  struct mgmt_hba_attribs hba_attribs;
447  u16 pci_vendor_id;
448  u16 pci_device_id;
449  u16 pci_sub_vendor_id;
450  u16 pci_sub_system_id;
451  u8 pci_bus_number;
452  u8 pci_device_number;
453  u8 pci_function_number;
454  u8 interface_type;
455  u64 unique_identifier;
456  u32 rsvd0[5];
457 };
458 
459 struct controller_id {
460  u32 vendor;
461  u32 device;
462  u32 subvendor;
463  u32 subdevice;
464 };
465 
466 struct flash_comp {
467  unsigned long offset;
468  int optype;
469  int size;
470  int img_type;
471 };
472 
473 struct image_hdr {
474  u32 imageid;
475  u32 imageoffset;
476  u32 imagelength;
477  u32 image_checksum;
478  u8 image_version[32];
479 };
480 struct flash_file_hdr_g2 {
481  u8 sign[32];
482  u32 cksum;
483  u32 antidote;
484  struct controller_id cont_id;
485  u32 file_len;
486  u32 chunk_num;
487  u32 total_chunks;
488  u32 num_imgs;
489  u8 build[24];
490 };
491 
492 struct flash_file_hdr_g3 {
493  u8 sign[52];
494  u8 ufi_version[4];
495  u32 file_len;
496  u32 cksum;
497  u32 antidote;
498  u32 num_imgs;
499  u8 build[24];
500  u8 rsvd[32];
501 };
502 
503 struct flash_section_hdr {
504  u32 format_rev;
505  u32 cksum;
506  u32 antidote;
507  u32 num_images;
508  u8 id_string[128];
509  u32 rsvd[4];
510 } __packed;
511 
512 struct flash_section_hdr_g2 {
513  u32 format_rev;
514  u32 cksum;
515  u32 antidote;
516  u32 build_num;
517  u8 id_string[128];
518  u32 rsvd[8];
519 } __packed;
520 
521 struct flash_section_entry {
522  u32 type;
523  u32 offset;
524  u32 pad_size;
525  u32 image_size;
526  u32 cksum;
527  u32 entry_point;
528  u32 rsvd0;
529  u32 rsvd1;
530  u8 ver_data[32];
531 } __packed;
532 
533 struct flash_section_info {
534  u8 cookie[32];
535  struct flash_section_hdr fsec_hdr;
536  struct flash_section_entry fsec_entry[32];
537 } __packed;
538 
539 struct flash_section_info_g2 {
540  u8 cookie[32];
541  struct flash_section_hdr_g2 fsec_hdr;
542  struct flash_section_entry fsec_entry[32];
543 } __packed;
Generated on Thu Jan 10 2013 14:01:06 for Linux Kernel by   doxygen 1.8.2