|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <linux/types.h>Go to the source code of this file.
Data Structures | |
| struct | bfin_spi_regs |
| struct | bfin6xx_spi_master |
| struct | bfin6xx_spi_chip |
Macros | |
| #define | SPI_CTL_EN 0x00000001 /* Enable */ |
| #define | SPI_CTL_MSTR 0x00000002 /* Master/Slave */ |
| #define | SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ |
| #define | SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ |
| #define | SPI_CTL_CPHA 0x00000010 /* Clock Phase */ |
| #define | SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ |
| #define | SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ |
| #define | SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ |
| #define | SPI_CTL_EMISO 0x00000100 /* Enable MISO */ |
| #define | SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ |
| #define | SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ |
| #define | SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ |
| #define | SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ |
| #define | SPI_CTL_LSBF 0x00001000 /* LSB First */ |
| #define | SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ |
| #define | SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ |
| #define | SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ |
| #define | SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ |
| #define | SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ |
| #define | SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ |
| #define | SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ |
| #define | SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ |
| #define | SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ |
| #define | SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ |
| #define | SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ |
| #define | SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ |
| #define | SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ |
| #define | SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ |
| #define | SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ |
| #define | SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ |
| #define | SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ |
| #define | SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ |
| #define | SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ |
| #define | SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ |
| #define | SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ |
| #define | SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ |
| #define | SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ |
| #define | SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ |
| #define | SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ |
| #define | SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ |
| #define | SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ |
| #define | SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ |
| #define | SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ |
| #define | SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ |
| #define | SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ |
| #define | SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ |
| #define | SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ |
| #define | SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ |
| #define | SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ |
| #define | SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ |
| #define | SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ |
| #define | SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ |
| #define | SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ |
| #define | SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ |
| #define | SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ |
| #define | SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ |
| #define | SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ |
| #define | SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ |
| #define | SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ |
| #define | SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ |
| #define | SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ |
| #define | SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ |
| #define | SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ |
| #define | SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ |
| #define | SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ |
| #define | SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ |
| #define | SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ |
| #define | SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ |
| #define | SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ |
| #define | SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ |
| #define | SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ |
| #define | SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ |
| #define | SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ |
| #define | SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ |
| #define | SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ |
| #define | SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ |
| #define | SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ |
| #define | SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ |
| #define | SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ |
| #define | SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ |
| #define | SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ |
| #define | SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ |
| #define | SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ |
| #define | SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ |
| #define | SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ |
| #define | SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ |
| #define | SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ |
| #define | SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ |
| #define | SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ |
| #define | SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ |
| #define | SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ |
| #define | SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ |
| #define | SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ |
| #define | SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
| #define | SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
| #define | SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
| #define | SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
| #define | SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
| #define | SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
| #define | SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
| #define | SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
| #define | SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
| #define | SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
| #define | SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
| #define | SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
| #define | SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
| #define | SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
| #define | SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
| #define | SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
| #define | SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
| #define | SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
| #define | SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
| #define | SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
| #define | SPI_STAT_SPIF 0x00000001 /* SPI Finished */ |
| #define | SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ |
| #define | SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ |
| #define | SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ |
| #define | SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ |
| #define | SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ |
| #define | SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ |
| #define | SPI_STAT_RS 0x00000100 /* Receive Start Indication */ |
| #define | SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ |
| #define | SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ |
| #define | SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ |
| #define | SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ |
| #define | SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ |
| #define | SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ |
| #define | SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ |
| #define | SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ |
| #define | SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ |
| #define | SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ |
| #define | SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ |
| #define | SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ |
| #define | SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ |
| #define | SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ |
| #define | SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ |
| #define | SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ |
| #define | SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ |
| #define | SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ |
| #define | SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ |
| #define | SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ |
| #define | SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ |
| #define | SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ |
| #define | SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ |
| #define | SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ |
| #define | SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ |
| #define | SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ |
| #define | SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ |
| #define | SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ |
| #define | SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ |
| #define | SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ |
| #define | SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ |
| #define | SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ |
| #define | SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ |
| #define | SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ |
| #define | SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ |
| #define | SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ |
| #define | SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ |
| #define | SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ |
| #define | MAX_CTRL_CS 8 /* cs in spi controller */ |
| #define MAX_CTRL_CS 8 /* cs in spi controller */ |
Definition at line 240 of file bfin6xx_spi.h.
| #define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ |
Definition at line 100 of file bfin6xx_spi.h.
| #define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ |
Definition at line 32 of file bfin6xx_spi.h.
| #define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ |
Definition at line 30 of file bfin6xx_spi.h.
| #define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ |
Definition at line 31 of file bfin6xx_spi.h.
| #define SPI_CTL_EMISO 0x00000100 /* Enable MISO */ |
Definition at line 34 of file bfin6xx_spi.h.
| #define SPI_CTL_EN 0x00000001 /* Enable */ |
Definition at line 26 of file bfin6xx_spi.h.
| #define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ |
Definition at line 41 of file bfin6xx_spi.h.
| #define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ |
Definition at line 40 of file bfin6xx_spi.h.
| #define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ |
Definition at line 42 of file bfin6xx_spi.h.
| #define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ |
Definition at line 43 of file bfin6xx_spi.h.
| #define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ |
Definition at line 44 of file bfin6xx_spi.h.
| #define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ |
Definition at line 45 of file bfin6xx_spi.h.
| #define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ |
Definition at line 46 of file bfin6xx_spi.h.
| #define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ |
Definition at line 47 of file bfin6xx_spi.h.
| #define SPI_CTL_LSBF 0x00001000 /* LSB First */ |
Definition at line 39 of file bfin6xx_spi.h.
| #define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ |
Definition at line 49 of file bfin6xx_spi.h.
| #define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ |
Definition at line 50 of file bfin6xx_spi.h.
| #define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ |
Definition at line 51 of file bfin6xx_spi.h.
| #define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ |
Definition at line 48 of file bfin6xx_spi.h.
| #define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ |
Definition at line 27 of file bfin6xx_spi.h.
| #define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ |
Definition at line 29 of file bfin6xx_spi.h.
| #define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ |
Definition at line 28 of file bfin6xx_spi.h.
| #define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ |
Definition at line 33 of file bfin6xx_spi.h.
| #define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ |
Definition at line 35 of file bfin6xx_spi.h.
| #define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ |
Definition at line 36 of file bfin6xx_spi.h.
| #define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ |
Definition at line 37 of file bfin6xx_spi.h.
| #define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ |
Definition at line 38 of file bfin6xx_spi.h.
| #define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ |
Definition at line 52 of file bfin6xx_spi.h.
| #define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ |
Definition at line 104 of file bfin6xx_spi.h.
| #define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ |
Definition at line 103 of file bfin6xx_spi.h.
| #define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ |
Definition at line 102 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ |
Definition at line 205 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ |
Definition at line 208 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ |
Definition at line 202 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ |
Definition at line 206 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ |
Definition at line 200 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ |
Definition at line 204 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ |
Definition at line 209 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ |
Definition at line 207 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ |
Definition at line 203 of file bfin6xx_spi.h.
| #define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ |
Definition at line 201 of file bfin6xx_spi.h.
| #define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ |
Definition at line 194 of file bfin6xx_spi.h.
| #define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ |
Definition at line 197 of file bfin6xx_spi.h.
| #define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ |
Definition at line 191 of file bfin6xx_spi.h.
| #define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ |
Definition at line 195 of file bfin6xx_spi.h.
| #define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ |
Definition at line 189 of file bfin6xx_spi.h.
| #define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ |
Definition at line 193 of file bfin6xx_spi.h.
| #define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ |
Definition at line 198 of file bfin6xx_spi.h.
| #define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ |
Definition at line 196 of file bfin6xx_spi.h.
| #define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ |
Definition at line 192 of file bfin6xx_spi.h.
| #define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ |
Definition at line 190 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
Definition at line 145 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
Definition at line 148 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
Definition at line 142 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
Definition at line 146 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
Definition at line 140 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
Definition at line 144 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
Definition at line 149 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
Definition at line 147 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
Definition at line 143 of file bfin6xx_spi.h.
| #define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
Definition at line 141 of file bfin6xx_spi.h.
| #define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
Definition at line 134 of file bfin6xx_spi.h.
| #define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
Definition at line 137 of file bfin6xx_spi.h.
| #define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
Definition at line 131 of file bfin6xx_spi.h.
| #define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
Definition at line 135 of file bfin6xx_spi.h.
| #define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
Definition at line 129 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ |
Definition at line 156 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ |
Definition at line 159 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ |
Definition at line 153 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ |
Definition at line 157 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ |
Definition at line 151 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
Definition at line 155 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
Definition at line 160 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
Definition at line 158 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
Definition at line 154 of file bfin6xx_spi.h.
| #define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
Definition at line 152 of file bfin6xx_spi.h.
| #define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ |
Definition at line 133 of file bfin6xx_spi.h.
| #define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ |
Definition at line 138 of file bfin6xx_spi.h.
| #define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ |
Definition at line 136 of file bfin6xx_spi.h.
| #define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ |
Definition at line 132 of file bfin6xx_spi.h.
| #define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ |
Definition at line 130 of file bfin6xx_spi.h.
| #define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ |
Definition at line 121 of file bfin6xx_spi.h.
| #define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ |
Definition at line 123 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ |
Definition at line 64 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ |
Definition at line 57 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ |
Definition at line 60 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ |
Definition at line 61 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ |
Definition at line 62 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ |
Definition at line 58 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ |
Definition at line 63 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ |
Definition at line 59 of file bfin6xx_spi.h.
| #define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ |
Definition at line 54 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ |
Definition at line 65 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ |
Definition at line 55 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ |
Definition at line 70 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ |
Definition at line 56 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ |
Definition at line 66 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ |
Definition at line 67 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ |
Definition at line 68 of file bfin6xx_spi.h.
| #define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ |
Definition at line 69 of file bfin6xx_spi.h.
| #define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ |
Definition at line 72 of file bfin6xx_spi.h.
| #define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ |
Definition at line 73 of file bfin6xx_spi.h.
| #define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ |
Definition at line 74 of file bfin6xx_spi.h.
| #define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ |
Definition at line 71 of file bfin6xx_spi.h.
| #define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ |
Definition at line 75 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ |
Definition at line 106 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ |
Definition at line 107 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ |
Definition at line 108 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ |
Definition at line 109 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ |
Definition at line 110 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ |
Definition at line 111 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ |
Definition at line 112 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ |
Definition at line 113 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ |
Definition at line 114 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ |
Definition at line 115 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ |
Definition at line 116 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ |
Definition at line 117 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ |
Definition at line 118 of file bfin6xx_spi.h.
| #define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ |
Definition at line 119 of file bfin6xx_spi.h.
| #define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ |
Definition at line 185 of file bfin6xx_spi.h.
| #define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ |
Definition at line 168 of file bfin6xx_spi.h.
| #define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ |
Definition at line 171 of file bfin6xx_spi.h.
| #define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ |
Definition at line 186 of file bfin6xx_spi.h.
| #define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ |
Definition at line 175 of file bfin6xx_spi.h.
| #define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ |
Definition at line 176 of file bfin6xx_spi.h.
| #define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ |
Definition at line 177 of file bfin6xx_spi.h.
| #define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ |
Definition at line 174 of file bfin6xx_spi.h.
| #define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ |
Definition at line 178 of file bfin6xx_spi.h.
| #define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ |
Definition at line 173 of file bfin6xx_spi.h.
| #define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ |
Definition at line 165 of file bfin6xx_spi.h.
| #define SPI_STAT_RS 0x00000100 /* Receive Start Indication */ |
Definition at line 169 of file bfin6xx_spi.h.
| #define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ |
Definition at line 163 of file bfin6xx_spi.h.
| #define SPI_STAT_SPIF 0x00000001 /* SPI Finished */ |
Definition at line 162 of file bfin6xx_spi.h.
| #define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ |
Definition at line 167 of file bfin6xx_spi.h.
| #define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ |
Definition at line 172 of file bfin6xx_spi.h.
| #define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ |
Definition at line 187 of file bfin6xx_spi.h.
| #define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ |
Definition at line 181 of file bfin6xx_spi.h.
| #define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ |
Definition at line 182 of file bfin6xx_spi.h.
| #define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ |
Definition at line 183 of file bfin6xx_spi.h.
| #define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ |
Definition at line 184 of file bfin6xx_spi.h.
| #define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ |
Definition at line 180 of file bfin6xx_spi.h.
| #define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ |
Definition at line 179 of file bfin6xx_spi.h.
| #define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ |
Definition at line 170 of file bfin6xx_spi.h.
| #define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ |
Definition at line 166 of file bfin6xx_spi.h.
| #define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ |
Definition at line 164 of file bfin6xx_spi.h.
| #define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ |
Definition at line 125 of file bfin6xx_spi.h.
| #define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ |
Definition at line 127 of file bfin6xx_spi.h.
| #define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ |
Definition at line 90 of file bfin6xx_spi.h.
| #define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ |
Definition at line 91 of file bfin6xx_spi.h.
| #define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ |
Definition at line 92 of file bfin6xx_spi.h.
| #define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ |
Definition at line 89 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ |
Definition at line 80 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ |
Definition at line 83 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ |
Definition at line 84 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ |
Definition at line 85 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ |
Definition at line 81 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ |
Definition at line 86 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ |
Definition at line 82 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ |
Definition at line 87 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ |
Definition at line 77 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ |
Definition at line 88 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ |
Definition at line 78 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ |
Definition at line 93 of file bfin6xx_spi.h.
| #define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ |
Definition at line 79 of file bfin6xx_spi.h.
| #define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ |
Definition at line 95 of file bfin6xx_spi.h.
| #define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ |
Definition at line 96 of file bfin6xx_spi.h.
| #define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ |
Definition at line 97 of file bfin6xx_spi.h.
| #define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ |
Definition at line 94 of file bfin6xx_spi.h.
| #define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ |
Definition at line 98 of file bfin6xx_spi.h.
1.8.2