Linux Kernel
3.7.1
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#include <linux/types.h>
Go to the source code of this file.
Data Structures | |
struct | bfin_dma_regs |
struct | bfin_hmdma_regs |
Macros | |
#define | DMAEN 0x0001 /* DMA Channel Enable */ |
#define | WNR 0x0002 /* Channel Direction (W/R*) */ |
#define | WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ |
#define | PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ |
#define | PSIZE_16 0x0000 /* Transfer Word Size = 16 */ |
#define | PSIZE_32 0x0000 /* Transfer Word Size = 32 */ |
#define | WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ |
#define | WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ |
#define | DMA2D 0x0010 /* DMA Mode (2D/1D*) */ |
#define | RESTART 0x0020 /* DMA Buffer Clear */ |
#define | DI_SEL 0x0040 /* Data Interrupt Timing Select */ |
#define | DI_EN 0x0080 /* Data Interrupt Enable */ |
#define | DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ |
#define | DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ |
#define | NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ |
#define | NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ |
#define | NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ |
#define | NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ |
#define | NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ |
#define | NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ |
#define | NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ |
#define | NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ |
#define | NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ |
#define | NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ |
#define | NDSIZE 0x0f00 /* Next Descriptor Size */ |
#define | NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ |
#define | DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ |
#define | DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ |
#define | DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ |
#define | DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ |
#define | DMA_RUN 0x0008 /* DMA Channel Running Indicator */ |
#define | DMAFLOW 0x7000 /* Flow Control */ |
#define | DMAFLOW_STOP 0x0000 /* Stop Mode */ |
#define | DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ |
#define | DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ |
#define | DMA_ERR 0x0002 /* DMA Error Interrupt Status */ |
#define | DMA_PIRQ 0 |
#define | __BFP(m) u16 m; u16 __pad_##m |
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ |
Definition at line 82 of file bfin_dma.h.
#define DI_EN 0x0080 /* Data Interrupt Enable */ |
Definition at line 64 of file bfin_dma.h.
#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ |
Definition at line 65 of file bfin_dma.h.
#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ |
Definition at line 66 of file bfin_dma.h.
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ |
Definition at line 63 of file bfin_dma.h.
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ |
Definition at line 61 of file bfin_dma.h.
#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ |
Definition at line 91 of file bfin_dma.h.
#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ |
Definition at line 92 of file bfin_dma.h.
#define DMA_PIRQ 0 |
Definition at line 96 of file bfin_dma.h.
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ |
Definition at line 83 of file bfin_dma.h.
#define DMAEN 0x0001 /* DMA Channel Enable */ |
Definition at line 15 of file bfin_dma.h.
#define DMAFLOW 0x7000 /* Flow Control */ |
Definition at line 86 of file bfin_dma.h.
#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ |
Definition at line 79 of file bfin_dma.h.
#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ |
Definition at line 88 of file bfin_dma.h.
#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ |
Definition at line 81 of file bfin_dma.h.
#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ |
Definition at line 80 of file bfin_dma.h.
#define DMAFLOW_STOP 0x0000 /* Stop Mode */ |
Definition at line 87 of file bfin_dma.h.
#define NDSIZE 0x0f00 /* Next Descriptor Size */ |
Definition at line 77 of file bfin_dma.h.
#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ |
Definition at line 67 of file bfin_dma.h.
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ |
Definition at line 68 of file bfin_dma.h.
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ |
Definition at line 69 of file bfin_dma.h.
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ |
Definition at line 70 of file bfin_dma.h.
#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ |
Definition at line 71 of file bfin_dma.h.
#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ |
Definition at line 72 of file bfin_dma.h.
#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ |
Definition at line 73 of file bfin_dma.h.
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ |
Definition at line 74 of file bfin_dma.h.
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ |
Definition at line 75 of file bfin_dma.h.
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ |
Definition at line 76 of file bfin_dma.h.
Definition at line 78 of file bfin_dma.h.
#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ |
Definition at line 57 of file bfin_dma.h.
#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ |
Definition at line 58 of file bfin_dma.h.
#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ |
Definition at line 18 of file bfin_dma.h.
#define RESTART 0x0020 /* DMA Buffer Clear */ |
Definition at line 62 of file bfin_dma.h.
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ |
Definition at line 59 of file bfin_dma.h.
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ |
Definition at line 60 of file bfin_dma.h.
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ |
Definition at line 17 of file bfin_dma.h.
#define WNR 0x0002 /* Channel Direction (W/R*) */ |
Definition at line 16 of file bfin_dma.h.