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10 #define __BFIN_SDH_H__
22 #define CMD_RSP (1 << 6)
23 #define CMD_L_RSP (1 << 7)
24 #define CMD_INT_E (1 << 8)
25 #define CMD_PEND_E (1 << 9)
26 #define CMD_E (1 << 10)
30 #define SD_CMD_OD (1 << 6)
31 #define ROD_CTL (1 << 7)
35 #define CLK_E (1 << 8)
36 #define PWR_SV_E (1 << 9)
37 #define CLKDIV_BYPASS (1 << 10)
38 #define WIDE_BUS (1 << 11)
44 #define DTX_E (1 << 0)
45 #define DTX_DIR (1 << 1)
46 #define DTX_MODE (1 << 2)
47 #define DTX_DMA_E (1 << 3)
48 #define DTX_BLK_LGTH (0xf << 4)
51 #define CMD_CRC_FAIL (1 << 0)
52 #define DAT_CRC_FAIL (1 << 1)
53 #define CMD_TIME_OUT (1 << 2)
54 #define DAT_TIME_OUT (1 << 3)
55 #define TX_UNDERRUN (1 << 4)
56 #define RX_OVERRUN (1 << 5)
57 #define CMD_RESP_END (1 << 6)
58 #define CMD_SENT (1 << 7)
59 #define DAT_END (1 << 8)
60 #define START_BIT_ERR (1 << 9)
61 #define DAT_BLK_END (1 << 10)
62 #define CMD_ACT (1 << 11)
63 #define TX_ACT (1 << 12)
64 #define RX_ACT (1 << 13)
65 #define TX_FIFO_STAT (1 << 14)
66 #define RX_FIFO_STAT (1 << 15)
67 #define TX_FIFO_FULL (1 << 16)
68 #define RX_FIFO_FULL (1 << 17)
69 #define TX_FIFO_ZERO (1 << 18)
70 #define RX_DAT_ZERO (1 << 19)
71 #define TX_DAT_RDY (1 << 20)
72 #define RX_FIFO_RDY (1 << 21)
75 #define CMD_CRC_FAIL_STAT (1 << 0)
76 #define DAT_CRC_FAIL_STAT (1 << 1)
77 #define CMD_TIMEOUT_STAT (1 << 2)
78 #define DAT_TIMEOUT_STAT (1 << 3)
79 #define TX_UNDERRUN_STAT (1 << 4)
80 #define RX_OVERRUN_STAT (1 << 5)
81 #define CMD_RESP_END_STAT (1 << 6)
82 #define CMD_SENT_STAT (1 << 7)
83 #define DAT_END_STAT (1 << 8)
84 #define START_BIT_ERR_STAT (1 << 9)
85 #define DAT_BLK_END_STAT (1 << 10)
88 #define CMD_CRC_FAIL_MASK (1 << 0)
89 #define DAT_CRC_FAIL_MASK (1 << 1)
90 #define CMD_TIMEOUT_MASK (1 << 2)
91 #define DAT_TIMEOUT_MASK (1 << 3)
92 #define TX_UNDERRUN_MASK (1 << 4)
93 #define RX_OVERRUN_MASK (1 << 5)
94 #define CMD_RESP_END_MASK (1 << 6)
95 #define CMD_SENT_MASK (1 << 7)
96 #define DAT_END_MASK (1 << 8)
97 #define START_BIT_ERR_MASK (1 << 9)
98 #define DAT_BLK_END_MASK (1 << 10)
99 #define CMD_ACT_MASK (1 << 11)
100 #define TX_ACT_MASK (1 << 12)
101 #define RX_ACT_MASK (1 << 13)
102 #define TX_FIFO_STAT_MASK (1 << 14)
103 #define RX_FIFO_STAT_MASK (1 << 15)
104 #define TX_FIFO_FULL_MASK (1 << 16)
105 #define RX_FIFO_FULL_MASK (1 << 17)
106 #define TX_FIFO_ZERO_MASK (1 << 18)
107 #define RX_DAT_ZERO_MASK (1 << 19)
108 #define TX_DAT_RDY_MASK (1 << 20)
109 #define RX_FIFO_RDY_MASK (1 << 21)
112 #define FIFO_COUNT 0x7fff
115 #define SDIO_INT_DET (1 << 1)
116 #define SD_CARD_DET (1 << 4)
119 #define SDIO_MSK (1 << 1)
120 #define SCD_MSK (1 << 6)
123 #define CLKS_EN (1 << 0)
124 #define SD4E (1 << 2)
126 #define SD_RST (1 << 4)
127 #define PUP_SDDAT (1 << 5)
128 #define PUP_SDDAT3 (1 << 6)
129 #define PD_SDDAT3 (1 << 7)