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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | bfin_sd_host |
Macros | |
| #define | CMD_IDX 0x3f /* Command Index */ |
| #define | CMD_RSP (1 << 6) /* Response */ |
| #define | CMD_L_RSP (1 << 7) /* Long Response */ |
| #define | CMD_INT_E (1 << 8) /* Command Interrupt */ |
| #define | CMD_PEND_E (1 << 9) /* Command Pending */ |
| #define | CMD_E (1 << 10) /* Command Enable */ |
| #define | PWR_ON 0x3 /* Power On */ |
| #define | SD_CMD_OD (1 << 6) /* Open Drain Output */ |
| #define | ROD_CTL (1 << 7) /* Rod Control */ |
| #define | CLKDIV 0xff /* MC_CLK Divisor */ |
| #define | CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ |
| #define | PWR_SV_E (1 << 9) /* Power Save Enable */ |
| #define | CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ |
| #define | WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ |
| #define | RESP_CMD 0x3f /* Response Command */ |
| #define | DTX_E (1 << 0) /* Data Transfer Enable */ |
| #define | DTX_DIR (1 << 1) /* Data Transfer Direction */ |
| #define | DTX_MODE (1 << 2) /* Data Transfer Mode */ |
| #define | DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ |
| #define | DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ |
| #define | CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ |
| #define | DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */ |
| #define | CMD_TIME_OUT (1 << 2) /* CMD Time Out */ |
| #define | DAT_TIME_OUT (1 << 3) /* Data Time Out */ |
| #define | TX_UNDERRUN (1 << 4) /* Transmit Underrun */ |
| #define | RX_OVERRUN (1 << 5) /* Receive Overrun */ |
| #define | CMD_RESP_END (1 << 6) /* CMD Response End */ |
| #define | CMD_SENT (1 << 7) /* CMD Sent */ |
| #define | DAT_END (1 << 8) /* Data End */ |
| #define | START_BIT_ERR (1 << 9) /* Start Bit Error */ |
| #define | DAT_BLK_END (1 << 10) /* Data Block End */ |
| #define | CMD_ACT (1 << 11) /* CMD Active */ |
| #define | TX_ACT (1 << 12) /* Transmit Active */ |
| #define | RX_ACT (1 << 13) /* Receive Active */ |
| #define | TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */ |
| #define | RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */ |
| #define | TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */ |
| #define | RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ |
| #define | TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */ |
| #define | RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ |
| #define | TX_DAT_RDY (1 << 20) /* Transmit Data Available */ |
| #define | RX_FIFO_RDY (1 << 21) /* Receive Data Available */ |
| #define | CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */ |
| #define | DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */ |
| #define | CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */ |
| #define | DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */ |
| #define | TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */ |
| #define | RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ |
| #define | CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */ |
| #define | CMD_SENT_STAT (1 << 7) /* CMD Sent Status */ |
| #define | DAT_END_STAT (1 << 8) /* Data End Status */ |
| #define | START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */ |
| #define | DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */ |
| #define | CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */ |
| #define | DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */ |
| #define | CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */ |
| #define | DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */ |
| #define | TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ |
| #define | RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ |
| #define | CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ |
| #define | CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ |
| #define | DAT_END_MASK (1 << 8) /* Data End Mask */ |
| #define | START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */ |
| #define | DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ |
| #define | CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ |
| #define | TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ |
| #define | RX_ACT_MASK (1 << 13) /* Receive Active Mask */ |
| #define | TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */ |
| #define | RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */ |
| #define | TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */ |
| #define | RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ |
| #define | TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */ |
| #define | RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ |
| #define | TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */ |
| #define | RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ |
| #define | FIFO_COUNT 0x7fff /* FIFO Count */ |
| #define | SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ |
| #define | SD_CARD_DET (1 << 4) /* SD Card Detect */ |
| #define | SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ |
| #define | SCD_MSK (1 << 6) /* Mask Card Detect */ |
| #define | CLKS_EN (1 << 0) /* Clocks Enable */ |
| #define | SD4E (1 << 2) /* SDIO 4-Bit Enable */ |
| #define | MWE (1 << 3) /* Moving Window Enable */ |
| #define | SD_RST (1 << 4) /* SDMMC Reset */ |
| #define | PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ |
| #define | PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ |
| #define | PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ |
| #define | RWR (1 << 0) /* Read Wait Request */ |
| #define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ |
Definition at line 35 of file bfin_sdh.h.
| #define CLKDIV 0xff /* MC_CLK Divisor */ |
Definition at line 34 of file bfin_sdh.h.
| #define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ |
Definition at line 37 of file bfin_sdh.h.
| #define CLKS_EN (1 << 0) /* Clocks Enable */ |
Definition at line 123 of file bfin_sdh.h.
| #define CMD_ACT (1 << 11) /* CMD Active */ |
Definition at line 62 of file bfin_sdh.h.
| #define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ |
Definition at line 99 of file bfin_sdh.h.
Definition at line 51 of file bfin_sdh.h.
Definition at line 88 of file bfin_sdh.h.
Definition at line 75 of file bfin_sdh.h.
| #define CMD_E (1 << 10) /* Command Enable */ |
Definition at line 26 of file bfin_sdh.h.
| #define CMD_IDX 0x3f /* Command Index */ |
Definition at line 21 of file bfin_sdh.h.
| #define CMD_INT_E (1 << 8) /* Command Interrupt */ |
Definition at line 24 of file bfin_sdh.h.
| #define CMD_L_RSP (1 << 7) /* Long Response */ |
Definition at line 23 of file bfin_sdh.h.
| #define CMD_PEND_E (1 << 9) /* Command Pending */ |
Definition at line 25 of file bfin_sdh.h.
| #define CMD_RESP_END (1 << 6) /* CMD Response End */ |
Definition at line 57 of file bfin_sdh.h.
| #define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ |
Definition at line 94 of file bfin_sdh.h.
Definition at line 81 of file bfin_sdh.h.
| #define CMD_RSP (1 << 6) /* Response */ |
Definition at line 22 of file bfin_sdh.h.
| #define CMD_SENT (1 << 7) /* CMD Sent */ |
Definition at line 58 of file bfin_sdh.h.
| #define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ |
Definition at line 95 of file bfin_sdh.h.
Definition at line 82 of file bfin_sdh.h.
Definition at line 53 of file bfin_sdh.h.
Definition at line 90 of file bfin_sdh.h.
Definition at line 77 of file bfin_sdh.h.
| #define DAT_BLK_END (1 << 10) /* Data Block End */ |
Definition at line 61 of file bfin_sdh.h.
| #define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ |
Definition at line 98 of file bfin_sdh.h.
Definition at line 85 of file bfin_sdh.h.
Definition at line 52 of file bfin_sdh.h.
Definition at line 89 of file bfin_sdh.h.
Definition at line 76 of file bfin_sdh.h.
| #define DAT_END (1 << 8) /* Data End */ |
Definition at line 59 of file bfin_sdh.h.
| #define DAT_END_MASK (1 << 8) /* Data End Mask */ |
Definition at line 96 of file bfin_sdh.h.
Definition at line 83 of file bfin_sdh.h.
Definition at line 54 of file bfin_sdh.h.
Definition at line 91 of file bfin_sdh.h.
Definition at line 78 of file bfin_sdh.h.
| #define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ |
Definition at line 48 of file bfin_sdh.h.
| #define DTX_DIR (1 << 1) /* Data Transfer Direction */ |
Definition at line 45 of file bfin_sdh.h.
Definition at line 47 of file bfin_sdh.h.
| #define DTX_E (1 << 0) /* Data Transfer Enable */ |
Definition at line 44 of file bfin_sdh.h.
Definition at line 46 of file bfin_sdh.h.
| #define FIFO_COUNT 0x7fff /* FIFO Count */ |
Definition at line 112 of file bfin_sdh.h.
| #define MWE (1 << 3) /* Moving Window Enable */ |
Definition at line 125 of file bfin_sdh.h.
| #define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ |
Definition at line 129 of file bfin_sdh.h.
| #define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ |
Definition at line 127 of file bfin_sdh.h.
| #define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ |
Definition at line 128 of file bfin_sdh.h.
| #define PWR_ON 0x3 /* Power On */ |
Definition at line 29 of file bfin_sdh.h.
| #define PWR_SV_E (1 << 9) /* Power Save Enable */ |
Definition at line 36 of file bfin_sdh.h.
| #define RESP_CMD 0x3f /* Response Command */ |
Definition at line 41 of file bfin_sdh.h.
| #define ROD_CTL (1 << 7) /* Rod Control */ |
Definition at line 31 of file bfin_sdh.h.
Definition at line 132 of file bfin_sdh.h.
| #define RX_ACT (1 << 13) /* Receive Active */ |
Definition at line 64 of file bfin_sdh.h.
| #define RX_ACT_MASK (1 << 13) /* Receive Active Mask */ |
Definition at line 101 of file bfin_sdh.h.
| #define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ |
Definition at line 70 of file bfin_sdh.h.
| #define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ |
Definition at line 107 of file bfin_sdh.h.
| #define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ |
Definition at line 68 of file bfin_sdh.h.
| #define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ |
Definition at line 105 of file bfin_sdh.h.
| #define RX_FIFO_RDY (1 << 21) /* Receive Data Available */ |
Definition at line 72 of file bfin_sdh.h.
| #define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ |
Definition at line 109 of file bfin_sdh.h.
Definition at line 66 of file bfin_sdh.h.
Definition at line 103 of file bfin_sdh.h.
| #define RX_OVERRUN (1 << 5) /* Receive Overrun */ |
Definition at line 56 of file bfin_sdh.h.
| #define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ |
Definition at line 93 of file bfin_sdh.h.
| #define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ |
Definition at line 80 of file bfin_sdh.h.
| #define SCD_MSK (1 << 6) /* Mask Card Detect */ |
Definition at line 120 of file bfin_sdh.h.
| #define SD4E (1 << 2) /* SDIO 4-Bit Enable */ |
Definition at line 124 of file bfin_sdh.h.
| #define SD_CARD_DET (1 << 4) /* SD Card Detect */ |
Definition at line 116 of file bfin_sdh.h.
| #define SD_CMD_OD (1 << 6) /* Open Drain Output */ |
Definition at line 30 of file bfin_sdh.h.
| #define SD_RST (1 << 4) /* SDMMC Reset */ |
Definition at line 126 of file bfin_sdh.h.
| #define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ |
Definition at line 115 of file bfin_sdh.h.
| #define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ |
Definition at line 119 of file bfin_sdh.h.
Definition at line 60 of file bfin_sdh.h.
Definition at line 97 of file bfin_sdh.h.
Definition at line 84 of file bfin_sdh.h.
| #define TX_ACT (1 << 12) /* Transmit Active */ |
Definition at line 63 of file bfin_sdh.h.
| #define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ |
Definition at line 100 of file bfin_sdh.h.
Definition at line 71 of file bfin_sdh.h.
Definition at line 108 of file bfin_sdh.h.
Definition at line 67 of file bfin_sdh.h.
Definition at line 104 of file bfin_sdh.h.
Definition at line 65 of file bfin_sdh.h.
Definition at line 102 of file bfin_sdh.h.
Definition at line 69 of file bfin_sdh.h.
Definition at line 106 of file bfin_sdh.h.
| #define TX_UNDERRUN (1 << 4) /* Transmit Underrun */ |
Definition at line 55 of file bfin_sdh.h.
| #define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ |
Definition at line 92 of file bfin_sdh.h.
Definition at line 79 of file bfin_sdh.h.
| #define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ |
Definition at line 38 of file bfin_sdh.h.
1.8.2