Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
kgdb.c
Go to the documentation of this file.
1 /*
2  * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
3  *
4  * Copyright 2005-2008 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2 or later.
7  */
8 
9 #include <linux/ptrace.h> /* for linux pt_regs struct */
10 #include <linux/kgdb.h>
11 #include <linux/uaccess.h>
12 
13 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
14 {
15  gdb_regs[BFIN_R0] = regs->r0;
16  gdb_regs[BFIN_R1] = regs->r1;
17  gdb_regs[BFIN_R2] = regs->r2;
18  gdb_regs[BFIN_R3] = regs->r3;
19  gdb_regs[BFIN_R4] = regs->r4;
20  gdb_regs[BFIN_R5] = regs->r5;
21  gdb_regs[BFIN_R6] = regs->r6;
22  gdb_regs[BFIN_R7] = regs->r7;
23  gdb_regs[BFIN_P0] = regs->p0;
24  gdb_regs[BFIN_P1] = regs->p1;
25  gdb_regs[BFIN_P2] = regs->p2;
26  gdb_regs[BFIN_P3] = regs->p3;
27  gdb_regs[BFIN_P4] = regs->p4;
28  gdb_regs[BFIN_P5] = regs->p5;
29  gdb_regs[BFIN_SP] = regs->reserved;
30  gdb_regs[BFIN_FP] = regs->fp;
31  gdb_regs[BFIN_I0] = regs->i0;
32  gdb_regs[BFIN_I1] = regs->i1;
33  gdb_regs[BFIN_I2] = regs->i2;
34  gdb_regs[BFIN_I3] = regs->i3;
35  gdb_regs[BFIN_M0] = regs->m0;
36  gdb_regs[BFIN_M1] = regs->m1;
37  gdb_regs[BFIN_M2] = regs->m2;
38  gdb_regs[BFIN_M3] = regs->m3;
39  gdb_regs[BFIN_B0] = regs->b0;
40  gdb_regs[BFIN_B1] = regs->b1;
41  gdb_regs[BFIN_B2] = regs->b2;
42  gdb_regs[BFIN_B3] = regs->b3;
43  gdb_regs[BFIN_L0] = regs->l0;
44  gdb_regs[BFIN_L1] = regs->l1;
45  gdb_regs[BFIN_L2] = regs->l2;
46  gdb_regs[BFIN_L3] = regs->l3;
47  gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
48  gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
49  gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
50  gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
51  gdb_regs[BFIN_ASTAT] = regs->astat;
52  gdb_regs[BFIN_RETS] = regs->rets;
53  gdb_regs[BFIN_LC0] = regs->lc0;
54  gdb_regs[BFIN_LT0] = regs->lt0;
55  gdb_regs[BFIN_LB0] = regs->lb0;
56  gdb_regs[BFIN_LC1] = regs->lc1;
57  gdb_regs[BFIN_LT1] = regs->lt1;
58  gdb_regs[BFIN_LB1] = regs->lb1;
59  gdb_regs[BFIN_CYCLES] = 0;
60  gdb_regs[BFIN_CYCLES2] = 0;
61  gdb_regs[BFIN_USP] = regs->usp;
62  gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
63  gdb_regs[BFIN_SYSCFG] = regs->syscfg;
64  gdb_regs[BFIN_RETI] = regs->pc;
65  gdb_regs[BFIN_RETX] = regs->retx;
66  gdb_regs[BFIN_RETN] = regs->retn;
67  gdb_regs[BFIN_RETE] = regs->rete;
68  gdb_regs[BFIN_PC] = regs->pc;
69  gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
70  gdb_regs[BFIN_EXTRA1] = 0;
71  gdb_regs[BFIN_EXTRA2] = 0;
72  gdb_regs[BFIN_EXTRA3] = 0;
73  gdb_regs[BFIN_IPEND] = regs->ipend;
74 }
75 
76 /*
77  * Extracts ebp, esp and eip values understandable by gdb from the values
78  * saved by switch_to.
79  * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
80  * prior to entering switch_to is 8 greater than the value that is saved.
81  * If switch_to changes, change following code appropriately.
82  */
83 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
84 {
85  gdb_regs[BFIN_SP] = p->thread.ksp;
86  gdb_regs[BFIN_PC] = p->thread.pc;
87  gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
88 }
89 
90 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
91 {
92  regs->r0 = gdb_regs[BFIN_R0];
93  regs->r1 = gdb_regs[BFIN_R1];
94  regs->r2 = gdb_regs[BFIN_R2];
95  regs->r3 = gdb_regs[BFIN_R3];
96  regs->r4 = gdb_regs[BFIN_R4];
97  regs->r5 = gdb_regs[BFIN_R5];
98  regs->r6 = gdb_regs[BFIN_R6];
99  regs->r7 = gdb_regs[BFIN_R7];
100  regs->p0 = gdb_regs[BFIN_P0];
101  regs->p1 = gdb_regs[BFIN_P1];
102  regs->p2 = gdb_regs[BFIN_P2];
103  regs->p3 = gdb_regs[BFIN_P3];
104  regs->p4 = gdb_regs[BFIN_P4];
105  regs->p5 = gdb_regs[BFIN_P5];
106  regs->fp = gdb_regs[BFIN_FP];
107  regs->i0 = gdb_regs[BFIN_I0];
108  regs->i1 = gdb_regs[BFIN_I1];
109  regs->i2 = gdb_regs[BFIN_I2];
110  regs->i3 = gdb_regs[BFIN_I3];
111  regs->m0 = gdb_regs[BFIN_M0];
112  regs->m1 = gdb_regs[BFIN_M1];
113  regs->m2 = gdb_regs[BFIN_M2];
114  regs->m3 = gdb_regs[BFIN_M3];
115  regs->b0 = gdb_regs[BFIN_B0];
116  regs->b1 = gdb_regs[BFIN_B1];
117  regs->b2 = gdb_regs[BFIN_B2];
118  regs->b3 = gdb_regs[BFIN_B3];
119  regs->l0 = gdb_regs[BFIN_L0];
120  regs->l1 = gdb_regs[BFIN_L1];
121  regs->l2 = gdb_regs[BFIN_L2];
122  regs->l3 = gdb_regs[BFIN_L3];
123  regs->a0x = gdb_regs[BFIN_A0_DOT_X];
124  regs->a0w = gdb_regs[BFIN_A0_DOT_W];
125  regs->a1x = gdb_regs[BFIN_A1_DOT_X];
126  regs->a1w = gdb_regs[BFIN_A1_DOT_W];
127  regs->rets = gdb_regs[BFIN_RETS];
128  regs->lc0 = gdb_regs[BFIN_LC0];
129  regs->lt0 = gdb_regs[BFIN_LT0];
130  regs->lb0 = gdb_regs[BFIN_LB0];
131  regs->lc1 = gdb_regs[BFIN_LC1];
132  regs->lt1 = gdb_regs[BFIN_LT1];
133  regs->lb1 = gdb_regs[BFIN_LB1];
134  regs->usp = gdb_regs[BFIN_USP];
135  regs->syscfg = gdb_regs[BFIN_SYSCFG];
136  regs->retx = gdb_regs[BFIN_RETX];
137  regs->retn = gdb_regs[BFIN_RETN];
138  regs->rete = gdb_regs[BFIN_RETE];
139  regs->pc = gdb_regs[BFIN_PC];
140 
141 #if 0 /* can't change these */
142  regs->astat = gdb_regs[BFIN_ASTAT];
143  regs->seqstat = gdb_regs[BFIN_SEQSTAT];
144  regs->ipend = gdb_regs[BFIN_IPEND];
145 #endif
146 }
147 
148 static struct hw_breakpoint {
149  unsigned int occupied:1;
150  unsigned int skip:1;
151  unsigned int enabled:1;
152  unsigned int type:1;
153  unsigned int dataacc:2;
154  unsigned short count;
155  unsigned int addr;
156 } breakinfo[HW_WATCHPOINT_NUM];
157 
158 static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
159 {
160  int breakno;
161  int bfin_type;
162  int dataacc = 0;
163 
164  switch (type) {
165  case BP_HARDWARE_BREAKPOINT:
166  bfin_type = TYPE_INST_WATCHPOINT;
167  break;
168  case BP_WRITE_WATCHPOINT:
169  dataacc = 1;
170  bfin_type = TYPE_DATA_WATCHPOINT;
171  break;
172  case BP_READ_WATCHPOINT:
173  dataacc = 2;
174  bfin_type = TYPE_DATA_WATCHPOINT;
175  break;
176  case BP_ACCESS_WATCHPOINT:
177  dataacc = 3;
178  bfin_type = TYPE_DATA_WATCHPOINT;
179  break;
180  default:
181  return -ENOSPC;
182  }
183 
184  /* Because hardware data watchpoint impelemented in current
185  * Blackfin can not trigger an exception event as the hardware
186  * instrction watchpoint does, we ignaore all data watch point here.
187  * They can be turned on easily after future blackfin design
188  * supports this feature.
189  */
190  for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
191  if (bfin_type == breakinfo[breakno].type
192  && !breakinfo[breakno].occupied) {
193  breakinfo[breakno].occupied = 1;
194  breakinfo[breakno].skip = 0;
195  breakinfo[breakno].enabled = 1;
196  breakinfo[breakno].addr = addr;
197  breakinfo[breakno].dataacc = dataacc;
198  breakinfo[breakno].count = 0;
199  return 0;
200  }
201 
202  return -ENOSPC;
203 }
204 
205 static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
206 {
207  int breakno;
208  int bfin_type;
209 
210  switch (type) {
211  case BP_HARDWARE_BREAKPOINT:
212  bfin_type = TYPE_INST_WATCHPOINT;
213  break;
214  case BP_WRITE_WATCHPOINT:
215  case BP_READ_WATCHPOINT:
216  case BP_ACCESS_WATCHPOINT:
217  bfin_type = TYPE_DATA_WATCHPOINT;
218  break;
219  default:
220  return 0;
221  }
222  for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
223  if (bfin_type == breakinfo[breakno].type
224  && breakinfo[breakno].occupied
225  && breakinfo[breakno].addr == addr) {
226  breakinfo[breakno].occupied = 0;
227  breakinfo[breakno].enabled = 0;
228  }
229 
230  return 0;
231 }
232 
233 static void bfin_remove_all_hw_break(void)
234 {
235  int breakno;
236 
237  memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
238 
239  for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
240  breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
241  for (; breakno < HW_WATCHPOINT_NUM; breakno++)
242  breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
243 }
244 
245 static void bfin_correct_hw_break(void)
246 {
247  int breakno;
248  unsigned int wpiactl = 0;
249  unsigned int wpdactl = 0;
250  int enable_wp = 0;
251 
252  for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
253  if (breakinfo[breakno].enabled) {
254  enable_wp = 1;
255 
256  switch (breakno) {
257  case 0:
258  wpiactl |= WPIAEN0|WPICNTEN0;
259  bfin_write_WPIA0(breakinfo[breakno].addr);
260  bfin_write_WPIACNT0(breakinfo[breakno].count
261  + breakinfo->skip);
262  break;
263  case 1:
264  wpiactl |= WPIAEN1|WPICNTEN1;
265  bfin_write_WPIA1(breakinfo[breakno].addr);
266  bfin_write_WPIACNT1(breakinfo[breakno].count
267  + breakinfo->skip);
268  break;
269  case 2:
270  wpiactl |= WPIAEN2|WPICNTEN2;
271  bfin_write_WPIA2(breakinfo[breakno].addr);
272  bfin_write_WPIACNT2(breakinfo[breakno].count
273  + breakinfo->skip);
274  break;
275  case 3:
276  wpiactl |= WPIAEN3|WPICNTEN3;
277  bfin_write_WPIA3(breakinfo[breakno].addr);
278  bfin_write_WPIACNT3(breakinfo[breakno].count
279  + breakinfo->skip);
280  break;
281  case 4:
282  wpiactl |= WPIAEN4|WPICNTEN4;
283  bfin_write_WPIA4(breakinfo[breakno].addr);
284  bfin_write_WPIACNT4(breakinfo[breakno].count
285  + breakinfo->skip);
286  break;
287  case 5:
288  wpiactl |= WPIAEN5|WPICNTEN5;
289  bfin_write_WPIA5(breakinfo[breakno].addr);
290  bfin_write_WPIACNT5(breakinfo[breakno].count
291  + breakinfo->skip);
292  break;
293  case 6:
294  wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
295  wpdactl |= breakinfo[breakno].dataacc
296  << WPDACC0_OFFSET;
297  bfin_write_WPDA0(breakinfo[breakno].addr);
298  bfin_write_WPDACNT0(breakinfo[breakno].count
299  + breakinfo->skip);
300  break;
301  case 7:
302  wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
303  wpdactl |= breakinfo[breakno].dataacc
304  << WPDACC1_OFFSET;
305  bfin_write_WPDA1(breakinfo[breakno].addr);
306  bfin_write_WPDACNT1(breakinfo[breakno].count
307  + breakinfo->skip);
308  break;
309  }
310  }
311 
312  /* Should enable WPPWR bit first before set any other
313  * WPIACTL and WPDACTL bits */
314  if (enable_wp) {
315  bfin_write_WPIACTL(WPPWR);
316  CSYNC();
317  bfin_write_WPIACTL(wpiactl|WPPWR);
318  bfin_write_WPDACTL(wpdactl);
319  CSYNC();
320  }
321 }
322 
323 static void bfin_disable_hw_debug(struct pt_regs *regs)
324 {
325  /* Disable hardware debugging while we are in kgdb */
326  bfin_write_WPIACTL(0);
327  bfin_write_WPDACTL(0);
328  CSYNC();
329 }
330 
331 #ifdef CONFIG_SMP
332 void kgdb_passive_cpu_callback(void *info)
333 {
334  kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
335 }
336 
337 void kgdb_roundup_cpus(unsigned long flags)
338 {
339  smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
340 }
341 
342 void kgdb_roundup_cpu(int cpu, unsigned long flags)
343 {
344  smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
345 }
346 #endif
347 
348 #ifdef CONFIG_IPIPE
349 static unsigned long kgdb_arch_imask;
350 #endif
351 
352 void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
353 {
354  if (kgdb_single_step)
355  preempt_enable();
356 
357 #ifdef CONFIG_IPIPE
358  if (kgdb_arch_imask) {
359  cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
360  kgdb_arch_imask = 0;
361  }
362 #endif
363 }
364 
365 int kgdb_arch_handle_exception(int vector, int signo,
366  int err_code, char *remcom_in_buffer,
367  char *remcom_out_buffer,
368  struct pt_regs *regs)
369 {
370  long addr;
371  char *ptr;
372  int newPC;
373  int i;
374 
375  switch (remcom_in_buffer[0]) {
376  case 'c':
377  case 's':
378  if (kgdb_contthread && kgdb_contthread != current) {
379  strcpy(remcom_out_buffer, "E00");
380  break;
381  }
382 
383  kgdb_contthread = NULL;
384 
385  /* try to read optional parameter, pc unchanged if no parm */
386  ptr = &remcom_in_buffer[1];
387  if (kgdb_hex2long(&ptr, &addr)) {
388  regs->retx = addr;
389  }
390  newPC = regs->retx;
391 
392  /* clear the trace bit */
393  regs->syscfg &= 0xfffffffe;
394 
395  /* set the trace bit if we're stepping */
396  if (remcom_in_buffer[0] == 's') {
397  regs->syscfg |= 0x1;
398  kgdb_single_step = regs->ipend;
399  kgdb_single_step >>= 6;
400  for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
401  if (kgdb_single_step & 1)
402  break;
403  /* i indicate event priority of current stopped instruction
404  * user space instruction is 0, IVG15 is 1, IVTMR is 10.
405  * kgdb_single_step > 0 means in single step mode
406  */
407  kgdb_single_step = i + 1;
408 
409  preempt_disable();
410 #ifdef CONFIG_IPIPE
411  kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
412  cpu_pda[raw_smp_processor_id()].ex_imask = 0;
413 #endif
414  }
415 
416  bfin_correct_hw_break();
417 
418  return 0;
419  } /* switch */
420  return -1; /* this means that we do not want to exit from the handler */
421 }
422 
423 struct kgdb_arch arch_kgdb_ops = {
424  .gdb_bpt_instr = {0xa1},
425  .flags = KGDB_HW_BREAKPOINT,
426  .set_hw_breakpoint = bfin_set_hw_break,
427  .remove_hw_breakpoint = bfin_remove_hw_break,
428  .disable_hw_break = bfin_disable_hw_debug,
429  .remove_all_hw_break = bfin_remove_all_hw_break,
430  .correct_hw_break = bfin_correct_hw_break,
431 };
432 
433 #define IN_MEM(addr, size, l1_addr, l1_size) \
434 ({ \
435  unsigned long __addr = (unsigned long)(addr); \
436  (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
437 })
438 #define ASYNC_BANK_SIZE \
439  (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
440  ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
441 
442 int kgdb_validate_break_address(unsigned long addr)
443 {
444  int cpu = raw_smp_processor_id();
445 
446  if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
447  return 0;
448  if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
449  return 0;
450  if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
451  return 0;
452 #ifdef CONFIG_SMP
453  else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
454  return 0;
455 #endif
456  if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
457  return 0;
458 
459  return -EFAULT;
460 }
461 
462 void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
463 {
464  regs->retx = ip;
465 }
466 
467 int kgdb_arch_init(void)
468 {
469  kgdb_single_step = 0;
470 #ifdef CONFIG_IPIPE
471  kgdb_arch_imask = 0;
472 #endif
473 
474  bfin_remove_all_hw_break();
475  return 0;
476 }
477 
478 void kgdb_arch_exit(void)
479 {
480 }
Generated on Thu Jan 10 2013 12:56:09 for Linux Kernel by   doxygen 1.8.2