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bnx2x_reg.h
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1 /* bnx2x_reg.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2012 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * The registers description starts with the register Access type followed
10  * by size in bits. For example [RW 32]. The access types are:
11  * R - Read only
12  * RC - Clear on read
13  * RW - Read/Write
14  * ST - Statistics register (clear on read)
15  * W - Write only
16  * WB - Wide bus register - the size is over 32 bits and it should be
17  * read/write in consecutive 32 bits accesses
18  * WR - Write Clear (write 1 to clear the bit)
19  *
20  */
21 #ifndef BNX2X_REG_H
22 #define BNX2X_REG_H
23 
24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32 /* [R 1] ATC initalization done */
33 #define ATC_REG_ATC_INIT_DONE 0x1100bc
34 /* [RC 6] Interrupt register #0 read clear */
35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36 /* [RW 5] Parity mask register #0 read/write */
37 #define ATC_REG_ATC_PRTY_MASK 0x1101d8
38 /* [RC 5] Parity register #0 read clear */
39 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
40 /* [RW 19] Interrupt mask register #0 read/write */
41 #define BRB1_REG_BRB1_INT_MASK 0x60128
42 /* [R 19] Interrupt register #0 read */
43 #define BRB1_REG_BRB1_INT_STS 0x6011c
44 /* [RW 4] Parity mask register #0 read/write */
45 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
46 /* [R 4] Parity register #0 read */
47 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
48 /* [RC 4] Parity register #0 read clear */
49 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
50 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
51  * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
52  * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
53  * following reset the first rbc access to this reg must be write; there can
54  * be no more rbc writes after the first one; there can be any number of rbc
55  * read following the first write; rbc access not following these rules will
56  * result in hang condition. */
57 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
58 /* [RW 10] The number of free blocks below which the full signal to class 0
59  * is asserted */
60 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
61 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
62 /* [RW 11] The number of free blocks above which the full signal to class 0
63  * is de-asserted */
64 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
65 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
66 /* [RW 11] The number of free blocks below which the full signal to class 1
67  * is asserted */
68 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
69 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
70 /* [RW 11] The number of free blocks above which the full signal to class 1
71  * is de-asserted */
72 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
73 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
74 /* [RW 11] The number of free blocks below which the full signal to the LB
75  * port is asserted */
76 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
77 /* [RW 10] The number of free blocks above which the full signal to the LB
78  * port is de-asserted */
79 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
80 /* [RW 10] The number of free blocks above which the High_llfc signal to
81  interface #n is de-asserted. */
82 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
83 /* [RW 10] The number of free blocks below which the High_llfc signal to
84  interface #n is asserted. */
85 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
86 /* [RW 11] The number of blocks guarantied for the LB port */
87 #define BRB1_REG_LB_GUARANTIED 0x601ec
88 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
89  * before signaling XON. */
90 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264
91 /* [RW 24] LL RAM data. */
92 #define BRB1_REG_LL_RAM 0x61000
93 /* [RW 10] The number of free blocks above which the Low_llfc signal to
94  interface #n is de-asserted. */
95 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
96 /* [RW 10] The number of free blocks below which the Low_llfc signal to
97  interface #n is asserted. */
98 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
99 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
100  * register is applicable only when per_class_guaranty_mode is set. */
101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
102 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
103  * 1 before signaling XON. The register is applicable only when
104  * per_class_guaranty_mode is set. */
105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
106 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
107  * register is applicable only when per_class_guaranty_mode is set. */
108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
109 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
110  * before signaling XON. The register is applicable only when
111  * per_class_guaranty_mode is set. */
112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
113 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
114  * is applicable only when per_class_guaranty_mode is set. */
115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
116 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
117  * 1 before signaling XON. The register is applicable only when
118  * per_class_guaranty_mode is set. */
119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
120 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
121  * register is applicable only when per_class_guaranty_mode is set. */
122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
123 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
124  * 1 before signaling XON. The register is applicable only when
125  * per_class_guaranty_mode is set. */
126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
127 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
128  * applicable only when per_class_guaranty_mode is reset. */
129 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
130 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
131 /* [R 24] The number of full blocks. */
132 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
133 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
134  was asserted. */
135 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
136 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
137 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
138 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
139  asserted. */
140 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
141 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
142 /* [RW 10] The number of free blocks below which the pause signal to class 0
143  * is asserted */
144 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
145 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
146 /* [RW 11] The number of free blocks above which the pause signal to class 0
147  * is de-asserted */
148 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
149 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
150 /* [RW 11] The number of free blocks below which the pause signal to class 1
151  * is asserted */
152 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
153 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
154 /* [RW 11] The number of free blocks above which the pause signal to class 1
155  * is de-asserted */
156 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
157 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
158 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
159 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
160 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
161 /* [RW 10] Write client 0: Assert pause threshold. */
162 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
163 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
164  * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
165  * mode). 1=per-class guaranty mode (new mode). */
166 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
167 /* [R 24] The number of full blocks occpied by port. */
168 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
169 /* [RW 1] Reset the design by software. */
170 #define BRB1_REG_SOFT_RESET 0x600dc
171 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
172 #define CCM_REG_CAM_OCCUP 0xd0188
173 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
174  acknowledge output is deasserted; all other signals are treated as usual;
175  if 1 - normal activity. */
176 #define CCM_REG_CCM_CFC_IFEN 0xd003c
177 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
178  disregarded; valid is deasserted; all other signals are treated as usual;
179  if 1 - normal activity. */
180 #define CCM_REG_CCM_CQM_IFEN 0xd000c
181 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
182  Otherwise 0 is inserted. */
183 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
184 /* [RW 11] Interrupt mask register #0 read/write */
185 #define CCM_REG_CCM_INT_MASK 0xd01e4
186 /* [R 11] Interrupt register #0 read */
187 #define CCM_REG_CCM_INT_STS 0xd01d8
188 /* [RW 27] Parity mask register #0 read/write */
189 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
190 /* [R 27] Parity register #0 read */
191 #define CCM_REG_CCM_PRTY_STS 0xd01e8
192 /* [RC 27] Parity register #0 read clear */
193 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
194 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
195  REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
196  Is used to determine the number of the AG context REG-pairs written back;
197  when the input message Reg1WbFlg isn't set. */
198 #define CCM_REG_CCM_REG0_SZ 0xd00c4
199 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
200  disregarded; valid is deasserted; all other signals are treated as usual;
201  if 1 - normal activity. */
202 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
203 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
204  disregarded; valid is deasserted; all other signals are treated as usual;
205  if 1 - normal activity. */
206 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
207 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
208  disregarded; valid output is deasserted; all other signals are treated as
209  usual; if 1 - normal activity. */
210 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
211 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
212  are disregarded; all other signals are treated as usual; if 1 - normal
213  activity. */
214 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
215 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
216  disregarded; valid output is deasserted; all other signals are treated as
217  usual; if 1 - normal activity. */
218 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
219 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
220  input is disregarded; all other signals are treated as usual; if 1 -
221  normal activity. */
222 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
223 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
224  the initial credit value; read returns the current value of the credit
225  counter. Must be initialized to 1 at start-up. */
226 #define CCM_REG_CFC_INIT_CRD 0xd0204
227 /* [RW 2] Auxiliary counter flag Q number 1. */
228 #define CCM_REG_CNT_AUX1_Q 0xd00c8
229 /* [RW 2] Auxiliary counter flag Q number 2. */
230 #define CCM_REG_CNT_AUX2_Q 0xd00cc
231 /* [RW 28] The CM header value for QM request (primary). */
232 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
233 /* [RW 28] The CM header value for QM request (secondary). */
234 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
235 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
236  acknowledge output is deasserted; all other signals are treated as usual;
237  if 1 - normal activity. */
238 #define CCM_REG_CQM_CCM_IFEN 0xd0014
239 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
240  the initial credit value; read returns the current value of the credit
241  counter. Must be initialized to 32 at start-up. */
242 #define CCM_REG_CQM_INIT_CRD 0xd020c
243 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
244  stands for weight 8 (the most prioritised); 1 stands for weight 1(least
245  prioritised); 2 stands for weight 2; tc. */
246 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
247 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
248  stands for weight 8 (the most prioritised); 1 stands for weight 1(least
249  prioritised); 2 stands for weight 2; tc. */
250 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
251 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
252  acknowledge output is deasserted; all other signals are treated as usual;
253  if 1 - normal activity. */
254 #define CCM_REG_CSDM_IFEN 0xd0018
255 /* [RC 1] Set when the message length mismatch (relative to last indication)
256  at the SDM interface is detected. */
257 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
258 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
259  weight 8 (the most prioritised); 1 stands for weight 1(least
260  prioritised); 2 stands for weight 2; tc. */
261 #define CCM_REG_CSDM_WEIGHT 0xd00b4
262 /* [RW 28] The CM header for QM formatting in case of an error in the QM
263  inputs. */
264 #define CCM_REG_ERR_CCM_HDR 0xd0094
265 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
266 #define CCM_REG_ERR_EVNT_ID 0xd0098
267 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
268  writes the initial credit value; read returns the current value of the
269  credit counter. Must be initialized to 64 at start-up. */
270 #define CCM_REG_FIC0_INIT_CRD 0xd0210
271 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
272  writes the initial credit value; read returns the current value of the
273  credit counter. Must be initialized to 64 at start-up. */
274 #define CCM_REG_FIC1_INIT_CRD 0xd0214
275 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
276  - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
277  ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
278  ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
279  outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
280 #define CCM_REG_GR_ARB_TYPE 0xd015c
281 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
282  highest priority is 3. It is supposed; that the Store channel priority is
283  the compliment to 4 of the rest priorities - Aggregation channel; Load
284  (FIC0) channel and Load (FIC1). */
285 #define CCM_REG_GR_LD0_PR 0xd0164
286 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
287  highest priority is 3. It is supposed; that the Store channel priority is
288  the compliment to 4 of the rest priorities - Aggregation channel; Load
289  (FIC0) channel and Load (FIC1). */
290 #define CCM_REG_GR_LD1_PR 0xd0168
291 /* [RW 2] General flags index. */
292 #define CCM_REG_INV_DONE_Q 0xd0108
293 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
294  context and sent to STORM; for a specific connection type. The double
295  REG-pairs are used in order to align to STORM context row size of 128
296  bits. The offset of these data in the STORM context is always 0. Index
297  _(0..15) stands for the connection type (one of 16). */
298 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
299 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
300 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
301 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
302 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
303 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
304  acknowledge output is deasserted; all other signals are treated as usual;
305  if 1 - normal activity. */
306 #define CCM_REG_PBF_IFEN 0xd0028
307 /* [RC 1] Set when the message length mismatch (relative to last indication)
308  at the pbf interface is detected. */
309 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
310 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
311  weight 8 (the most prioritised); 1 stands for weight 1(least
312  prioritised); 2 stands for weight 2; tc. */
313 #define CCM_REG_PBF_WEIGHT 0xd00ac
314 #define CCM_REG_PHYS_QNUM1_0 0xd0134
315 #define CCM_REG_PHYS_QNUM1_1 0xd0138
316 #define CCM_REG_PHYS_QNUM2_0 0xd013c
317 #define CCM_REG_PHYS_QNUM2_1 0xd0140
318 #define CCM_REG_PHYS_QNUM3_0 0xd0144
319 #define CCM_REG_PHYS_QNUM3_1 0xd0148
320 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
321 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
322 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
323 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
324 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
325 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
326 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
327 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
328 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
329  disregarded; acknowledge output is deasserted; all other signals are
330  treated as usual; if 1 - normal activity. */
331 #define CCM_REG_STORM_CCM_IFEN 0xd0010
332 /* [RC 1] Set when the message length mismatch (relative to last indication)
333  at the STORM interface is detected. */
334 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
335 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
336  mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
337  weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
338  tc. */
339 #define CCM_REG_STORM_WEIGHT 0xd009c
340 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
341  disregarded; acknowledge output is deasserted; all other signals are
342  treated as usual; if 1 - normal activity. */
343 #define CCM_REG_TSEM_IFEN 0xd001c
344 /* [RC 1] Set when the message length mismatch (relative to last indication)
345  at the tsem interface is detected. */
346 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
347 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
348  weight 8 (the most prioritised); 1 stands for weight 1(least
349  prioritised); 2 stands for weight 2; tc. */
350 #define CCM_REG_TSEM_WEIGHT 0xd00a0
351 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
352  disregarded; acknowledge output is deasserted; all other signals are
353  treated as usual; if 1 - normal activity. */
354 #define CCM_REG_USEM_IFEN 0xd0024
355 /* [RC 1] Set when message length mismatch (relative to last indication) at
356  the usem interface is detected. */
357 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
358 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
359  weight 8 (the most prioritised); 1 stands for weight 1(least
360  prioritised); 2 stands for weight 2; tc. */
361 #define CCM_REG_USEM_WEIGHT 0xd00a8
362 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
363  disregarded; acknowledge output is deasserted; all other signals are
364  treated as usual; if 1 - normal activity. */
365 #define CCM_REG_XSEM_IFEN 0xd0020
366 /* [RC 1] Set when the message length mismatch (relative to last indication)
367  at the xsem interface is detected. */
368 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
369 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
370  weight 8 (the most prioritised); 1 stands for weight 1(least
371  prioritised); 2 stands for weight 2; tc. */
372 #define CCM_REG_XSEM_WEIGHT 0xd00a4
373 /* [RW 19] Indirect access to the descriptor table of the XX protection
374  mechanism. The fields are: [5:0] - message length; [12:6] - message
375  pointer; 18:13] - next pointer. */
376 #define CCM_REG_XX_DESCR_TABLE 0xd0300
377 #define CCM_REG_XX_DESCR_TABLE_SIZE 24
378 /* [R 7] Used to read the value of XX protection Free counter. */
379 #define CCM_REG_XX_FREE 0xd0184
380 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
381  of the Input Stage XX protection buffer by the XX protection pending
382  messages. Max credit available - 127. Write writes the initial credit
383  value; read returns the current value of the credit counter. Must be
384  initialized to maximum XX protected message size - 2 at start-up. */
385 #define CCM_REG_XX_INIT_CRD 0xd0220
386 /* [RW 7] The maximum number of pending messages; which may be stored in XX
387  protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
388  At write comprises the start value of the ~ccm_registers_xx_free.xx_free
389  counter. */
390 #define CCM_REG_XX_MSG_NUM 0xd0224
391 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
392 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
393 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
394  The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
395  header pointer. */
396 #define CCM_REG_XX_TABLE 0xd0280
397 #define CDU_REG_CDU_CHK_MASK0 0x101000
398 #define CDU_REG_CDU_CHK_MASK1 0x101004
399 #define CDU_REG_CDU_CONTROL0 0x101008
400 #define CDU_REG_CDU_DEBUG 0x101010
401 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
402 /* [RW 7] Interrupt mask register #0 read/write */
403 #define CDU_REG_CDU_INT_MASK 0x10103c
404 /* [R 7] Interrupt register #0 read */
405 #define CDU_REG_CDU_INT_STS 0x101030
406 /* [RW 5] Parity mask register #0 read/write */
407 #define CDU_REG_CDU_PRTY_MASK 0x10104c
408 /* [R 5] Parity register #0 read */
409 #define CDU_REG_CDU_PRTY_STS 0x101040
410 /* [RC 5] Parity register #0 read clear */
411 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
412 /* [RC 32] logging of error data in case of a CDU load error:
413  {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
414  ype_error; ctual_active; ctual_compressed_context}; */
415 #define CDU_REG_ERROR_DATA 0x101014
416 /* [WB 216] L1TT ram access. each entry has the following format :
417  {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
418  ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
419 #define CDU_REG_L1TT 0x101800
420 /* [WB 24] MATT ram access. each entry has the following
421  format:{RegionLength[11:0]; egionOffset[11:0]} */
422 #define CDU_REG_MATT 0x101100
423 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
424 #define CDU_REG_MF_MODE 0x101050
425 /* [R 1] indication the initializing the activity counter by the hardware
426  was done. */
427 #define CFC_REG_AC_INIT_DONE 0x104078
428 /* [RW 13] activity counter ram access */
429 #define CFC_REG_ACTIVITY_COUNTER 0x104400
430 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
431 /* [R 1] indication the initializing the cams by the hardware was done. */
432 #define CFC_REG_CAM_INIT_DONE 0x10407c
433 /* [RW 2] Interrupt mask register #0 read/write */
434 #define CFC_REG_CFC_INT_MASK 0x104108
435 /* [R 2] Interrupt register #0 read */
436 #define CFC_REG_CFC_INT_STS 0x1040fc
437 /* [RC 2] Interrupt register #0 read clear */
438 #define CFC_REG_CFC_INT_STS_CLR 0x104100
439 /* [RW 4] Parity mask register #0 read/write */
440 #define CFC_REG_CFC_PRTY_MASK 0x104118
441 /* [R 4] Parity register #0 read */
442 #define CFC_REG_CFC_PRTY_STS 0x10410c
443 /* [RC 4] Parity register #0 read clear */
444 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
445 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
446 #define CFC_REG_CID_CAM 0x104800
447 #define CFC_REG_CONTROL0 0x104028
448 #define CFC_REG_DEBUG0 0x104050
449 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
450  vector) whether the cfc should be disabled upon it */
451 #define CFC_REG_DISABLE_ON_ERROR 0x104044
452 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
453  set one of these bits. the bit description can be found in CFC
454  specifications */
455 #define CFC_REG_ERROR_VECTOR 0x10403c
456 /* [WB 93] LCID info ram access */
457 #define CFC_REG_INFO_RAM 0x105000
458 #define CFC_REG_INFO_RAM_SIZE 1024
459 #define CFC_REG_INIT_REG 0x10404c
460 #define CFC_REG_INTERFACES 0x104058
461 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
462  field allows changing the priorities of the weighted-round-robin arbiter
463  which selects which CFC load client should be served next */
464 #define CFC_REG_LCREQ_WEIGHTS 0x104084
465 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
466 #define CFC_REG_LINK_LIST 0x104c00
467 #define CFC_REG_LINK_LIST_SIZE 256
468 /* [R 1] indication the initializing the link list by the hardware was done. */
469 #define CFC_REG_LL_INIT_DONE 0x104074
470 /* [R 9] Number of allocated LCIDs which are at empty state */
471 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
472 /* [R 9] Number of Arriving LCIDs in Link List Block */
473 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
474 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
475 /* [R 9] Number of Leaving LCIDs in Link List Block */
476 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
477 #define CFC_REG_WEAK_ENABLE_PF 0x104124
478 /* [RW 8] The event id for aggregated interrupt 0 */
479 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
480 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
481 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
482 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
483 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
484 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
485 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
486 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
487 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
488 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
489 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
490 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
491 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
492 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
493 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
494 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
495 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
496  or auto-mask-mode (1) */
497 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
498 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
499 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
500 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
501 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
502 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
503 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
504 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
505 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
506 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
507 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
508 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
509 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
510 /* [RW 16] The maximum value of the completion counter #0 */
511 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
512 /* [RW 16] The maximum value of the completion counter #1 */
513 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
514 /* [RW 16] The maximum value of the completion counter #2 */
515 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
516 /* [RW 16] The maximum value of the completion counter #3 */
517 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
518 /* [RW 13] The start address in the internal RAM for the completion
519  counters. */
520 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
521 /* [RW 32] Interrupt mask register #0 read/write */
522 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
523 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
524 /* [R 32] Interrupt register #0 read */
525 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
526 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
527 /* [RW 11] Parity mask register #0 read/write */
528 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
529 /* [R 11] Parity register #0 read */
530 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
531 /* [RC 11] Parity register #0 read clear */
532 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
533 #define CSDM_REG_ENABLE_IN1 0xc2238
534 #define CSDM_REG_ENABLE_IN2 0xc223c
535 #define CSDM_REG_ENABLE_OUT1 0xc2240
536 #define CSDM_REG_ENABLE_OUT2 0xc2244
537 /* [RW 4] The initial number of messages that can be sent to the pxp control
538  interface without receiving any ACK. */
539 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
540 /* [ST 32] The number of ACK after placement messages received */
541 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
542 /* [ST 32] The number of packet end messages received from the parser */
543 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
544 /* [ST 32] The number of requests received from the pxp async if */
545 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
546 /* [ST 32] The number of commands received in queue 0 */
547 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
548 /* [ST 32] The number of commands received in queue 10 */
549 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
550 /* [ST 32] The number of commands received in queue 11 */
551 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
552 /* [ST 32] The number of commands received in queue 1 */
553 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
554 /* [ST 32] The number of commands received in queue 3 */
555 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
556 /* [ST 32] The number of commands received in queue 4 */
557 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
558 /* [ST 32] The number of commands received in queue 5 */
559 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
560 /* [ST 32] The number of commands received in queue 6 */
561 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
562 /* [ST 32] The number of commands received in queue 7 */
563 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
564 /* [ST 32] The number of commands received in queue 8 */
565 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
566 /* [ST 32] The number of commands received in queue 9 */
567 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
568 /* [RW 13] The start address in the internal RAM for queue counters */
569 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
570 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
571 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
572 /* [R 1] parser fifo empty in sdm_sync block */
573 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
574 /* [R 1] parser serial fifo empty in sdm_sync block */
575 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
576 /* [RW 32] Tick for timer counter. Applicable only when
577  ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
578 #define CSDM_REG_TIMER_TICK 0xc2000
579 /* [RW 5] The number of time_slots in the arbitration cycle */
580 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
581 /* [RW 3] The source that is associated with arbitration element 0. Source
582  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
583  sleeping thread with priority 1; 4- sleeping thread with priority 2 */
584 #define CSEM_REG_ARB_ELEMENT0 0x200020
585 /* [RW 3] The source that is associated with arbitration element 1. Source
586  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587  sleeping thread with priority 1; 4- sleeping thread with priority 2.
588  Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
589 #define CSEM_REG_ARB_ELEMENT1 0x200024
590 /* [RW 3] The source that is associated with arbitration element 2. Source
591  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
592  sleeping thread with priority 1; 4- sleeping thread with priority 2.
593  Could not be equal to register ~csem_registers_arb_element0.arb_element0
594  and ~csem_registers_arb_element1.arb_element1 */
595 #define CSEM_REG_ARB_ELEMENT2 0x200028
596 /* [RW 3] The source that is associated with arbitration element 3. Source
597  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
598  sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
599  not be equal to register ~csem_registers_arb_element0.arb_element0 and
600  ~csem_registers_arb_element1.arb_element1 and
601  ~csem_registers_arb_element2.arb_element2 */
602 #define CSEM_REG_ARB_ELEMENT3 0x20002c
603 /* [RW 3] The source that is associated with arbitration element 4. Source
604  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
605  sleeping thread with priority 1; 4- sleeping thread with priority 2.
606  Could not be equal to register ~csem_registers_arb_element0.arb_element0
607  and ~csem_registers_arb_element1.arb_element1 and
608  ~csem_registers_arb_element2.arb_element2 and
609  ~csem_registers_arb_element3.arb_element3 */
610 #define CSEM_REG_ARB_ELEMENT4 0x200030
611 /* [RW 32] Interrupt mask register #0 read/write */
612 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
613 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
614 /* [R 32] Interrupt register #0 read */
615 #define CSEM_REG_CSEM_INT_STS_0 0x200104
616 #define CSEM_REG_CSEM_INT_STS_1 0x200114
617 /* [RW 32] Parity mask register #0 read/write */
618 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
619 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
620 /* [R 32] Parity register #0 read */
621 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
622 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
623 /* [RC 32] Parity register #0 read clear */
624 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
625 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
626 #define CSEM_REG_ENABLE_IN 0x2000a4
627 #define CSEM_REG_ENABLE_OUT 0x2000a8
628 /* [RW 32] This address space contains all registers and memories that are
629  placed in SEM_FAST block. The SEM_FAST registers are described in
630  appendix B. In order to access the sem_fast registers the base address
631  ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
632 #define CSEM_REG_FAST_MEMORY 0x220000
633 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
634  by the microcode */
635 #define CSEM_REG_FIC0_DISABLE 0x200224
636 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
637  by the microcode */
638 #define CSEM_REG_FIC1_DISABLE 0x200234
639 /* [RW 15] Interrupt table Read and write access to it is not possible in
640  the middle of the work */
641 #define CSEM_REG_INT_TABLE 0x200400
642 /* [ST 24] Statistics register. The number of messages that entered through
643  FIC0 */
644 #define CSEM_REG_MSG_NUM_FIC0 0x200000
645 /* [ST 24] Statistics register. The number of messages that entered through
646  FIC1 */
647 #define CSEM_REG_MSG_NUM_FIC1 0x200004
648 /* [ST 24] Statistics register. The number of messages that were sent to
649  FOC0 */
650 #define CSEM_REG_MSG_NUM_FOC0 0x200008
651 /* [ST 24] Statistics register. The number of messages that were sent to
652  FOC1 */
653 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
654 /* [ST 24] Statistics register. The number of messages that were sent to
655  FOC2 */
656 #define CSEM_REG_MSG_NUM_FOC2 0x200010
657 /* [ST 24] Statistics register. The number of messages that were sent to
658  FOC3 */
659 #define CSEM_REG_MSG_NUM_FOC3 0x200014
660 /* [RW 1] Disables input messages from the passive buffer May be updated
661  during run_time by the microcode */
662 #define CSEM_REG_PAS_DISABLE 0x20024c
663 /* [WB 128] Debug only. Passive buffer memory */
664 #define CSEM_REG_PASSIVE_BUFFER 0x202000
665 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
666 #define CSEM_REG_PRAM 0x240000
667 /* [R 16] Valid sleeping threads indication have bit per thread */
668 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
669 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
670 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
671 /* [RW 16] List of free threads . There is a bit per thread. */
672 #define CSEM_REG_THREADS_LIST 0x2002e4
673 /* [RW 3] The arbitration scheme of time_slot 0 */
674 #define CSEM_REG_TS_0_AS 0x200038
675 /* [RW 3] The arbitration scheme of time_slot 10 */
676 #define CSEM_REG_TS_10_AS 0x200060
677 /* [RW 3] The arbitration scheme of time_slot 11 */
678 #define CSEM_REG_TS_11_AS 0x200064
679 /* [RW 3] The arbitration scheme of time_slot 12 */
680 #define CSEM_REG_TS_12_AS 0x200068
681 /* [RW 3] The arbitration scheme of time_slot 13 */
682 #define CSEM_REG_TS_13_AS 0x20006c
683 /* [RW 3] The arbitration scheme of time_slot 14 */
684 #define CSEM_REG_TS_14_AS 0x200070
685 /* [RW 3] The arbitration scheme of time_slot 15 */
686 #define CSEM_REG_TS_15_AS 0x200074
687 /* [RW 3] The arbitration scheme of time_slot 16 */
688 #define CSEM_REG_TS_16_AS 0x200078
689 /* [RW 3] The arbitration scheme of time_slot 17 */
690 #define CSEM_REG_TS_17_AS 0x20007c
691 /* [RW 3] The arbitration scheme of time_slot 18 */
692 #define CSEM_REG_TS_18_AS 0x200080
693 /* [RW 3] The arbitration scheme of time_slot 1 */
694 #define CSEM_REG_TS_1_AS 0x20003c
695 /* [RW 3] The arbitration scheme of time_slot 2 */
696 #define CSEM_REG_TS_2_AS 0x200040
697 /* [RW 3] The arbitration scheme of time_slot 3 */
698 #define CSEM_REG_TS_3_AS 0x200044
699 /* [RW 3] The arbitration scheme of time_slot 4 */
700 #define CSEM_REG_TS_4_AS 0x200048
701 /* [RW 3] The arbitration scheme of time_slot 5 */
702 #define CSEM_REG_TS_5_AS 0x20004c
703 /* [RW 3] The arbitration scheme of time_slot 6 */
704 #define CSEM_REG_TS_6_AS 0x200050
705 /* [RW 3] The arbitration scheme of time_slot 7 */
706 #define CSEM_REG_TS_7_AS 0x200054
707 /* [RW 3] The arbitration scheme of time_slot 8 */
708 #define CSEM_REG_TS_8_AS 0x200058
709 /* [RW 3] The arbitration scheme of time_slot 9 */
710 #define CSEM_REG_TS_9_AS 0x20005c
711 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
712  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
713 #define CSEM_REG_VFPF_ERR_NUM 0x200380
714 /* [RW 1] Parity mask register #0 read/write */
715 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
716 /* [R 1] Parity register #0 read */
717 #define DBG_REG_DBG_PRTY_STS 0xc09c
718 /* [RC 1] Parity register #0 read clear */
719 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
720 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
721  * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
722  * 4.Completion function=0; 5.Error handling=0 */
723 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
724 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
725  as 14*X+Y. */
726 #define DMAE_REG_CMD_MEM 0x102400
727 #define DMAE_REG_CMD_MEM_SIZE 224
728 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
729  initial value is all ones. */
730 #define DMAE_REG_CRC16C_INIT 0x10201c
731 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
732  CRC-16 T10 initial value is all ones. */
733 #define DMAE_REG_CRC16T10_INIT 0x102020
734 /* [RW 2] Interrupt mask register #0 read/write */
735 #define DMAE_REG_DMAE_INT_MASK 0x102054
736 /* [RW 4] Parity mask register #0 read/write */
737 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
738 /* [R 4] Parity register #0 read */
739 #define DMAE_REG_DMAE_PRTY_STS 0x102058
740 /* [RC 4] Parity register #0 read clear */
741 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
742 /* [RW 1] Command 0 go. */
743 #define DMAE_REG_GO_C0 0x102080
744 /* [RW 1] Command 1 go. */
745 #define DMAE_REG_GO_C1 0x102084
746 /* [RW 1] Command 10 go. */
747 #define DMAE_REG_GO_C10 0x102088
748 /* [RW 1] Command 11 go. */
749 #define DMAE_REG_GO_C11 0x10208c
750 /* [RW 1] Command 12 go. */
751 #define DMAE_REG_GO_C12 0x102090
752 /* [RW 1] Command 13 go. */
753 #define DMAE_REG_GO_C13 0x102094
754 /* [RW 1] Command 14 go. */
755 #define DMAE_REG_GO_C14 0x102098
756 /* [RW 1] Command 15 go. */
757 #define DMAE_REG_GO_C15 0x10209c
758 /* [RW 1] Command 2 go. */
759 #define DMAE_REG_GO_C2 0x1020a0
760 /* [RW 1] Command 3 go. */
761 #define DMAE_REG_GO_C3 0x1020a4
762 /* [RW 1] Command 4 go. */
763 #define DMAE_REG_GO_C4 0x1020a8
764 /* [RW 1] Command 5 go. */
765 #define DMAE_REG_GO_C5 0x1020ac
766 /* [RW 1] Command 6 go. */
767 #define DMAE_REG_GO_C6 0x1020b0
768 /* [RW 1] Command 7 go. */
769 #define DMAE_REG_GO_C7 0x1020b4
770 /* [RW 1] Command 8 go. */
771 #define DMAE_REG_GO_C8 0x1020b8
772 /* [RW 1] Command 9 go. */
773 #define DMAE_REG_GO_C9 0x1020bc
774 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
775  input is disregarded; valid is deasserted; all other signals are treated
776  as usual; if 1 - normal activity. */
777 #define DMAE_REG_GRC_IFEN 0x102008
778 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
779  acknowledge input is disregarded; valid is deasserted; full is asserted;
780  all other signals are treated as usual; if 1 - normal activity. */
781 #define DMAE_REG_PCI_IFEN 0x102004
782 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
783  initial value to the credit counter; related to the address. Read returns
784  the current value of the counter. */
785 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
786 /* [RW 8] Aggregation command. */
787 #define DORQ_REG_AGG_CMD0 0x170060
788 /* [RW 8] Aggregation command. */
789 #define DORQ_REG_AGG_CMD1 0x170064
790 /* [RW 8] Aggregation command. */
791 #define DORQ_REG_AGG_CMD2 0x170068
792 /* [RW 8] Aggregation command. */
793 #define DORQ_REG_AGG_CMD3 0x17006c
794 /* [RW 28] UCM Header. */
795 #define DORQ_REG_CMHEAD_RX 0x170050
796 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
797 #define DORQ_REG_DB_ADDR0 0x17008c
798 /* [RW 5] Interrupt mask register #0 read/write */
799 #define DORQ_REG_DORQ_INT_MASK 0x170180
800 /* [R 5] Interrupt register #0 read */
801 #define DORQ_REG_DORQ_INT_STS 0x170174
802 /* [RC 5] Interrupt register #0 read clear */
803 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
804 /* [RW 2] Parity mask register #0 read/write */
805 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
806 /* [R 2] Parity register #0 read */
807 #define DORQ_REG_DORQ_PRTY_STS 0x170184
808 /* [RC 2] Parity register #0 read clear */
809 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
810 /* [RW 8] The address to write the DPM CID to STORM. */
811 #define DORQ_REG_DPM_CID_ADDR 0x170044
812 /* [RW 5] The DPM mode CID extraction offset. */
813 #define DORQ_REG_DPM_CID_OFST 0x170030
814 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
815 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
816 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
817 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
818 /* [R 13] Current value of the DQ FIFO fill level according to following
819  pointer. The range is 0 - 256 FIFO rows; where each row stands for the
820  doorbell. */
821 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
822 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
823  equal to full threshold; reset on full clear. */
824 #define DORQ_REG_DQ_FULL_ST 0x1700c0
825 /* [RW 28] The value sent to CM header in the case of CFC load error. */
826 #define DORQ_REG_ERR_CMHEAD 0x170058
827 #define DORQ_REG_IF_EN 0x170004
828 #define DORQ_REG_MODE_ACT 0x170008
829 /* [RW 5] The normal mode CID extraction offset. */
830 #define DORQ_REG_NORM_CID_OFST 0x17002c
831 /* [RW 28] TCM Header when only TCP context is loaded. */
832 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
833 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
834  Interface. */
835 #define DORQ_REG_OUTST_REQ 0x17003c
836 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
837 #define DORQ_REG_REGN 0x170038
838 /* [R 4] Current value of response A counter credit. Initial credit is
839  configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
840  register. */
841 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
842 /* [R 4] Current value of response B counter credit. Initial credit is
843  configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
844  register. */
845 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
846 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
847  writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
848  read reads this written value. */
849 #define DORQ_REG_RSP_INIT_CRD 0x170048
850 /* [RW 4] Initial activity counter value on the load request; when the
851  shortcut is done. */
852 #define DORQ_REG_SHRT_ACT_CNT 0x170070
853 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
854 #define DORQ_REG_SHRT_CMHEAD 0x170054
855 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
856 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
857 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
858 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
859 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
860 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
861 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
862 #define HC_REG_AGG_INT_0 0x108050
863 #define HC_REG_AGG_INT_1 0x108054
864 #define HC_REG_ATTN_BIT 0x108120
865 #define HC_REG_ATTN_IDX 0x108100
866 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
867 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
868 #define HC_REG_ATTN_NUM_P0 0x108038
869 #define HC_REG_ATTN_NUM_P1 0x10803c
870 #define HC_REG_COMMAND_REG 0x108180
871 #define HC_REG_CONFIG_0 0x108000
872 #define HC_REG_CONFIG_1 0x108004
873 #define HC_REG_FUNC_NUM_P0 0x1080ac
874 #define HC_REG_FUNC_NUM_P1 0x1080b0
875 /* [RW 3] Parity mask register #0 read/write */
876 #define HC_REG_HC_PRTY_MASK 0x1080a0
877 /* [R 3] Parity register #0 read */
878 #define HC_REG_HC_PRTY_STS 0x108094
879 /* [RC 3] Parity register #0 read clear */
880 #define HC_REG_HC_PRTY_STS_CLR 0x108098
881 #define HC_REG_INT_MASK 0x108108
882 #define HC_REG_LEADING_EDGE_0 0x108040
883 #define HC_REG_LEADING_EDGE_1 0x108048
884 #define HC_REG_MAIN_MEMORY 0x108800
885 #define HC_REG_MAIN_MEMORY_SIZE 152
886 #define HC_REG_P0_PROD_CONS 0x108200
887 #define HC_REG_P1_PROD_CONS 0x108400
888 #define HC_REG_PBA_COMMAND 0x108140
889 #define HC_REG_PCI_CONFIG_0 0x108010
890 #define HC_REG_PCI_CONFIG_1 0x108014
891 #define HC_REG_STATISTIC_COUNTERS 0x109000
892 #define HC_REG_TRAILING_EDGE_0 0x108044
893 #define HC_REG_TRAILING_EDGE_1 0x10804c
894 #define HC_REG_UC_RAM_ADDR_0 0x108028
895 #define HC_REG_UC_RAM_ADDR_1 0x108030
896 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
897 #define HC_REG_VQID_0 0x108008
898 #define HC_REG_VQID_1 0x10800c
899 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
900 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
901 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
902 /* [R 4] Debug: attn_fsm */
903 #define IGU_REG_ATTN_FSM 0x130054
904 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
905 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
906 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
907  * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
908  * write done didn't receive. */
909 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
910 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
911 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
912 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
913 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
914  * is clear. The bits in this registers are set and clear via the producer
915  * command. Data valid only in addresses 0-4. all the rest are zero. */
916 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
917 /* [R 5] Debug: ctrl_fsm */
918 #define IGU_REG_CTRL_FSM 0x130064
919 /* [R 1] data available for error memory. If this bit is clear do not red
920  * from error_handling_memory. */
921 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
922 /* [RW 11] Parity mask register #0 read/write */
923 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
924 /* [R 11] Parity register #0 read */
925 #define IGU_REG_IGU_PRTY_STS 0x13009c
926 /* [RC 11] Parity register #0 read clear */
927 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
928 /* [R 4] Debug: int_handle_fsm */
929 #define IGU_REG_INT_HANDLE_FSM 0x130050
930 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
931 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
932  * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
933  * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
934 #define IGU_REG_MAPPING_MEMORY 0x131000
935 #define IGU_REG_MAPPING_MEMORY_SIZE 136
936 #define IGU_REG_PBA_STATUS_LSB 0x130138
937 #define IGU_REG_PBA_STATUS_MSB 0x13013c
938 #define IGU_REG_PCI_PF_MSI_EN 0x130140
939 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
940 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
941 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
942  * pending; 1 = pending. Pendings means interrupt was asserted; and write
943  * done was not received. Data valid only in addresses 0-4. all the rest are
944  * zero. */
945 #define IGU_REG_PENDING_BITS_STATUS 0x130300
946 #define IGU_REG_PF_CONFIGURATION 0x130154
947 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
948  * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
949  * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
950  * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
951  * - In backward compatible mode; for non default SB; each even line in the
952  * memory holds the U producer and each odd line hold the C producer. The
953  * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
954  * last 20 producers are for the DSB for each PF. each PF has five segments
955  * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
956  * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
957 #define IGU_REG_PROD_CONS_MEMORY 0x132000
958 /* [R 3] Debug: pxp_arb_fsm */
959 #define IGU_REG_PXP_ARB_FSM 0x130068
960 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
961  * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
962  * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
963  * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
964 #define IGU_REG_RESET_MEMORIES 0x130158
965 /* [R 4] Debug: sb_ctrl_fsm */
966 #define IGU_REG_SB_CTRL_FSM 0x13004c
967 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
968 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
969 #define IGU_REG_SB_MASK_LSB 0x130164
970 #define IGU_REG_SB_MASK_MSB 0x130168
971 /* [RW 16] Number of command that were dropped without causing an interrupt
972  * due to: read access for WO BAR address; or write access for RO BAR
973  * address or any access for reserved address or PCI function error is set
974  * and address is not MSIX; PBA or cleanup */
975 #define IGU_REG_SILENT_DROP 0x13016c
976 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
977  * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
978  * PF; 68-71 number of ATTN messages per PF */
979 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
980 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
981  * timer mask command arrives. Value must be bigger than 100. */
982 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
983 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
984 #define IGU_REG_VF_CONFIGURATION 0x130170
985 /* [WB_R 32] Each bit represent write done pending bits status for that SB
986  * (MSI/MSIX message was sent and write done was not received yet). 0 =
987  * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
988 #define IGU_REG_WRITE_DONE_PENDING 0x130480
989 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
990 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
991 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
992 #define MCP_REG_MCPR_GP_INPUTS 0x800c0
993 #define MCP_REG_MCPR_GP_OENABLE 0x800c8
994 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
995 #define MCP_REG_MCPR_IMC_COMMAND 0x85900
996 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920
997 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
998 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
999 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
1000 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
1001 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
1002 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
1003 #define MCP_REG_MCPR_NVM_READ 0x86410
1004 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1005 #define MCP_REG_MCPR_NVM_WRITE 0x86408
1006 #define MCP_REG_MCPR_SCRATCH 0xa0000
1007 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1008 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1009 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1010  follows: [0] NIG attention for function0; [1] NIG attention for
1011  function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1012  [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1013  GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1014  glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1015  [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1016  MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1017  Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1018  interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1019  error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1020  interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1021  Parity error; [31] PBF Hw interrupt; */
1022 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1023 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1024 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1025  NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1026  mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1027  [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1028  PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1029  function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1030  Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1031  mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1032  BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1033  Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1034  interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1035  Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1036  interrupt; */
1037 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1038 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1039  follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1040  Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1041  interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1042  error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1043  interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1044  NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1045  [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1046  interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1047  Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1048  Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1049  Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1050  interrupt; */
1051 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1052 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1053 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1054  PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1055  [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1056  [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1057  XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1058  DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1059  error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1060  PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1061  [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1062  [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1063  [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1064  [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1065 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1066 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1067  follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1068  error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1069  PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1070  interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1071  error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1072  Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1073  pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1074  MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1075  SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1076  timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1077  func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1078  attn1; */
1079 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1080 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1081 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1082  CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1083  Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1084  Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1085  error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1086  interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1087  MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1088  Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1089  timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1090  func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1091  func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1092  timers attn_4 func1; [30] General attn0; [31] General attn1; */
1093 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1094 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1095  follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1096  General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1097  [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1098  attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1099  [14] General attn16; [15] General attn17; [16] General attn18; [17]
1100  General attn19; [18] General attn20; [19] General attn21; [20] Main power
1101  interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1102  Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1103  Latched timeout attention; [27] GRC Latched reserved access attention;
1104  [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1105  Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1106 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1107 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1108 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1109  General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1110  [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1111  attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1112  General attn13; [12] General attn14; [13] General attn15; [14] General
1113  attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1114  [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1115  RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1116  RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1117  attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1118  rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1119  ump_tx_parity; [31] MCP Latched scpad_parity; */
1120 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1121 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1122  * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1123  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1124  * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1125 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1126 /* [W 14] write to this register results with the clear of the latched
1127  signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1128  d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1129  latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1130  GRC Latched reserved access attention; one in d7 clears Latched
1131  rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1132  Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1133  ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1134  pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1135  from this register return zero */
1136 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1137 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1138  as follows: [0] NIG attention for function0; [1] NIG attention for
1139  function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1140  0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1141  GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1142  function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1143  Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1144  SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1145  indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1146  [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1147  SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1148  TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1149  TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1150 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1151 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1152 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1153 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1154 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1155 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1156 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1157 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1158  as follows: [0] NIG attention for function0; [1] NIG attention for
1159  function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1160  1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1161  GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1162  function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1163  Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1164  SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1165  indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1166  [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1167  SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1168  TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1169  TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1170 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1171 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1172 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1173 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1174 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1175 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1176 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1177 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1178  as follows: [0] NIG attention for function0; [1] NIG attention for
1179  function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1180  0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1181  GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1182  function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1183  Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1184  SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1185  indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1186  [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1187  SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1188  TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1189  TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1190 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1191 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1192 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1193  as follows: [0] NIG attention for function0; [1] NIG attention for
1194  function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1195  0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1196  GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1197  function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1198  Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1199  SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1200  indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1201  [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1202  SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1203  TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1204  TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1205 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1206 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1207 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1208  as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1209  Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1210  interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1211  error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1212  interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1213  NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1214  [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1215  interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1216  Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1217  Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1218  Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1219  interrupt; */
1220 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1221 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1222 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1223  as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1224  Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1225  interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1226  error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1227  interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1228  NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1229  [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1230  interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1231  Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1232  Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1233  Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1234  interrupt; */
1235 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1236 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1237 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1238  as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1239  Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1240  interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1241  error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1242  interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1243  NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1244  [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1245  interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1246  Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1247  Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1248  Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1249  interrupt; */
1250 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1251 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1252 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1253  as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1254  Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1255  interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1256  error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1257  interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1258  NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1259  [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1260  interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1261  Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1262  Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1263  Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1264  interrupt; */
1265 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1266 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1267 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1268  as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1269  Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1270  [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1271  interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1272  error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1273  Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1274  pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1275  MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1276  SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1277  timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1278  func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1279  attn1; */
1280 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1281 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1282 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1283  as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1284  Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1285  [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1286  interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1287  error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1288  Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1289  pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1290  MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1291  SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1292  timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1293  func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1294  attn1; */
1295 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1296 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1297 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1298  as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1299  Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1300  [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1301  interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1302  error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1303  Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1304  pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1305  MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1306  SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1307  timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1308  func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1309  attn1; */
1310 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1311 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1312 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1313  as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1314  Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1315  [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1316  interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1317  error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1318  Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1319  pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1320  MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1321  SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1322  timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1323  func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1324  attn1; */
1325 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1326 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1327 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1328  as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1329  General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1330  [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1331  attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1332  [14] General attn16; [15] General attn17; [16] General attn18; [17]
1333  General attn19; [18] General attn20; [19] General attn21; [20] Main power
1334  interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1335  Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1336  Latched timeout attention; [27] GRC Latched reserved access attention;
1337  [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1338  Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1339 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1340 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1341 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1342 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1343 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1344 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1345 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1346  as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1347  General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1348  [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1349  attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1350  [14] General attn16; [15] General attn17; [16] General attn18; [17]
1351  General attn19; [18] General attn20; [19] General attn21; [20] Main power
1352  interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1353  Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1354  Latched timeout attention; [27] GRC Latched reserved access attention;
1355  [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1356  Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1357 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1358 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1359 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1360 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1361 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1362 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1363 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1364  as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1365  General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1366  [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1367  attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1368  [14] General attn16; [15] General attn17; [16] General attn18; [17]
1369  General attn19; [18] General attn20; [19] General attn21; [20] Main power
1370  interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1371  Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1372  Latched timeout attention; [27] GRC Latched reserved access attention;
1373  [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1374  Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1375 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1376 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1377 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1378  as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1379  General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1380  [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1381  attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1382  [14] General attn16; [15] General attn17; [16] General attn18; [17]
1383  General attn19; [18] General attn20; [19] General attn21; [20] Main power
1384  interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1385  Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1386  Latched timeout attention; [27] GRC Latched reserved access attention;
1387  [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1388  Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1389 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1390 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1391 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1392  * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1393  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1394  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1395  * parity; [31-10] Reserved; */
1396 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
1397 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1398  * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1399  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1400  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1401  * parity; [31-10] Reserved; */
1402 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
1403 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1404  128 bit vector */
1405 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1406 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1407 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1408 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1409 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1410 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1411 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1412 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1413 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1414 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1415 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1416 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1417 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1418 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1419 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1420  0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1421  function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1422  [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1423  [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1424  function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1425  Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1426  SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1427  for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1428  Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1429  interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1430  Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1431  Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1432 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1433 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1434 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1435  0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1436  error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1437  interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1438  Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1439  interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1440  DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1441  error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1442  PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1443  [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1444  [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1445  [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1446  [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1447 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1448 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1449 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1450  [9:8] = raserved. Zero = mask; one = unmask */
1451 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1452 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1453 /* [RW 1] If set a system kill occurred */
1454 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1455 /* [RW 32] Represent the status of the input vector to the AEU when a system
1456  kill occurred. The register is reset in por reset. Mapped as follows: [0]
1457  NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1458  mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1459  [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1460  PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1461  function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1462  Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1463  mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1464  BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1465  Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1466  interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1467  Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1468  interrupt; */
1469 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1470 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1471 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1472 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1473 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1474  Port. */
1475 #define MISC_REG_BOND_ID 0xa400
1476 /* [R 8] These bits indicate the metal revision of the chip. This value
1477  starts at 0x00 for each all-layer tape-out and increments by one for each
1478  tape-out. */
1479 #define MISC_REG_CHIP_METAL 0xa404
1480 /* [R 16] These bits indicate the part number for the chip. */
1481 #define MISC_REG_CHIP_NUM 0xa408
1482 /* [R 4] These bits indicate the base revision of the chip. This value
1483  starts at 0x0 for the A0 tape-out and increments by one for each
1484  all-layer tape-out. */
1485 #define MISC_REG_CHIP_REV 0xa40c
1486 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1487  * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1488  * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1489 #define MISC_REG_CHIP_TYPE 0xac60
1490 #define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)
1491 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
1492 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
1493  * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
1494  * 25MHz. Reset on hard reset. */
1495 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
1496 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
1497  * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
1498 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
1499 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1500  * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
1501  * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1502  * the FW command that all Queues are empty is disabled. When 0 indicates
1503  * that the FW command that all Queues are empty is enabled. [2] - FW Early
1504  * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
1505  * Exit command is disabled. When 0 indicates that the FW Early Exit command
1506  * is enabled. This bit applicable only in the EXIT Events Mask registers.
1507  * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1508  * is disabled. When 0 indicates that the PBF Request indication is enabled.
1509  * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1510  * Request indication is disabled. When 0 indicates that the Tx Other Than
1511  * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1512  * indicates that the RX EEE LPI Status indication is disabled. When 0
1513  * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
1514  * Events Masks registers; this bit masks the falling edge detect of the LPI
1515  * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1516  * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
1517  * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1518  * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
1519  * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1520  * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
1521  * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1522  * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
1523  * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1524  * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
1525  * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
1526  * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
1527  * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1528  * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1529  * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1530  * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1531  * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1532  * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1533  * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
1534  * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1535  * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1536  * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1537  * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1538  * REQ indication is disabled. When =0 indicates that the L1 indication is
1539  * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1540  * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
1541  * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1542  * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1543  * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1544  * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
1545  * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1546  * When =0 indicates that the L1 Status Falling Edge Detect indication from
1547  * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1548  * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
1549 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
1550 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1551  * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
1552  * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1553  * that the FW command that all Queues are empty is disabled. When 0
1554  * indicates that the FW command that all Queues are empty is enabled. [2] -
1555  * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
1556  * Early Exit command is disabled. When 0 indicates that the FW Early Exit
1557  * command is enabled. This bit applicable only in the EXIT Events Mask
1558  * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1559  * indication is disabled. When 0 indicates that the PBF Request indication
1560  * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1561  * Than PBF Request indication is disabled. When 0 indicates that the Tx
1562  * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1563  * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
1564  * When 0 indicates that the RX LPI Status indication is enabled. In the
1565  * EXIT Events Masks registers; this bit masks the falling edge detect of
1566  * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1567  * indicates that the Tx Pause indication is disabled. When 0 indicates that
1568  * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1569  * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
1570  * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1571  * indicates that the QM IDLE indication is disabled. When 0 indicates that
1572  * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
1573  * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1574  * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
1575  * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1576  * Status indication from the PCIE CORE is disabled. When 0 indicates that
1577  * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
1578  * EXIT Events Masks registers; this bit masks the falling edge detect of
1579  * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1580  * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
1581  * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1582  * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
1583  * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1584  * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1585  * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1586  * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1587  * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1588  * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1589  * indicates that the L1 REQ indication is disabled. When =0 indicates that
1590  * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1591  * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
1592  * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1593  * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
1594  * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1595  * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1596  * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
1597  * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1598  * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1599  * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
1600  * Reset on hard reset. */
1601 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
1602 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1603  * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1604  * register. Reset on hard reset. */
1605 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
1606 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1607  * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1608  * register. Reset on hard reset. */
1609 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
1610 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1611  32 clients. Each client can be controlled by one driver only. One in each
1612  bit represent that this driver control the appropriate client (Ex: bit 5
1613  is set means this driver control client number 5). addr1 = set; addr0 =
1614  clear; read from both addresses will give the same result = status. write
1615  to address 1 will set a request to control all the clients that their
1616  appropriate bit (in the write command) is set. if the client is free (the
1617  appropriate bit in all the other drivers is clear) one will be written to
1618  that driver register; if the client isn't free the bit will remain zero.
1619  if the appropriate bit is set (the driver request to gain control on a
1620  client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1621  interrupt will be asserted). write to address 0 will set a request to
1622  free all the clients that their appropriate bit (in the write command) is
1623  set. if the appropriate bit is clear (the driver request to free a client
1624  it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1625  be asserted). */
1626 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1627 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1628 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1629  only. */
1630 #define MISC_REG_E1HMF_MODE 0xa5f8
1631 /* [R 1] Status of four port mode path swap input pin. */
1632 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1633 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1634  the path_swap output is equal to 4 port mode path swap input pin; if it
1635  is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1636  Overwrite value. If bit[0] of this register is 1 this is the value that
1637  receives the path_swap output. Reset on Hard reset. */
1638 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1639 /* [R 1] Status of 4 port mode port swap input pin. */
1640 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1641 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1642  the port_swap output is equal to 4 port mode port swap input pin; if it
1643  is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1644  Overwrite value. If bit[0] of this register is 1 this is the value that
1645  receives the port_swap output. Reset on Hard reset. */
1646 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1647 /* [RW 32] Debug only: spare RW register reset by core reset */
1648 #define MISC_REG_GENERIC_CR_0 0xa460
1649 #define MISC_REG_GENERIC_CR_1 0xa464
1650 /* [RW 32] Debug only: spare RW register reset by por reset */
1651 #define MISC_REG_GENERIC_POR_1 0xa474
1652 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1653  use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1654  can not be configured as an output. Each output has its output enable in
1655  the MCP register space; but this bit needs to be set to make use of that.
1656  Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1657  set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1658  When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1659  the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1660  spare. Global register. Reset by hard reset. */
1661 #define MISC_REG_GEN_PURP_HWG 0xa9a0
1662 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1663  these bits is written as a '1'; the corresponding SPIO bit will turn off
1664  it's drivers and become an input. This is the reset state of all GPIO
1665  pins. The read value of these bits will be a '1' if that last command
1666  (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1667  [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1668  as a '1'; the corresponding GPIO bit will drive low. The read value of
1669  these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1670  this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1671  SET When any of these bits is written as a '1'; the corresponding GPIO
1672  bit will drive high (if it has that capability). The read value of these
1673  bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1674  bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1675  RO; These bits indicate the read value of each of the eight GPIO pins.
1676  This is the result value of the pin; not the drive value. Writing these
1677  bits will have not effect. */
1678 #define MISC_REG_GPIO 0xa490
1679 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1680  IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1681  p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1682  [7] p1_gpio_3; */
1683 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1684 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1685  '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1686  This will acknowledge an interrupt on the falling edge of corresponding
1687  GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1688  Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1689  register. This will acknowledge an interrupt on the rising edge of
1690  corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1691  OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1692  value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1693  of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1694  interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1695  is '1'; then the interrupt is due to a high to low edge (reset value 0).
1696  [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1697  current GPIO interrupt state for each GPIO pin. This bit is cleared when
1698  the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1699  set when the GPIO input does not match the current value in #OLD_VALUE
1700  (reset value 0). */
1701 #define MISC_REG_GPIO_INT 0xa494
1702 /* [R 28] this field hold the last information that caused reserved
1703  attention. bits [19:0] - address; [22:20] function; [23] reserved;
1704  [27:24] the master that caused the attention - according to the following
1705  encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1706  dbu; 8 = dmae */
1707 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1708 /* [R 28] this field hold the last information that caused timeout
1709  attention. bits [19:0] - address; [22:20] function; [23] reserved;
1710  [27:24] the master that caused the attention - according to the following
1711  encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1712  dbu; 8 = dmae */
1713 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1714 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1715  access that does not finish within
1716  ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1717  cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1718  assert it attention output. */
1719 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1720 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1721  the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1722  111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1723  (reset value 001) Charge pump current control; 111 for 720u; 011 for
1724  600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1725  Global bias control; When bit 7 is high bias current will be 10 0gh; When
1726  bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1727  Pll_observe (reset value 010) Bits to control observability. bit 10 is
1728  for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1729  (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1730  and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1731  sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1732  internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1733  connected to RESET input directly. [15] capRetry_en (reset value 0)
1734  enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1735  value 0) bit to continuously monitor vco freq (inverted). [17]
1736  freqDetRestart_en (reset value 0) bit to enable restart when not freq
1737  locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1738  retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1739  0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1740  pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1741  (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1742  0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1743  bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1744  enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1745  capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1746  restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1747  register bits. */
1748 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1749 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1750 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1751  * reset. */
1752 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
1753 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1754 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
1755 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1756  * reset. */
1757 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
1758 /* [RW 4] Interrupt mask register #0 read/write */
1759 #define MISC_REG_MISC_INT_MASK 0xa388
1760 /* [RW 1] Parity mask register #0 read/write */
1761 #define MISC_REG_MISC_PRTY_MASK 0xa398
1762 /* [R 1] Parity register #0 read */
1763 #define MISC_REG_MISC_PRTY_STS 0xa38c
1764 /* [RC 1] Parity register #0 read clear */
1765 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1766 #define MISC_REG_NIG_WOL_P0 0xa270
1767 #define MISC_REG_NIG_WOL_P1 0xa274
1768 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1769  assertion */
1770 #define MISC_REG_PCIE_HOT_RESET 0xa618
1771 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1772  inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1773  divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1774  divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1775  divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1776  divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1777  freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1778  (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1779  1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1780  Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1781  value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1782  1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1783  [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1784  Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1785  testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1786  testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1787  testa_en (reset value 0); */
1788 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1789 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1790 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1791 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1792 /* [R 1] Status of 4 port mode enable input pin. */
1793 #define MISC_REG_PORT4MODE_EN 0xa750
1794 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1795  * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1796  * the port4mode_en output is equal to bit[1] of this register; [1] -
1797  * Overwrite value. If bit[0] of this register is 1 this is the value that
1798  * receives the port4mode_en output . */
1799 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1800 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1801  write/read zero = the specific block is in reset; addr 0-wr- the write
1802  value will be written to the register; addr 1-set - one will be written
1803  to all the bits that have the value of one in the data written (bits that
1804  have the value of zero will not be change) ; addr 2-clear - zero will be
1805  written to all the bits that have the value of one in the data written
1806  (bits that have the value of zero will not be change); addr 3-ignore;
1807  read ignore from all addr except addr 00; inside order of the bits is:
1808  [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1809  [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1810  rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1811  [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1812  Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1813  rst_pxp_rq_rd_wr; 31:17] reserved */
1814 #define MISC_REG_RESET_REG_1 0xa580
1815 #define MISC_REG_RESET_REG_2 0xa590
1816 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1817  shared with the driver resides */
1818 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1819 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1820  the corresponding SPIO bit will turn off it's drivers and become an
1821  input. This is the reset state of all SPIO pins. The read value of these
1822  bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1823  bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1824  is written as a '1'; the corresponding SPIO bit will drive low. The read
1825  value of these bits will be a '1' if that last command (#SET; #CLR; or
1826 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1827  these bits is written as a '1'; the corresponding SPIO bit will drive
1828  high (if it has that capability). The read value of these bits will be a
1829  '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1830  (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1831  each of the eight SPIO pins. This is the result value of the pin; not the
1832  drive value. Writing these bits will have not effect. Each 8 bits field
1833  is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1834  from VAUX. (This is an output pin only; the FLOAT field is not applicable
1835  for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1836  VAUX. (This is an output pin only; FLOAT field is not applicable for this
1837  pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1838  select VAUX supply. (This is an output pin only; it is not controlled by
1839  the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1840  field is not applicable for this pin; only the VALUE fields is relevant -
1841  it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1842  Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1843  device ID select; read by UMP firmware. */
1844 #define MISC_REG_SPIO 0xa4fc
1845 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1846  according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1847  [7:0] reserved */
1848 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1849 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1850  corresponding bit in the #OLD_VALUE register. This will acknowledge an
1851  interrupt on the falling edge of corresponding SPIO input (reset value
1852  0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1853  in the #OLD_VALUE register. This will acknowledge an interrupt on the
1854  rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1855  RO; These bits indicate the old value of the SPIO input value. When the
1856  ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1857  that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1858  to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1859  interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1860  RO; These bits indicate the current SPIO interrupt state for each SPIO
1861  pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1862  command bit is written. This bit is set when the SPIO input does not
1863  match the current value in #OLD_VALUE (reset value 0). */
1864 #define MISC_REG_SPIO_INT 0xa500
1865 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1866  the counter reached zero and the reload bit
1867  (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1868 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1869 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1870  in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1871  timer 8 */
1872 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1873 /* [R 1] Status of two port mode path swap input pin. */
1874 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1875 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1876  path_swap output is equal to 2 port mode path swap input pin; if it is 1
1877  - the path_swap output is equal to bit[1] of this register; [1] -
1878  Overwrite value. If bit[0] of this register is 1 this is the value that
1879  receives the path_swap output. Reset on Hard reset. */
1880 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1881 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1882  loaded; 0-prepare; -unprepare */
1883 #define MISC_REG_UNPREPARED 0xa424
1884 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1885 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1886 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1887 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1888 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1889 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1890  * not it is the recipient of the message on the MDIO interface. The value
1891  * is compared to the value on ctrl_md_devad. Drives output
1892  * misc_xgxs0_phy_addr. Global register. */
1893 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1894 #define MISC_REG_WC0_RESET 0xac30
1895 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1896  side. This should be less than or equal to phy_port_mode; if some of the
1897  ports are not used. This enables reduction of frequency on the core side.
1898  This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1899  Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1900  input for the XMAC_MP core; and should be changed only while reset is
1901  held low. Reset on Hard reset. */
1902 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1903 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1904  Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1905  01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1906  XMAC_MP core; and should be changed only while reset is held low. Reset
1907  on Hard reset. */
1908 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1909 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1910  * Reads from this register will clear bits 31:0. */
1911 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1912 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1913  * 31:0. Reads from this register will clear bits 31:0. */
1914 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1915 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1916 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1917 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1918 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1919 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1920 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1921 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1922 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1923 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1924 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1925 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1926 /* [RW 1] Input enable for RX_BMAC0 IF */
1927 #define NIG_REG_BMAC0_IN_EN 0x100ac
1928 /* [RW 1] output enable for TX_BMAC0 IF */
1929 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1930 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1931 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1932 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1933 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1934 /* [RW 1] output enable for RX BRB1 port0 IF */
1935 #define NIG_REG_BRB0_OUT_EN 0x100f8
1936 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1937 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1938 /* [RW 1] output enable for RX BRB1 port1 IF */
1939 #define NIG_REG_BRB1_OUT_EN 0x100fc
1940 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1941 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1942 /* [RW 1] output enable for RX BRB1 LP IF */
1943 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1944 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1945  error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1946  72:73]-vnic_num; 81:74]-sideband_info */
1947 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1948 /* [RW 1] Input enable for TX Debug packet */
1949 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1950 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1951  packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1952  First packet may be deleted from the middle. And last packet will be
1953  always deleted till the end. */
1954 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1955 /* [RW 1] Output enable to EMAC0 */
1956 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1957 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1958  to emac for port0; other way to bmac for port0 */
1959 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1960 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1961 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1962 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1963 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1964 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1965 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1966 /* [RW 1] Input enable for RX_EMAC0 IF */
1967 #define NIG_REG_EMAC0_IN_EN 0x100a4
1968 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1969 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1970 /* [R 1] status from emac0. This bit is set when MDINT from either the
1971  EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1972  be cleared in the attached PHY device that is driving the MINT pin. */
1973 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1974 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1975  are described in appendix A. In order to access the BMAC0 registers; the
1976  base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1977  added to each BMAC register offset */
1978 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1979 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1980  are described in appendix A. In order to access the BMAC0 registers; the
1981  base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1982  added to each BMAC register offset */
1983 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1984 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1985 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1986 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1987  packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1988 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1989 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1990  logic for interrupts must be used. Enable per bit of interrupt of
1991  ~latch_status.latch_status */
1992 #define NIG_REG_LATCH_BC_0 0x16210
1993 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1994  status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1995  b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1996  b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1997  b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1998  b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1999  b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
2000  b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
2001  b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
2002  b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
2003  b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
2004  b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
2005  b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
2006 #define NIG_REG_LATCH_STATUS_0 0x18000
2007 /* [RW 1] led 10g for port 0 */
2008 #define NIG_REG_LED_10G_P0 0x10320
2009 /* [RW 1] led 10g for port 1 */
2010 #define NIG_REG_LED_10G_P1 0x10324
2011 /* [RW 1] Port0: This bit is set to enable the use of the
2012  ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
2013  defined below. If this bit is cleared; then the blink rate will be about
2014  8Hz. */
2015 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
2016 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
2017  Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2018  is reset to 0x080; giving a default blink period of approximately 8Hz. */
2019 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
2020 /* [RW 1] Port0: If set along with the
2021  ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
2022  bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
2023  bit; the Traffic LED will blink with the blink rate specified in
2024  ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2025  ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2026  fields. */
2027 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
2028 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
2029  Traffic LED will then be controlled via bit ~nig_registers_
2030  led_control_traffic_p0.led_control_traffic_p0 and bit
2031  ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
2032 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
2033 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
2034  turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
2035  set; the LED will blink with blink rate specified in
2036  ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2037  ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2038  fields. */
2039 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
2040 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2041  9-11PHY7; 12 MAC4; 13-15 PHY10; */
2042 #define NIG_REG_LED_MODE_P0 0x102f0
2043 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2044  tsdm enable; b2- usdm enable */
2045 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
2046 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
2047 /* [RW 1] SAFC enable for port0. This register may get 1 only when
2048  ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
2049  port */
2050 #define NIG_REG_LLFC_ENABLE_0 0x16208
2051 #define NIG_REG_LLFC_ENABLE_1 0x1620c
2052 /* [RW 16] classes are high-priority for port0 */
2053 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
2054 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
2055 /* [RW 16] classes are low-priority for port0 */
2056 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
2057 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
2058 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
2059 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
2060 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
2061 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
2062 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
2063 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
2064 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
2065 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2066 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
2067 /* [RW 2] Determine the classification participants. 0: no classification.1:
2068  classification upon VLAN id. 2: classification upon MAC address. 3:
2069  classification upon both VLAN id & MAC addr. */
2070 #define NIG_REG_LLH0_CLS_TYPE 0x16080
2071 /* [RW 32] cm header for llh0 */
2072 #define NIG_REG_LLH0_CM_HEADER 0x1007c
2073 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
2074 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
2075 /* [RW 16] destination TCP address 1. The LLH will look for this address in
2076  all incoming packets. */
2077 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
2078 /* [RW 16] destination UDP address 1 The LLH will look for this address in
2079  all incoming packets. */
2080 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
2081 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
2082 /* [RW 8] event id for llh0 */
2083 #define NIG_REG_LLH0_EVENT_ID 0x10084
2084 #define NIG_REG_LLH0_FUNC_EN 0x160fc
2085 #define NIG_REG_LLH0_FUNC_MEM 0x16180
2086 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
2087 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
2088 /* [RW 1] Determine the IP version to look for in
2089  ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2090 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
2091 /* [RW 1] t bit for llh0 */
2092 #define NIG_REG_LLH0_T_BIT 0x10074
2093 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
2094 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
2095 /* [RW 8] init credit counter for port0 in LLH */
2096 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
2097 #define NIG_REG_LLH0_XCM_MASK 0x10130
2098 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
2099 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2100 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
2101 /* [RW 2] Determine the classification participants. 0: no classification.1:
2102  classification upon VLAN id. 2: classification upon MAC address. 3:
2103  classification upon both VLAN id & MAC addr. */
2104 #define NIG_REG_LLH1_CLS_TYPE 0x16084
2105 /* [RW 32] cm header for llh1 */
2106 #define NIG_REG_LLH1_CM_HEADER 0x10080
2107 #define NIG_REG_LLH1_ERROR_MASK 0x10090
2108 /* [RW 8] event id for llh1 */
2109 #define NIG_REG_LLH1_EVENT_ID 0x10088
2110 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
2111 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
2112 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
2113 /* [RW 1] When this bit is set; the LLH will classify the packet before
2114  * sending it to the BRB or calculating WoL on it. This bit controls port 1
2115  * only. The legacy llh_multi_function_mode bit controls port 0. */
2116 #define NIG_REG_LLH1_MF_MODE 0x18614
2117 /* [RW 8] init credit counter for port1 in LLH */
2118 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
2119 #define NIG_REG_LLH1_XCM_MASK 0x10134
2120 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
2121  e1hov */
2122 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
2123 /* [RW 1] When this bit is set; the LLH will classify the packet before
2124  sending it to the BRB or calculating WoL on it. */
2125 #define NIG_REG_LLH_MF_MODE 0x16024
2126 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
2127 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
2128 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2129 #define NIG_REG_NIG_EMAC0_EN 0x1003c
2130 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2131 #define NIG_REG_NIG_EMAC1_EN 0x10040
2132 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2133  EMAC0 to strip the CRC from the ingress packets. */
2134 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
2135 /* [R 32] Interrupt register #0 read */
2136 #define NIG_REG_NIG_INT_STS_0 0x103b0
2137 #define NIG_REG_NIG_INT_STS_1 0x103c0
2138 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
2139 #define NIG_REG_NIG_PRTY_MASK 0x103dc
2140 /* [RW 32] Parity mask register #0 read/write */
2141 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8
2142 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8
2143 /* [R 32] Legacy E1 and E1H location for parity error status register. */
2144 #define NIG_REG_NIG_PRTY_STS 0x103d0
2145 /* [R 32] Parity register #0 read */
2146 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
2147 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
2148 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2149 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2150 /* [RC 32] Parity register #0 read clear */
2151 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2152 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
2153 #define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2154 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2155 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2156 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
2157 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2158  * Ethernet header. */
2159 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2160 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2161  * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2162  * disabled when this bit is set. */
2163 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
2164 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2165 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2166 /* [RW 1] Input enable for RX MAC interface. */
2167 #define NIG_REG_P0_MAC_IN_EN 0x185ac
2168 /* [RW 1] Output enable for TX MAC interface */
2169 #define NIG_REG_P0_MAC_OUT_EN 0x185b0
2170 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2171 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2172 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2173  * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2174  * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2175  * priority field is extracted from the outer-most VLAN in receive packet.
2176  * Only COS 0 and COS 1 are supported in E2. */
2177 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2178 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2179  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2180  * than one bit may be set; allowing multiple priorities to be mapped to one
2181  * COS. */
2182 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2183 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2184  * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2185  * than one bit may be set; allowing multiple priorities to be mapped to one
2186  * COS. */
2187 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2188 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2189  * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2190  * than one bit may be set; allowing multiple priorities to be mapped to one
2191  * COS. */
2192 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2193 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2194  * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2195  * than one bit may be set; allowing multiple priorities to be mapped to one
2196  * COS. */
2197 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2198 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2199  * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2200  * than one bit may be set; allowing multiple priorities to be mapped to one
2201  * COS. */
2202 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2203 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2204  * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2205  * than one bit may be set; allowing multiple priorities to be mapped to one
2206  * COS. */
2207 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2208 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2209 /* [RW 15] Specify which of the credit registers the client is to be mapped
2210  * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2211  * clients that are not subject to WFQ credit blocking - their
2212  * specifications here are not used. */
2213 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2214 /* [RW 32] Specify which of the credit registers the client is to be mapped
2215  * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2216  * for client 0; bits [35:32] are for client 8. For clients that are not
2217  * subject to WFQ credit blocking - their specifications here are not used.
2218  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2219  * input clients to ETS arbiter. The reset default is set for management and
2220  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2221  * use credit registers 0-5 respectively (0x543210876). Note that credit
2222  * registers can not be shared between clients. */
2223 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2224 /* [RW 4] Specify which of the credit registers the client is to be mapped
2225  * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2226  * for client 0; bits [35:32] are for client 8. For clients that are not
2227  * subject to WFQ credit blocking - their specifications here are not used.
2228  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2229  * input clients to ETS arbiter. The reset default is set for management and
2230  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2231  * use credit registers 0-5 respectively (0x543210876). Note that credit
2232  * registers can not be shared between clients. */
2233 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
2234 /* [RW 5] Specify whether the client competes directly in the strict
2235  * priority arbiter. The bits are mapped according to client ID (client IDs
2236  * are defined in tx_arb_priority_client). Default value is set to enable
2237  * strict priorities for clients 0-2 -- management and debug traffic. */
2238 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2239 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2240  * bits are mapped according to client ID (client IDs are defined in
2241  * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2242  * blocking. */
2243 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2244 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2245  * reach. */
2246 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2247 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2248 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2249 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2250 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2251 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2252 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2253 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2254 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
2255 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2256  * when it is time to increment. */
2257 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2258 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2259 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2260 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2261 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2262 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2263 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2264 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2265 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
2266 /* [RW 12] Specify the number of strict priority arbitration slots between
2267  * two round-robin arbitration slots to avoid starvation. A value of 0 means
2268  * no strict priority cycles - the strict priority with anti-starvation
2269  * arbiter becomes a round-robin arbiter. */
2270 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2271 /* [RW 15] Specify the client number to be assigned to each priority of the
2272  * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2273  * are for priority 0 client; bits [14:12] are for priority 4 client. The
2274  * clients are assigned the following IDs: 0-management; 1-debug traffic
2275  * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2276  * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2277  * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2278  * traffic at priority 3; and COS1 traffic at priority 4. */
2279 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2280 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2281  * Ethernet header. */
2282 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2283 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2284 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2285 /* [RW 32] Specify the client number to be assigned to each priority of the
2286  * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2287  * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2288  * client; bits [35-32] are for priority 8 client. The clients are assigned
2289  * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2290  * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2291  * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2292  * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2293  * accommodate the 9 input clients to ETS arbiter. */
2294 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2295 /* [RW 4] Specify the client number to be assigned to each priority of the
2296  * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2297  * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2298  * client; bits [35-32] are for priority 8 client. The clients are assigned
2299  * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2300  * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2301  * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2302  * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2303  * accommodate the 9 input clients to ETS arbiter. */
2304 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2305 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0
2306 #define NIG_REG_P1_MAC_IN_EN 0x185c0
2307 /* [RW 1] Output enable for TX MAC interface */
2308 #define NIG_REG_P1_MAC_OUT_EN 0x185c4
2309 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2310 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2311 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2312  * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2313  * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2314  * priority field is extracted from the outer-most VLAN in receive packet.
2315  * Only COS 0 and COS 1 are supported in E2. */
2316 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2317 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2318  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2319  * than one bit may be set; allowing multiple priorities to be mapped to one
2320  * COS. */
2321 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2322 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2323  * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2324  * than one bit may be set; allowing multiple priorities to be mapped to one
2325  * COS. */
2326 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2327 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2328  * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2329  * than one bit may be set; allowing multiple priorities to be mapped to one
2330  * COS. */
2331 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2332 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2333 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2334 /* [R 1] TLLH FIFO is empty. */
2335 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2336 /* [RW 32] Specify which of the credit registers the client is to be mapped
2337  * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2338  * for client 0; bits [35:32] are for client 8. For clients that are not
2339  * subject to WFQ credit blocking - their specifications here are not used.
2340  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2341  * input clients to ETS arbiter. The reset default is set for management and
2342  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2343  * use credit registers 0-5 respectively (0x543210876). Note that credit
2344  * registers can not be shared between clients. Note also that there are
2345  * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2346  * credit registers 0-5 are valid. This register should be configured
2347  * appropriately before enabling WFQ. */
2348 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2349 /* [RW 4] Specify which of the credit registers the client is to be mapped
2350  * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2351  * for client 0; bits [35:32] are for client 8. For clients that are not
2352  * subject to WFQ credit blocking - their specifications here are not used.
2353  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2354  * input clients to ETS arbiter. The reset default is set for management and
2355  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2356  * use credit registers 0-5 respectively (0x543210876). Note that credit
2357  * registers can not be shared between clients. Note also that there are
2358  * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2359  * credit registers 0-5 are valid. This register should be configured
2360  * appropriately before enabling WFQ. */
2361 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2362 /* [RW 9] Specify whether the client competes directly in the strict
2363  * priority arbiter. The bits are mapped according to client ID (client IDs
2364  * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2365  * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2366  * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2367  * Default value is set to enable strict priorities for all clients. */
2368 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2369 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2370  * bits are mapped according to client ID (client IDs are defined in
2371  * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2372  * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2373  * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2374  * 0 for not using WFQ credit blocking. */
2375 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2376 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2377 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2378 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2379 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2380 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2381 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2382 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2383  * when it is time to increment. */
2384 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2385 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2386 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2387 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2388 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2389 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2390 /* [RW 12] Specify the number of strict priority arbitration slots between
2391  two round-robin arbitration slots to avoid starvation. A value of 0 means
2392  no strict priority cycles - the strict priority with anti-starvation
2393  arbiter becomes a round-robin arbiter. */
2394 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2395 /* [RW 32] Specify the client number to be assigned to each priority of the
2396  strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2397  value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2398  client; bits [35-32] are for priority 8 client. The clients are assigned
2399  the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2400  traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2401  6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2402  set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2403  accommodate the 9 input clients to ETS arbiter. Note that this register
2404  is the same as the one for port 0, except that port 1 only has COS 0-2
2405  traffic. There is no traffic for COS 3-5 of port 1. */
2406 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2407 /* [RW 4] Specify the client number to be assigned to each priority of the
2408  strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2409  value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2410  client; bits [35-32] are for priority 8 client. The clients are assigned
2411  the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2412  traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2413  6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2414  set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2415  accommodate the 9 input clients to ETS arbiter. Note that this register
2416  is the same as the one for port 0, except that port 1 only has COS 0-2
2417  traffic. There is no traffic for COS 3-5 of port 1. */
2418 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2419 /* [R 1] TX FIFO for transmitting data to MAC is empty. */
2420 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2421 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2422  forwarded to the host. */
2423 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2424 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2425  * reach. */
2426 /* [RW 1] Pause enable for port0. This register may get 1 only when
2427  ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2428  port */
2429 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
2430 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
2431 /* [RW 1] Input enable for RX PBF LP IF */
2432 #define NIG_REG_PBF_LB_IN_EN 0x100b4
2433 /* [RW 1] Value of this register will be transmitted to port swap when
2434  ~nig_registers_strap_override.strap_override =1 */
2435 #define NIG_REG_PORT_SWAP 0x10394
2436 /* [RW 1] PPP enable for port0. This register may get 1 only when
2437  * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2438  * same port */
2439 #define NIG_REG_PPP_ENABLE_0 0x160b0
2440 #define NIG_REG_PPP_ENABLE_1 0x160b4
2441 /* [RW 1] output enable for RX parser descriptor IF */
2442 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2443 /* [RW 1] Input enable for RX parser request IF */
2444 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2445 /* [RW 5] control to serdes - CL45 DEVAD */
2446 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2447 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2448 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2449 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2450 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2451 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2452 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2453 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2454  for port0 */
2455 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2456 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2457  for port0 */
2458 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2459 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2460  between 1024 and 1522 bytes for port0 */
2461 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2462 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2463  between 1523 bytes and above for port0 */
2464 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2465 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2466  for port1 */
2467 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2468 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2469  between 1024 and 1522 bytes for port1 */
2470 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2471 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2472  between 1523 bytes and above for port1 */
2473 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2474 /* [WB_R 64] Rx statistics : User octets received for LP */
2475 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2476 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2477 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2478 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2479  swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2480  ort swap is equal to ~nig_registers_port_swap.port_swap */
2481 #define NIG_REG_STRAP_OVERRIDE 0x10398
2482 /* [RW 1] output enable for RX_XCM0 IF */
2483 #define NIG_REG_XCM0_OUT_EN 0x100f0
2484 /* [RW 1] output enable for RX_XCM1 IF */
2485 #define NIG_REG_XCM1_OUT_EN 0x100f4
2486 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2487 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2488 /* [RW 5] control to xgxs - CL45 DEVAD */
2489 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2490 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2491 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2492 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2493 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2494 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2495 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2496 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2497 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2498 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2499 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2500 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2501 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2502 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2503 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2504 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2505 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2506 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2507 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2508 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2509 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2510  * of port 0. */
2511 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2512 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2513  * of port 1. */
2514 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2515 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2516 #define PBF_REG_COS0_WEIGHT 0x15c054
2517 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2518 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2519 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2520 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2521 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2522 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2523 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2524 #define PBF_REG_COS1_WEIGHT 0x15c058
2525 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2526 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2527 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2528 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2529 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2530 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2531 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2532 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2533 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2534 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2535 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2536 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2537 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2538 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2539 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2540  * lines. */
2541 #define PBF_REG_CREDIT_LB_Q 0x140338
2542 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2543  * lines. */
2544 #define PBF_REG_CREDIT_Q0 0x14033c
2545 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2546  * lines. */
2547 #define PBF_REG_CREDIT_Q1 0x140340
2548 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2549  current task in process). */
2550 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2551 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2552  current task in process). */
2553 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2554 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2555  current task in process). */
2556 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2557 #define PBF_REG_DISABLE_PF 0x1402e8
2558 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2559  * corresponding bit is 1); indicates to which of the credit registers this
2560  * client is mapped. For clients which are not credit blocked; their mapping
2561  * is dont care. */
2562 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2563 /* [RW 9] For port 1: For each client that is subject to WFQ (the
2564  * corresponding bit is 1); indicates to which of the credit registers this
2565  * client is mapped. For clients which are not credit blocked; their mapping
2566  * is dont care. */
2567 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2568 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2569  * the strict priority arbiter directly (corresponding bit = 1); or first
2570  * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2571  * lowest priority in the strict-priority arbiter. */
2572 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2573 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2574  * the strict priority arbiter directly (corresponding bit = 1); or first
2575  * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2576  * lowest priority in the strict-priority arbiter. */
2577 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2578 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2579  * WFQ credit blocking (corresponding bit = 1). */
2580 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2581 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2582  * WFQ credit blocking (corresponding bit = 1). */
2583 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2584 /* [RW 16] For port 0: The number of strict priority arbitration slots
2585  * between 2 RR arbitration slots. A value of 0 means no strict priority
2586  * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2587  * arbiter. */
2588 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2589 /* [RW 16] For port 1: The number of strict priority arbitration slots
2590  * between 2 RR arbitration slots. A value of 0 means no strict priority
2591  * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2592  * arbiter. */
2593 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2594 /* [RW 18] For port 0: Indicates which client is connected to each priority
2595  * in the strict-priority arbiter. Priority 0 is the highest priority, and
2596  * priority 5 is the lowest; to which the RR output is connected to (this is
2597  * not configurable). */
2598 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2599 /* [RW 9] For port 1: Indicates which client is connected to each priority
2600  * in the strict-priority arbiter. Priority 0 is the highest priority, and
2601  * priority 5 is the lowest; to which the RR output is connected to (this is
2602  * not configurable). */
2603 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2604 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2605  * arbiter. If reset strict priority w/ anti-starvation will be performed
2606  * w/o WFQ. */
2607 #define PBF_REG_ETS_ENABLED 0x15c050
2608 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2609  * Ethernet header. */
2610 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2611 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2612 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2613 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2614  * priority in the command arbiter. */
2615 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2616 #define PBF_REG_IF_ENABLE_REG 0x140044
2617 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2618  registers (except the port credits). Should be set and then reset after
2619  the configuration of the block has ended. */
2620 #define PBF_REG_INIT 0x140000
2621 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2622  * lines. */
2623 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2624 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2625  * lines. */
2626 #define PBF_REG_INIT_CRD_Q0 0x15c230
2627 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2628  * lines. */
2629 #define PBF_REG_INIT_CRD_Q1 0x15c234
2630 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2631  copied to the credit register. Should be set and then reset after the
2632  configuration of the port has ended. */
2633 #define PBF_REG_INIT_P0 0x140004
2634 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2635  copied to the credit register. Should be set and then reset after the
2636  configuration of the port has ended. */
2637 #define PBF_REG_INIT_P1 0x140008
2638 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2639  copied to the credit register. Should be set and then reset after the
2640  configuration of the port has ended. */
2641 #define PBF_REG_INIT_P4 0x14000c
2642 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2643  * the LB queue. Reset upon init. */
2644 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2645 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2646  * queue 0. Reset upon init. */
2647 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2648 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2649  * queue 1. Reset upon init. */
2650 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2651 /* [RW 1] Enable for mac interface 0. */
2652 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2653 /* [RW 1] Enable for mac interface 1. */
2654 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2655 /* [RW 1] Enable for the loopback interface. */
2656 #define PBF_REG_MAC_LB_ENABLE 0x140040
2657 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2658 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2659 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2660  * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2661  * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2662 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2663 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2664  not suppoterd. */
2665 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2666 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2667 #define PBF_REG_P0_CREDIT 0x140200
2668 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2669  lines. */
2670 #define PBF_REG_P0_INIT_CRD 0x1400d0
2671 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2672  * port 0. Reset upon init. */
2673 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2674 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2675 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2676 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2677 #define PBF_REG_P0_TASK_CNT 0x140204
2678 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2679  * freed from the task queue of port 0. Reset upon init. */
2680 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2681 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2682 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2683 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2684  * buffers in 16 byte lines. */
2685 #define PBF_REG_P1_CREDIT 0x140208
2686 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2687  * buffers in 16 byte lines. */
2688 #define PBF_REG_P1_INIT_CRD 0x1400d4
2689 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2690  * port 1. Reset upon init. */
2691 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2692 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2693 #define PBF_REG_P1_TASK_CNT 0x14020c
2694 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2695  * freed from the task queue of port 1. Reset upon init. */
2696 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2697 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2698 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2699 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2700 #define PBF_REG_P4_CREDIT 0x140210
2701 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2702  lines. */
2703 #define PBF_REG_P4_INIT_CRD 0x1400e0
2704 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2705  * port 4. Reset upon init. */
2706 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2707 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2708 #define PBF_REG_P4_TASK_CNT 0x140214
2709 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2710  * freed from the task queue of port 4. Reset upon init. */
2711 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2712 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2713 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2714 /* [RW 5] Interrupt mask register #0 read/write */
2715 #define PBF_REG_PBF_INT_MASK 0x1401d4
2716 /* [R 5] Interrupt register #0 read */
2717 #define PBF_REG_PBF_INT_STS 0x1401c8
2718 /* [RW 20] Parity mask register #0 read/write */
2719 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2720 /* [RC 20] Parity register #0 read clear */
2721 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2722 /* [RW 16] The Ethernet type value for L2 tag 0 */
2723 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2724 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2725  * 2B and 14B; in 2B granularity */
2726 #define PBF_REG_TAG_LEN_0 0x15c09c
2727 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2728  * queue. Reset upon init. */
2729 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2730 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2731  * queue 0. Reset upon init. */
2732 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2733 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2734  * Reset upon init. */
2735 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2736 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2737  * queue. */
2738 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2739 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2740 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2741 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2742 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2743 #define PB_REG_CONTROL 0
2744 /* [RW 2] Interrupt mask register #0 read/write */
2745 #define PB_REG_PB_INT_MASK 0x28
2746 /* [R 2] Interrupt register #0 read */
2747 #define PB_REG_PB_INT_STS 0x1c
2748 /* [RW 4] Parity mask register #0 read/write */
2749 #define PB_REG_PB_PRTY_MASK 0x38
2750 /* [R 4] Parity register #0 read */
2751 #define PB_REG_PB_PRTY_STS 0x2c
2752 /* [RC 4] Parity register #0 read clear */
2753 #define PB_REG_PB_PRTY_STS_CLR 0x30
2754 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2755 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2756 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2757 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2758 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2759 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2760 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2761 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2762 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2763 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2764  * corresponding PF generates config space A attention. Set by PXP. Reset by
2765  * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2766  * from both paths. */
2767 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2768 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2769  * corresponding PF generates config space B attention. Set by PXP. Reset by
2770  * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2771  * from both paths. */
2772 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2773 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2774  * - enable. */
2775 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2776 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2777  * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2778 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2779 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2780  * - enable. */
2781 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2782 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2783 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2784 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2785 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2786 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2787 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2788 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2789 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2790 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2791  * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2792  * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2793  * from both paths. */
2794 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2795 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2796  * to a bit in this register in order to clear the corresponding bit in
2797  * flr_request_pf_7_0 register. Note: register contains bits from both
2798  * paths. */
2799 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2800 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2801  * indicates that the FLR register of the corresponding VF was set. Set by
2802  * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2803 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2804 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2805  * indicates that the FLR register of the corresponding VF was set. Set by
2806  * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2807 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2808 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2809  * indicates that the FLR register of the corresponding VF was set. Set by
2810  * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2811 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2812 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2813  * indicates that the FLR register of the corresponding VF was set. Set by
2814  * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2815 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2816 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2817  * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2818  * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2819  * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2820  * an uncorrectable error. Bit 4 - Completion with Configuration Request
2821  * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2822  * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2823  * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2824  * and pcie_rx_last not asserted. */
2825 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2826 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2827 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2828 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2829 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2830 /* [R 9] Interrupt register #0 read */
2831 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2832 /* [RC 9] Interrupt register #0 read clear */
2833 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2834 /* [RW 2] Parity mask register #0 read/write */
2835 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
2836 /* [R 2] Parity register #0 read */
2837 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2838 /* [RC 2] Parity register #0 read clear */
2839 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
2840 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2841  * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2842  * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2843  * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2844  * if there was a completion error since the last time this register was
2845  * cleared. */
2846 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2847 /* [R 18] Details of first ATS Translation Completion request received with
2848  * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2849  * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2850  * unsupported request. 2 - completer abort. 3 - Illegal value for this
2851  * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2852  * completion error since the last time this register was cleared. */
2853 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2854 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2855  * a bit in this register in order to clear the corresponding bit in
2856  * shadow_bme_pf_7_0 register. MCP should never use this unless a
2857  * work-around is needed. Note: register contains bits from both paths. */
2858 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2859 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2860  * VF enable register of the corresponding PF is written to 0 and was
2861  * previously 1. Set by PXP. Reset by MCP writing 1 to
2862  * sr_iov_disabled_request_clr. Note: register contains bits from both
2863  * paths. */
2864 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2865 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2866  * completion did not return yet. 1 - tag is unused. Same functionality as
2867  * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2868 #define PGLUE_B_REG_TAGS_63_32 0x9244
2869 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2870  * - enable. */
2871 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2872 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2873 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2874 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2875 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2876 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2877 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2878 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2879 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2880 /* [R 32] Address [31:0] of first read request not submitted due to error */
2881 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2882 /* [R 32] Address [63:32] of first read request not submitted due to error */
2883 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2884 /* [R 31] Details of first read request not submitted due to error. [4:0]
2885  * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2886  * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2887  * VFID. */
2888 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2889 /* [R 26] Details of first read request not submitted due to error. [15:0]
2890  * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2891  * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2892  * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2893  * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2894  * indicates if there was a request not submitted due to error since the
2895  * last time this register was cleared. */
2896 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2897 /* [R 32] Address [31:0] of first write request not submitted due to error */
2898 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2899 /* [R 32] Address [63:32] of first write request not submitted due to error */
2900 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2901 /* [R 31] Details of first write request not submitted due to error. [4:0]
2902  * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2903  * - VFID. */
2904 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2905 /* [R 26] Details of first write request not submitted due to error. [15:0]
2906  * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2907  * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2908  * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2909  * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2910  * indicates if there was a request not submitted due to error since the
2911  * last time this register was cleared. */
2912 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2913 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2914  * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2915  * value (Byte resolution address). */
2916 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2917 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2918 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2919 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2920 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2921 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2922 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2923 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2924  * - enable. */
2925 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2926 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2927  * - enable. */
2928 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2929 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2930  * - enable. */
2931 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2932 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2933 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2934 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2935 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2936 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2937 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2938 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2939 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2940 /* [R 26] Details of first target VF request accessing VF GRC space that
2941  * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2942  * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2943  * request accessing VF GRC space that failed permission check since the
2944  * last time this register was cleared. Permission checks are: function
2945  * permission; R/W permission; address range permission. */
2946 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2947 /* [R 31] Details of first target VF request with length violation (too many
2948  * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2949  * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2950  * valid - indicates if there was a request with length violation since the
2951  * last time this register was cleared. Length violations: length of more
2952  * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2953  * length is more than 1 DW. */
2954 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2955 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2956  * that there was a completion with uncorrectable error for the
2957  * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2958  * was_error_pf_7_0_clr. */
2959 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2960 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2961  * to a bit in this register in order to clear the corresponding bit in
2962  * flr_request_pf_7_0 register. */
2963 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2964 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2965  * indicates that there was a completion with uncorrectable error for the
2966  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2967  * was_error_vf_127_96_clr. */
2968 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2969 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2970  * writes 1 to a bit in this register in order to clear the corresponding
2971  * bit in was_error_vf_127_96 register. */
2972 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2973 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2974  * indicates that there was a completion with uncorrectable error for the
2975  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2976  * was_error_vf_31_0_clr. */
2977 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2978 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2979  * 1 to a bit in this register in order to clear the corresponding bit in
2980  * was_error_vf_31_0 register. */
2981 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2982 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2983  * indicates that there was a completion with uncorrectable error for the
2984  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2985  * was_error_vf_63_32_clr. */
2986 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2987 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2988  * 1 to a bit in this register in order to clear the corresponding bit in
2989  * was_error_vf_63_32 register. */
2990 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2991 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2992  * indicates that there was a completion with uncorrectable error for the
2993  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2994  * was_error_vf_95_64_clr. */
2995 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2996 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2997  * 1 to a bit in this register in order to clear the corresponding bit in
2998  * was_error_vf_95_64 register. */
2999 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
3000 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3001  * - enable. */
3002 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
3003 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
3004 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
3005 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
3006 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
3007 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
3008 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
3009 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3010 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
3011 #define PRS_REG_A_PRSU_20 0x40134
3012 /* [R 8] debug only: CFC load request current credit. Transaction based. */
3013 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
3014 /* [R 8] debug only: CFC search request current credit. Transaction based. */
3015 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
3016 /* [RW 6] The initial credit for the search message to the CFC interface.
3017  Credit is transaction based. */
3018 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
3019 /* [RW 24] CID for port 0 if no match */
3020 #define PRS_REG_CID_PORT_0 0x400fc
3021 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3022  load response is reset and packet type is 0. Used in packet start message
3023  to TCM. */
3024 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
3025 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
3026 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
3027 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
3028 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
3029 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
3030 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3031  load response is set and packet type is 0. Used in packet start message
3032  to TCM. */
3033 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
3034 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
3035 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
3036 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
3037 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
3038 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
3039 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
3040  Used in packet start message to TCM. */
3041 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
3042 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
3043 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
3044 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
3045 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
3046  message to TCM. */
3047 #define PRS_REG_CM_HDR_TYPE_0 0x40078
3048 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
3049 #define PRS_REG_CM_HDR_TYPE_2 0x40080
3050 #define PRS_REG_CM_HDR_TYPE_3 0x40084
3051 #define PRS_REG_CM_HDR_TYPE_4 0x40088
3052 /* [RW 32] The CM header in case there was not a match on the connection */
3053 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
3054 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3055 #define PRS_REG_E1HOV_MODE 0x401c8
3056 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3057  start message to TCM. */
3058 #define PRS_REG_EVENT_ID_1 0x40054
3059 #define PRS_REG_EVENT_ID_2 0x40058
3060 #define PRS_REG_EVENT_ID_3 0x4005c
3061 /* [RW 16] The Ethernet type value for FCoE */
3062 #define PRS_REG_FCOE_TYPE 0x401d0
3063 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3064  load request message. */
3065 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
3066 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
3067 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
3068 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
3069 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
3070 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
3071 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
3072 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
3073 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3074  * Ethernet header. */
3075 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
3076 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3077  * Ethernet header for port 0 packets. */
3078 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
3079 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
3080 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3081 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
3082 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3083  * port 0 packets */
3084 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
3085 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
3086 /* [RW 4] The increment value to send in the CFC load request message */
3087 #define PRS_REG_INC_VALUE 0x40048
3088 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3089 #define PRS_REG_MUST_HAVE_HDRS 0x40254
3090 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3091  * port 0 packets */
3092 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
3093 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
3094 #define PRS_REG_NIC_MODE 0x40138
3095 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3096  connection. Used in packet start message to TCM. */
3097 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
3098 /* [ST 24] The number of input CFC flush packets */
3099 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
3100 /* [ST 32] The number of cycles the Parser halted its operation since it
3101  could not allocate the next serial number */
3102 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
3103 /* [ST 24] The number of input packets */
3104 #define PRS_REG_NUM_OF_PACKETS 0x40124
3105 /* [ST 24] The number of input transparent flush packets */
3106 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
3107 /* [RW 8] Context region for received Ethernet packet with a match and
3108  packet type 0. Used in CFC load request message */
3109 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
3110 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
3111 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
3112 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
3113 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
3114 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
3115 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
3116 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
3117 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
3118 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
3119 /* [R 2] debug only: Number of pending requests for header parsing. */
3120 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
3121 /* [R 1] Interrupt register #0 read */
3122 #define PRS_REG_PRS_INT_STS 0x40188
3123 /* [RW 8] Parity mask register #0 read/write */
3124 #define PRS_REG_PRS_PRTY_MASK 0x401a4
3125 /* [R 8] Parity register #0 read */
3126 #define PRS_REG_PRS_PRTY_STS 0x40198
3127 /* [RC 8] Parity register #0 read clear */
3128 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
3129 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3130  request message */
3131 #define PRS_REG_PURE_REGIONS 0x40024
3132 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
3133  serail number was released by SDM but cannot be used because a previous
3134  serial number was not released. */
3135 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
3136 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3137  serail number was released by SDM but cannot be used because a previous
3138  serial number was not released. */
3139 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
3140 /* [R 4] debug only: SRC current credit. Transaction based. */
3141 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
3142 /* [RW 16] The Ethernet type value for L2 tag 0 */
3143 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
3144 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3145  * 2B and 14B; in 2B granularity */
3146 #define PRS_REG_TAG_LEN_0 0x4022c
3147 /* [R 8] debug only: TCM current credit. Cycle based. */
3148 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
3149 /* [R 8] debug only: TSDM current credit. Transaction based. */
3150 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
3151 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3152 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3153 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3154 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3155 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3156 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3157 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3158 /* [R 6] Debug only: Number of used entries in the data FIFO */
3159 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3160 /* [R 7] Debug only: Number of used entries in the header FIFO */
3161 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3162 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
3163 /* [R 32] GRC address for configuration access to PCIE config address 0x88.
3164  * any write to this PCIE address will cause a GRC write access to the
3165  * address that's in t this register */
3166 #define PXP2_REG_PGL_ADDR_88_F1 0x120544
3167 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3168 /* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3169  * any write to this PCIE address will cause a GRC write access to the
3170  * address that's in t this register */
3171 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548
3172 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3173 /* [R 32] GRC address for configuration access to PCIE config address 0x90.
3174  * any write to this PCIE address will cause a GRC write access to the
3175  * address that's in t this register */
3176 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c
3177 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
3178 /* [R 32] GRC address for configuration access to PCIE config address 0x94.
3179  * any write to this PCIE address will cause a GRC write access to the
3180  * address that's in t this register */
3181 #define PXP2_REG_PGL_ADDR_94_F1 0x120550
3182 #define PXP2_REG_PGL_CONTROL0 0x120490
3183 #define PXP2_REG_PGL_CONTROL1 0x120514
3184 #define PXP2_REG_PGL_DEBUG 0x120520
3185 /* [RW 32] third dword data of expansion rom request. this register is
3186  special. reading from it provides a vector outstanding read requests. if
3187  a bit is zero it means that a read request on the corresponding tag did
3188  not finish yet (not all completions have arrived for it) */
3189 #define PXP2_REG_PGL_EXP_ROM2 0x120808
3190 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3191  its[15:0]-address */
3192 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3193 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3194 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3195 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
3196 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
3197 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
3198 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3199 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
3200 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3201  its[15:0]-address */
3202 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
3203 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
3204 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3205 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3206 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3207 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3208 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3209 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3210 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3211  its[15:0]-address */
3212 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3213 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3214 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3215 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3216 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3217 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3218 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3219 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3220 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3221  its[15:0]-address */
3222 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3223 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3224 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3225 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3226 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3227 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3228 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3229 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
3230 /* [RW 3] this field allows one function to pretend being another function
3231  when accessing any BAR mapped resource within the device. the value of
3232  the field is the number of the function that will be accessed
3233  effectively. after software write to this bit it must read it in order to
3234  know that the new value is updated */
3235 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3236 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3237 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3238 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3239 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3240 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3241 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3242 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
3243 /* [R 1] this bit indicates that a read request was blocked because of
3244  bus_master_en was deasserted */
3245 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
3246 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
3247 /* [R 18] debug only */
3248 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
3249 /* [R 1] this bit indicates that a write request was blocked because of
3250  bus_master_en was deasserted */
3251 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3252 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3253 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3254 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
3255 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3256 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
3257 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3258 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3259 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3260 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3261 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3262 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3263 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3264 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3265 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
3266 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3267 #define PXP2_REG_PSWRQ_BW_L28 0x120318
3268 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3269 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3270 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3271 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3272 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3273 #define PXP2_REG_PSWRQ_BW_RD 0x120324
3274 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
3275 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3276 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
3277 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3278 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
3279 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
3280 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3281 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
3282 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
3283 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
3284 #define PXP2_REG_PSWRQ_BW_WR 0x120328
3285 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3286 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3287 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3288 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
3289 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
3290 /* [RW 32] Interrupt mask register #0 read/write */
3291 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
3292 /* [R 32] Interrupt register #0 read */
3293 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
3294 #define PXP2_REG_PXP2_INT_STS_1 0x120608
3295 /* [RC 32] Interrupt register #0 read clear */
3296 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
3297 /* [RW 32] Parity mask register #0 read/write */
3298 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3299 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
3300 /* [R 32] Parity register #0 read */
3301 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3302 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
3303 /* [RC 32] Parity register #0 read clear */
3304 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3305 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
3306 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3307  indication about backpressure) */
3308 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3309 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3310 #define PXP2_REG_RD_BLK_CNT 0x120418
3311 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3312  Must be bigger than 6. Normally should not be changed. */
3313 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3314 /* [RW 2] CDU byte swapping mode configuration for master read requests */
3315 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3316 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3317 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3318 /* [R 1] PSWRD internal memories initialization is done */
3319 #define PXP2_REG_RD_INIT_DONE 0x120370
3320 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3321  allocated for vq10 */
3322 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3323 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3324  allocated for vq11 */
3325 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3326 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3327  allocated for vq17 */
3328 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3329 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3330  allocated for vq18 */
3331 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3332 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3333  allocated for vq19 */
3334 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3335 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3336  allocated for vq22 */
3337 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3338 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3339  allocated for vq25 */
3340 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3341 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3342  allocated for vq6 */
3343 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3344 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3345  allocated for vq9 */
3346 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3347 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3348 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3349 /* [R 1] Debug only: Indication if delivery ports are idle */
3350 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3351 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3352 /* [RW 2] QM byte swapping mode configuration for master read requests */
3353 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3354 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3355 #define PXP2_REG_RD_SR_CNT 0x120414
3356 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3357 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3358 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3359  be bigger than 1. Normally should not be changed. */
3360 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
3361 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3362 #define PXP2_REG_RD_START_INIT 0x12036c
3363 /* [RW 2] TM byte swapping mode configuration for master read requests */
3364 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3365 /* [RW 10] Bandwidth addition to VQ0 write requests */
3366 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3367 /* [RW 10] Bandwidth addition to VQ12 read requests */
3368 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3369 /* [RW 10] Bandwidth addition to VQ13 read requests */
3370 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3371 /* [RW 10] Bandwidth addition to VQ14 read requests */
3372 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3373 /* [RW 10] Bandwidth addition to VQ15 read requests */
3374 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3375 /* [RW 10] Bandwidth addition to VQ16 read requests */
3376 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3377 /* [RW 10] Bandwidth addition to VQ17 read requests */
3378 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3379 /* [RW 10] Bandwidth addition to VQ18 read requests */
3380 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3381 /* [RW 10] Bandwidth addition to VQ19 read requests */
3382 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3383 /* [RW 10] Bandwidth addition to VQ20 read requests */
3384 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3385 /* [RW 10] Bandwidth addition to VQ22 read requests */
3386 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3387 /* [RW 10] Bandwidth addition to VQ23 read requests */
3388 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3389 /* [RW 10] Bandwidth addition to VQ24 read requests */
3390 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3391 /* [RW 10] Bandwidth addition to VQ25 read requests */
3392 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3393 /* [RW 10] Bandwidth addition to VQ26 read requests */
3394 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3395 /* [RW 10] Bandwidth addition to VQ27 read requests */
3396 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3397 /* [RW 10] Bandwidth addition to VQ4 read requests */
3398 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3399 /* [RW 10] Bandwidth addition to VQ5 read requests */
3400 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3401 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3402 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3403 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3404 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3405 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3406 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3407 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3408 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3409 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3410 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3411 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3412 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3413 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3414 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3415 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3416 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3417 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3418 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3419 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3420 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3421 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3422 #define PXP2_REG_RQ_BW_RD_L22 0x120300
3423 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3424 #define PXP2_REG_RQ_BW_RD_L23 0x120304
3425 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3426 #define PXP2_REG_RQ_BW_RD_L24 0x120308
3427 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3428 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
3429 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3430 #define PXP2_REG_RQ_BW_RD_L26 0x120310
3431 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3432 #define PXP2_REG_RQ_BW_RD_L27 0x120314
3433 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3434 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3435 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3436 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3437 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3438 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3439 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3440 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3441 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3442 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3443 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3444 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3445 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3446 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3447 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3448 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3449 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3450 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3451 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3452 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3453 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3454 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3455 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3456 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3457 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3458 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3459 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3460 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3461 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3462 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3463 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3464 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3465 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3466 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3467 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3468 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3469 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3470 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3471 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3472 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3473 /* [RW 10] Bandwidth addition to VQ29 write requests */
3474 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3475 /* [RW 10] Bandwidth addition to VQ30 write requests */
3476 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3477 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3478 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
3479 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3480 #define PXP2_REG_RQ_BW_WR_L30 0x120320
3481 /* [RW 7] Bandwidth upper bound for VQ29 */
3482 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3483 /* [RW 7] Bandwidth upper bound for VQ30 */
3484 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3485 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3486 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3487 /* [RW 2] Endian mode for cdu */
3488 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3489 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3490 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3491 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3492  -128k */
3493 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3494 /* [R 1] 1' indicates that the requester has finished its internal
3495  configuration */
3496 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
3497 /* [RW 2] Endian mode for debug */
3498 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3499 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3500  towards the glue */
3501 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3502 /* [RW 4] Determines alignment of write SRs when a request is split into
3503  * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3504  * aligned. 4 - 512B aligned. */
3505 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3506 /* [RW 4] Determines alignment of read SRs when a request is split into
3507  * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3508  * aligned. 4 - 512B aligned. */
3509 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3510 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3511  * the original alignment method (E1 E1H) will be applied */
3512 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3513 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3514  be asserted */
3515 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3516 /* [RW 2] Endian mode for hc */
3517 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3518 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3519  compatibility needs; Note that different registers are used per mode */
3520 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
3521 /* [WB 53] Onchip address table */
3522 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
3523 /* [WB 53] Onchip address table - B0 */
3524 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3525 /* [RW 13] Pending read limiter threshold; in Dwords */
3526 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3527 /* [RW 2] Endian mode for qm */
3528 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3529 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3530 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3531 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3532  -128k */
3533 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3534 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3535 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3536 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3537  001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3538 #define PXP2_REG_RQ_RD_MBS0 0x120160
3539 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3540  001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3541 #define PXP2_REG_RQ_RD_MBS1 0x120168
3542 /* [RW 2] Endian mode for src */
3543 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3544 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3545 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3546 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3547  -128k */
3548 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3549 /* [RW 2] Endian mode for tm */
3550 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3551 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3552 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3553 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3554  -128k */
3555 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3556 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3557 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3558 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3559 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3560 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3561 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3562 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3563 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3564 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3565 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3566 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3567 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3568 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3569 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3570 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3571 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3572 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3573 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3574 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3575 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3576 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3577 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3578 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3579 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3580 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3581 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3582 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3583 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3584 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3585 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3586 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3587 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3588 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3589 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3590 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3591 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3592 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3593 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3594 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3595 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3596 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3597 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3598 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3599 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3600 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3601 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3602 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3603 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3604 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3605 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3606 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3607 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3608 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3609 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3610 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3611 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3612 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3613 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3614 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3615 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3616 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3617 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3618 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3619 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3620 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3621 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3622 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3623 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3624 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3625  001:256B; 010: 512B; */
3626 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3627 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3628  001:256B; 010: 512B; */
3629 #define PXP2_REG_RQ_WR_MBS1 0x120164
3630 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3631  buffer reaches this number has_payload will be asserted */
3632 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3633 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3634  buffer reaches this number has_payload will be asserted */
3635 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3636 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3637  buffer reaches this number has_payload will be asserted */
3638 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3639 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3640  buffer reaches this number has_payload will be asserted */
3641 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3642 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3643  threshold then has_payload indication will be asserted; the default value
3644  should be equal to &gt; write MBS size! */
3645 #define PXP2_REG_WR_DMAE_TH 0x120368
3646 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3647  buffer reaches this number has_payload will be asserted */
3648 #define PXP2_REG_WR_HC_MPS 0x1205c8
3649 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3650  buffer reaches this number has_payload will be asserted */
3651 #define PXP2_REG_WR_QM_MPS 0x1205dc
3652 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3653 #define PXP2_REG_WR_REV_MODE 0x120670
3654 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3655  buffer reaches this number has_payload will be asserted */
3656 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3657 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3658  buffer reaches this number has_payload will be asserted */
3659 #define PXP2_REG_WR_TM_MPS 0x1205e0
3660 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3661  buffer reaches this number has_payload will be asserted */
3662 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3663 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3664  threshold then has_payload indication will be asserted; the default value
3665  should be equal to &gt; write MBS size! */
3666 #define PXP2_REG_WR_USDMDP_TH 0x120348
3667 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3668  buffer reaches this number has_payload will be asserted */
3669 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3670 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3671  buffer reaches this number has_payload will be asserted */
3672 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3673 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3674 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3675 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3676  this client is waiting for the arbiter. */
3677 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3678 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3679  block. Should be used for close the gates. */
3680 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3681 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3682  should update according to 'hst_discard_doorbells' register when the state
3683  machine is idle */
3684 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3685 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3686  Should be used for close the gates. */
3687 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3688 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3689  means this PSWHST is discarding inputs from this client. Each bit should
3690  update according to 'hst_discard_internal_writes' register when the state
3691  machine is idle. */
3692 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3693 /* [WB 160] Used for initialization of the inbound interrupts memory */
3694 #define PXP_REG_HST_INBOUND_INT 0x103800
3695 /* [RW 32] Interrupt mask register #0 read/write */
3696 #define PXP_REG_PXP_INT_MASK_0 0x103074
3697 #define PXP_REG_PXP_INT_MASK_1 0x103084
3698 /* [R 32] Interrupt register #0 read */
3699 #define PXP_REG_PXP_INT_STS_0 0x103068
3700 #define PXP_REG_PXP_INT_STS_1 0x103078
3701 /* [RC 32] Interrupt register #0 read clear */
3702 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3703 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3704 /* [RW 27] Parity mask register #0 read/write */
3705 #define PXP_REG_PXP_PRTY_MASK 0x103094
3706 /* [R 26] Parity register #0 read */
3707 #define PXP_REG_PXP_PRTY_STS 0x103088
3708 /* [RC 27] Parity register #0 read clear */
3709 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3710 /* [RW 4] The activity counter initial increment value sent in the load
3711  request */
3712 #define QM_REG_ACTCTRINITVAL_0 0x168040
3713 #define QM_REG_ACTCTRINITVAL_1 0x168044
3714 #define QM_REG_ACTCTRINITVAL_2 0x168048
3715 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3716 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3717  index I represents the physical queue number. The 12 lsbs are ignore and
3718  considered zero so practically there are only 20 bits in this register;
3719  queues 63-0 */
3720 #define QM_REG_BASEADDR 0x168900
3721 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3722  index I represents the physical queue number. The 12 lsbs are ignore and
3723  considered zero so practically there are only 20 bits in this register;
3724  queues 127-64 */
3725 #define QM_REG_BASEADDR_EXT_A 0x16e100
3726 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3727 #define QM_REG_BYTECRDCOST 0x168234
3728 /* [RW 16] The initial byte credit value for both ports. */
3729 #define QM_REG_BYTECRDINITVAL 0x168238
3730 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3731  queue uses port 0 else it uses port 1; queues 31-0 */
3732 #define QM_REG_BYTECRDPORT_LSB 0x168228
3733 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3734  queue uses port 0 else it uses port 1; queues 95-64 */
3735 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3736 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3737  queue uses port 0 else it uses port 1; queues 63-32 */
3738 #define QM_REG_BYTECRDPORT_MSB 0x168224
3739 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3740  queue uses port 0 else it uses port 1; queues 127-96 */
3741 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3742 /* [RW 16] The byte credit value that if above the QM is considered almost
3743  full */
3744 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3745 /* [RW 4] The initial credit for interface */
3746 #define QM_REG_CMINITCRD_0 0x1680cc
3747 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3748 #define QM_REG_CMINITCRD_1 0x1680d0
3749 #define QM_REG_CMINITCRD_2 0x1680d4
3750 #define QM_REG_CMINITCRD_3 0x1680d8
3751 #define QM_REG_CMINITCRD_4 0x1680dc
3752 #define QM_REG_CMINITCRD_5 0x1680e0
3753 #define QM_REG_CMINITCRD_6 0x1680e4
3754 #define QM_REG_CMINITCRD_7 0x1680e8
3755 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3756  is masked */
3757 #define QM_REG_CMINTEN 0x1680ec
3758 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3759  interface 0 */
3760 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3761 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3762 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3763 #define QM_REG_CMINTVOQMASK_3 0x168200
3764 #define QM_REG_CMINTVOQMASK_4 0x168204
3765 #define QM_REG_CMINTVOQMASK_5 0x168208
3766 #define QM_REG_CMINTVOQMASK_6 0x16820c
3767 #define QM_REG_CMINTVOQMASK_7 0x168210
3768 /* [RW 20] The number of connections divided by 16 which dictates the size
3769  of each queue which belongs to even function number. */
3770 #define QM_REG_CONNNUM_0 0x168020
3771 /* [R 6] Keep the fill level of the fifo from write client 4 */
3772 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3773 /* [RW 8] The context regions sent in the CFC load request */
3774 #define QM_REG_CTXREG_0 0x168030
3775 #define QM_REG_CTXREG_1 0x168034
3776 #define QM_REG_CTXREG_2 0x168038
3777 #define QM_REG_CTXREG_3 0x16803c
3778 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3779  bypass enable */
3780 #define QM_REG_ENBYPVOQMASK 0x16823c
3781 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3782  physical queue uses the byte credit; queues 31-0 */
3783 #define QM_REG_ENBYTECRD_LSB 0x168220
3784 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3785  physical queue uses the byte credit; queues 95-64 */
3786 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3787 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3788  physical queue uses the byte credit; queues 63-32 */
3789 #define QM_REG_ENBYTECRD_MSB 0x16821c
3790 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3791  physical queue uses the byte credit; queues 127-96 */
3792 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3793 /* [RW 4] If cleared then the secondary interface will not be served by the
3794  RR arbiter */
3795 #define QM_REG_ENSEC 0x1680f0
3796 /* [RW 32] NA */
3797 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3798 /* [RW 32] NA */
3799 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3800 /* [RW 32] A mask register to mask the Almost empty signals which will not
3801  be use for the almost empty indication to the HW block; queues 31:0 */
3802 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3803 /* [RW 32] A mask register to mask the Almost empty signals which will not
3804  be use for the almost empty indication to the HW block; queues 95-64 */
3805 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3806 /* [RW 32] A mask register to mask the Almost empty signals which will not
3807  be use for the almost empty indication to the HW block; queues 63:32 */
3808 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3809 /* [RW 32] A mask register to mask the Almost empty signals which will not
3810  be use for the almost empty indication to the HW block; queues 127-96 */
3811 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3812 /* [RW 4] The number of outstanding request to CFC */
3813 #define QM_REG_OUTLDREQ 0x168804
3814 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3815  queues. */
3816 #define QM_REG_OVFERROR 0x16805c
3817 /* [RC 7] the Q where the overflow occurs */
3818 #define QM_REG_OVFQNUM 0x168058
3819 /* [R 16] Pause state for physical queues 15-0 */
3820 #define QM_REG_PAUSESTATE0 0x168410
3821 /* [R 16] Pause state for physical queues 31-16 */
3822 #define QM_REG_PAUSESTATE1 0x168414
3823 /* [R 16] Pause state for physical queues 47-32 */
3824 #define QM_REG_PAUSESTATE2 0x16e684
3825 /* [R 16] Pause state for physical queues 63-48 */
3826 #define QM_REG_PAUSESTATE3 0x16e688
3827 /* [R 16] Pause state for physical queues 79-64 */
3828 #define QM_REG_PAUSESTATE4 0x16e68c
3829 /* [R 16] Pause state for physical queues 95-80 */
3830 #define QM_REG_PAUSESTATE5 0x16e690
3831 /* [R 16] Pause state for physical queues 111-96 */
3832 #define QM_REG_PAUSESTATE6 0x16e694
3833 /* [R 16] Pause state for physical queues 127-112 */
3834 #define QM_REG_PAUSESTATE7 0x16e698
3835 /* [RW 2] The PCI attributes field used in the PCI request. */
3836 #define QM_REG_PCIREQAT 0x168054
3837 #define QM_REG_PF_EN 0x16e70c
3838 /* [R 24] The number of tasks stored in the QM for the PF. only even
3839  * functions are valid in E2 (odd I registers will be hard wired to 0) */
3840 #define QM_REG_PF_USG_CNT_0 0x16e040
3841 /* [R 16] NOT USED */
3842 #define QM_REG_PORT0BYTECRD 0x168300
3843 /* [R 16] The byte credit of port 1 */
3844 #define QM_REG_PORT1BYTECRD 0x168304
3845 /* [RW 3] pci function number of queues 15-0 */
3846 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3847 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3848 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3849 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3850 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3851 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3852 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3853 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3854 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3855  ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3856  bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3857 #define QM_REG_PTRTBL 0x168a00
3858 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3859  ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3860  bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3861 #define QM_REG_PTRTBL_EXT_A 0x16e200
3862 /* [RW 2] Interrupt mask register #0 read/write */
3863 #define QM_REG_QM_INT_MASK 0x168444
3864 /* [R 2] Interrupt register #0 read */
3865 #define QM_REG_QM_INT_STS 0x168438
3866 /* [RW 12] Parity mask register #0 read/write */
3867 #define QM_REG_QM_PRTY_MASK 0x168454
3868 /* [R 12] Parity register #0 read */
3869 #define QM_REG_QM_PRTY_STS 0x168448
3870 /* [RC 12] Parity register #0 read clear */
3871 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
3872 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3873 #define QM_REG_QSTATUS_HIGH 0x16802c
3874 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3875 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3876 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3877 #define QM_REG_QSTATUS_LOW 0x168028
3878 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3879 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3880 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3881 #define QM_REG_QTASKCTR_0 0x168308
3882 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3883 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3884 /* [RW 4] Queue tied to VOQ */
3885 #define QM_REG_QVOQIDX_0 0x1680f4
3886 #define QM_REG_QVOQIDX_10 0x16811c
3887 #define QM_REG_QVOQIDX_100 0x16e49c
3888 #define QM_REG_QVOQIDX_101 0x16e4a0
3889 #define QM_REG_QVOQIDX_102 0x16e4a4
3890 #define QM_REG_QVOQIDX_103 0x16e4a8
3891 #define QM_REG_QVOQIDX_104 0x16e4ac
3892 #define QM_REG_QVOQIDX_105 0x16e4b0
3893 #define QM_REG_QVOQIDX_106 0x16e4b4
3894 #define QM_REG_QVOQIDX_107 0x16e4b8
3895 #define QM_REG_QVOQIDX_108 0x16e4bc
3896 #define QM_REG_QVOQIDX_109 0x16e4c0
3897 #define QM_REG_QVOQIDX_11 0x168120
3898 #define QM_REG_QVOQIDX_110 0x16e4c4
3899 #define QM_REG_QVOQIDX_111 0x16e4c8
3900 #define QM_REG_QVOQIDX_112 0x16e4cc
3901 #define QM_REG_QVOQIDX_113 0x16e4d0
3902 #define QM_REG_QVOQIDX_114 0x16e4d4
3903 #define QM_REG_QVOQIDX_115 0x16e4d8
3904 #define QM_REG_QVOQIDX_116 0x16e4dc
3905 #define QM_REG_QVOQIDX_117 0x16e4e0
3906 #define QM_REG_QVOQIDX_118 0x16e4e4
3907 #define QM_REG_QVOQIDX_119 0x16e4e8
3908 #define QM_REG_QVOQIDX_12 0x168124
3909 #define QM_REG_QVOQIDX_120 0x16e4ec
3910 #define QM_REG_QVOQIDX_121 0x16e4f0
3911 #define QM_REG_QVOQIDX_122 0x16e4f4
3912 #define QM_REG_QVOQIDX_123 0x16e4f8
3913 #define QM_REG_QVOQIDX_124 0x16e4fc
3914 #define QM_REG_QVOQIDX_125 0x16e500
3915 #define QM_REG_QVOQIDX_126 0x16e504
3916 #define QM_REG_QVOQIDX_127 0x16e508
3917 #define QM_REG_QVOQIDX_13 0x168128
3918 #define QM_REG_QVOQIDX_14 0x16812c
3919 #define QM_REG_QVOQIDX_15 0x168130
3920 #define QM_REG_QVOQIDX_16 0x168134
3921 #define QM_REG_QVOQIDX_17 0x168138
3922 #define QM_REG_QVOQIDX_21 0x168148
3923 #define QM_REG_QVOQIDX_22 0x16814c
3924 #define QM_REG_QVOQIDX_23 0x168150
3925 #define QM_REG_QVOQIDX_24 0x168154
3926 #define QM_REG_QVOQIDX_25 0x168158
3927 #define QM_REG_QVOQIDX_26 0x16815c
3928 #define QM_REG_QVOQIDX_27 0x168160
3929 #define QM_REG_QVOQIDX_28 0x168164
3930 #define QM_REG_QVOQIDX_29 0x168168
3931 #define QM_REG_QVOQIDX_30 0x16816c
3932 #define QM_REG_QVOQIDX_31 0x168170
3933 #define QM_REG_QVOQIDX_32 0x168174
3934 #define QM_REG_QVOQIDX_33 0x168178
3935 #define QM_REG_QVOQIDX_34 0x16817c
3936 #define QM_REG_QVOQIDX_35 0x168180
3937 #define QM_REG_QVOQIDX_36 0x168184
3938 #define QM_REG_QVOQIDX_37 0x168188
3939 #define QM_REG_QVOQIDX_38 0x16818c
3940 #define QM_REG_QVOQIDX_39 0x168190
3941 #define QM_REG_QVOQIDX_40 0x168194
3942 #define QM_REG_QVOQIDX_41 0x168198
3943 #define QM_REG_QVOQIDX_42 0x16819c
3944 #define QM_REG_QVOQIDX_43 0x1681a0
3945 #define QM_REG_QVOQIDX_44 0x1681a4
3946 #define QM_REG_QVOQIDX_45 0x1681a8
3947 #define QM_REG_QVOQIDX_46 0x1681ac
3948 #define QM_REG_QVOQIDX_47 0x1681b0
3949 #define QM_REG_QVOQIDX_48 0x1681b4
3950 #define QM_REG_QVOQIDX_49 0x1681b8
3951 #define QM_REG_QVOQIDX_5 0x168108
3952 #define QM_REG_QVOQIDX_50 0x1681bc
3953 #define QM_REG_QVOQIDX_51 0x1681c0
3954 #define QM_REG_QVOQIDX_52 0x1681c4
3955 #define QM_REG_QVOQIDX_53 0x1681c8
3956 #define QM_REG_QVOQIDX_54 0x1681cc
3957 #define QM_REG_QVOQIDX_55 0x1681d0
3958 #define QM_REG_QVOQIDX_56 0x1681d4
3959 #define QM_REG_QVOQIDX_57 0x1681d8
3960 #define QM_REG_QVOQIDX_58 0x1681dc
3961 #define QM_REG_QVOQIDX_59 0x1681e0
3962 #define QM_REG_QVOQIDX_6 0x16810c
3963 #define QM_REG_QVOQIDX_60 0x1681e4
3964 #define QM_REG_QVOQIDX_61 0x1681e8
3965 #define QM_REG_QVOQIDX_62 0x1681ec
3966 #define QM_REG_QVOQIDX_63 0x1681f0
3967 #define QM_REG_QVOQIDX_64 0x16e40c
3968 #define QM_REG_QVOQIDX_65 0x16e410
3969 #define QM_REG_QVOQIDX_69 0x16e420
3970 #define QM_REG_QVOQIDX_7 0x168110
3971 #define QM_REG_QVOQIDX_70 0x16e424
3972 #define QM_REG_QVOQIDX_71 0x16e428
3973 #define QM_REG_QVOQIDX_72 0x16e42c
3974 #define QM_REG_QVOQIDX_73 0x16e430
3975 #define QM_REG_QVOQIDX_74 0x16e434
3976 #define QM_REG_QVOQIDX_75 0x16e438
3977 #define QM_REG_QVOQIDX_76 0x16e43c
3978 #define QM_REG_QVOQIDX_77 0x16e440
3979 #define QM_REG_QVOQIDX_78 0x16e444
3980 #define QM_REG_QVOQIDX_79 0x16e448
3981 #define QM_REG_QVOQIDX_8 0x168114
3982 #define QM_REG_QVOQIDX_80 0x16e44c
3983 #define QM_REG_QVOQIDX_81 0x16e450
3984 #define QM_REG_QVOQIDX_85 0x16e460
3985 #define QM_REG_QVOQIDX_86 0x16e464
3986 #define QM_REG_QVOQIDX_87 0x16e468
3987 #define QM_REG_QVOQIDX_88 0x16e46c
3988 #define QM_REG_QVOQIDX_89 0x16e470
3989 #define QM_REG_QVOQIDX_9 0x168118
3990 #define QM_REG_QVOQIDX_90 0x16e474
3991 #define QM_REG_QVOQIDX_91 0x16e478
3992 #define QM_REG_QVOQIDX_92 0x16e47c
3993 #define QM_REG_QVOQIDX_93 0x16e480
3994 #define QM_REG_QVOQIDX_94 0x16e484
3995 #define QM_REG_QVOQIDX_95 0x16e488
3996 #define QM_REG_QVOQIDX_96 0x16e48c
3997 #define QM_REG_QVOQIDX_97 0x16e490
3998 #define QM_REG_QVOQIDX_98 0x16e494
3999 #define QM_REG_QVOQIDX_99 0x16e498
4000 /* [RW 1] Initialization bit command */
4001 #define QM_REG_SOFT_RESET 0x168428
4002 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
4003 #define QM_REG_TASKCRDCOST_0 0x16809c
4004 #define QM_REG_TASKCRDCOST_1 0x1680a0
4005 #define QM_REG_TASKCRDCOST_2 0x1680a4
4006 #define QM_REG_TASKCRDCOST_4 0x1680ac
4007 #define QM_REG_TASKCRDCOST_5 0x1680b0
4008 /* [R 6] Keep the fill level of the fifo from write client 3 */
4009 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
4010 /* [R 6] Keep the fill level of the fifo from write client 2 */
4011 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
4012 /* [RC 32] Credit update error register */
4013 #define QM_REG_VOQCRDERRREG 0x168408
4014 /* [R 16] The credit value for each VOQ */
4015 #define QM_REG_VOQCREDIT_0 0x1682d0
4016 #define QM_REG_VOQCREDIT_1 0x1682d4
4017 #define QM_REG_VOQCREDIT_4 0x1682e0
4018 /* [RW 16] The credit value that if above the QM is considered almost full */
4019 #define QM_REG_VOQCREDITAFULLTHR 0x168090
4020 /* [RW 16] The init and maximum credit for each VoQ */
4021 #define QM_REG_VOQINITCREDIT_0 0x168060
4022 #define QM_REG_VOQINITCREDIT_1 0x168064
4023 #define QM_REG_VOQINITCREDIT_2 0x168068
4024 #define QM_REG_VOQINITCREDIT_4 0x168070
4025 #define QM_REG_VOQINITCREDIT_5 0x168074
4026 /* [RW 1] The port of which VOQ belongs */
4027 #define QM_REG_VOQPORT_0 0x1682a0
4028 #define QM_REG_VOQPORT_1 0x1682a4
4029 #define QM_REG_VOQPORT_2 0x1682a8
4030 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4031 #define QM_REG_VOQQMASK_0_LSB 0x168240
4032 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4033 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
4034 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4035 #define QM_REG_VOQQMASK_0_MSB 0x168244
4036 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4037 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
4038 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4039 #define QM_REG_VOQQMASK_10_LSB 0x168290
4040 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4041 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
4042 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4043 #define QM_REG_VOQQMASK_10_MSB 0x168294
4044 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4045 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
4046 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4047 #define QM_REG_VOQQMASK_11_LSB 0x168298
4048 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4049 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
4050 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4051 #define QM_REG_VOQQMASK_11_MSB 0x16829c
4052 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4053 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
4054 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4055 #define QM_REG_VOQQMASK_1_LSB 0x168248
4056 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4057 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
4058 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4059 #define QM_REG_VOQQMASK_1_MSB 0x16824c
4060 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4061 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
4062 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4063 #define QM_REG_VOQQMASK_2_LSB 0x168250
4064 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4065 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
4066 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4067 #define QM_REG_VOQQMASK_2_MSB 0x168254
4068 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4069 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
4070 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4071 #define QM_REG_VOQQMASK_3_LSB 0x168258
4072 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4073 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
4074 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4075 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
4076 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4077 #define QM_REG_VOQQMASK_4_LSB 0x168260
4078 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4079 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
4080 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4081 #define QM_REG_VOQQMASK_4_MSB 0x168264
4082 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4083 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
4084 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4085 #define QM_REG_VOQQMASK_5_LSB 0x168268
4086 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4087 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
4088 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4089 #define QM_REG_VOQQMASK_5_MSB 0x16826c
4090 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4091 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
4092 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4093 #define QM_REG_VOQQMASK_6_LSB 0x168270
4094 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4095 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
4096 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4097 #define QM_REG_VOQQMASK_6_MSB 0x168274
4098 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4099 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
4100 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4101 #define QM_REG_VOQQMASK_7_LSB 0x168278
4102 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4103 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
4104 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4105 #define QM_REG_VOQQMASK_7_MSB 0x16827c
4106 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4107 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
4108 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4109 #define QM_REG_VOQQMASK_8_LSB 0x168280
4110 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4111 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
4112 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4113 #define QM_REG_VOQQMASK_8_MSB 0x168284
4114 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4115 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
4116 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4117 #define QM_REG_VOQQMASK_9_LSB 0x168288
4118 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4119 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
4120 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4121 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
4122 /* [RW 32] Wrr weights */
4123 #define QM_REG_WRRWEIGHTS_0 0x16880c
4124 #define QM_REG_WRRWEIGHTS_1 0x168810
4125 #define QM_REG_WRRWEIGHTS_10 0x168814
4126 #define QM_REG_WRRWEIGHTS_11 0x168818
4127 #define QM_REG_WRRWEIGHTS_12 0x16881c
4128 #define QM_REG_WRRWEIGHTS_13 0x168820
4129 #define QM_REG_WRRWEIGHTS_14 0x168824
4130 #define QM_REG_WRRWEIGHTS_15 0x168828
4131 #define QM_REG_WRRWEIGHTS_16 0x16e000
4132 #define QM_REG_WRRWEIGHTS_17 0x16e004
4133 #define QM_REG_WRRWEIGHTS_18 0x16e008
4134 #define QM_REG_WRRWEIGHTS_19 0x16e00c
4135 #define QM_REG_WRRWEIGHTS_2 0x16882c
4136 #define QM_REG_WRRWEIGHTS_20 0x16e010
4137 #define QM_REG_WRRWEIGHTS_21 0x16e014
4138 #define QM_REG_WRRWEIGHTS_22 0x16e018
4139 #define QM_REG_WRRWEIGHTS_23 0x16e01c
4140 #define QM_REG_WRRWEIGHTS_24 0x16e020
4141 #define QM_REG_WRRWEIGHTS_25 0x16e024
4142 #define QM_REG_WRRWEIGHTS_26 0x16e028
4143 #define QM_REG_WRRWEIGHTS_27 0x16e02c
4144 #define QM_REG_WRRWEIGHTS_28 0x16e030
4145 #define QM_REG_WRRWEIGHTS_29 0x16e034
4146 #define QM_REG_WRRWEIGHTS_3 0x168830
4147 #define QM_REG_WRRWEIGHTS_30 0x16e038
4148 #define QM_REG_WRRWEIGHTS_31 0x16e03c
4149 #define QM_REG_WRRWEIGHTS_4 0x168834
4150 #define QM_REG_WRRWEIGHTS_5 0x168838
4151 #define QM_REG_WRRWEIGHTS_6 0x16883c
4152 #define QM_REG_WRRWEIGHTS_7 0x168840
4153 #define QM_REG_WRRWEIGHTS_8 0x168844
4154 #define QM_REG_WRRWEIGHTS_9 0x168848
4155 /* [R 6] Keep the fill level of the fifo from write client 1 */
4156 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
4157 /* [W 1] reset to parity interrupt */
4158 #define SEM_FAST_REG_PARITY_RST 0x18840
4159 #define SRC_REG_COUNTFREE0 0x40500
4160 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4161  ports. If set the searcher support 8 functions. */
4162 #define SRC_REG_E1HMF_ENABLE 0x404cc
4163 #define SRC_REG_FIRSTFREE0 0x40510
4164 #define SRC_REG_KEYRSS0_0 0x40408
4165 #define SRC_REG_KEYRSS0_7 0x40424
4166 #define SRC_REG_KEYRSS1_9 0x40454
4167 #define SRC_REG_KEYSEARCH_0 0x40458
4168 #define SRC_REG_KEYSEARCH_1 0x4045c
4169 #define SRC_REG_KEYSEARCH_2 0x40460
4170 #define SRC_REG_KEYSEARCH_3 0x40464
4171 #define SRC_REG_KEYSEARCH_4 0x40468
4172 #define SRC_REG_KEYSEARCH_5 0x4046c
4173 #define SRC_REG_KEYSEARCH_6 0x40470
4174 #define SRC_REG_KEYSEARCH_7 0x40474
4175 #define SRC_REG_KEYSEARCH_8 0x40478
4176 #define SRC_REG_KEYSEARCH_9 0x4047c
4177 #define SRC_REG_LASTFREE0 0x40530
4178 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
4179 /* [RW 1] Reset internal state machines. */
4180 #define SRC_REG_SOFT_RST 0x4049c
4181 /* [R 3] Interrupt register #0 read */
4182 #define SRC_REG_SRC_INT_STS 0x404ac
4183 /* [RW 3] Parity mask register #0 read/write */
4184 #define SRC_REG_SRC_PRTY_MASK 0x404c8
4185 /* [R 3] Parity register #0 read */
4186 #define SRC_REG_SRC_PRTY_STS 0x404bc
4187 /* [RC 3] Parity register #0 read clear */
4188 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
4189 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4190 #define TCM_REG_CAM_OCCUP 0x5017c
4191 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4192  disregarded; valid output is deasserted; all other signals are treated as
4193  usual; if 1 - normal activity. */
4194 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
4195 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4196  are disregarded; all other signals are treated as usual; if 1 - normal
4197  activity. */
4198 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
4199 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4200  disregarded; valid output is deasserted; all other signals are treated as
4201  usual; if 1 - normal activity. */
4202 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4203 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4204  input is disregarded; all other signals are treated as usual; if 1 -
4205  normal activity. */
4206 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
4207 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4208  the initial credit value; read returns the current value of the credit
4209  counter. Must be initialized to 1 at start-up. */
4210 #define TCM_REG_CFC_INIT_CRD 0x50204
4211 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4212  weight 8 (the most prioritised); 1 stands for weight 1(least
4213  prioritised); 2 stands for weight 2; tc. */
4214 #define TCM_REG_CP_WEIGHT 0x500c0
4215 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4216  disregarded; acknowledge output is deasserted; all other signals are
4217  treated as usual; if 1 - normal activity. */
4218 #define TCM_REG_CSEM_IFEN 0x5002c
4219 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
4220  interface. */
4221 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
4222 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4223  weight 8 (the most prioritised); 1 stands for weight 1(least
4224  prioritised); 2 stands for weight 2; tc. */
4225 #define TCM_REG_CSEM_WEIGHT 0x500bc
4226 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4227 #define TCM_REG_ERR_EVNT_ID 0x500a0
4228 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4229 #define TCM_REG_ERR_TCM_HDR 0x5009c
4230 /* [RW 8] The Event ID for Timers expiration. */
4231 #define TCM_REG_EXPR_EVNT_ID 0x500a4
4232 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4233  writes the initial credit value; read returns the current value of the
4234  credit counter. Must be initialized to 64 at start-up. */
4235 #define TCM_REG_FIC0_INIT_CRD 0x5020c
4236 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4237  writes the initial credit value; read returns the current value of the
4238  credit counter. Must be initialized to 64 at start-up. */
4239 #define TCM_REG_FIC1_INIT_CRD 0x50210
4240 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4241  - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4242  ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4243  ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4244 #define TCM_REG_GR_ARB_TYPE 0x50114
4245 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4246  highest priority is 3. It is supposed that the Store channel is the
4247  compliment of the other 3 groups. */
4248 #define TCM_REG_GR_LD0_PR 0x5011c
4249 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4250  highest priority is 3. It is supposed that the Store channel is the
4251  compliment of the other 3 groups. */
4252 #define TCM_REG_GR_LD1_PR 0x50120
4253 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4254  sent to STORM; for a specific connection type. The double REG-pairs are
4255  used to align to STORM context row size of 128 bits. The offset of these
4256  data in the STORM context is always 0. Index _i stands for the connection
4257  type (one of 16). */
4258 #define TCM_REG_N_SM_CTX_LD_0 0x50050
4259 #define TCM_REG_N_SM_CTX_LD_1 0x50054
4260 #define TCM_REG_N_SM_CTX_LD_2 0x50058
4261 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
4262 #define TCM_REG_N_SM_CTX_LD_4 0x50060
4263 #define TCM_REG_N_SM_CTX_LD_5 0x50064
4264 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4265  acknowledge output is deasserted; all other signals are treated as usual;
4266  if 1 - normal activity. */
4267 #define TCM_REG_PBF_IFEN 0x50024
4268 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
4269  interface. */
4270 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
4271 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4272  weight 8 (the most prioritised); 1 stands for weight 1(least
4273  prioritised); 2 stands for weight 2; tc. */
4274 #define TCM_REG_PBF_WEIGHT 0x500b4
4275 #define TCM_REG_PHYS_QNUM0_0 0x500e0
4276 #define TCM_REG_PHYS_QNUM0_1 0x500e4
4277 #define TCM_REG_PHYS_QNUM1_0 0x500e8
4278 #define TCM_REG_PHYS_QNUM1_1 0x500ec
4279 #define TCM_REG_PHYS_QNUM2_0 0x500f0
4280 #define TCM_REG_PHYS_QNUM2_1 0x500f4
4281 #define TCM_REG_PHYS_QNUM3_0 0x500f8
4282 #define TCM_REG_PHYS_QNUM3_1 0x500fc
4283 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4284  acknowledge output is deasserted; all other signals are treated as usual;
4285  if 1 - normal activity. */
4286 #define TCM_REG_PRS_IFEN 0x50020
4287 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
4288  interface. */
4289 #define TCM_REG_PRS_LENGTH_MIS 0x50168
4290 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4291  weight 8 (the most prioritised); 1 stands for weight 1(least
4292  prioritised); 2 stands for weight 2; tc. */
4293 #define TCM_REG_PRS_WEIGHT 0x500b0
4294 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4295 #define TCM_REG_STOP_EVNT_ID 0x500a8
4296 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
4297  interface. */
4298 #define TCM_REG_STORM_LENGTH_MIS 0x50160
4299 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4300  disregarded; acknowledge output is deasserted; all other signals are
4301  treated as usual; if 1 - normal activity. */
4302 #define TCM_REG_STORM_TCM_IFEN 0x50010
4303 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4304  weight 8 (the most prioritised); 1 stands for weight 1(least
4305  prioritised); 2 stands for weight 2; tc. */
4306 #define TCM_REG_STORM_WEIGHT 0x500ac
4307 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4308  acknowledge output is deasserted; all other signals are treated as usual;
4309  if 1 - normal activity. */
4310 #define TCM_REG_TCM_CFC_IFEN 0x50040
4311 /* [RW 11] Interrupt mask register #0 read/write */
4312 #define TCM_REG_TCM_INT_MASK 0x501dc
4313 /* [R 11] Interrupt register #0 read */
4314 #define TCM_REG_TCM_INT_STS 0x501d0
4315 /* [RW 27] Parity mask register #0 read/write */
4316 #define TCM_REG_TCM_PRTY_MASK 0x501ec
4317 /* [R 27] Parity register #0 read */
4318 #define TCM_REG_TCM_PRTY_STS 0x501e0
4319 /* [RC 27] Parity register #0 read clear */
4320 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
4321 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4322  REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4323  Is used to determine the number of the AG context REG-pairs written back;
4324  when the input message Reg1WbFlg isn't set. */
4325 #define TCM_REG_TCM_REG0_SZ 0x500d8
4326 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4327  disregarded; valid is deasserted; all other signals are treated as usual;
4328  if 1 - normal activity. */
4329 #define TCM_REG_TCM_STORM0_IFEN 0x50004
4330 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4331  disregarded; valid is deasserted; all other signals are treated as usual;
4332  if 1 - normal activity. */
4333 #define TCM_REG_TCM_STORM1_IFEN 0x50008
4334 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4335  disregarded; valid is deasserted; all other signals are treated as usual;
4336  if 1 - normal activity. */
4337 #define TCM_REG_TCM_TQM_IFEN 0x5000c
4338 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4339 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
4340 /* [RW 28] The CM header for Timers expiration command. */
4341 #define TCM_REG_TM_TCM_HDR 0x50098
4342 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4343  disregarded; acknowledge output is deasserted; all other signals are
4344  treated as usual; if 1 - normal activity. */
4345 #define TCM_REG_TM_TCM_IFEN 0x5001c
4346 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4347  weight 8 (the most prioritised); 1 stands for weight 1(least
4348  prioritised); 2 stands for weight 2; tc. */
4349 #define TCM_REG_TM_WEIGHT 0x500d0
4350 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4351  the initial credit value; read returns the current value of the credit
4352  counter. Must be initialized to 32 at start-up. */
4353 #define TCM_REG_TQM_INIT_CRD 0x5021c
4354 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4355  stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4356  prioritised); 2 stands for weight 2; tc. */
4357 #define TCM_REG_TQM_P_WEIGHT 0x500c8
4358 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4359  stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4360  prioritised); 2 stands for weight 2; tc. */
4361 #define TCM_REG_TQM_S_WEIGHT 0x500cc
4362 /* [RW 28] The CM header value for QM request (primary). */
4363 #define TCM_REG_TQM_TCM_HDR_P 0x50090
4364 /* [RW 28] The CM header value for QM request (secondary). */
4365 #define TCM_REG_TQM_TCM_HDR_S 0x50094
4366 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4367  acknowledge output is deasserted; all other signals are treated as usual;
4368  if 1 - normal activity. */
4369 #define TCM_REG_TQM_TCM_IFEN 0x50014
4370 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4371  acknowledge output is deasserted; all other signals are treated as usual;
4372  if 1 - normal activity. */
4373 #define TCM_REG_TSDM_IFEN 0x50018
4374 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
4375  interface. */
4376 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
4377 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4378  weight 8 (the most prioritised); 1 stands for weight 1(least
4379  prioritised); 2 stands for weight 2; tc. */
4380 #define TCM_REG_TSDM_WEIGHT 0x500c4
4381 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4382  disregarded; acknowledge output is deasserted; all other signals are
4383  treated as usual; if 1 - normal activity. */
4384 #define TCM_REG_USEM_IFEN 0x50028
4385 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
4386  interface. */
4387 #define TCM_REG_USEM_LENGTH_MIS 0x50170
4388 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4389  weight 8 (the most prioritised); 1 stands for weight 1(least
4390  prioritised); 2 stands for weight 2; tc. */
4391 #define TCM_REG_USEM_WEIGHT 0x500b8
4392 /* [RW 21] Indirect access to the descriptor table of the XX protection
4393  mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4394  pointer; 20:16] - next pointer. */
4395 #define TCM_REG_XX_DESCR_TABLE 0x50280
4396 #define TCM_REG_XX_DESCR_TABLE_SIZE 29
4397 /* [R 6] Use to read the value of XX protection Free counter. */
4398 #define TCM_REG_XX_FREE 0x50178
4399 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4400  of the Input Stage XX protection buffer by the XX protection pending
4401  messages. Max credit available - 127.Write writes the initial credit
4402  value; read returns the current value of the credit counter. Must be
4403  initialized to 19 at start-up. */
4404 #define TCM_REG_XX_INIT_CRD 0x50220
4405 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4406  protection. */
4407 #define TCM_REG_XX_MAX_LL_SZ 0x50044
4408 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4409  protection. ~tcm_registers_xx_free.xx_free is read on read. */
4410 #define TCM_REG_XX_MSG_NUM 0x50224
4411 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4412 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4413 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4414  The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4415  header pointer. */
4416 #define TCM_REG_XX_TABLE 0x50240
4417 /* [RW 4] Load value for cfc ac credit cnt. */
4418 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4419 /* [RW 4] Load value for cfc cld credit cnt. */
4420 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4421 /* [RW 8] Client0 context region. */
4422 #define TM_REG_CL0_CONT_REGION 0x164030
4423 /* [RW 8] Client1 context region. */
4424 #define TM_REG_CL1_CONT_REGION 0x164034
4425 /* [RW 8] Client2 context region. */
4426 #define TM_REG_CL2_CONT_REGION 0x164038
4427 /* [RW 2] Client in High priority client number. */
4428 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4429 /* [RW 4] Load value for clout0 cred cnt. */
4430 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4431 /* [RW 4] Load value for clout1 cred cnt. */
4432 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4433 /* [RW 4] Load value for clout2 cred cnt. */
4434 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4435 /* [RW 1] Enable client0 input. */
4436 #define TM_REG_EN_CL0_INPUT 0x164008
4437 /* [RW 1] Enable client1 input. */
4438 #define TM_REG_EN_CL1_INPUT 0x16400c
4439 /* [RW 1] Enable client2 input. */
4440 #define TM_REG_EN_CL2_INPUT 0x164010
4441 #define TM_REG_EN_LINEAR0_TIMER 0x164014
4442 /* [RW 1] Enable real time counter. */
4443 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4444 /* [RW 1] Enable for Timers state machines. */
4445 #define TM_REG_EN_TIMERS 0x164000
4446 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4447  outstanding load requests for timers (expiration) context loading. */
4448 #define TM_REG_EXP_CRDCNT_VAL 0x164238
4449 /* [RW 32] Linear0 logic address. */
4450 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
4451 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4452 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4453 /* [ST 16] Linear0 Number of scans counter. */
4454 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
4455 /* [WB 64] Linear0 phy address. */
4456 #define TM_REG_LIN0_PHY_ADDR 0x164270
4457 /* [RW 1] Linear0 physical address valid. */
4458 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4459 #define TM_REG_LIN0_SCAN_ON 0x1640d0
4460 /* [RW 24] Linear0 array scan timeout. */
4461 #define TM_REG_LIN0_SCAN_TIME 0x16403c
4462 #define TM_REG_LIN0_VNIC_UC 0x164128
4463 /* [RW 32] Linear1 logic address. */
4464 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
4465 /* [WB 64] Linear1 phy address. */
4466 #define TM_REG_LIN1_PHY_ADDR 0x164280
4467 /* [RW 1] Linear1 physical address valid. */
4468 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4469 /* [RW 6] Linear timer set_clear fifo threshold. */
4470 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4471 /* [RW 2] Load value for pci arbiter credit cnt. */
4472 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4473 /* [RW 20] The amount of hardware cycles for each timer tick. */
4474 #define TM_REG_TIMER_TICK_SIZE 0x16401c
4475 /* [RW 8] Timers Context region. */
4476 #define TM_REG_TM_CONTEXT_REGION 0x164044
4477 /* [RW 1] Interrupt mask register #0 read/write */
4478 #define TM_REG_TM_INT_MASK 0x1640fc
4479 /* [R 1] Interrupt register #0 read */
4480 #define TM_REG_TM_INT_STS 0x1640f0
4481 /* [RW 7] Parity mask register #0 read/write */
4482 #define TM_REG_TM_PRTY_MASK 0x16410c
4483 /* [RC 7] Parity register #0 read clear */
4484 #define TM_REG_TM_PRTY_STS_CLR 0x164104
4485 /* [RW 8] The event id for aggregated interrupt 0 */
4486 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
4487 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4488 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
4489 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
4490 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
4491 /* [RW 1] The T bit for aggregated interrupt 0 */
4492 #define TSDM_REG_AGG_INT_T_0 0x420b8
4493 #define TSDM_REG_AGG_INT_T_1 0x420bc
4494 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4495 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4496 /* [RW 16] The maximum value of the completion counter #0 */
4497 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4498 /* [RW 16] The maximum value of the completion counter #1 */
4499 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4500 /* [RW 16] The maximum value of the completion counter #2 */
4501 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4502 /* [RW 16] The maximum value of the completion counter #3 */
4503 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4504 /* [RW 13] The start address in the internal RAM for the completion
4505  counters. */
4506 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4507 #define TSDM_REG_ENABLE_IN1 0x42238
4508 #define TSDM_REG_ENABLE_IN2 0x4223c
4509 #define TSDM_REG_ENABLE_OUT1 0x42240
4510 #define TSDM_REG_ENABLE_OUT2 0x42244
4511 /* [RW 4] The initial number of messages that can be sent to the pxp control
4512  interface without receiving any ACK. */
4513 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4514 /* [ST 32] The number of ACK after placement messages received */
4515 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4516 /* [ST 32] The number of packet end messages received from the parser */
4517 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4518 /* [ST 32] The number of requests received from the pxp async if */
4519 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4520 /* [ST 32] The number of commands received in queue 0 */
4521 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4522 /* [ST 32] The number of commands received in queue 10 */
4523 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4524 /* [ST 32] The number of commands received in queue 11 */
4525 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4526 /* [ST 32] The number of commands received in queue 1 */
4527 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4528 /* [ST 32] The number of commands received in queue 3 */
4529 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4530 /* [ST 32] The number of commands received in queue 4 */
4531 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4532 /* [ST 32] The number of commands received in queue 5 */
4533 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4534 /* [ST 32] The number of commands received in queue 6 */
4535 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4536 /* [ST 32] The number of commands received in queue 7 */
4537 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4538 /* [ST 32] The number of commands received in queue 8 */
4539 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4540 /* [ST 32] The number of commands received in queue 9 */
4541 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4542 /* [RW 13] The start address in the internal RAM for the packet end message */
4543 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4544 /* [RW 13] The start address in the internal RAM for queue counters */
4545 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4546 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4547 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4548 /* [R 1] parser fifo empty in sdm_sync block */
4549 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4550 /* [R 1] parser serial fifo empty in sdm_sync block */
4551 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4552 /* [RW 32] Tick for timer counter. Applicable only when
4553  ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4554 #define TSDM_REG_TIMER_TICK 0x42000
4555 /* [RW 32] Interrupt mask register #0 read/write */
4556 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4557 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4558 /* [R 32] Interrupt register #0 read */
4559 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4560 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4561 /* [RW 11] Parity mask register #0 read/write */
4562 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4563 /* [R 11] Parity register #0 read */
4564 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4565 /* [RC 11] Parity register #0 read clear */
4566 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4567 /* [RW 5] The number of time_slots in the arbitration cycle */
4568 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4569 /* [RW 3] The source that is associated with arbitration element 0. Source
4570  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4571  sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4572 #define TSEM_REG_ARB_ELEMENT0 0x180020
4573 /* [RW 3] The source that is associated with arbitration element 1. Source
4574  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4575  sleeping thread with priority 1; 4- sleeping thread with priority 2.
4576  Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4577 #define TSEM_REG_ARB_ELEMENT1 0x180024
4578 /* [RW 3] The source that is associated with arbitration element 2. Source
4579  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4580  sleeping thread with priority 1; 4- sleeping thread with priority 2.
4581  Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4582  and ~tsem_registers_arb_element1.arb_element1 */
4583 #define TSEM_REG_ARB_ELEMENT2 0x180028
4584 /* [RW 3] The source that is associated with arbitration element 3. Source
4585  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4586  sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4587  not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4588  ~tsem_registers_arb_element1.arb_element1 and
4589  ~tsem_registers_arb_element2.arb_element2 */
4590 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4591 /* [RW 3] The source that is associated with arbitration element 4. Source
4592  decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4593  sleeping thread with priority 1; 4- sleeping thread with priority 2.
4594  Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4595  and ~tsem_registers_arb_element1.arb_element1 and
4596  ~tsem_registers_arb_element2.arb_element2 and
4597  ~tsem_registers_arb_element3.arb_element3 */
4598 #define TSEM_REG_ARB_ELEMENT4 0x180030
4599 #define TSEM_REG_ENABLE_IN 0x1800a4
4600 #define TSEM_REG_ENABLE_OUT 0x1800a8
4601 /* [RW 32] This address space contains all registers and memories that are
4602  placed in SEM_FAST block. The SEM_FAST registers are described in
4603  appendix B. In order to access the sem_fast registers the base address
4604  ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4605 #define TSEM_REG_FAST_MEMORY 0x1a0000
4606 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4607  by the microcode */
4608 #define TSEM_REG_FIC0_DISABLE 0x180224
4609 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4610  by the microcode */
4611 #define TSEM_REG_FIC1_DISABLE 0x180234
4612 /* [RW 15] Interrupt table Read and write access to it is not possible in
4613  the middle of the work */
4614 #define TSEM_REG_INT_TABLE 0x180400
4615 /* [ST 24] Statistics register. The number of messages that entered through
4616  FIC0 */
4617 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4618 /* [ST 24] Statistics register. The number of messages that entered through
4619  FIC1 */
4620 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4621 /* [ST 24] Statistics register. The number of messages that were sent to
4622  FOC0 */
4623 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4624 /* [ST 24] Statistics register. The number of messages that were sent to
4625  FOC1 */
4626 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4627 /* [ST 24] Statistics register. The number of messages that were sent to
4628  FOC2 */
4629 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4630 /* [ST 24] Statistics register. The number of messages that were sent to
4631  FOC3 */
4632 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4633 /* [RW 1] Disables input messages from the passive buffer May be updated
4634  during run_time by the microcode */
4635 #define TSEM_REG_PAS_DISABLE 0x18024c
4636 /* [WB 128] Debug only. Passive buffer memory */
4637 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4638 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4639 #define TSEM_REG_PRAM 0x1c0000
4640 /* [R 8] Valid sleeping threads indication have bit per thread */
4641 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4642 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4643 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4644 /* [RW 8] List of free threads . There is a bit per thread. */
4645 #define TSEM_REG_THREADS_LIST 0x1802e4
4646 /* [RC 32] Parity register #0 read clear */
4647 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4648 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4649 /* [RW 3] The arbitration scheme of time_slot 0 */
4650 #define TSEM_REG_TS_0_AS 0x180038
4651 /* [RW 3] The arbitration scheme of time_slot 10 */
4652 #define TSEM_REG_TS_10_AS 0x180060
4653 /* [RW 3] The arbitration scheme of time_slot 11 */
4654 #define TSEM_REG_TS_11_AS 0x180064
4655 /* [RW 3] The arbitration scheme of time_slot 12 */
4656 #define TSEM_REG_TS_12_AS 0x180068
4657 /* [RW 3] The arbitration scheme of time_slot 13 */
4658 #define TSEM_REG_TS_13_AS 0x18006c
4659 /* [RW 3] The arbitration scheme of time_slot 14 */
4660 #define TSEM_REG_TS_14_AS 0x180070
4661 /* [RW 3] The arbitration scheme of time_slot 15 */
4662 #define TSEM_REG_TS_15_AS 0x180074
4663 /* [RW 3] The arbitration scheme of time_slot 16 */
4664 #define TSEM_REG_TS_16_AS 0x180078
4665 /* [RW 3] The arbitration scheme of time_slot 17 */
4666 #define TSEM_REG_TS_17_AS 0x18007c
4667 /* [RW 3] The arbitration scheme of time_slot 18 */
4668 #define TSEM_REG_TS_18_AS 0x180080
4669 /* [RW 3] The arbitration scheme of time_slot 1 */
4670 #define TSEM_REG_TS_1_AS 0x18003c
4671 /* [RW 3] The arbitration scheme of time_slot 2 */
4672 #define TSEM_REG_TS_2_AS 0x180040
4673 /* [RW 3] The arbitration scheme of time_slot 3 */
4674 #define TSEM_REG_TS_3_AS 0x180044
4675 /* [RW 3] The arbitration scheme of time_slot 4 */
4676 #define TSEM_REG_TS_4_AS 0x180048
4677 /* [RW 3] The arbitration scheme of time_slot 5 */
4678 #define TSEM_REG_TS_5_AS 0x18004c
4679 /* [RW 3] The arbitration scheme of time_slot 6 */
4680 #define TSEM_REG_TS_6_AS 0x180050
4681 /* [RW 3] The arbitration scheme of time_slot 7 */
4682 #define TSEM_REG_TS_7_AS 0x180054
4683 /* [RW 3] The arbitration scheme of time_slot 8 */
4684 #define TSEM_REG_TS_8_AS 0x180058
4685 /* [RW 3] The arbitration scheme of time_slot 9 */
4686 #define TSEM_REG_TS_9_AS 0x18005c
4687 /* [RW 32] Interrupt mask register #0 read/write */
4688 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4689 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4690 /* [R 32] Interrupt register #0 read */
4691 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4692 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4693 /* [RW 32] Parity mask register #0 read/write */
4694 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120