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Macros
bnx2x_reg.h File Reference

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Macros

#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR   (0x1<<0)
 
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS   (0x1<<2)
 
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU   (0x1<<5)
 
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT   (0x1<<3)
 
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR   (0x1<<4)
 
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND   (0x1<<1)
 
#define ATC_REG_ATC_INIT_ARRAY   0x1100b8
 
#define ATC_REG_ATC_INIT_DONE   0x1100bc
 
#define ATC_REG_ATC_INT_STS_CLR   0x1101c0
 
#define ATC_REG_ATC_PRTY_MASK   0x1101d8
 
#define ATC_REG_ATC_PRTY_STS_CLR   0x1101d0
 
#define BRB1_REG_BRB1_INT_MASK   0x60128
 
#define BRB1_REG_BRB1_INT_STS   0x6011c
 
#define BRB1_REG_BRB1_PRTY_MASK   0x60138
 
#define BRB1_REG_BRB1_PRTY_STS   0x6012c
 
#define BRB1_REG_BRB1_PRTY_STS_CLR   0x60130
 
#define BRB1_REG_FREE_LIST_PRS_CRDT   0x60200
 
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0   0x601d0
 
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1   0x60230
 
#define BRB1_REG_FULL_0_XON_THRESHOLD_0   0x601d4
 
#define BRB1_REG_FULL_0_XON_THRESHOLD_1   0x60234
 
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0   0x601d8
 
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1   0x60238
 
#define BRB1_REG_FULL_1_XON_THRESHOLD_0   0x601dc
 
#define BRB1_REG_FULL_1_XON_THRESHOLD_1   0x6023c
 
#define BRB1_REG_FULL_LB_XOFF_THRESHOLD   0x601e0
 
#define BRB1_REG_FULL_LB_XON_THRESHOLD   0x601e4
 
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0   0x6014c
 
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0   0x6013c
 
#define BRB1_REG_LB_GUARANTIED   0x601ec
 
#define BRB1_REG_LB_GUARANTIED_HYST   0x60264
 
#define BRB1_REG_LL_RAM   0x61000
 
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0   0x6016c
 
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0   0x6015c
 
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED   0x60244
 
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST   0x60254
 
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED   0x60248
 
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST   0x60258
 
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED   0x6024c
 
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST   0x6025c
 
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED   0x60250
 
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST   0x60260
 
#define BRB1_REG_MAC_GUARANTIED_0   0x601e8
 
#define BRB1_REG_MAC_GUARANTIED_1   0x60240
 
#define BRB1_REG_NUM_OF_FULL_BLOCKS   0x60090
 
#define BRB1_REG_NUM_OF_FULL_CYCLES_0   0x600c8
 
#define BRB1_REG_NUM_OF_FULL_CYCLES_1   0x600cc
 
#define BRB1_REG_NUM_OF_FULL_CYCLES_4   0x600d8
 
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0   0x600b8
 
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1   0x600bc
 
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0   0x601c0
 
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1   0x60220
 
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0   0x601c4
 
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1   0x60224
 
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0   0x601c8
 
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1   0x60228
 
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0   0x601cc
 
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1   0x6022c
 
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0   0x60078
 
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1   0x6007c
 
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0   0x60068
 
#define BRB1_REG_PER_CLASS_GUARANTY_MODE   0x60268
 
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0   0x60094
 
#define BRB1_REG_SOFT_RESET   0x600dc
 
#define CCM_REG_CAM_OCCUP   0xd0188
 
#define CCM_REG_CCM_CFC_IFEN   0xd003c
 
#define CCM_REG_CCM_CQM_IFEN   0xd000c
 
#define CCM_REG_CCM_CQM_USE_Q   0xd00c0
 
#define CCM_REG_CCM_INT_MASK   0xd01e4
 
#define CCM_REG_CCM_INT_STS   0xd01d8
 
#define CCM_REG_CCM_PRTY_MASK   0xd01f4
 
#define CCM_REG_CCM_PRTY_STS   0xd01e8
 
#define CCM_REG_CCM_PRTY_STS_CLR   0xd01ec
 
#define CCM_REG_CCM_REG0_SZ   0xd00c4
 
#define CCM_REG_CCM_STORM0_IFEN   0xd0004
 
#define CCM_REG_CCM_STORM1_IFEN   0xd0008
 
#define CCM_REG_CDU_AG_RD_IFEN   0xd0030
 
#define CCM_REG_CDU_AG_WR_IFEN   0xd002c
 
#define CCM_REG_CDU_SM_RD_IFEN   0xd0038
 
#define CCM_REG_CDU_SM_WR_IFEN   0xd0034
 
#define CCM_REG_CFC_INIT_CRD   0xd0204
 
#define CCM_REG_CNT_AUX1_Q   0xd00c8
 
#define CCM_REG_CNT_AUX2_Q   0xd00cc
 
#define CCM_REG_CQM_CCM_HDR_P   0xd008c
 
#define CCM_REG_CQM_CCM_HDR_S   0xd0090
 
#define CCM_REG_CQM_CCM_IFEN   0xd0014
 
#define CCM_REG_CQM_INIT_CRD   0xd020c
 
#define CCM_REG_CQM_P_WEIGHT   0xd00b8
 
#define CCM_REG_CQM_S_WEIGHT   0xd00bc
 
#define CCM_REG_CSDM_IFEN   0xd0018
 
#define CCM_REG_CSDM_LENGTH_MIS   0xd0170
 
#define CCM_REG_CSDM_WEIGHT   0xd00b4
 
#define CCM_REG_ERR_CCM_HDR   0xd0094
 
#define CCM_REG_ERR_EVNT_ID   0xd0098
 
#define CCM_REG_FIC0_INIT_CRD   0xd0210
 
#define CCM_REG_FIC1_INIT_CRD   0xd0214
 
#define CCM_REG_GR_ARB_TYPE   0xd015c
 
#define CCM_REG_GR_LD0_PR   0xd0164
 
#define CCM_REG_GR_LD1_PR   0xd0168
 
#define CCM_REG_INV_DONE_Q   0xd0108
 
#define CCM_REG_N_SM_CTX_LD_0   0xd004c
 
#define CCM_REG_N_SM_CTX_LD_1   0xd0050
 
#define CCM_REG_N_SM_CTX_LD_2   0xd0054
 
#define CCM_REG_N_SM_CTX_LD_3   0xd0058
 
#define CCM_REG_N_SM_CTX_LD_4   0xd005c
 
#define CCM_REG_PBF_IFEN   0xd0028
 
#define CCM_REG_PBF_LENGTH_MIS   0xd0180
 
#define CCM_REG_PBF_WEIGHT   0xd00ac
 
#define CCM_REG_PHYS_QNUM1_0   0xd0134
 
#define CCM_REG_PHYS_QNUM1_1   0xd0138
 
#define CCM_REG_PHYS_QNUM2_0   0xd013c
 
#define CCM_REG_PHYS_QNUM2_1   0xd0140
 
#define CCM_REG_PHYS_QNUM3_0   0xd0144
 
#define CCM_REG_PHYS_QNUM3_1   0xd0148
 
#define CCM_REG_QOS_PHYS_QNUM0_0   0xd0114
 
#define CCM_REG_QOS_PHYS_QNUM0_1   0xd0118
 
#define CCM_REG_QOS_PHYS_QNUM1_0   0xd011c
 
#define CCM_REG_QOS_PHYS_QNUM1_1   0xd0120
 
#define CCM_REG_QOS_PHYS_QNUM2_0   0xd0124
 
#define CCM_REG_QOS_PHYS_QNUM2_1   0xd0128
 
#define CCM_REG_QOS_PHYS_QNUM3_0   0xd012c
 
#define CCM_REG_QOS_PHYS_QNUM3_1   0xd0130
 
#define CCM_REG_STORM_CCM_IFEN   0xd0010
 
#define CCM_REG_STORM_LENGTH_MIS   0xd016c
 
#define CCM_REG_STORM_WEIGHT   0xd009c
 
#define CCM_REG_TSEM_IFEN   0xd001c
 
#define CCM_REG_TSEM_LENGTH_MIS   0xd0174
 
#define CCM_REG_TSEM_WEIGHT   0xd00a0
 
#define CCM_REG_USEM_IFEN   0xd0024
 
#define CCM_REG_USEM_LENGTH_MIS   0xd017c
 
#define CCM_REG_USEM_WEIGHT   0xd00a8
 
#define CCM_REG_XSEM_IFEN   0xd0020
 
#define CCM_REG_XSEM_LENGTH_MIS   0xd0178
 
#define CCM_REG_XSEM_WEIGHT   0xd00a4
 
#define CCM_REG_XX_DESCR_TABLE   0xd0300
 
#define CCM_REG_XX_DESCR_TABLE_SIZE   24
 
#define CCM_REG_XX_FREE   0xd0184
 
#define CCM_REG_XX_INIT_CRD   0xd0220
 
#define CCM_REG_XX_MSG_NUM   0xd0224
 
#define CCM_REG_XX_OVFL_EVNT_ID   0xd0044
 
#define CCM_REG_XX_TABLE   0xd0280
 
#define CDU_REG_CDU_CHK_MASK0   0x101000
 
#define CDU_REG_CDU_CHK_MASK1   0x101004
 
#define CDU_REG_CDU_CONTROL0   0x101008
 
#define CDU_REG_CDU_DEBUG   0x101010
 
#define CDU_REG_CDU_GLOBAL_PARAMS   0x101020
 
#define CDU_REG_CDU_INT_MASK   0x10103c
 
#define CDU_REG_CDU_INT_STS   0x101030
 
#define CDU_REG_CDU_PRTY_MASK   0x10104c
 
#define CDU_REG_CDU_PRTY_STS   0x101040
 
#define CDU_REG_CDU_PRTY_STS_CLR   0x101044
 
#define CDU_REG_ERROR_DATA   0x101014
 
#define CDU_REG_L1TT   0x101800
 
#define CDU_REG_MATT   0x101100
 
#define CDU_REG_MF_MODE   0x101050
 
#define CFC_REG_AC_INIT_DONE   0x104078
 
#define CFC_REG_ACTIVITY_COUNTER   0x104400
 
#define CFC_REG_ACTIVITY_COUNTER_SIZE   256
 
#define CFC_REG_CAM_INIT_DONE   0x10407c
 
#define CFC_REG_CFC_INT_MASK   0x104108
 
#define CFC_REG_CFC_INT_STS   0x1040fc
 
#define CFC_REG_CFC_INT_STS_CLR   0x104100
 
#define CFC_REG_CFC_PRTY_MASK   0x104118
 
#define CFC_REG_CFC_PRTY_STS   0x10410c
 
#define CFC_REG_CFC_PRTY_STS_CLR   0x104110
 
#define CFC_REG_CID_CAM   0x104800
 
#define CFC_REG_CONTROL0   0x104028
 
#define CFC_REG_DEBUG0   0x104050
 
#define CFC_REG_DISABLE_ON_ERROR   0x104044
 
#define CFC_REG_ERROR_VECTOR   0x10403c
 
#define CFC_REG_INFO_RAM   0x105000
 
#define CFC_REG_INFO_RAM_SIZE   1024
 
#define CFC_REG_INIT_REG   0x10404c
 
#define CFC_REG_INTERFACES   0x104058
 
#define CFC_REG_LCREQ_WEIGHTS   0x104084
 
#define CFC_REG_LINK_LIST   0x104c00
 
#define CFC_REG_LINK_LIST_SIZE   256
 
#define CFC_REG_LL_INIT_DONE   0x104074
 
#define CFC_REG_NUM_LCIDS_ALLOC   0x104020
 
#define CFC_REG_NUM_LCIDS_ARRIVING   0x104004
 
#define CFC_REG_NUM_LCIDS_INSIDE_PF   0x104120
 
#define CFC_REG_NUM_LCIDS_LEAVING   0x104018
 
#define CFC_REG_WEAK_ENABLE_PF   0x104124
 
#define CSDM_REG_AGG_INT_EVENT_0   0xc2038
 
#define CSDM_REG_AGG_INT_EVENT_10   0xc2060
 
#define CSDM_REG_AGG_INT_EVENT_11   0xc2064
 
#define CSDM_REG_AGG_INT_EVENT_12   0xc2068
 
#define CSDM_REG_AGG_INT_EVENT_13   0xc206c
 
#define CSDM_REG_AGG_INT_EVENT_14   0xc2070
 
#define CSDM_REG_AGG_INT_EVENT_15   0xc2074
 
#define CSDM_REG_AGG_INT_EVENT_16   0xc2078
 
#define CSDM_REG_AGG_INT_EVENT_2   0xc2040
 
#define CSDM_REG_AGG_INT_EVENT_3   0xc2044
 
#define CSDM_REG_AGG_INT_EVENT_4   0xc2048
 
#define CSDM_REG_AGG_INT_EVENT_5   0xc204c
 
#define CSDM_REG_AGG_INT_EVENT_6   0xc2050
 
#define CSDM_REG_AGG_INT_EVENT_7   0xc2054
 
#define CSDM_REG_AGG_INT_EVENT_8   0xc2058
 
#define CSDM_REG_AGG_INT_EVENT_9   0xc205c
 
#define CSDM_REG_AGG_INT_MODE_10   0xc21e0
 
#define CSDM_REG_AGG_INT_MODE_11   0xc21e4
 
#define CSDM_REG_AGG_INT_MODE_12   0xc21e8
 
#define CSDM_REG_AGG_INT_MODE_13   0xc21ec
 
#define CSDM_REG_AGG_INT_MODE_14   0xc21f0
 
#define CSDM_REG_AGG_INT_MODE_15   0xc21f4
 
#define CSDM_REG_AGG_INT_MODE_16   0xc21f8
 
#define CSDM_REG_AGG_INT_MODE_6   0xc21d0
 
#define CSDM_REG_AGG_INT_MODE_7   0xc21d4
 
#define CSDM_REG_AGG_INT_MODE_8   0xc21d8
 
#define CSDM_REG_AGG_INT_MODE_9   0xc21dc
 
#define CSDM_REG_CFC_RSP_START_ADDR   0xc2008
 
#define CSDM_REG_CMP_COUNTER_MAX0   0xc201c
 
#define CSDM_REG_CMP_COUNTER_MAX1   0xc2020
 
#define CSDM_REG_CMP_COUNTER_MAX2   0xc2024
 
#define CSDM_REG_CMP_COUNTER_MAX3   0xc2028
 
#define CSDM_REG_CMP_COUNTER_START_ADDR   0xc200c
 
#define CSDM_REG_CSDM_INT_MASK_0   0xc229c
 
#define CSDM_REG_CSDM_INT_MASK_1   0xc22ac
 
#define CSDM_REG_CSDM_INT_STS_0   0xc2290
 
#define CSDM_REG_CSDM_INT_STS_1   0xc22a0
 
#define CSDM_REG_CSDM_PRTY_MASK   0xc22bc
 
#define CSDM_REG_CSDM_PRTY_STS   0xc22b0
 
#define CSDM_REG_CSDM_PRTY_STS_CLR   0xc22b4
 
#define CSDM_REG_ENABLE_IN1   0xc2238
 
#define CSDM_REG_ENABLE_IN2   0xc223c
 
#define CSDM_REG_ENABLE_OUT1   0xc2240
 
#define CSDM_REG_ENABLE_OUT2   0xc2244
 
#define CSDM_REG_INIT_CREDIT_PXP_CTRL   0xc24bc
 
#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE   0xc227c
 
#define CSDM_REG_NUM_OF_PKT_END_MSG   0xc2274
 
#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ   0xc2278
 
#define CSDM_REG_NUM_OF_Q0_CMD   0xc2248
 
#define CSDM_REG_NUM_OF_Q10_CMD   0xc226c
 
#define CSDM_REG_NUM_OF_Q11_CMD   0xc2270
 
#define CSDM_REG_NUM_OF_Q1_CMD   0xc224c
 
#define CSDM_REG_NUM_OF_Q3_CMD   0xc2250
 
#define CSDM_REG_NUM_OF_Q4_CMD   0xc2254
 
#define CSDM_REG_NUM_OF_Q5_CMD   0xc2258
 
#define CSDM_REG_NUM_OF_Q6_CMD   0xc225c
 
#define CSDM_REG_NUM_OF_Q7_CMD   0xc2260
 
#define CSDM_REG_NUM_OF_Q8_CMD   0xc2264
 
#define CSDM_REG_NUM_OF_Q9_CMD   0xc2268
 
#define CSDM_REG_Q_COUNTER_START_ADDR   0xc2010
 
#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0xc2548
 
#define CSDM_REG_SYNC_PARSER_EMPTY   0xc2550
 
#define CSDM_REG_SYNC_SYNC_EMPTY   0xc2558
 
#define CSDM_REG_TIMER_TICK   0xc2000
 
#define CSEM_REG_ARB_CYCLE_SIZE   0x200034
 
#define CSEM_REG_ARB_ELEMENT0   0x200020
 
#define CSEM_REG_ARB_ELEMENT1   0x200024
 
#define CSEM_REG_ARB_ELEMENT2   0x200028
 
#define CSEM_REG_ARB_ELEMENT3   0x20002c
 
#define CSEM_REG_ARB_ELEMENT4   0x200030
 
#define CSEM_REG_CSEM_INT_MASK_0   0x200110
 
#define CSEM_REG_CSEM_INT_MASK_1   0x200120
 
#define CSEM_REG_CSEM_INT_STS_0   0x200104
 
#define CSEM_REG_CSEM_INT_STS_1   0x200114
 
#define CSEM_REG_CSEM_PRTY_MASK_0   0x200130
 
#define CSEM_REG_CSEM_PRTY_MASK_1   0x200140
 
#define CSEM_REG_CSEM_PRTY_STS_0   0x200124
 
#define CSEM_REG_CSEM_PRTY_STS_1   0x200134
 
#define CSEM_REG_CSEM_PRTY_STS_CLR_0   0x200128
 
#define CSEM_REG_CSEM_PRTY_STS_CLR_1   0x200138
 
#define CSEM_REG_ENABLE_IN   0x2000a4
 
#define CSEM_REG_ENABLE_OUT   0x2000a8
 
#define CSEM_REG_FAST_MEMORY   0x220000
 
#define CSEM_REG_FIC0_DISABLE   0x200224
 
#define CSEM_REG_FIC1_DISABLE   0x200234
 
#define CSEM_REG_INT_TABLE   0x200400
 
#define CSEM_REG_MSG_NUM_FIC0   0x200000
 
#define CSEM_REG_MSG_NUM_FIC1   0x200004
 
#define CSEM_REG_MSG_NUM_FOC0   0x200008
 
#define CSEM_REG_MSG_NUM_FOC1   0x20000c
 
#define CSEM_REG_MSG_NUM_FOC2   0x200010
 
#define CSEM_REG_MSG_NUM_FOC3   0x200014
 
#define CSEM_REG_PAS_DISABLE   0x20024c
 
#define CSEM_REG_PASSIVE_BUFFER   0x202000
 
#define CSEM_REG_PRAM   0x240000
 
#define CSEM_REG_SLEEP_THREADS_VALID   0x20026c
 
#define CSEM_REG_SLOW_EXT_STORE_EMPTY   0x2002a0
 
#define CSEM_REG_THREADS_LIST   0x2002e4
 
#define CSEM_REG_TS_0_AS   0x200038
 
#define CSEM_REG_TS_10_AS   0x200060
 
#define CSEM_REG_TS_11_AS   0x200064
 
#define CSEM_REG_TS_12_AS   0x200068
 
#define CSEM_REG_TS_13_AS   0x20006c
 
#define CSEM_REG_TS_14_AS   0x200070
 
#define CSEM_REG_TS_15_AS   0x200074
 
#define CSEM_REG_TS_16_AS   0x200078
 
#define CSEM_REG_TS_17_AS   0x20007c
 
#define CSEM_REG_TS_18_AS   0x200080
 
#define CSEM_REG_TS_1_AS   0x20003c
 
#define CSEM_REG_TS_2_AS   0x200040
 
#define CSEM_REG_TS_3_AS   0x200044
 
#define CSEM_REG_TS_4_AS   0x200048
 
#define CSEM_REG_TS_5_AS   0x20004c
 
#define CSEM_REG_TS_6_AS   0x200050
 
#define CSEM_REG_TS_7_AS   0x200054
 
#define CSEM_REG_TS_8_AS   0x200058
 
#define CSEM_REG_TS_9_AS   0x20005c
 
#define CSEM_REG_VFPF_ERR_NUM   0x200380
 
#define DBG_REG_DBG_PRTY_MASK   0xc0a8
 
#define DBG_REG_DBG_PRTY_STS   0xc09c
 
#define DBG_REG_DBG_PRTY_STS_CLR   0xc0a0
 
#define DMAE_REG_BACKWARD_COMP_EN   0x10207c
 
#define DMAE_REG_CMD_MEM   0x102400
 
#define DMAE_REG_CMD_MEM_SIZE   224
 
#define DMAE_REG_CRC16C_INIT   0x10201c
 
#define DMAE_REG_CRC16T10_INIT   0x102020
 
#define DMAE_REG_DMAE_INT_MASK   0x102054
 
#define DMAE_REG_DMAE_PRTY_MASK   0x102064
 
#define DMAE_REG_DMAE_PRTY_STS   0x102058
 
#define DMAE_REG_DMAE_PRTY_STS_CLR   0x10205c
 
#define DMAE_REG_GO_C0   0x102080
 
#define DMAE_REG_GO_C1   0x102084
 
#define DMAE_REG_GO_C10   0x102088
 
#define DMAE_REG_GO_C11   0x10208c
 
#define DMAE_REG_GO_C12   0x102090
 
#define DMAE_REG_GO_C13   0x102094
 
#define DMAE_REG_GO_C14   0x102098
 
#define DMAE_REG_GO_C15   0x10209c
 
#define DMAE_REG_GO_C2   0x1020a0
 
#define DMAE_REG_GO_C3   0x1020a4
 
#define DMAE_REG_GO_C4   0x1020a8
 
#define DMAE_REG_GO_C5   0x1020ac
 
#define DMAE_REG_GO_C6   0x1020b0
 
#define DMAE_REG_GO_C7   0x1020b4
 
#define DMAE_REG_GO_C8   0x1020b8
 
#define DMAE_REG_GO_C9   0x1020bc
 
#define DMAE_REG_GRC_IFEN   0x102008
 
#define DMAE_REG_PCI_IFEN   0x102004
 
#define DMAE_REG_PXP_REQ_INIT_CRD   0x1020c0
 
#define DORQ_REG_AGG_CMD0   0x170060
 
#define DORQ_REG_AGG_CMD1   0x170064
 
#define DORQ_REG_AGG_CMD2   0x170068
 
#define DORQ_REG_AGG_CMD3   0x17006c
 
#define DORQ_REG_CMHEAD_RX   0x170050
 
#define DORQ_REG_DB_ADDR0   0x17008c
 
#define DORQ_REG_DORQ_INT_MASK   0x170180
 
#define DORQ_REG_DORQ_INT_STS   0x170174
 
#define DORQ_REG_DORQ_INT_STS_CLR   0x170178
 
#define DORQ_REG_DORQ_PRTY_MASK   0x170190
 
#define DORQ_REG_DORQ_PRTY_STS   0x170184
 
#define DORQ_REG_DORQ_PRTY_STS_CLR   0x170188
 
#define DORQ_REG_DPM_CID_ADDR   0x170044
 
#define DORQ_REG_DPM_CID_OFST   0x170030
 
#define DORQ_REG_DQ_FIFO_AFULL_TH   0x17007c
 
#define DORQ_REG_DQ_FIFO_FULL_TH   0x170078
 
#define DORQ_REG_DQ_FILL_LVLF   0x1700a4
 
#define DORQ_REG_DQ_FULL_ST   0x1700c0
 
#define DORQ_REG_ERR_CMHEAD   0x170058
 
#define DORQ_REG_IF_EN   0x170004
 
#define DORQ_REG_MODE_ACT   0x170008
 
#define DORQ_REG_NORM_CID_OFST   0x17002c
 
#define DORQ_REG_NORM_CMHEAD_TX   0x17004c
 
#define DORQ_REG_OUTST_REQ   0x17003c
 
#define DORQ_REG_PF_USAGE_CNT   0x1701d0
 
#define DORQ_REG_REGN   0x170038
 
#define DORQ_REG_RSPA_CRD_CNT   0x1700ac
 
#define DORQ_REG_RSPB_CRD_CNT   0x1700b0
 
#define DORQ_REG_RSP_INIT_CRD   0x170048
 
#define DORQ_REG_SHRT_ACT_CNT   0x170070
 
#define DORQ_REG_SHRT_CMHEAD   0x170054
 
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0   (0x1<<4)
 
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0   (0x1<<0)
 
#define HC_CONFIG_0_REG_INT_LINE_EN_0   (0x1<<3)
 
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0   (0x1<<7)
 
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0   (0x1<<2)
 
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0   (0x1<<1)
 
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1   (0x1<<0)
 
#define HC_REG_AGG_INT_0   0x108050
 
#define HC_REG_AGG_INT_1   0x108054
 
#define HC_REG_ATTN_BIT   0x108120
 
#define HC_REG_ATTN_IDX   0x108100
 
#define HC_REG_ATTN_MSG0_ADDR_L   0x108018
 
#define HC_REG_ATTN_MSG1_ADDR_L   0x108020
 
#define HC_REG_ATTN_NUM_P0   0x108038
 
#define HC_REG_ATTN_NUM_P1   0x10803c
 
#define HC_REG_COMMAND_REG   0x108180
 
#define HC_REG_CONFIG_0   0x108000
 
#define HC_REG_CONFIG_1   0x108004
 
#define HC_REG_FUNC_NUM_P0   0x1080ac
 
#define HC_REG_FUNC_NUM_P1   0x1080b0
 
#define HC_REG_HC_PRTY_MASK   0x1080a0
 
#define HC_REG_HC_PRTY_STS   0x108094
 
#define HC_REG_HC_PRTY_STS_CLR   0x108098
 
#define HC_REG_INT_MASK   0x108108
 
#define HC_REG_LEADING_EDGE_0   0x108040
 
#define HC_REG_LEADING_EDGE_1   0x108048
 
#define HC_REG_MAIN_MEMORY   0x108800
 
#define HC_REG_MAIN_MEMORY_SIZE   152
 
#define HC_REG_P0_PROD_CONS   0x108200
 
#define HC_REG_P1_PROD_CONS   0x108400
 
#define HC_REG_PBA_COMMAND   0x108140
 
#define HC_REG_PCI_CONFIG_0   0x108010
 
#define HC_REG_PCI_CONFIG_1   0x108014
 
#define HC_REG_STATISTIC_COUNTERS   0x109000
 
#define HC_REG_TRAILING_EDGE_0   0x108044
 
#define HC_REG_TRAILING_EDGE_1   0x10804c
 
#define HC_REG_UC_RAM_ADDR_0   0x108028
 
#define HC_REG_UC_RAM_ADDR_1   0x108030
 
#define HC_REG_USTORM_ADDR_FOR_COALESCE   0x108068
 
#define HC_REG_VQID_0   0x108008
 
#define HC_REG_VQID_1   0x10800c
 
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN   (0x1<<1)
 
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE   (0x1<<0)
 
#define IGU_REG_ATTENTION_ACK_BITS   0x130108
 
#define IGU_REG_ATTN_FSM   0x130054
 
#define IGU_REG_ATTN_MSG_ADDR_H   0x13011c
 
#define IGU_REG_ATTN_MSG_ADDR_L   0x130120
 
#define IGU_REG_ATTN_WRITE_DONE_PENDING   0x130030
 
#define IGU_REG_BLOCK_CONFIGURATION   0x130000
 
#define IGU_REG_COMMAND_REG_32LSB_DATA   0x130124
 
#define IGU_REG_COMMAND_REG_CTRL   0x13012c
 
#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP   0x130200
 
#define IGU_REG_CTRL_FSM   0x130064
 
#define IGU_REG_ERROR_HANDLING_DATA_VALID   0x130130
 
#define IGU_REG_IGU_PRTY_MASK   0x1300a8
 
#define IGU_REG_IGU_PRTY_STS   0x13009c
 
#define IGU_REG_IGU_PRTY_STS_CLR   0x1300a0
 
#define IGU_REG_INT_HANDLE_FSM   0x130050
 
#define IGU_REG_LEADING_EDGE_LATCH   0x130134
 
#define IGU_REG_MAPPING_MEMORY   0x131000
 
#define IGU_REG_MAPPING_MEMORY_SIZE   136
 
#define IGU_REG_PBA_STATUS_LSB   0x130138
 
#define IGU_REG_PBA_STATUS_MSB   0x13013c
 
#define IGU_REG_PCI_PF_MSI_EN   0x130140
 
#define IGU_REG_PCI_PF_MSIX_EN   0x130144
 
#define IGU_REG_PCI_PF_MSIX_FUNC_MASK   0x130148
 
#define IGU_REG_PENDING_BITS_STATUS   0x130300
 
#define IGU_REG_PF_CONFIGURATION   0x130154
 
#define IGU_REG_PROD_CONS_MEMORY   0x132000
 
#define IGU_REG_PXP_ARB_FSM   0x130068
 
#define IGU_REG_RESET_MEMORIES   0x130158
 
#define IGU_REG_SB_CTRL_FSM   0x13004c
 
#define IGU_REG_SB_INT_BEFORE_MASK_LSB   0x13015c
 
#define IGU_REG_SB_INT_BEFORE_MASK_MSB   0x130160
 
#define IGU_REG_SB_MASK_LSB   0x130164
 
#define IGU_REG_SB_MASK_MSB   0x130168
 
#define IGU_REG_SILENT_DROP   0x13016c
 
#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT   0x130800
 
#define IGU_REG_TIMER_MASKING_VALUE   0x13003c
 
#define IGU_REG_TRAILING_EDGE_LATCH   0x130104
 
#define IGU_REG_VF_CONFIGURATION   0x130170
 
#define IGU_REG_WRITE_DONE_PENDING   0x130480
 
#define MCP_A_REG_MCPR_SCRATCH   0x3a0000
 
#define MCP_REG_MCPR_ACCESS_LOCK   0x8009c
 
#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER   0x8501c
 
#define MCP_REG_MCPR_GP_INPUTS   0x800c0
 
#define MCP_REG_MCPR_GP_OENABLE   0x800c8
 
#define MCP_REG_MCPR_GP_OUTPUTS   0x800c4
 
#define MCP_REG_MCPR_IMC_COMMAND   0x85900
 
#define MCP_REG_MCPR_IMC_DATAREG0   0x85920
 
#define MCP_REG_MCPR_IMC_SLAVE_CONTROL   0x85904
 
#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER   0x8501c
 
#define MCP_REG_MCPR_NVM_ACCESS_ENABLE   0x86424
 
#define MCP_REG_MCPR_NVM_ADDR   0x8640c
 
#define MCP_REG_MCPR_NVM_CFG4   0x8642c
 
#define MCP_REG_MCPR_NVM_COMMAND   0x86400
 
#define MCP_REG_MCPR_NVM_READ   0x86410
 
#define MCP_REG_MCPR_NVM_SW_ARB   0x86420
 
#define MCP_REG_MCPR_NVM_WRITE   0x86408
 
#define MCP_REG_MCPR_SCRATCH   0xa0000
 
#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK   (0x1<<1)
 
#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK   (0x1<<0)
 
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0   0xa42c
 
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1   0xa430
 
#define MISC_REG_AEU_AFTER_INVERT_1_MCP   0xa434
 
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0   0xa438
 
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1   0xa43c
 
#define MISC_REG_AEU_AFTER_INVERT_2_MCP   0xa440
 
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0   0xa444
 
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1   0xa448
 
#define MISC_REG_AEU_AFTER_INVERT_3_MCP   0xa44c
 
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0   0xa450
 
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1   0xa454
 
#define MISC_REG_AEU_AFTER_INVERT_4_MCP   0xa458
 
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0   0xa700
 
#define MISC_REG_AEU_CLR_LATCH_SIGNAL   0xa45c
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0   0xa06c
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1   0xa07c
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2   0xa08c
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3   0xa09c
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5   0xa0bc
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6   0xa0cc
 
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7   0xa0dc
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0   0xa10c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1   0xa11c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2   0xa12c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3   0xa13c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5   0xa15c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6   0xa16c
 
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7   0xa17c
 
#define MISC_REG_AEU_ENABLE1_NIG_0   0xa0ec
 
#define MISC_REG_AEU_ENABLE1_NIG_1   0xa18c
 
#define MISC_REG_AEU_ENABLE1_PXP_0   0xa0fc
 
#define MISC_REG_AEU_ENABLE1_PXP_1   0xa19c
 
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0   0xa070
 
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1   0xa080
 
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0   0xa110
 
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1   0xa120
 
#define MISC_REG_AEU_ENABLE2_NIG_0   0xa0f0
 
#define MISC_REG_AEU_ENABLE2_NIG_1   0xa190
 
#define MISC_REG_AEU_ENABLE2_PXP_0   0xa100
 
#define MISC_REG_AEU_ENABLE2_PXP_1   0xa1a0
 
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0   0xa074
 
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1   0xa084
 
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0   0xa114
 
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1   0xa124
 
#define MISC_REG_AEU_ENABLE3_NIG_0   0xa0f4
 
#define MISC_REG_AEU_ENABLE3_NIG_1   0xa194
 
#define MISC_REG_AEU_ENABLE3_PXP_0   0xa104
 
#define MISC_REG_AEU_ENABLE3_PXP_1   0xa1a4
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0   0xa078
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2   0xa098
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4   0xa0b8
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5   0xa0c8
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6   0xa0d8
 
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7   0xa0e8
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0   0xa118
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2   0xa138
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4   0xa158
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5   0xa168
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6   0xa178
 
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7   0xa188
 
#define MISC_REG_AEU_ENABLE4_NIG_0   0xa0f8
 
#define MISC_REG_AEU_ENABLE4_NIG_1   0xa198
 
#define MISC_REG_AEU_ENABLE4_PXP_0   0xa108
 
#define MISC_REG_AEU_ENABLE4_PXP_1   0xa1a8
 
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0   0xa688
 
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0   0xa6b0
 
#define MISC_REG_AEU_GENERAL_ATTN_0   0xa000
 
#define MISC_REG_AEU_GENERAL_ATTN_1   0xa004
 
#define MISC_REG_AEU_GENERAL_ATTN_10   0xa028
 
#define MISC_REG_AEU_GENERAL_ATTN_11   0xa02c
 
#define MISC_REG_AEU_GENERAL_ATTN_12   0xa030
 
#define MISC_REG_AEU_GENERAL_ATTN_2   0xa008
 
#define MISC_REG_AEU_GENERAL_ATTN_3   0xa00c
 
#define MISC_REG_AEU_GENERAL_ATTN_4   0xa010
 
#define MISC_REG_AEU_GENERAL_ATTN_5   0xa014
 
#define MISC_REG_AEU_GENERAL_ATTN_6   0xa018
 
#define MISC_REG_AEU_GENERAL_ATTN_7   0xa01c
 
#define MISC_REG_AEU_GENERAL_ATTN_8   0xa020
 
#define MISC_REG_AEU_GENERAL_ATTN_9   0xa024
 
#define MISC_REG_AEU_GENERAL_MASK   0xa61c
 
#define MISC_REG_AEU_INVERTER_1_FUNC_0   0xa22c
 
#define MISC_REG_AEU_INVERTER_1_FUNC_1   0xa23c
 
#define MISC_REG_AEU_INVERTER_2_FUNC_0   0xa230
 
#define MISC_REG_AEU_INVERTER_2_FUNC_1   0xa240
 
#define MISC_REG_AEU_MASK_ATTN_FUNC_0   0xa060
 
#define MISC_REG_AEU_MASK_ATTN_FUNC_1   0xa064
 
#define MISC_REG_AEU_SYS_KILL_OCCURRED   0xa610
 
#define MISC_REG_AEU_SYS_KILL_STATUS_0   0xa600
 
#define MISC_REG_AEU_SYS_KILL_STATUS_1   0xa604
 
#define MISC_REG_AEU_SYS_KILL_STATUS_2   0xa608
 
#define MISC_REG_AEU_SYS_KILL_STATUS_3   0xa60c
 
#define MISC_REG_BOND_ID   0xa400
 
#define MISC_REG_CHIP_METAL   0xa404
 
#define MISC_REG_CHIP_NUM   0xa408
 
#define MISC_REG_CHIP_REV   0xa40c
 
#define MISC_REG_CHIP_TYPE   0xac60
 
#define MISC_REG_CHIP_TYPE_57811_MASK   (1<<1)
 
#define MISC_REG_CPMU_LP_DR_ENABLE   0xa858
 
#define MISC_REG_CPMU_LP_FW_ENABLE_P0   0xa84c
 
#define MISC_REG_CPMU_LP_IDLE_THR_P0   0xa8a0
 
#define MISC_REG_CPMU_LP_MASK_ENT_P0   0xa880
 
#define MISC_REG_CPMU_LP_MASK_EXT_P0   0xa888
 
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0   0xa8b8
 
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1   0xa8bc
 
#define MISC_REG_DRIVER_CONTROL_1   0xa510
 
#define MISC_REG_DRIVER_CONTROL_7   0xa3c8
 
#define MISC_REG_E1HMF_MODE   0xa5f8
 
#define MISC_REG_FOUR_PORT_PATH_SWAP   0xa75c
 
#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR   0xa738
 
#define MISC_REG_FOUR_PORT_PORT_SWAP   0xa754
 
#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR   0xa734
 
#define MISC_REG_GENERIC_CR_0   0xa460
 
#define MISC_REG_GENERIC_CR_1   0xa464
 
#define MISC_REG_GENERIC_POR_1   0xa474
 
#define MISC_REG_GEN_PURP_HWG   0xa9a0
 
#define MISC_REG_GPIO   0xa490
 
#define MISC_REG_GPIO_EVENT_EN   0xa2bc
 
#define MISC_REG_GPIO_INT   0xa494
 
#define MISC_REG_GRC_RSV_ATTN   0xa3c0
 
#define MISC_REG_GRC_TIMEOUT_ATTN   0xa3c4
 
#define MISC_REG_GRC_TIMEOUT_EN   0xa280
 
#define MISC_REG_LCPLL_CTRL_1   0xa2a4
 
#define MISC_REG_LCPLL_CTRL_REG_2   0xa2a8
 
#define MISC_REG_LCPLL_E40_PWRDWN   0xaa74
 
#define MISC_REG_LCPLL_E40_RESETB_ANA   0xaa78
 
#define MISC_REG_LCPLL_E40_RESETB_DIG   0xaa7c
 
#define MISC_REG_MISC_INT_MASK   0xa388
 
#define MISC_REG_MISC_PRTY_MASK   0xa398
 
#define MISC_REG_MISC_PRTY_STS   0xa38c
 
#define MISC_REG_MISC_PRTY_STS_CLR   0xa390
 
#define MISC_REG_NIG_WOL_P0   0xa270
 
#define MISC_REG_NIG_WOL_P1   0xa274
 
#define MISC_REG_PCIE_HOT_RESET   0xa618
 
#define MISC_REG_PLL_STORM_CTRL_1   0xa294
 
#define MISC_REG_PLL_STORM_CTRL_2   0xa298
 
#define MISC_REG_PLL_STORM_CTRL_3   0xa29c
 
#define MISC_REG_PLL_STORM_CTRL_4   0xa2a0
 
#define MISC_REG_PORT4MODE_EN   0xa750
 
#define MISC_REG_PORT4MODE_EN_OVWR   0xa720
 
#define MISC_REG_RESET_REG_1   0xa580
 
#define MISC_REG_RESET_REG_2   0xa590
 
#define MISC_REG_SHARED_MEM_ADDR   0xa2b4
 
#define MISC_REG_SPIO   0xa4fc
 
#define MISC_REG_SPIO_EVENT_EN   0xa2b8
 
#define MISC_REG_SPIO_INT   0xa500
 
#define MISC_REG_SW_TIMER_RELOAD_VAL_4   0xa2fc
 
#define MISC_REG_SW_TIMER_VAL   0xa5c0
 
#define MISC_REG_TWO_PORT_PATH_SWAP   0xa758
 
#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR   0xa72c
 
#define MISC_REG_UNPREPARED   0xa424
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST   (0x1<<0)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST   (0x1<<1)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN   (0x1<<4)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST   (0x1<<2)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN   (0x1<<3)
 
#define MISC_REG_WC0_CTRL_PHY_ADDR   0xa9cc
 
#define MISC_REG_WC0_RESET   0xac30
 
#define MISC_REG_XMAC_CORE_PORT_MODE   0xa964
 
#define MISC_REG_XMAC_PHY_PORT_MODE   0xa960
 
#define MSTAT_REG_RX_STAT_GR64_LO   0x200
 
#define MSTAT_REG_TX_STAT_GTXPOK_LO   0
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST   (0x1<<0)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST   (0x1<<1)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN   (0x1<<4)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST   (0x1<<2)
 
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN   (0x1<<3)
 
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN   (0x1<<0)
 
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN   (0x1<<0)
 
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT   (0x1<<0)
 
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS   (0x1<<9)
 
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G   (0x1<<15)
 
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS   (0xf<<18)
 
#define NIG_REG_BMAC0_IN_EN   0x100ac
 
#define NIG_REG_BMAC0_OUT_EN   0x100e0
 
#define NIG_REG_BMAC0_PAUSE_OUT_EN   0x10110
 
#define NIG_REG_BMAC0_REGS_OUT_EN   0x100e8
 
#define NIG_REG_BRB0_OUT_EN   0x100f8
 
#define NIG_REG_BRB0_PAUSE_IN_EN   0x100c4
 
#define NIG_REG_BRB1_OUT_EN   0x100fc
 
#define NIG_REG_BRB1_PAUSE_IN_EN   0x100c8
 
#define NIG_REG_BRB_LB_OUT_EN   0x10100
 
#define NIG_REG_DEBUG_PACKET_LB   0x10800
 
#define NIG_REG_EGRESS_DEBUG_IN_EN   0x100dc
 
#define NIG_REG_EGRESS_DRAIN0_MODE   0x10060
 
#define NIG_REG_EGRESS_EMAC0_OUT_EN   0x10120
 
#define NIG_REG_EGRESS_EMAC0_PORT   0x10058
 
#define NIG_REG_EGRESS_PBF0_IN_EN   0x100cc
 
#define NIG_REG_EGRESS_PBF1_IN_EN   0x100d0
 
#define NIG_REG_EGRESS_UMP0_IN_EN   0x100d4
 
#define NIG_REG_EMAC0_IN_EN   0x100a4
 
#define NIG_REG_EMAC0_PAUSE_OUT_EN   0x10118
 
#define NIG_REG_EMAC0_STATUS_MISC_MI_INT   0x10494
 
#define NIG_REG_INGRESS_BMAC0_MEM   0x10c00
 
#define NIG_REG_INGRESS_BMAC1_MEM   0x11000
 
#define NIG_REG_INGRESS_EOP_LB_EMPTY   0x104e0
 
#define NIG_REG_INGRESS_EOP_LB_FIFO   0x104e4
 
#define NIG_REG_LATCH_BC_0   0x16210
 
#define NIG_REG_LATCH_STATUS_0   0x18000
 
#define NIG_REG_LED_10G_P0   0x10320
 
#define NIG_REG_LED_10G_P1   0x10324
 
#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0   0x10318
 
#define NIG_REG_LED_CONTROL_BLINK_RATE_P0   0x10310
 
#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0   0x10308
 
#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0   0x102f8
 
#define NIG_REG_LED_CONTROL_TRAFFIC_P0   0x10300
 
#define NIG_REG_LED_MODE_P0   0x102f0
 
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0   0x16070
 
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1   0x16074
 
#define NIG_REG_LLFC_ENABLE_0   0x16208
 
#define NIG_REG_LLFC_ENABLE_1   0x1620c
 
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0   0x16058
 
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1   0x1605c
 
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0   0x16060
 
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1   0x16064
 
#define NIG_REG_LLFC_OUT_EN_0   0x160c8
 
#define NIG_REG_LLFC_OUT_EN_1   0x160cc
 
#define NIG_REG_LLH0_ACPI_PAT_0_CRC   0x1015c
 
#define NIG_REG_LLH0_ACPI_PAT_6_LEN   0x10154
 
#define NIG_REG_LLH0_BRB1_DRV_MASK   0x10244
 
#define NIG_REG_LLH0_BRB1_DRV_MASK_MF   0x16048
 
#define NIG_REG_LLH0_BRB1_NOT_MCP   0x1025c
 
#define NIG_REG_LLH0_CLS_TYPE   0x16080
 
#define NIG_REG_LLH0_CM_HEADER   0x1007c
 
#define NIG_REG_LLH0_DEST_IP_0_1   0x101dc
 
#define NIG_REG_LLH0_DEST_MAC_0_0   0x101c0
 
#define NIG_REG_LLH0_DEST_TCP_0   0x10220
 
#define NIG_REG_LLH0_DEST_UDP_0   0x10214
 
#define NIG_REG_LLH0_ERROR_MASK   0x1008c
 
#define NIG_REG_LLH0_EVENT_ID   0x10084
 
#define NIG_REG_LLH0_FUNC_EN   0x160fc
 
#define NIG_REG_LLH0_FUNC_MEM   0x16180
 
#define NIG_REG_LLH0_FUNC_MEM_ENABLE   0x16140
 
#define NIG_REG_LLH0_FUNC_VLAN_ID   0x16100
 
#define NIG_REG_LLH0_IPV4_IPV6_0   0x10208
 
#define NIG_REG_LLH0_T_BIT   0x10074
 
#define NIG_REG_LLH0_VLAN_ID_0   0x1022c
 
#define NIG_REG_LLH0_XCM_INIT_CREDIT   0x10554
 
#define NIG_REG_LLH0_XCM_MASK   0x10130
 
#define NIG_REG_LLH1_BRB1_DRV_MASK   0x10248
 
#define NIG_REG_LLH1_BRB1_NOT_MCP   0x102dc
 
#define NIG_REG_LLH1_CLS_TYPE   0x16084
 
#define NIG_REG_LLH1_CM_HEADER   0x10080
 
#define NIG_REG_LLH1_ERROR_MASK   0x10090
 
#define NIG_REG_LLH1_EVENT_ID   0x10088
 
#define NIG_REG_LLH1_FUNC_MEM   0x161c0
 
#define NIG_REG_LLH1_FUNC_MEM_ENABLE   0x16160
 
#define NIG_REG_LLH1_FUNC_MEM_SIZE   16
 
#define NIG_REG_LLH1_MF_MODE   0x18614
 
#define NIG_REG_LLH1_XCM_INIT_CREDIT   0x10564
 
#define NIG_REG_LLH1_XCM_MASK   0x10134
 
#define NIG_REG_LLH_E1HOV_MODE   0x160d8
 
#define NIG_REG_LLH_MF_MODE   0x16024
 
#define NIG_REG_MASK_INTERRUPT_PORT0   0x10330
 
#define NIG_REG_MASK_INTERRUPT_PORT1   0x10334
 
#define NIG_REG_NIG_EMAC0_EN   0x1003c
 
#define NIG_REG_NIG_EMAC1_EN   0x10040
 
#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC   0x10044
 
#define NIG_REG_NIG_INT_STS_0   0x103b0
 
#define NIG_REG_NIG_INT_STS_1   0x103c0
 
#define NIG_REG_NIG_PRTY_MASK   0x103dc
 
#define NIG_REG_NIG_PRTY_MASK_0   0x183c8
 
#define NIG_REG_NIG_PRTY_MASK_1   0x183d8
 
#define NIG_REG_NIG_PRTY_STS   0x103d0
 
#define NIG_REG_NIG_PRTY_STS_0   0x183bc
 
#define NIG_REG_NIG_PRTY_STS_1   0x183cc
 
#define NIG_REG_NIG_PRTY_STS_CLR   0x103d4
 
#define NIG_REG_NIG_PRTY_STS_CLR_0   0x183c0
 
#define NIG_REG_NIG_PRTY_STS_CLR_1   0x183d0
 
#define MCPR_IMC_COMMAND_ENABLE   (1L<<31)
 
#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT   16
 
#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT   28
 
#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT   8
 
#define NIG_REG_P0_HDRS_AFTER_BASIC   0x18038
 
#define NIG_REG_P0_HWPFC_ENABLE   0x18078
 
#define NIG_REG_P0_LLH_FUNC_MEM2   0x18480
 
#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE   0x18440
 
#define NIG_REG_P0_MAC_IN_EN   0x185ac
 
#define NIG_REG_P0_MAC_OUT_EN   0x185b0
 
#define NIG_REG_P0_MAC_PAUSE_OUT_EN   0x185b4
 
#define NIG_REG_P0_PKT_PRIORITY_TO_COS   0x18054
 
#define NIG_REG_P0_RX_COS0_PRIORITY_MASK   0x18058
 
#define NIG_REG_P0_RX_COS1_PRIORITY_MASK   0x1805c
 
#define NIG_REG_P0_RX_COS2_PRIORITY_MASK   0x186b0
 
#define NIG_REG_P0_RX_COS3_PRIORITY_MASK   0x186b4
 
#define NIG_REG_P0_RX_COS4_PRIORITY_MASK   0x186b8
 
#define NIG_REG_P0_RX_COS5_PRIORITY_MASK   0x186bc
 
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP   0x180f0
 
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB   0x18688
 
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB   0x1868c
 
#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT   0x180e8
 
#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ   0x180ec
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0   0x1810c
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1   0x18110
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2   0x18114
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3   0x18118
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4   0x1811c
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5   0x186a0
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6   0x186a4
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7   0x186a8
 
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8   0x186ac
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0   0x180f8
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1   0x180fc
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2   0x18100
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3   0x18104
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4   0x18108
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5   0x18690
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6   0x18694
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7   0x18698
 
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8   0x1869c
 
#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS   0x180f4
 
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT   0x180e4
 
#define NIG_REG_P1_HDRS_AFTER_BASIC   0x1818c
 
#define NIG_REG_P1_LLH_FUNC_MEM2   0x184c0
 
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE   0x18460
 
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB   0x18680
 
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB   0x18684
 
#define NIG_REG_P1_HWPFC_ENABLE   0x181d0
 
#define NIG_REG_P1_MAC_IN_EN   0x185c0
 
#define NIG_REG_P1_MAC_OUT_EN   0x185c4
 
#define NIG_REG_P1_MAC_PAUSE_OUT_EN   0x185c8
 
#define NIG_REG_P1_PKT_PRIORITY_TO_COS   0x181a8
 
#define NIG_REG_P1_RX_COS0_PRIORITY_MASK   0x181ac
 
#define NIG_REG_P1_RX_COS1_PRIORITY_MASK   0x181b0
 
#define NIG_REG_P1_RX_COS2_PRIORITY_MASK   0x186f8
 
#define NIG_REG_P1_RX_MACFIFO_EMPTY   0x1858c
 
#define NIG_REG_P1_TLLH_FIFO_EMPTY   0x18338
 
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB   0x186e8
 
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB   0x186ec
 
#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT   0x18234
 
#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ   0x18238
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0   0x18258
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1   0x1825c
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2   0x18260
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3   0x18264
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4   0x18268
 
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5   0x186f4
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0   0x18244
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1   0x18248
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2   0x1824c
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3   0x18250
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4   0x18254
 
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5   0x186f0
 
#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS   0x18240
 
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB   0x186e0
 
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB   0x186e4
 
#define NIG_REG_P1_TX_MACFIFO_EMPTY   0x18594
 
#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY   0x182b8
 
#define NIG_REG_PAUSE_ENABLE_0   0x160c0
 
#define NIG_REG_PAUSE_ENABLE_1   0x160c4
 
#define NIG_REG_PBF_LB_IN_EN   0x100b4
 
#define NIG_REG_PORT_SWAP   0x10394
 
#define NIG_REG_PPP_ENABLE_0   0x160b0
 
#define NIG_REG_PPP_ENABLE_1   0x160b4
 
#define NIG_REG_PRS_EOP_OUT_EN   0x10104
 
#define NIG_REG_PRS_REQ_IN_EN   0x100b8
 
#define NIG_REG_SERDES0_CTRL_MD_DEVAD   0x10370
 
#define NIG_REG_SERDES0_CTRL_MD_ST   0x1036c
 
#define NIG_REG_SERDES0_CTRL_PHY_ADDR   0x10374
 
#define NIG_REG_SERDES0_STATUS_LINK_STATUS   0x10578
 
#define NIG_REG_STAT0_BRB_DISCARD   0x105f0
 
#define NIG_REG_STAT0_BRB_TRUNCATE   0x105f8
 
#define NIG_REG_STAT0_EGRESS_MAC_PKT0   0x10750
 
#define NIG_REG_STAT0_EGRESS_MAC_PKT1   0x10760
 
#define NIG_REG_STAT1_BRB_DISCARD   0x10628
 
#define NIG_REG_STAT1_EGRESS_MAC_PKT0   0x107a0
 
#define NIG_REG_STAT1_EGRESS_MAC_PKT1   0x107b0
 
#define NIG_REG_STAT2_BRB_OCTET   0x107e0
 
#define NIG_REG_STATUS_INTERRUPT_PORT0   0x10328
 
#define NIG_REG_STATUS_INTERRUPT_PORT1   0x1032c
 
#define NIG_REG_STRAP_OVERRIDE   0x10398
 
#define NIG_REG_XCM0_OUT_EN   0x100f0
 
#define NIG_REG_XCM1_OUT_EN   0x100f4
 
#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST   0x10348
 
#define NIG_REG_XGXS0_CTRL_MD_DEVAD   0x1033c
 
#define NIG_REG_XGXS0_CTRL_MD_ST   0x10338
 
#define NIG_REG_XGXS0_CTRL_PHY_ADDR   0x10340
 
#define NIG_REG_XGXS0_STATUS_LINK10G   0x10680
 
#define NIG_REG_XGXS0_STATUS_LINK_STATUS   0x10684
 
#define NIG_REG_XGXS_LANE_SEL_P0   0x102e8
 
#define NIG_REG_XGXS_SERDES0_MODE_SEL   0x102e0
 
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT   (0x1<<0)
 
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS   (0x1<<9)
 
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G   (0x1<<15)
 
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS   (0xf<<18)
 
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE   18
 
#define PBF_REG_COS0_UPPER_BOUND   0x15c05c
 
#define PBF_REG_COS0_UPPER_BOUND_P0   0x15c2cc
 
#define PBF_REG_COS0_UPPER_BOUND_P1   0x15c2e4
 
#define PBF_REG_COS0_WEIGHT   0x15c054
 
#define PBF_REG_COS0_WEIGHT_P0   0x15c2a8
 
#define PBF_REG_COS0_WEIGHT_P1   0x15c2c0
 
#define PBF_REG_COS1_UPPER_BOUND   0x15c060
 
#define PBF_REG_COS1_WEIGHT   0x15c058
 
#define PBF_REG_COS1_WEIGHT_P0   0x15c2ac
 
#define PBF_REG_COS1_WEIGHT_P1   0x15c2c4
 
#define PBF_REG_COS2_WEIGHT_P0   0x15c2b0
 
#define PBF_REG_COS2_WEIGHT_P1   0x15c2c8
 
#define PBF_REG_COS3_WEIGHT_P0   0x15c2b4
 
#define PBF_REG_COS4_WEIGHT_P0   0x15c2b8
 
#define PBF_REG_COS5_WEIGHT_P0   0x15c2bc
 
#define PBF_REG_CREDIT_LB_Q   0x140338
 
#define PBF_REG_CREDIT_Q0   0x14033c
 
#define PBF_REG_CREDIT_Q1   0x140340
 
#define PBF_REG_DISABLE_NEW_TASK_PROC_P0   0x14005c
 
#define PBF_REG_DISABLE_NEW_TASK_PROC_P1   0x140060
 
#define PBF_REG_DISABLE_NEW_TASK_PROC_P4   0x14006c
 
#define PBF_REG_DISABLE_PF   0x1402e8
 
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0   0x15c288
 
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1   0x15c28c
 
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0   0x15c278
 
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1   0x15c27c
 
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0   0x15c280
 
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1   0x15c284
 
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0   0x15c2a0
 
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1   0x15c2a4
 
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0   0x15c270
 
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1   0x15c274
 
#define PBF_REG_ETS_ENABLED   0x15c050
 
#define PBF_REG_HDRS_AFTER_BASIC   0x15c0a8
 
#define PBF_REG_HDRS_AFTER_TAG_0   0x15c0b8
 
#define PBF_REG_HIGH_PRIORITY_COS_NUM   0x15c04c
 
#define PBF_REG_IF_ENABLE_REG   0x140044
 
#define PBF_REG_INIT   0x140000
 
#define PBF_REG_INIT_CRD_LB_Q   0x15c248
 
#define PBF_REG_INIT_CRD_Q0   0x15c230
 
#define PBF_REG_INIT_CRD_Q1   0x15c234
 
#define PBF_REG_INIT_P0   0x140004
 
#define PBF_REG_INIT_P1   0x140008
 
#define PBF_REG_INIT_P4   0x14000c
 
#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q   0x140354
 
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0   0x140358
 
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1   0x14035c
 
#define PBF_REG_MAC_IF0_ENABLE   0x140030
 
#define PBF_REG_MAC_IF1_ENABLE   0x140034
 
#define PBF_REG_MAC_LB_ENABLE   0x140040
 
#define PBF_REG_MUST_HAVE_HDRS   0x15c0c4
 
#define PBF_REG_NUM_STRICT_ARB_SLOTS   0x15c064
 
#define PBF_REG_P0_ARB_THRSH   0x1400e4
 
#define PBF_REG_P0_CREDIT   0x140200
 
#define PBF_REG_P0_INIT_CRD   0x1400d0
 
#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT   0x140308
 
#define PBF_REG_P0_PAUSE_ENABLE   0x140014
 
#define PBF_REG_P0_TASK_CNT   0x140204
 
#define PBF_REG_P0_TQ_LINES_FREED_CNT   0x1402f0
 
#define PBF_REG_P0_TQ_OCCUPANCY   0x1402fc
 
#define PBF_REG_P1_CREDIT   0x140208
 
#define PBF_REG_P1_INIT_CRD   0x1400d4
 
#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT   0x14030c
 
#define PBF_REG_P1_TASK_CNT   0x14020c
 
#define PBF_REG_P1_TQ_LINES_FREED_CNT   0x1402f4
 
#define PBF_REG_P1_TQ_OCCUPANCY   0x140300
 
#define PBF_REG_P4_CREDIT   0x140210
 
#define PBF_REG_P4_INIT_CRD   0x1400e0
 
#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT   0x140310
 
#define PBF_REG_P4_TASK_CNT   0x140214
 
#define PBF_REG_P4_TQ_LINES_FREED_CNT   0x1402f8
 
#define PBF_REG_P4_TQ_OCCUPANCY   0x140304
 
#define PBF_REG_PBF_INT_MASK   0x1401d4
 
#define PBF_REG_PBF_INT_STS   0x1401c8
 
#define PBF_REG_PBF_PRTY_MASK   0x1401e4
 
#define PBF_REG_PBF_PRTY_STS_CLR   0x1401dc
 
#define PBF_REG_TAG_ETHERTYPE_0   0x15c090
 
#define PBF_REG_TAG_LEN_0   0x15c09c
 
#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q   0x14038c
 
#define PBF_REG_TQ_LINES_FREED_CNT_Q0   0x140390
 
#define PBF_REG_TQ_LINES_FREED_CNT_Q1   0x140394
 
#define PBF_REG_TQ_OCCUPANCY_LB_Q   0x1403a8
 
#define PBF_REG_TQ_OCCUPANCY_Q0   0x1403ac
 
#define PBF_REG_TQ_OCCUPANCY_Q1   0x1403b0
 
#define PB_REG_CONTROL   0
 
#define PB_REG_PB_INT_MASK   0x28
 
#define PB_REG_PB_INT_STS   0x1c
 
#define PB_REG_PB_PRTY_MASK   0x38
 
#define PB_REG_PB_PRTY_STS   0x2c
 
#define PB_REG_PB_PRTY_STS_CLR   0x30
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR   (0x1<<0)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW   (0x1<<8)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR   (0x1<<1)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN   (0x1<<6)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN   (0x1<<7)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN   (0x1<<4)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN   (0x1<<3)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN   (0x1<<5)
 
#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN   (0x1<<2)
 
#define PGLUE_B_REG_CFG_SPACE_A_REQUEST   0x9010
 
#define PGLUE_B_REG_CFG_SPACE_B_REQUEST   0x9014
 
#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE   0x9194
 
#define PGLUE_B_REG_CSDM_INB_INT_B_VF   0x916c
 
#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE   0x919c
 
#define PGLUE_B_REG_CSDM_START_OFFSET_A   0x9100
 
#define PGLUE_B_REG_CSDM_START_OFFSET_B   0x9108
 
#define PGLUE_B_REG_CSDM_VF_SHIFT_B   0x9110
 
#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF   0x91ac
 
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0   0x9028
 
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR   0x9418
 
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96   0x9024
 
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0   0x9018
 
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32   0x901c
 
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64   0x9020
 
#define PGLUE_B_REG_INCORRECT_RCV_DETAILS   0x9068
 
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER   0x942c
 
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ   0x9430
 
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE   0x9434
 
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE   0x9438
 
#define PGLUE_B_REG_PGLUE_B_INT_STS   0x9298
 
#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR   0x929c
 
#define PGLUE_B_REG_PGLUE_B_PRTY_MASK   0x92b4
 
#define PGLUE_B_REG_PGLUE_B_PRTY_STS   0x92a8
 
#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR   0x92ac
 
#define PGLUE_B_REG_RX_ERR_DETAILS   0x9080
 
#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS   0x9084
 
#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR   0x9458
 
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST   0x9030
 
#define PGLUE_B_REG_TAGS_63_32   0x9244
 
#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE   0x9170
 
#define PGLUE_B_REG_TSDM_START_OFFSET_A   0x90c4
 
#define PGLUE_B_REG_TSDM_START_OFFSET_B   0x90cc
 
#define PGLUE_B_REG_TSDM_VF_SHIFT_B   0x90d4
 
#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF   0x91a0
 
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0   0x9098
 
#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32   0x909c
 
#define PGLUE_B_REG_TX_ERR_RD_DETAILS   0x90a0
 
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2   0x90a4
 
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0   0x9088
 
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32   0x908c
 
#define PGLUE_B_REG_TX_ERR_WR_DETAILS   0x9090
 
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2   0x9094
 
#define PGLUE_B_REG_USDM_INB_INT_A_0   0x9128
 
#define PGLUE_B_REG_USDM_INB_INT_A_1   0x912c
 
#define PGLUE_B_REG_USDM_INB_INT_A_2   0x9130
 
#define PGLUE_B_REG_USDM_INB_INT_A_3   0x9134
 
#define PGLUE_B_REG_USDM_INB_INT_A_4   0x9138
 
#define PGLUE_B_REG_USDM_INB_INT_A_5   0x913c
 
#define PGLUE_B_REG_USDM_INB_INT_A_6   0x9140
 
#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE   0x917c
 
#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE   0x9180
 
#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE   0x9184
 
#define PGLUE_B_REG_USDM_START_OFFSET_A   0x90d8
 
#define PGLUE_B_REG_USDM_START_OFFSET_B   0x90e0
 
#define PGLUE_B_REG_USDM_VF_SHIFT_B   0x90e8
 
#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF   0x91a4
 
#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS   0x9234
 
#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS   0x9230
 
#define PGLUE_B_REG_WAS_ERROR_PF_7_0   0x907c
 
#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR   0x9470
 
#define PGLUE_B_REG_WAS_ERROR_VF_127_96   0x9078
 
#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR   0x9474
 
#define PGLUE_B_REG_WAS_ERROR_VF_31_0   0x906c
 
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR   0x9478
 
#define PGLUE_B_REG_WAS_ERROR_VF_63_32   0x9070
 
#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR   0x947c
 
#define PGLUE_B_REG_WAS_ERROR_VF_95_64   0x9074
 
#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR   0x9480
 
#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE   0x9188
 
#define PGLUE_B_REG_XSDM_START_OFFSET_A   0x90ec
 
#define PGLUE_B_REG_XSDM_START_OFFSET_B   0x90f4
 
#define PGLUE_B_REG_XSDM_VF_SHIFT_B   0x90fc
 
#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF   0x91a8
 
#define PRS_REG_A_PRSU_20   0x40134
 
#define PRS_REG_CFC_LD_CURRENT_CREDIT   0x40164
 
#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT   0x40168
 
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT   0x4011c
 
#define PRS_REG_CID_PORT_0   0x400fc
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0   0x400dc
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1   0x400e0
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2   0x400e4
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3   0x400e8
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4   0x400ec
 
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5   0x400f0
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0   0x400bc
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1   0x400c0
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2   0x400c4
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3   0x400c8
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4   0x400cc
 
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5   0x400d0
 
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1   0x4009c
 
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2   0x400a0
 
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3   0x400a4
 
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4   0x400a8
 
#define PRS_REG_CM_HDR_TYPE_0   0x40078
 
#define PRS_REG_CM_HDR_TYPE_1   0x4007c
 
#define PRS_REG_CM_HDR_TYPE_2   0x40080
 
#define PRS_REG_CM_HDR_TYPE_3   0x40084
 
#define PRS_REG_CM_HDR_TYPE_4   0x40088
 
#define PRS_REG_CM_NO_MATCH_HDR   0x400b8
 
#define PRS_REG_E1HOV_MODE   0x401c8
 
#define PRS_REG_EVENT_ID_1   0x40054
 
#define PRS_REG_EVENT_ID_2   0x40058
 
#define PRS_REG_EVENT_ID_3   0x4005c
 
#define PRS_REG_FCOE_TYPE   0x401d0
 
#define PRS_REG_FLUSH_REGIONS_TYPE_0   0x40004
 
#define PRS_REG_FLUSH_REGIONS_TYPE_1   0x40008
 
#define PRS_REG_FLUSH_REGIONS_TYPE_2   0x4000c
 
#define PRS_REG_FLUSH_REGIONS_TYPE_3   0x40010
 
#define PRS_REG_FLUSH_REGIONS_TYPE_4   0x40014
 
#define PRS_REG_FLUSH_REGIONS_TYPE_5   0x40018
 
#define PRS_REG_FLUSH_REGIONS_TYPE_6   0x4001c
 
#define PRS_REG_FLUSH_REGIONS_TYPE_7   0x40020
 
#define PRS_REG_HDRS_AFTER_BASIC   0x40238
 
#define PRS_REG_HDRS_AFTER_BASIC_PORT_0   0x40270
 
#define PRS_REG_HDRS_AFTER_BASIC_PORT_1   0x40290
 
#define PRS_REG_HDRS_AFTER_TAG_0   0x40248
 
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0   0x40280
 
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1   0x402a0
 
#define PRS_REG_INC_VALUE   0x40048
 
#define PRS_REG_MUST_HAVE_HDRS   0x40254
 
#define PRS_REG_MUST_HAVE_HDRS_PORT_0   0x4028c
 
#define PRS_REG_MUST_HAVE_HDRS_PORT_1   0x402ac
 
#define PRS_REG_NIC_MODE   0x40138
 
#define PRS_REG_NO_MATCH_EVENT_ID   0x40070
 
#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES   0x40128
 
#define PRS_REG_NUM_OF_DEAD_CYCLES   0x40130
 
#define PRS_REG_NUM_OF_PACKETS   0x40124
 
#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES   0x4012c
 
#define PRS_REG_PACKET_REGIONS_TYPE_0   0x40028
 
#define PRS_REG_PACKET_REGIONS_TYPE_1   0x4002c
 
#define PRS_REG_PACKET_REGIONS_TYPE_2   0x40030
 
#define PRS_REG_PACKET_REGIONS_TYPE_3   0x40034
 
#define PRS_REG_PACKET_REGIONS_TYPE_4   0x40038
 
#define PRS_REG_PACKET_REGIONS_TYPE_5   0x4003c
 
#define PRS_REG_PACKET_REGIONS_TYPE_6   0x40040
 
#define PRS_REG_PACKET_REGIONS_TYPE_7   0x40044
 
#define PRS_REG_PENDING_BRB_CAC0_RQ   0x40174
 
#define PRS_REG_PENDING_BRB_PRS_RQ   0x40170
 
#define PRS_REG_PRS_INT_STS   0x40188
 
#define PRS_REG_PRS_PRTY_MASK   0x401a4
 
#define PRS_REG_PRS_PRTY_STS   0x40198
 
#define PRS_REG_PRS_PRTY_STS_CLR   0x4019c
 
#define PRS_REG_PURE_REGIONS   0x40024
 
#define PRS_REG_SERIAL_NUM_STATUS_LSB   0x40154
 
#define PRS_REG_SERIAL_NUM_STATUS_MSB   0x40158
 
#define PRS_REG_SRC_CURRENT_CREDIT   0x4016c
 
#define PRS_REG_TAG_ETHERTYPE_0   0x401d4
 
#define PRS_REG_TAG_LEN_0   0x4022c
 
#define PRS_REG_TCM_CURRENT_CREDIT   0x40160
 
#define PRS_REG_TSDM_CURRENT_CREDIT   0x4015c
 
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT   (0x1<<19)
 
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF   (0x1<<20)
 
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN   (0x1<<22)
 
#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED   (0x1<<23)
 
#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED   (0x1<<24)
 
#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR   (0x1<<7)
 
#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR   (0x1<<7)
 
#define PXP2_REG_HST_DATA_FIFO_STATUS   0x12047c
 
#define PXP2_REG_HST_HEADER_FIFO_STATUS   0x120478
 
#define PXP2_REG_PGL_ADDR_88_F0   0x120534
 
#define PXP2_REG_PGL_ADDR_88_F1   0x120544
 
#define PXP2_REG_PGL_ADDR_8C_F0   0x120538
 
#define PXP2_REG_PGL_ADDR_8C_F1   0x120548
 
#define PXP2_REG_PGL_ADDR_90_F0   0x12053c
 
#define PXP2_REG_PGL_ADDR_90_F1   0x12054c
 
#define PXP2_REG_PGL_ADDR_94_F0   0x120540
 
#define PXP2_REG_PGL_ADDR_94_F1   0x120550
 
#define PXP2_REG_PGL_CONTROL0   0x120490
 
#define PXP2_REG_PGL_CONTROL1   0x120514
 
#define PXP2_REG_PGL_DEBUG   0x120520
 
#define PXP2_REG_PGL_EXP_ROM2   0x120808
 
#define PXP2_REG_PGL_INT_CSDM_0   0x1204f4
 
#define PXP2_REG_PGL_INT_CSDM_1   0x1204f8
 
#define PXP2_REG_PGL_INT_CSDM_2   0x1204fc
 
#define PXP2_REG_PGL_INT_CSDM_3   0x120500
 
#define PXP2_REG_PGL_INT_CSDM_4   0x120504
 
#define PXP2_REG_PGL_INT_CSDM_5   0x120508
 
#define PXP2_REG_PGL_INT_CSDM_6   0x12050c
 
#define PXP2_REG_PGL_INT_CSDM_7   0x120510
 
#define PXP2_REG_PGL_INT_TSDM_0   0x120494
 
#define PXP2_REG_PGL_INT_TSDM_1   0x120498
 
#define PXP2_REG_PGL_INT_TSDM_2   0x12049c
 
#define PXP2_REG_PGL_INT_TSDM_3   0x1204a0
 
#define PXP2_REG_PGL_INT_TSDM_4   0x1204a4
 
#define PXP2_REG_PGL_INT_TSDM_5   0x1204a8
 
#define PXP2_REG_PGL_INT_TSDM_6   0x1204ac
 
#define PXP2_REG_PGL_INT_TSDM_7   0x1204b0
 
#define PXP2_REG_PGL_INT_USDM_0   0x1204b4
 
#define PXP2_REG_PGL_INT_USDM_1   0x1204b8
 
#define PXP2_REG_PGL_INT_USDM_2   0x1204bc
 
#define PXP2_REG_PGL_INT_USDM_3   0x1204c0
 
#define PXP2_REG_PGL_INT_USDM_4   0x1204c4
 
#define PXP2_REG_PGL_INT_USDM_5   0x1204c8
 
#define PXP2_REG_PGL_INT_USDM_6   0x1204cc
 
#define PXP2_REG_PGL_INT_USDM_7   0x1204d0
 
#define PXP2_REG_PGL_INT_XSDM_0   0x1204d4
 
#define PXP2_REG_PGL_INT_XSDM_1   0x1204d8
 
#define PXP2_REG_PGL_INT_XSDM_2   0x1204dc
 
#define PXP2_REG_PGL_INT_XSDM_3   0x1204e0
 
#define PXP2_REG_PGL_INT_XSDM_4   0x1204e4
 
#define PXP2_REG_PGL_INT_XSDM_5   0x1204e8
 
#define PXP2_REG_PGL_INT_XSDM_6   0x1204ec
 
#define PXP2_REG_PGL_INT_XSDM_7   0x1204f0
 
#define PXP2_REG_PGL_PRETEND_FUNC_F0   0x120674
 
#define PXP2_REG_PGL_PRETEND_FUNC_F1   0x120678
 
#define PXP2_REG_PGL_PRETEND_FUNC_F2   0x12067c
 
#define PXP2_REG_PGL_PRETEND_FUNC_F3   0x120680
 
#define PXP2_REG_PGL_PRETEND_FUNC_F4   0x120684
 
#define PXP2_REG_PGL_PRETEND_FUNC_F5   0x120688
 
#define PXP2_REG_PGL_PRETEND_FUNC_F6   0x12068c
 
#define PXP2_REG_PGL_PRETEND_FUNC_F7   0x120690
 
#define PXP2_REG_PGL_READ_BLOCKED   0x120568
 
#define PXP2_REG_PGL_TAGS_LIMIT   0x1205a8
 
#define PXP2_REG_PGL_TXW_CDTS   0x12052c
 
#define PXP2_REG_PGL_WRITE_BLOCKED   0x120564
 
#define PXP2_REG_PSWRQ_BW_ADD1   0x1201c0
 
#define PXP2_REG_PSWRQ_BW_ADD10   0x1201e4
 
#define PXP2_REG_PSWRQ_BW_ADD11   0x1201e8
 
#define PXP2_REG_PSWRQ_BW_ADD2   0x1201c4
 
#define PXP2_REG_PSWRQ_BW_ADD28   0x120228
 
#define PXP2_REG_PSWRQ_BW_ADD3   0x1201c8
 
#define PXP2_REG_PSWRQ_BW_ADD6   0x1201d4
 
#define PXP2_REG_PSWRQ_BW_ADD7   0x1201d8
 
#define PXP2_REG_PSWRQ_BW_ADD8   0x1201dc
 
#define PXP2_REG_PSWRQ_BW_ADD9   0x1201e0
 
#define PXP2_REG_PSWRQ_BW_CREDIT   0x12032c
 
#define PXP2_REG_PSWRQ_BW_L1   0x1202b0
 
#define PXP2_REG_PSWRQ_BW_L10   0x1202d4
 
#define PXP2_REG_PSWRQ_BW_L11   0x1202d8
 
#define PXP2_REG_PSWRQ_BW_L2   0x1202b4
 
#define PXP2_REG_PSWRQ_BW_L28   0x120318
 
#define PXP2_REG_PSWRQ_BW_L3   0x1202b8
 
#define PXP2_REG_PSWRQ_BW_L6   0x1202c4
 
#define PXP2_REG_PSWRQ_BW_L7   0x1202c8
 
#define PXP2_REG_PSWRQ_BW_L8   0x1202cc
 
#define PXP2_REG_PSWRQ_BW_L9   0x1202d0
 
#define PXP2_REG_PSWRQ_BW_RD   0x120324
 
#define PXP2_REG_PSWRQ_BW_UB1   0x120238
 
#define PXP2_REG_PSWRQ_BW_UB10   0x12025c
 
#define PXP2_REG_PSWRQ_BW_UB11   0x120260
 
#define PXP2_REG_PSWRQ_BW_UB2   0x12023c
 
#define PXP2_REG_PSWRQ_BW_UB28   0x1202a0
 
#define PXP2_REG_PSWRQ_BW_UB3   0x120240
 
#define PXP2_REG_PSWRQ_BW_UB6   0x12024c
 
#define PXP2_REG_PSWRQ_BW_UB7   0x120250
 
#define PXP2_REG_PSWRQ_BW_UB8   0x120254
 
#define PXP2_REG_PSWRQ_BW_UB9   0x120258
 
#define PXP2_REG_PSWRQ_BW_WR   0x120328
 
#define PXP2_REG_PSWRQ_CDU0_L2P   0x120000
 
#define PXP2_REG_PSWRQ_QM0_L2P   0x120038
 
#define PXP2_REG_PSWRQ_SRC0_L2P   0x120054
 
#define PXP2_REG_PSWRQ_TM0_L2P   0x12001c
 
#define PXP2_REG_PSWRQ_TSDM0_L2P   0x1200e0
 
#define PXP2_REG_PXP2_INT_MASK_0   0x120578
 
#define PXP2_REG_PXP2_INT_STS_0   0x12056c
 
#define PXP2_REG_PXP2_INT_STS_1   0x120608
 
#define PXP2_REG_PXP2_INT_STS_CLR_0   0x120570
 
#define PXP2_REG_PXP2_PRTY_MASK_0   0x120588
 
#define PXP2_REG_PXP2_PRTY_MASK_1   0x120598
 
#define PXP2_REG_PXP2_PRTY_STS_0   0x12057c
 
#define PXP2_REG_PXP2_PRTY_STS_1   0x12058c
 
#define PXP2_REG_PXP2_PRTY_STS_CLR_0   0x120580
 
#define PXP2_REG_PXP2_PRTY_STS_CLR_1   0x120590
 
#define PXP2_REG_RD_ALMOST_FULL_0   0x120424
 
#define PXP2_REG_RD_BLK_CNT   0x120418
 
#define PXP2_REG_RD_BLK_NUM_CFG   0x12040c
 
#define PXP2_REG_RD_CDURD_SWAP_MODE   0x120404
 
#define PXP2_REG_RD_DISABLE_INPUTS   0x120374
 
#define PXP2_REG_RD_INIT_DONE   0x120370
 
#define PXP2_REG_RD_MAX_BLKS_VQ10   0x1203a0
 
#define PXP2_REG_RD_MAX_BLKS_VQ11   0x1203a4
 
#define PXP2_REG_RD_MAX_BLKS_VQ17   0x1203bc
 
#define PXP2_REG_RD_MAX_BLKS_VQ18   0x1203c0
 
#define PXP2_REG_RD_MAX_BLKS_VQ19   0x1203c4
 
#define PXP2_REG_RD_MAX_BLKS_VQ22   0x1203d0
 
#define PXP2_REG_RD_MAX_BLKS_VQ25   0x1203dc
 
#define PXP2_REG_RD_MAX_BLKS_VQ6   0x120390
 
#define PXP2_REG_RD_MAX_BLKS_VQ9   0x12039c
 
#define PXP2_REG_RD_PBF_SWAP_MODE   0x1203f4
 
#define PXP2_REG_RD_PORT_IS_IDLE_0   0x12041c
 
#define PXP2_REG_RD_PORT_IS_IDLE_1   0x120420
 
#define PXP2_REG_RD_QM_SWAP_MODE   0x1203f8
 
#define PXP2_REG_RD_SR_CNT   0x120414
 
#define PXP2_REG_RD_SRC_SWAP_MODE   0x120400
 
#define PXP2_REG_RD_SR_NUM_CFG   0x120408
 
#define PXP2_REG_RD_START_INIT   0x12036c
 
#define PXP2_REG_RD_TM_SWAP_MODE   0x1203fc
 
#define PXP2_REG_RQ_BW_RD_ADD0   0x1201bc
 
#define PXP2_REG_RQ_BW_RD_ADD12   0x1201ec
 
#define PXP2_REG_RQ_BW_RD_ADD13   0x1201f0
 
#define PXP2_REG_RQ_BW_RD_ADD14   0x1201f4
 
#define PXP2_REG_RQ_BW_RD_ADD15   0x1201f8
 
#define PXP2_REG_RQ_BW_RD_ADD16   0x1201fc
 
#define PXP2_REG_RQ_BW_RD_ADD17   0x120200
 
#define PXP2_REG_RQ_BW_RD_ADD18   0x120204
 
#define PXP2_REG_RQ_BW_RD_ADD19   0x120208
 
#define PXP2_REG_RQ_BW_RD_ADD20   0x12020c
 
#define PXP2_REG_RQ_BW_RD_ADD22   0x120210
 
#define PXP2_REG_RQ_BW_RD_ADD23   0x120214
 
#define PXP2_REG_RQ_BW_RD_ADD24   0x120218
 
#define PXP2_REG_RQ_BW_RD_ADD25   0x12021c
 
#define PXP2_REG_RQ_BW_RD_ADD26   0x120220
 
#define PXP2_REG_RQ_BW_RD_ADD27   0x120224
 
#define PXP2_REG_RQ_BW_RD_ADD4   0x1201cc
 
#define PXP2_REG_RQ_BW_RD_ADD5   0x1201d0
 
#define PXP2_REG_RQ_BW_RD_L0   0x1202ac
 
#define PXP2_REG_RQ_BW_RD_L12   0x1202dc
 
#define PXP2_REG_RQ_BW_RD_L13   0x1202e0
 
#define PXP2_REG_RQ_BW_RD_L14   0x1202e4
 
#define PXP2_REG_RQ_BW_RD_L15   0x1202e8
 
#define PXP2_REG_RQ_BW_RD_L16   0x1202ec
 
#define PXP2_REG_RQ_BW_RD_L17   0x1202f0
 
#define PXP2_REG_RQ_BW_RD_L18   0x1202f4
 
#define PXP2_REG_RQ_BW_RD_L19   0x1202f8
 
#define PXP2_REG_RQ_BW_RD_L20   0x1202fc
 
#define PXP2_REG_RQ_BW_RD_L22   0x120300
 
#define PXP2_REG_RQ_BW_RD_L23   0x120304
 
#define PXP2_REG_RQ_BW_RD_L24   0x120308
 
#define PXP2_REG_RQ_BW_RD_L25   0x12030c
 
#define PXP2_REG_RQ_BW_RD_L26   0x120310
 
#define PXP2_REG_RQ_BW_RD_L27   0x120314
 
#define PXP2_REG_RQ_BW_RD_L4   0x1202bc
 
#define PXP2_REG_RQ_BW_RD_L5   0x1202c0
 
#define PXP2_REG_RQ_BW_RD_UBOUND0   0x120234
 
#define PXP2_REG_RQ_BW_RD_UBOUND12   0x120264
 
#define PXP2_REG_RQ_BW_RD_UBOUND13   0x120268
 
#define PXP2_REG_RQ_BW_RD_UBOUND14   0x12026c
 
#define PXP2_REG_RQ_BW_RD_UBOUND15   0x120270
 
#define PXP2_REG_RQ_BW_RD_UBOUND16   0x120274
 
#define PXP2_REG_RQ_BW_RD_UBOUND17   0x120278
 
#define PXP2_REG_RQ_BW_RD_UBOUND18   0x12027c
 
#define PXP2_REG_RQ_BW_RD_UBOUND19   0x120280
 
#define PXP2_REG_RQ_BW_RD_UBOUND20   0x120284
 
#define PXP2_REG_RQ_BW_RD_UBOUND22   0x120288
 
#define PXP2_REG_RQ_BW_RD_UBOUND23   0x12028c
 
#define PXP2_REG_RQ_BW_RD_UBOUND24   0x120290
 
#define PXP2_REG_RQ_BW_RD_UBOUND25   0x120294
 
#define PXP2_REG_RQ_BW_RD_UBOUND26   0x120298
 
#define PXP2_REG_RQ_BW_RD_UBOUND27   0x12029c
 
#define PXP2_REG_RQ_BW_RD_UBOUND4   0x120244
 
#define PXP2_REG_RQ_BW_RD_UBOUND5   0x120248
 
#define PXP2_REG_RQ_BW_WR_ADD29   0x12022c
 
#define PXP2_REG_RQ_BW_WR_ADD30   0x120230
 
#define PXP2_REG_RQ_BW_WR_L29   0x12031c
 
#define PXP2_REG_RQ_BW_WR_L30   0x120320
 
#define PXP2_REG_RQ_BW_WR_UBOUND29   0x1202a4
 
#define PXP2_REG_RQ_BW_WR_UBOUND30   0x1202a8
 
#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR   0x120008
 
#define PXP2_REG_RQ_CDU_ENDIAN_M   0x1201a0
 
#define PXP2_REG_RQ_CDU_FIRST_ILT   0x12061c
 
#define PXP2_REG_RQ_CDU_LAST_ILT   0x120620
 
#define PXP2_REG_RQ_CDU_P_SIZE   0x120018
 
#define PXP2_REG_RQ_CFG_DONE   0x1201b4
 
#define PXP2_REG_RQ_DBG_ENDIAN_M   0x1201a4
 
#define PXP2_REG_RQ_DISABLE_INPUTS   0x120330
 
#define PXP2_REG_RQ_DRAM_ALIGN   0x1205b0
 
#define PXP2_REG_RQ_DRAM_ALIGN_RD   0x12092c
 
#define PXP2_REG_RQ_DRAM_ALIGN_SEL   0x120930
 
#define PXP2_REG_RQ_ELT_DISABLE   0x12066c
 
#define PXP2_REG_RQ_HC_ENDIAN_M   0x1201a8
 
#define PXP2_REG_RQ_ILT_MODE   0x1205b4
 
#define PXP2_REG_RQ_ONCHIP_AT   0x122000
 
#define PXP2_REG_RQ_ONCHIP_AT_B0   0x128000
 
#define PXP2_REG_RQ_PDR_LIMIT   0x12033c
 
#define PXP2_REG_RQ_QM_ENDIAN_M   0x120194
 
#define PXP2_REG_RQ_QM_FIRST_ILT   0x120634
 
#define PXP2_REG_RQ_QM_LAST_ILT   0x120638
 
#define PXP2_REG_RQ_QM_P_SIZE   0x120050
 
#define PXP2_REG_RQ_RBC_DONE   0x1201b0
 
#define PXP2_REG_RQ_RD_MBS0   0x120160
 
#define PXP2_REG_RQ_RD_MBS1   0x120168
 
#define PXP2_REG_RQ_SRC_ENDIAN_M   0x12019c
 
#define PXP2_REG_RQ_SRC_FIRST_ILT   0x12063c
 
#define PXP2_REG_RQ_SRC_LAST_ILT   0x120640
 
#define PXP2_REG_RQ_SRC_P_SIZE   0x12006c
 
#define PXP2_REG_RQ_TM_ENDIAN_M   0x120198
 
#define PXP2_REG_RQ_TM_FIRST_ILT   0x120644
 
#define PXP2_REG_RQ_TM_LAST_ILT   0x120648
 
#define PXP2_REG_RQ_TM_P_SIZE   0x120034
 
#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY   0x12080c
 
#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR   0x120094
 
#define PXP2_REG_RQ_VQ0_ENTRY_CNT   0x120810
 
#define PXP2_REG_RQ_VQ10_ENTRY_CNT   0x120818
 
#define PXP2_REG_RQ_VQ11_ENTRY_CNT   0x120820
 
#define PXP2_REG_RQ_VQ12_ENTRY_CNT   0x120828
 
#define PXP2_REG_RQ_VQ13_ENTRY_CNT   0x120830
 
#define PXP2_REG_RQ_VQ14_ENTRY_CNT   0x120838
 
#define PXP2_REG_RQ_VQ15_ENTRY_CNT   0x120840
 
#define PXP2_REG_RQ_VQ16_ENTRY_CNT   0x120848
 
#define PXP2_REG_RQ_VQ17_ENTRY_CNT   0x120850
 
#define PXP2_REG_RQ_VQ18_ENTRY_CNT   0x120858
 
#define PXP2_REG_RQ_VQ19_ENTRY_CNT   0x120860
 
#define PXP2_REG_RQ_VQ1_ENTRY_CNT   0x120868
 
#define PXP2_REG_RQ_VQ20_ENTRY_CNT   0x120870
 
#define PXP2_REG_RQ_VQ21_ENTRY_CNT   0x120878
 
#define PXP2_REG_RQ_VQ22_ENTRY_CNT   0x120880
 
#define PXP2_REG_RQ_VQ23_ENTRY_CNT   0x120888
 
#define PXP2_REG_RQ_VQ24_ENTRY_CNT   0x120890
 
#define PXP2_REG_RQ_VQ25_ENTRY_CNT   0x120898
 
#define PXP2_REG_RQ_VQ26_ENTRY_CNT   0x1208a0
 
#define PXP2_REG_RQ_VQ27_ENTRY_CNT   0x1208a8
 
#define PXP2_REG_RQ_VQ28_ENTRY_CNT   0x1208b0
 
#define PXP2_REG_RQ_VQ29_ENTRY_CNT   0x1208b8
 
#define PXP2_REG_RQ_VQ2_ENTRY_CNT   0x1208c0
 
#define PXP2_REG_RQ_VQ30_ENTRY_CNT   0x1208c8
 
#define PXP2_REG_RQ_VQ31_ENTRY_CNT   0x1208d0
 
#define PXP2_REG_RQ_VQ3_ENTRY_CNT   0x1208d8
 
#define PXP2_REG_RQ_VQ4_ENTRY_CNT   0x1208e0
 
#define PXP2_REG_RQ_VQ5_ENTRY_CNT   0x1208e8
 
#define PXP2_REG_RQ_VQ6_ENTRY_CNT   0x1208f0
 
#define PXP2_REG_RQ_VQ7_ENTRY_CNT   0x1208f8
 
#define PXP2_REG_RQ_VQ8_ENTRY_CNT   0x120900
 
#define PXP2_REG_RQ_VQ9_ENTRY_CNT   0x120908
 
#define PXP2_REG_RQ_WR_MBS0   0x12015c
 
#define PXP2_REG_RQ_WR_MBS1   0x120164
 
#define PXP2_REG_WR_CDU_MPS   0x1205f0
 
#define PXP2_REG_WR_CSDM_MPS   0x1205d0
 
#define PXP2_REG_WR_DBG_MPS   0x1205e8
 
#define PXP2_REG_WR_DMAE_MPS   0x1205ec
 
#define PXP2_REG_WR_DMAE_TH   0x120368
 
#define PXP2_REG_WR_HC_MPS   0x1205c8
 
#define PXP2_REG_WR_QM_MPS   0x1205dc
 
#define PXP2_REG_WR_REV_MODE   0x120670
 
#define PXP2_REG_WR_SRC_MPS   0x1205e4
 
#define PXP2_REG_WR_TM_MPS   0x1205e0
 
#define PXP2_REG_WR_TSDM_MPS   0x1205d4
 
#define PXP2_REG_WR_USDMDP_TH   0x120348
 
#define PXP2_REG_WR_USDM_MPS   0x1205cc
 
#define PXP2_REG_WR_XSDM_MPS   0x1205d8
 
#define PXP_REG_HST_ARB_IS_IDLE   0x103004
 
#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB   0x103008
 
#define PXP_REG_HST_DISCARD_DOORBELLS   0x1030a4
 
#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS   0x1030a0
 
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES   0x1030a8
 
#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS   0x10309c
 
#define PXP_REG_HST_INBOUND_INT   0x103800
 
#define PXP_REG_PXP_INT_MASK_0   0x103074
 
#define PXP_REG_PXP_INT_MASK_1   0x103084
 
#define PXP_REG_PXP_INT_STS_0   0x103068
 
#define PXP_REG_PXP_INT_STS_1   0x103078
 
#define PXP_REG_PXP_INT_STS_CLR_0   0x10306c
 
#define PXP_REG_PXP_INT_STS_CLR_1   0x10307c
 
#define PXP_REG_PXP_PRTY_MASK   0x103094
 
#define PXP_REG_PXP_PRTY_STS   0x103088
 
#define PXP_REG_PXP_PRTY_STS_CLR   0x10308c
 
#define QM_REG_ACTCTRINITVAL_0   0x168040
 
#define QM_REG_ACTCTRINITVAL_1   0x168044
 
#define QM_REG_ACTCTRINITVAL_2   0x168048
 
#define QM_REG_ACTCTRINITVAL_3   0x16804c
 
#define QM_REG_BASEADDR   0x168900
 
#define QM_REG_BASEADDR_EXT_A   0x16e100
 
#define QM_REG_BYTECRDCOST   0x168234
 
#define QM_REG_BYTECRDINITVAL   0x168238
 
#define QM_REG_BYTECRDPORT_LSB   0x168228
 
#define QM_REG_BYTECRDPORT_LSB_EXT_A   0x16e520
 
#define QM_REG_BYTECRDPORT_MSB   0x168224
 
#define QM_REG_BYTECRDPORT_MSB_EXT_A   0x16e51c
 
#define QM_REG_BYTECREDITAFULLTHR   0x168094
 
#define QM_REG_CMINITCRD_0   0x1680cc
 
#define QM_REG_BYTECRDCMDQ_0   0x16e6e8
 
#define QM_REG_CMINITCRD_1   0x1680d0
 
#define QM_REG_CMINITCRD_2   0x1680d4
 
#define QM_REG_CMINITCRD_3   0x1680d8
 
#define QM_REG_CMINITCRD_4   0x1680dc
 
#define QM_REG_CMINITCRD_5   0x1680e0
 
#define QM_REG_CMINITCRD_6   0x1680e4
 
#define QM_REG_CMINITCRD_7   0x1680e8
 
#define QM_REG_CMINTEN   0x1680ec
 
#define QM_REG_CMINTVOQMASK_0   0x1681f4
 
#define QM_REG_CMINTVOQMASK_1   0x1681f8
 
#define QM_REG_CMINTVOQMASK_2   0x1681fc
 
#define QM_REG_CMINTVOQMASK_3   0x168200
 
#define QM_REG_CMINTVOQMASK_4   0x168204
 
#define QM_REG_CMINTVOQMASK_5   0x168208
 
#define QM_REG_CMINTVOQMASK_6   0x16820c
 
#define QM_REG_CMINTVOQMASK_7   0x168210
 
#define QM_REG_CONNNUM_0   0x168020
 
#define QM_REG_CQM_WRC_FIFOLVL   0x168018
 
#define QM_REG_CTXREG_0   0x168030
 
#define QM_REG_CTXREG_1   0x168034
 
#define QM_REG_CTXREG_2   0x168038
 
#define QM_REG_CTXREG_3   0x16803c
 
#define QM_REG_ENBYPVOQMASK   0x16823c
 
#define QM_REG_ENBYTECRD_LSB   0x168220
 
#define QM_REG_ENBYTECRD_LSB_EXT_A   0x16e518
 
#define QM_REG_ENBYTECRD_MSB   0x16821c
 
#define QM_REG_ENBYTECRD_MSB_EXT_A   0x16e514
 
#define QM_REG_ENSEC   0x1680f0
 
#define QM_REG_FUNCNUMSEL_LSB   0x168230
 
#define QM_REG_FUNCNUMSEL_MSB   0x16822c
 
#define QM_REG_HWAEMPTYMASK_LSB   0x168218
 
#define QM_REG_HWAEMPTYMASK_LSB_EXT_A   0x16e510
 
#define QM_REG_HWAEMPTYMASK_MSB   0x168214
 
#define QM_REG_HWAEMPTYMASK_MSB_EXT_A   0x16e50c
 
#define QM_REG_OUTLDREQ   0x168804
 
#define QM_REG_OVFERROR   0x16805c
 
#define QM_REG_OVFQNUM   0x168058
 
#define QM_REG_PAUSESTATE0   0x168410
 
#define QM_REG_PAUSESTATE1   0x168414
 
#define QM_REG_PAUSESTATE2   0x16e684
 
#define QM_REG_PAUSESTATE3   0x16e688
 
#define QM_REG_PAUSESTATE4   0x16e68c
 
#define QM_REG_PAUSESTATE5   0x16e690
 
#define QM_REG_PAUSESTATE6   0x16e694
 
#define QM_REG_PAUSESTATE7   0x16e698
 
#define QM_REG_PCIREQAT   0x168054
 
#define QM_REG_PF_EN   0x16e70c
 
#define QM_REG_PF_USG_CNT_0   0x16e040
 
#define QM_REG_PORT0BYTECRD   0x168300
 
#define QM_REG_PORT1BYTECRD   0x168304
 
#define QM_REG_PQ2PCIFUNC_0   0x16e6bc
 
#define QM_REG_PQ2PCIFUNC_1   0x16e6c0
 
#define QM_REG_PQ2PCIFUNC_2   0x16e6c4
 
#define QM_REG_PQ2PCIFUNC_3   0x16e6c8
 
#define QM_REG_PQ2PCIFUNC_4   0x16e6cc
 
#define QM_REG_PQ2PCIFUNC_5   0x16e6d0
 
#define QM_REG_PQ2PCIFUNC_6   0x16e6d4
 
#define QM_REG_PQ2PCIFUNC_7   0x16e6d8
 
#define QM_REG_PTRTBL   0x168a00
 
#define QM_REG_PTRTBL_EXT_A   0x16e200
 
#define QM_REG_QM_INT_MASK   0x168444
 
#define QM_REG_QM_INT_STS   0x168438
 
#define QM_REG_QM_PRTY_MASK   0x168454
 
#define QM_REG_QM_PRTY_STS   0x168448
 
#define QM_REG_QM_PRTY_STS_CLR   0x16844c
 
#define QM_REG_QSTATUS_HIGH   0x16802c
 
#define QM_REG_QSTATUS_HIGH_EXT_A   0x16e408
 
#define QM_REG_QSTATUS_LOW   0x168028
 
#define QM_REG_QSTATUS_LOW_EXT_A   0x16e404
 
#define QM_REG_QTASKCTR_0   0x168308
 
#define QM_REG_QTASKCTR_EXT_A_0   0x16e584
 
#define QM_REG_QVOQIDX_0   0x1680f4
 
#define QM_REG_QVOQIDX_10   0x16811c
 
#define QM_REG_QVOQIDX_100   0x16e49c
 
#define QM_REG_QVOQIDX_101   0x16e4a0
 
#define QM_REG_QVOQIDX_102   0x16e4a4
 
#define QM_REG_QVOQIDX_103   0x16e4a8
 
#define QM_REG_QVOQIDX_104   0x16e4ac
 
#define QM_REG_QVOQIDX_105   0x16e4b0
 
#define QM_REG_QVOQIDX_106   0x16e4b4
 
#define QM_REG_QVOQIDX_107   0x16e4b8
 
#define QM_REG_QVOQIDX_108   0x16e4bc
 
#define QM_REG_QVOQIDX_109   0x16e4c0
 
#define QM_REG_QVOQIDX_11   0x168120
 
#define QM_REG_QVOQIDX_110   0x16e4c4
 
#define QM_REG_QVOQIDX_111   0x16e4c8
 
#define QM_REG_QVOQIDX_112   0x16e4cc
 
#define QM_REG_QVOQIDX_113   0x16e4d0
 
#define QM_REG_QVOQIDX_114   0x16e4d4
 
#define QM_REG_QVOQIDX_115   0x16e4d8
 
#define QM_REG_QVOQIDX_116   0x16e4dc
 
#define QM_REG_QVOQIDX_117   0x16e4e0
 
#define QM_REG_QVOQIDX_118   0x16e4e4
 
#define QM_REG_QVOQIDX_119   0x16e4e8
 
#define QM_REG_QVOQIDX_12   0x168124
 
#define QM_REG_QVOQIDX_120   0x16e4ec
 
#define QM_REG_QVOQIDX_121   0x16e4f0
 
#define QM_REG_QVOQIDX_122   0x16e4f4
 
#define QM_REG_QVOQIDX_123   0x16e4f8
 
#define QM_REG_QVOQIDX_124   0x16e4fc
 
#define QM_REG_QVOQIDX_125   0x16e500
 
#define QM_REG_QVOQIDX_126   0x16e504
 
#define QM_REG_QVOQIDX_127   0x16e508
 
#define QM_REG_QVOQIDX_13   0x168128
 
#define QM_REG_QVOQIDX_14   0x16812c
 
#define QM_REG_QVOQIDX_15   0x168130
 
#define QM_REG_QVOQIDX_16   0x168134
 
#define QM_REG_QVOQIDX_17   0x168138
 
#define QM_REG_QVOQIDX_21   0x168148
 
#define QM_REG_QVOQIDX_22   0x16814c
 
#define QM_REG_QVOQIDX_23   0x168150
 
#define QM_REG_QVOQIDX_24   0x168154
 
#define QM_REG_QVOQIDX_25   0x168158
 
#define QM_REG_QVOQIDX_26   0x16815c
 
#define QM_REG_QVOQIDX_27   0x168160
 
#define QM_REG_QVOQIDX_28   0x168164
 
#define QM_REG_QVOQIDX_29   0x168168
 
#define QM_REG_QVOQIDX_30   0x16816c
 
#define QM_REG_QVOQIDX_31   0x168170
 
#define QM_REG_QVOQIDX_32   0x168174
 
#define QM_REG_QVOQIDX_33   0x168178
 
#define QM_REG_QVOQIDX_34   0x16817c
 
#define QM_REG_QVOQIDX_35   0x168180
 
#define QM_REG_QVOQIDX_36   0x168184
 
#define QM_REG_QVOQIDX_37   0x168188
 
#define QM_REG_QVOQIDX_38   0x16818c
 
#define QM_REG_QVOQIDX_39   0x168190
 
#define QM_REG_QVOQIDX_40   0x168194
 
#define QM_REG_QVOQIDX_41   0x168198
 
#define QM_REG_QVOQIDX_42   0x16819c
 
#define QM_REG_QVOQIDX_43   0x1681a0
 
#define QM_REG_QVOQIDX_44   0x1681a4
 
#define QM_REG_QVOQIDX_45   0x1681a8
 
#define QM_REG_QVOQIDX_46   0x1681ac
 
#define QM_REG_QVOQIDX_47   0x1681b0
 
#define QM_REG_QVOQIDX_48   0x1681b4
 
#define QM_REG_QVOQIDX_49   0x1681b8
 
#define QM_REG_QVOQIDX_5   0x168108
 
#define QM_REG_QVOQIDX_50   0x1681bc
 
#define QM_REG_QVOQIDX_51   0x1681c0
 
#define QM_REG_QVOQIDX_52   0x1681c4
 
#define QM_REG_QVOQIDX_53   0x1681c8
 
#define QM_REG_QVOQIDX_54   0x1681cc
 
#define QM_REG_QVOQIDX_55   0x1681d0
 
#define QM_REG_QVOQIDX_56   0x1681d4
 
#define QM_REG_QVOQIDX_57   0x1681d8
 
#define QM_REG_QVOQIDX_58   0x1681dc
 
#define QM_REG_QVOQIDX_59   0x1681e0
 
#define QM_REG_QVOQIDX_6   0x16810c
 
#define QM_REG_QVOQIDX_60   0x1681e4
 
#define QM_REG_QVOQIDX_61   0x1681e8
 
#define QM_REG_QVOQIDX_62   0x1681ec
 
#define QM_REG_QVOQIDX_63   0x1681f0
 
#define QM_REG_QVOQIDX_64   0x16e40c
 
#define QM_REG_QVOQIDX_65   0x16e410
 
#define QM_REG_QVOQIDX_69   0x16e420
 
#define QM_REG_QVOQIDX_7   0x168110
 
#define QM_REG_QVOQIDX_70   0x16e424
 
#define QM_REG_QVOQIDX_71   0x16e428
 
#define QM_REG_QVOQIDX_72   0x16e42c
 
#define QM_REG_QVOQIDX_73   0x16e430
 
#define QM_REG_QVOQIDX_74   0x16e434
 
#define QM_REG_QVOQIDX_75   0x16e438
 
#define QM_REG_QVOQIDX_76   0x16e43c
 
#define QM_REG_QVOQIDX_77   0x16e440
 
#define QM_REG_QVOQIDX_78   0x16e444
 
#define QM_REG_QVOQIDX_79   0x16e448
 
#define QM_REG_QVOQIDX_8   0x168114
 
#define QM_REG_QVOQIDX_80   0x16e44c
 
#define QM_REG_QVOQIDX_81   0x16e450
 
#define QM_REG_QVOQIDX_85   0x16e460
 
#define QM_REG_QVOQIDX_86   0x16e464
 
#define QM_REG_QVOQIDX_87   0x16e468
 
#define QM_REG_QVOQIDX_88   0x16e46c
 
#define QM_REG_QVOQIDX_89   0x16e470
 
#define QM_REG_QVOQIDX_9   0x168118
 
#define QM_REG_QVOQIDX_90   0x16e474
 
#define QM_REG_QVOQIDX_91   0x16e478
 
#define QM_REG_QVOQIDX_92   0x16e47c
 
#define QM_REG_QVOQIDX_93   0x16e480
 
#define QM_REG_QVOQIDX_94   0x16e484
 
#define QM_REG_QVOQIDX_95   0x16e488
 
#define QM_REG_QVOQIDX_96   0x16e48c
 
#define QM_REG_QVOQIDX_97   0x16e490
 
#define QM_REG_QVOQIDX_98   0x16e494
 
#define QM_REG_QVOQIDX_99   0x16e498
 
#define QM_REG_SOFT_RESET   0x168428
 
#define QM_REG_TASKCRDCOST_0   0x16809c
 
#define QM_REG_TASKCRDCOST_1   0x1680a0
 
#define QM_REG_TASKCRDCOST_2   0x1680a4
 
#define QM_REG_TASKCRDCOST_4   0x1680ac
 
#define QM_REG_TASKCRDCOST_5   0x1680b0
 
#define QM_REG_TQM_WRC_FIFOLVL   0x168010
 
#define QM_REG_UQM_WRC_FIFOLVL   0x168008
 
#define QM_REG_VOQCRDERRREG   0x168408
 
#define QM_REG_VOQCREDIT_0   0x1682d0
 
#define QM_REG_VOQCREDIT_1   0x1682d4
 
#define QM_REG_VOQCREDIT_4   0x1682e0
 
#define QM_REG_VOQCREDITAFULLTHR   0x168090
 
#define QM_REG_VOQINITCREDIT_0   0x168060
 
#define QM_REG_VOQINITCREDIT_1   0x168064
 
#define QM_REG_VOQINITCREDIT_2   0x168068
 
#define QM_REG_VOQINITCREDIT_4   0x168070
 
#define QM_REG_VOQINITCREDIT_5   0x168074
 
#define QM_REG_VOQPORT_0   0x1682a0
 
#define QM_REG_VOQPORT_1   0x1682a4
 
#define QM_REG_VOQPORT_2   0x1682a8
 
#define QM_REG_VOQQMASK_0_LSB   0x168240
 
#define QM_REG_VOQQMASK_0_LSB_EXT_A   0x16e524
 
#define QM_REG_VOQQMASK_0_MSB   0x168244
 
#define QM_REG_VOQQMASK_0_MSB_EXT_A   0x16e528
 
#define QM_REG_VOQQMASK_10_LSB   0x168290
 
#define QM_REG_VOQQMASK_10_LSB_EXT_A   0x16e574
 
#define QM_REG_VOQQMASK_10_MSB   0x168294
 
#define QM_REG_VOQQMASK_10_MSB_EXT_A   0x16e578
 
#define QM_REG_VOQQMASK_11_LSB   0x168298
 
#define QM_REG_VOQQMASK_11_LSB_EXT_A   0x16e57c
 
#define QM_REG_VOQQMASK_11_MSB   0x16829c
 
#define QM_REG_VOQQMASK_11_MSB_EXT_A   0x16e580
 
#define QM_REG_VOQQMASK_1_LSB   0x168248
 
#define QM_REG_VOQQMASK_1_LSB_EXT_A   0x16e52c
 
#define QM_REG_VOQQMASK_1_MSB   0x16824c
 
#define QM_REG_VOQQMASK_1_MSB_EXT_A   0x16e530
 
#define QM_REG_VOQQMASK_2_LSB   0x168250
 
#define QM_REG_VOQQMASK_2_LSB_EXT_A   0x16e534
 
#define QM_REG_VOQQMASK_2_MSB   0x168254
 
#define QM_REG_VOQQMASK_2_MSB_EXT_A   0x16e538
 
#define QM_REG_VOQQMASK_3_LSB   0x168258
 
#define QM_REG_VOQQMASK_3_LSB_EXT_A   0x16e53c
 
#define QM_REG_VOQQMASK_3_MSB_EXT_A   0x16e540
 
#define QM_REG_VOQQMASK_4_LSB   0x168260
 
#define QM_REG_VOQQMASK_4_LSB_EXT_A   0x16e544
 
#define QM_REG_VOQQMASK_4_MSB   0x168264
 
#define QM_REG_VOQQMASK_4_MSB_EXT_A   0x16e548
 
#define QM_REG_VOQQMASK_5_LSB   0x168268
 
#define QM_REG_VOQQMASK_5_LSB_EXT_A   0x16e54c
 
#define QM_REG_VOQQMASK_5_MSB   0x16826c
 
#define QM_REG_VOQQMASK_5_MSB_EXT_A   0x16e550
 
#define QM_REG_VOQQMASK_6_LSB   0x168270
 
#define QM_REG_VOQQMASK_6_LSB_EXT_A   0x16e554
 
#define QM_REG_VOQQMASK_6_MSB   0x168274
 
#define QM_REG_VOQQMASK_6_MSB_EXT_A   0x16e558
 
#define QM_REG_VOQQMASK_7_LSB   0x168278
 
#define QM_REG_VOQQMASK_7_LSB_EXT_A   0x16e55c
 
#define QM_REG_VOQQMASK_7_MSB   0x16827c
 
#define QM_REG_VOQQMASK_7_MSB_EXT_A   0x16e560
 
#define QM_REG_VOQQMASK_8_LSB   0x168280
 
#define QM_REG_VOQQMASK_8_LSB_EXT_A   0x16e564
 
#define QM_REG_VOQQMASK_8_MSB   0x168284
 
#define QM_REG_VOQQMASK_8_MSB_EXT_A   0x16e568
 
#define QM_REG_VOQQMASK_9_LSB   0x168288
 
#define QM_REG_VOQQMASK_9_LSB_EXT_A   0x16e56c
 
#define QM_REG_VOQQMASK_9_MSB_EXT_A   0x16e570
 
#define QM_REG_WRRWEIGHTS_0   0x16880c
 
#define QM_REG_WRRWEIGHTS_1   0x168810
 
#define QM_REG_WRRWEIGHTS_10   0x168814
 
#define QM_REG_WRRWEIGHTS_11   0x168818
 
#define QM_REG_WRRWEIGHTS_12   0x16881c
 
#define QM_REG_WRRWEIGHTS_13   0x168820
 
#define QM_REG_WRRWEIGHTS_14   0x168824
 
#define QM_REG_WRRWEIGHTS_15   0x168828
 
#define QM_REG_WRRWEIGHTS_16   0x16e000
 
#define QM_REG_WRRWEIGHTS_17   0x16e004
 
#define QM_REG_WRRWEIGHTS_18   0x16e008
 
#define QM_REG_WRRWEIGHTS_19   0x16e00c
 
#define QM_REG_WRRWEIGHTS_2   0x16882c
 
#define QM_REG_WRRWEIGHTS_20   0x16e010
 
#define QM_REG_WRRWEIGHTS_21   0x16e014
 
#define QM_REG_WRRWEIGHTS_22   0x16e018
 
#define QM_REG_WRRWEIGHTS_23   0x16e01c
 
#define QM_REG_WRRWEIGHTS_24   0x16e020
 
#define QM_REG_WRRWEIGHTS_25   0x16e024
 
#define QM_REG_WRRWEIGHTS_26   0x16e028
 
#define QM_REG_WRRWEIGHTS_27   0x16e02c
 
#define QM_REG_WRRWEIGHTS_28   0x16e030
 
#define QM_REG_WRRWEIGHTS_29   0x16e034
 
#define QM_REG_WRRWEIGHTS_3   0x168830
 
#define QM_REG_WRRWEIGHTS_30   0x16e038
 
#define QM_REG_WRRWEIGHTS_31   0x16e03c
 
#define QM_REG_WRRWEIGHTS_4   0x168834
 
#define QM_REG_WRRWEIGHTS_5   0x168838
 
#define QM_REG_WRRWEIGHTS_6   0x16883c
 
#define QM_REG_WRRWEIGHTS_7   0x168840
 
#define QM_REG_WRRWEIGHTS_8   0x168844
 
#define QM_REG_WRRWEIGHTS_9   0x168848
 
#define QM_REG_XQM_WRC_FIFOLVL   0x168000
 
#define SEM_FAST_REG_PARITY_RST   0x18840
 
#define SRC_REG_COUNTFREE0   0x40500
 
#define SRC_REG_E1HMF_ENABLE   0x404cc
 
#define SRC_REG_FIRSTFREE0   0x40510
 
#define SRC_REG_KEYRSS0_0   0x40408
 
#define SRC_REG_KEYRSS0_7   0x40424
 
#define SRC_REG_KEYRSS1_9   0x40454
 
#define SRC_REG_KEYSEARCH_0   0x40458
 
#define SRC_REG_KEYSEARCH_1   0x4045c
 
#define SRC_REG_KEYSEARCH_2   0x40460
 
#define SRC_REG_KEYSEARCH_3   0x40464
 
#define SRC_REG_KEYSEARCH_4   0x40468
 
#define SRC_REG_KEYSEARCH_5   0x4046c
 
#define SRC_REG_KEYSEARCH_6   0x40470
 
#define SRC_REG_KEYSEARCH_7   0x40474
 
#define SRC_REG_KEYSEARCH_8   0x40478
 
#define SRC_REG_KEYSEARCH_9   0x4047c
 
#define SRC_REG_LASTFREE0   0x40530
 
#define SRC_REG_NUMBER_HASH_BITS0   0x40400
 
#define SRC_REG_SOFT_RST   0x4049c
 
#define SRC_REG_SRC_INT_STS   0x404ac
 
#define SRC_REG_SRC_PRTY_MASK   0x404c8
 
#define SRC_REG_SRC_PRTY_STS   0x404bc
 
#define SRC_REG_SRC_PRTY_STS_CLR   0x404c0
 
#define TCM_REG_CAM_OCCUP   0x5017c
 
#define TCM_REG_CDU_AG_RD_IFEN   0x50034
 
#define TCM_REG_CDU_AG_WR_IFEN   0x50030
 
#define TCM_REG_CDU_SM_RD_IFEN   0x5003c
 
#define TCM_REG_CDU_SM_WR_IFEN   0x50038
 
#define TCM_REG_CFC_INIT_CRD   0x50204
 
#define TCM_REG_CP_WEIGHT   0x500c0
 
#define TCM_REG_CSEM_IFEN   0x5002c
 
#define TCM_REG_CSEM_LENGTH_MIS   0x50174
 
#define TCM_REG_CSEM_WEIGHT   0x500bc
 
#define TCM_REG_ERR_EVNT_ID   0x500a0
 
#define TCM_REG_ERR_TCM_HDR   0x5009c
 
#define TCM_REG_EXPR_EVNT_ID   0x500a4
 
#define TCM_REG_FIC0_INIT_CRD   0x5020c
 
#define TCM_REG_FIC1_INIT_CRD   0x50210
 
#define TCM_REG_GR_ARB_TYPE   0x50114
 
#define TCM_REG_GR_LD0_PR   0x5011c
 
#define TCM_REG_GR_LD1_PR   0x50120
 
#define TCM_REG_N_SM_CTX_LD_0   0x50050
 
#define TCM_REG_N_SM_CTX_LD_1   0x50054
 
#define TCM_REG_N_SM_CTX_LD_2   0x50058
 
#define TCM_REG_N_SM_CTX_LD_3   0x5005c
 
#define TCM_REG_N_SM_CTX_LD_4   0x50060
 
#define TCM_REG_N_SM_CTX_LD_5   0x50064
 
#define TCM_REG_PBF_IFEN   0x50024
 
#define TCM_REG_PBF_LENGTH_MIS   0x5016c
 
#define TCM_REG_PBF_WEIGHT   0x500b4
 
#define TCM_REG_PHYS_QNUM0_0   0x500e0
 
#define TCM_REG_PHYS_QNUM0_1   0x500e4
 
#define TCM_REG_PHYS_QNUM1_0   0x500e8
 
#define TCM_REG_PHYS_QNUM1_1   0x500ec
 
#define TCM_REG_PHYS_QNUM2_0   0x500f0
 
#define TCM_REG_PHYS_QNUM2_1   0x500f4
 
#define TCM_REG_PHYS_QNUM3_0   0x500f8
 
#define TCM_REG_PHYS_QNUM3_1   0x500fc
 
#define TCM_REG_PRS_IFEN   0x50020
 
#define TCM_REG_PRS_LENGTH_MIS   0x50168
 
#define TCM_REG_PRS_WEIGHT   0x500b0
 
#define TCM_REG_STOP_EVNT_ID   0x500a8
 
#define TCM_REG_STORM_LENGTH_MIS   0x50160
 
#define TCM_REG_STORM_TCM_IFEN   0x50010
 
#define TCM_REG_STORM_WEIGHT   0x500ac
 
#define TCM_REG_TCM_CFC_IFEN   0x50040
 
#define TCM_REG_TCM_INT_MASK   0x501dc
 
#define TCM_REG_TCM_INT_STS   0x501d0
 
#define TCM_REG_TCM_PRTY_MASK   0x501ec
 
#define TCM_REG_TCM_PRTY_STS   0x501e0
 
#define TCM_REG_TCM_PRTY_STS_CLR   0x501e4
 
#define TCM_REG_TCM_REG0_SZ   0x500d8
 
#define TCM_REG_TCM_STORM0_IFEN   0x50004
 
#define TCM_REG_TCM_STORM1_IFEN   0x50008
 
#define TCM_REG_TCM_TQM_IFEN   0x5000c
 
#define TCM_REG_TCM_TQM_USE_Q   0x500d4
 
#define TCM_REG_TM_TCM_HDR   0x50098
 
#define TCM_REG_TM_TCM_IFEN   0x5001c
 
#define TCM_REG_TM_WEIGHT   0x500d0
 
#define TCM_REG_TQM_INIT_CRD   0x5021c
 
#define TCM_REG_TQM_P_WEIGHT   0x500c8
 
#define TCM_REG_TQM_S_WEIGHT   0x500cc
 
#define TCM_REG_TQM_TCM_HDR_P   0x50090
 
#define TCM_REG_TQM_TCM_HDR_S   0x50094
 
#define TCM_REG_TQM_TCM_IFEN   0x50014
 
#define TCM_REG_TSDM_IFEN   0x50018
 
#define TCM_REG_TSDM_LENGTH_MIS   0x50164
 
#define TCM_REG_TSDM_WEIGHT   0x500c4
 
#define TCM_REG_USEM_IFEN   0x50028
 
#define TCM_REG_USEM_LENGTH_MIS   0x50170
 
#define TCM_REG_USEM_WEIGHT   0x500b8
 
#define TCM_REG_XX_DESCR_TABLE   0x50280
 
#define TCM_REG_XX_DESCR_TABLE_SIZE   29
 
#define TCM_REG_XX_FREE   0x50178
 
#define TCM_REG_XX_INIT_CRD   0x50220
 
#define TCM_REG_XX_MAX_LL_SZ   0x50044
 
#define TCM_REG_XX_MSG_NUM   0x50224
 
#define TCM_REG_XX_OVFL_EVNT_ID   0x50048
 
#define TCM_REG_XX_TABLE   0x50240
 
#define TM_REG_CFC_AC_CRDCNT_VAL   0x164208
 
#define TM_REG_CFC_CLD_CRDCNT_VAL   0x164210
 
#define TM_REG_CL0_CONT_REGION   0x164030
 
#define TM_REG_CL1_CONT_REGION   0x164034
 
#define TM_REG_CL2_CONT_REGION   0x164038
 
#define TM_REG_CLIN_PRIOR0_CLIENT   0x164024
 
#define TM_REG_CLOUT_CRDCNT0_VAL   0x164220
 
#define TM_REG_CLOUT_CRDCNT1_VAL   0x164228
 
#define TM_REG_CLOUT_CRDCNT2_VAL   0x164230
 
#define TM_REG_EN_CL0_INPUT   0x164008
 
#define TM_REG_EN_CL1_INPUT   0x16400c
 
#define TM_REG_EN_CL2_INPUT   0x164010
 
#define TM_REG_EN_LINEAR0_TIMER   0x164014
 
#define TM_REG_EN_REAL_TIME_CNT   0x1640d8
 
#define TM_REG_EN_TIMERS   0x164000
 
#define TM_REG_EXP_CRDCNT_VAL   0x164238
 
#define TM_REG_LIN0_LOGIC_ADDR   0x164240
 
#define TM_REG_LIN0_MAX_ACTIVE_CID   0x164048
 
#define TM_REG_LIN0_NUM_SCANS   0x1640a0
 
#define TM_REG_LIN0_PHY_ADDR   0x164270
 
#define TM_REG_LIN0_PHY_ADDR_VALID   0x164248
 
#define TM_REG_LIN0_SCAN_ON   0x1640d0
 
#define TM_REG_LIN0_SCAN_TIME   0x16403c
 
#define TM_REG_LIN0_VNIC_UC   0x164128
 
#define TM_REG_LIN1_LOGIC_ADDR   0x164250
 
#define TM_REG_LIN1_PHY_ADDR   0x164280
 
#define TM_REG_LIN1_PHY_ADDR_VALID   0x164258
 
#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR   0x164070
 
#define TM_REG_PCIARB_CRDCNT_VAL   0x164260
 
#define TM_REG_TIMER_TICK_SIZE   0x16401c
 
#define TM_REG_TM_CONTEXT_REGION   0x164044
 
#define TM_REG_TM_INT_MASK   0x1640fc
 
#define TM_REG_TM_INT_STS   0x1640f0
 
#define TM_REG_TM_PRTY_MASK   0x16410c
 
#define TM_REG_TM_PRTY_STS_CLR   0x164104
 
#define TSDM_REG_AGG_INT_EVENT_0   0x42038
 
#define TSDM_REG_AGG_INT_EVENT_1   0x4203c
 
#define TSDM_REG_AGG_INT_EVENT_2   0x42040
 
#define TSDM_REG_AGG_INT_EVENT_3   0x42044
 
#define TSDM_REG_AGG_INT_EVENT_4   0x42048
 
#define TSDM_REG_AGG_INT_T_0   0x420b8
 
#define TSDM_REG_AGG_INT_T_1   0x420bc
 
#define TSDM_REG_CFC_RSP_START_ADDR   0x42008
 
#define TSDM_REG_CMP_COUNTER_MAX0   0x4201c
 
#define TSDM_REG_CMP_COUNTER_MAX1   0x42020
 
#define TSDM_REG_CMP_COUNTER_MAX2   0x42024
 
#define TSDM_REG_CMP_COUNTER_MAX3   0x42028
 
#define TSDM_REG_CMP_COUNTER_START_ADDR   0x4200c
 
#define TSDM_REG_ENABLE_IN1   0x42238
 
#define TSDM_REG_ENABLE_IN2   0x4223c
 
#define TSDM_REG_ENABLE_OUT1   0x42240
 
#define TSDM_REG_ENABLE_OUT2   0x42244
 
#define TSDM_REG_INIT_CREDIT_PXP_CTRL   0x424bc
 
#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE   0x4227c
 
#define TSDM_REG_NUM_OF_PKT_END_MSG   0x42274
 
#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ   0x42278
 
#define TSDM_REG_NUM_OF_Q0_CMD   0x42248
 
#define TSDM_REG_NUM_OF_Q10_CMD   0x4226c
 
#define TSDM_REG_NUM_OF_Q11_CMD   0x42270
 
#define TSDM_REG_NUM_OF_Q1_CMD   0x4224c
 
#define TSDM_REG_NUM_OF_Q3_CMD   0x42250
 
#define TSDM_REG_NUM_OF_Q4_CMD   0x42254
 
#define TSDM_REG_NUM_OF_Q5_CMD   0x42258
 
#define TSDM_REG_NUM_OF_Q6_CMD   0x4225c
 
#define TSDM_REG_NUM_OF_Q7_CMD   0x42260
 
#define TSDM_REG_NUM_OF_Q8_CMD   0x42264
 
#define TSDM_REG_NUM_OF_Q9_CMD   0x42268
 
#define TSDM_REG_PCK_END_MSG_START_ADDR   0x42014
 
#define TSDM_REG_Q_COUNTER_START_ADDR   0x42010
 
#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0x42548
 
#define TSDM_REG_SYNC_PARSER_EMPTY   0x42550
 
#define TSDM_REG_SYNC_SYNC_EMPTY   0x42558
 
#define TSDM_REG_TIMER_TICK   0x42000
 
#define TSDM_REG_TSDM_INT_MASK_0   0x4229c
 
#define TSDM_REG_TSDM_INT_MASK_1   0x422ac
 
#define TSDM_REG_TSDM_INT_STS_0   0x42290
 
#define TSDM_REG_TSDM_INT_STS_1   0x422a0
 
#define TSDM_REG_TSDM_PRTY_MASK   0x422bc
 
#define TSDM_REG_TSDM_PRTY_STS   0x422b0
 
#define TSDM_REG_TSDM_PRTY_STS_CLR   0x422b4
 
#define TSEM_REG_ARB_CYCLE_SIZE   0x180034
 
#define TSEM_REG_ARB_ELEMENT0   0x180020
 
#define TSEM_REG_ARB_ELEMENT1   0x180024
 
#define TSEM_REG_ARB_ELEMENT2   0x180028
 
#define TSEM_REG_ARB_ELEMENT3   0x18002c
 
#define TSEM_REG_ARB_ELEMENT4   0x180030
 
#define TSEM_REG_ENABLE_IN   0x1800a4
 
#define TSEM_REG_ENABLE_OUT   0x1800a8
 
#define TSEM_REG_FAST_MEMORY   0x1a0000
 
#define TSEM_REG_FIC0_DISABLE   0x180224
 
#define TSEM_REG_FIC1_DISABLE   0x180234
 
#define TSEM_REG_INT_TABLE   0x180400
 
#define TSEM_REG_MSG_NUM_FIC0   0x180000
 
#define TSEM_REG_MSG_NUM_FIC1   0x180004
 
#define TSEM_REG_MSG_NUM_FOC0   0x180008
 
#define TSEM_REG_MSG_NUM_FOC1   0x18000c
 
#define TSEM_REG_MSG_NUM_FOC2   0x180010
 
#define TSEM_REG_MSG_NUM_FOC3   0x180014
 
#define TSEM_REG_PAS_DISABLE   0x18024c
 
#define TSEM_REG_PASSIVE_BUFFER   0x181000
 
#define TSEM_REG_PRAM   0x1c0000
 
#define TSEM_REG_SLEEP_THREADS_VALID   0x18026c
 
#define TSEM_REG_SLOW_EXT_STORE_EMPTY   0x1802a0
 
#define TSEM_REG_THREADS_LIST   0x1802e4
 
#define TSEM_REG_TSEM_PRTY_STS_CLR_0   0x180118
 
#define TSEM_REG_TSEM_PRTY_STS_CLR_1   0x180128
 
#define TSEM_REG_TS_0_AS   0x180038
 
#define TSEM_REG_TS_10_AS   0x180060
 
#define TSEM_REG_TS_11_AS   0x180064
 
#define TSEM_REG_TS_12_AS   0x180068
 
#define TSEM_REG_TS_13_AS   0x18006c
 
#define TSEM_REG_TS_14_AS   0x180070
 
#define TSEM_REG_TS_15_AS   0x180074
 
#define TSEM_REG_TS_16_AS   0x180078
 
#define TSEM_REG_TS_17_AS   0x18007c
 
#define TSEM_REG_TS_18_AS   0x180080
 
#define TSEM_REG_TS_1_AS   0x18003c
 
#define TSEM_REG_TS_2_AS   0x180040
 
#define TSEM_REG_TS_3_AS   0x180044
 
#define TSEM_REG_TS_4_AS   0x180048
 
#define TSEM_REG_TS_5_AS   0x18004c
 
#define TSEM_REG_TS_6_AS   0x180050
 
#define TSEM_REG_TS_7_AS   0x180054
 
#define TSEM_REG_TS_8_AS   0x180058
 
#define TSEM_REG_TS_9_AS   0x18005c
 
#define TSEM_REG_TSEM_INT_MASK_0   0x180100
 
#define TSEM_REG_TSEM_INT_MASK_1   0x180110
 
#define TSEM_REG_TSEM_INT_STS_0   0x1800f4
 
#define TSEM_REG_TSEM_INT_STS_1   0x180104
 
#define TSEM_REG_TSEM_PRTY_MASK_0   0x180120
 
#define TSEM_REG_TSEM_PRTY_MASK_1   0x180130
 
#define TSEM_REG_TSEM_PRTY_STS_0   0x180114
 
#define TSEM_REG_TSEM_PRTY_STS_1   0x180124
 
#define TSEM_REG_VFPF_ERR_NUM   0x180380
 
#define UCM_REG_AG_CTX   0xe2000
 
#define UCM_REG_CAM_OCCUP   0xe0170
 
#define UCM_REG_CDU_AG_RD_IFEN   0xe0038
 
#define UCM_REG_CDU_AG_WR_IFEN   0xe0034
 
#define UCM_REG_CDU_SM_RD_IFEN   0xe0040
 
#define UCM_REG_CDU_SM_WR_IFEN   0xe003c
 
#define UCM_REG_CFC_INIT_CRD   0xe0204
 
#define UCM_REG_CP_WEIGHT   0xe00c4
 
#define UCM_REG_CSEM_IFEN   0xe0028
 
#define UCM_REG_CSEM_LENGTH_MIS   0xe0160
 
#define UCM_REG_CSEM_WEIGHT   0xe00b8
 
#define UCM_REG_DORQ_IFEN   0xe0030
 
#define UCM_REG_DORQ_LENGTH_MIS   0xe0168
 
#define UCM_REG_DORQ_WEIGHT   0xe00c0
 
#define UCM_REG_ERR_EVNT_ID   0xe00a4
 
#define UCM_REG_ERR_UCM_HDR   0xe00a0
 
#define UCM_REG_EXPR_EVNT_ID   0xe00a8
 
#define UCM_REG_FIC0_INIT_CRD   0xe020c
 
#define UCM_REG_FIC1_INIT_CRD   0xe0210
 
#define UCM_REG_GR_ARB_TYPE   0xe0144
 
#define UCM_REG_GR_LD0_PR   0xe014c
 
#define UCM_REG_GR_LD1_PR   0xe0150
 
#define UCM_REG_INV_CFLG_Q   0xe00e4
 
#define UCM_REG_N_SM_CTX_LD_0   0xe0054
 
#define UCM_REG_N_SM_CTX_LD_1   0xe0058
 
#define UCM_REG_N_SM_CTX_LD_2   0xe005c
 
#define UCM_REG_N_SM_CTX_LD_3   0xe0060
 
#define UCM_REG_N_SM_CTX_LD_4   0xe0064
 
#define UCM_REG_N_SM_CTX_LD_5   0xe0068
 
#define UCM_REG_PHYS_QNUM0_0   0xe0110
 
#define UCM_REG_PHYS_QNUM0_1   0xe0114
 
#define UCM_REG_PHYS_QNUM1_0   0xe0118
 
#define UCM_REG_PHYS_QNUM1_1   0xe011c
 
#define UCM_REG_PHYS_QNUM2_0   0xe0120
 
#define UCM_REG_PHYS_QNUM2_1   0xe0124
 
#define UCM_REG_PHYS_QNUM3_0   0xe0128
 
#define UCM_REG_PHYS_QNUM3_1   0xe012c
 
#define UCM_REG_STOP_EVNT_ID   0xe00ac
 
#define UCM_REG_STORM_LENGTH_MIS   0xe0154
 
#define UCM_REG_STORM_UCM_IFEN   0xe0010
 
#define UCM_REG_STORM_WEIGHT   0xe00b0
 
#define UCM_REG_TM_INIT_CRD   0xe021c
 
#define UCM_REG_TM_UCM_HDR   0xe009c
 
#define UCM_REG_TM_UCM_IFEN   0xe001c
 
#define UCM_REG_TM_WEIGHT   0xe00d4
 
#define UCM_REG_TSEM_IFEN   0xe0024
 
#define UCM_REG_TSEM_LENGTH_MIS   0xe015c
 
#define UCM_REG_TSEM_WEIGHT   0xe00b4
 
#define UCM_REG_UCM_CFC_IFEN   0xe0044
 
#define UCM_REG_UCM_INT_MASK   0xe01d4
 
#define UCM_REG_UCM_INT_STS   0xe01c8
 
#define UCM_REG_UCM_PRTY_MASK   0xe01e4
 
#define UCM_REG_UCM_PRTY_STS   0xe01d8
 
#define UCM_REG_UCM_PRTY_STS_CLR   0xe01dc
 
#define UCM_REG_UCM_REG0_SZ   0xe00dc
 
#define UCM_REG_UCM_STORM0_IFEN   0xe0004
 
#define UCM_REG_UCM_STORM1_IFEN   0xe0008
 
#define UCM_REG_UCM_TM_IFEN   0xe0020
 
#define UCM_REG_UCM_UQM_IFEN   0xe000c
 
#define UCM_REG_UCM_UQM_USE_Q   0xe00d8
 
#define UCM_REG_UQM_INIT_CRD   0xe0220
 
#define UCM_REG_UQM_P_WEIGHT   0xe00cc
 
#define UCM_REG_UQM_S_WEIGHT   0xe00d0
 
#define UCM_REG_UQM_UCM_HDR_P   0xe0094
 
#define UCM_REG_UQM_UCM_HDR_S   0xe0098
 
#define UCM_REG_UQM_UCM_IFEN   0xe0014
 
#define UCM_REG_USDM_IFEN   0xe0018
 
#define UCM_REG_USDM_LENGTH_MIS   0xe0158
 
#define UCM_REG_USDM_WEIGHT   0xe00c8
 
#define UCM_REG_XSEM_IFEN   0xe002c
 
#define UCM_REG_XSEM_LENGTH_MIS   0xe0164
 
#define UCM_REG_XSEM_WEIGHT   0xe00bc
 
#define UCM_REG_XX_DESCR_TABLE   0xe0280
 
#define UCM_REG_XX_DESCR_TABLE_SIZE   27
 
#define UCM_REG_XX_FREE   0xe016c
 
#define UCM_REG_XX_INIT_CRD   0xe0224
 
#define UCM_REG_XX_MSG_NUM   0xe0228
 
#define UCM_REG_XX_OVFL_EVNT_ID   0xe004c
 
#define UCM_REG_XX_TABLE   0xe0300
 
#define UMAC_COMMAND_CONFIG_REG_HD_ENA   (0x1<<10)
 
#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE   (0x1<<28)
 
#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA   (0x1<<15)
 
#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK   (0x1<<24)
 
#define UMAC_COMMAND_CONFIG_REG_PAD_EN   (0x1<<5)
 
#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE   (0x1<<8)
 
#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN   (0x1<<4)
 
#define UMAC_COMMAND_CONFIG_REG_RX_ENA   (0x1<<1)
 
#define UMAC_COMMAND_CONFIG_REG_SW_RESET   (0x1<<13)
 
#define UMAC_COMMAND_CONFIG_REG_TX_ENA   (0x1<<0)
 
#define UMAC_REG_COMMAND_CONFIG   0x8
 
#define UMAC_REG_EEE_WAKE_TIMER   0x6c
 
#define UMAC_REG_MAC_ADDR0   0xc
 
#define UMAC_REG_MAC_ADDR1   0x10
 
#define UMAC_REG_MAXFR   0x14
 
#define UMAC_REG_UMAC_EEE_CTRL   0x64
 
#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN   (0x1<<3)
 
#define USDM_REG_AGG_INT_EVENT_0   0xc4038
 
#define USDM_REG_AGG_INT_EVENT_1   0xc403c
 
#define USDM_REG_AGG_INT_EVENT_2   0xc4040
 
#define USDM_REG_AGG_INT_EVENT_4   0xc4048
 
#define USDM_REG_AGG_INT_EVENT_5   0xc404c
 
#define USDM_REG_AGG_INT_EVENT_6   0xc4050
 
#define USDM_REG_AGG_INT_MODE_0   0xc41b8
 
#define USDM_REG_AGG_INT_MODE_1   0xc41bc
 
#define USDM_REG_AGG_INT_MODE_4   0xc41c8
 
#define USDM_REG_AGG_INT_MODE_5   0xc41cc
 
#define USDM_REG_AGG_INT_MODE_6   0xc41d0
 
#define USDM_REG_AGG_INT_T_5   0xc40cc
 
#define USDM_REG_AGG_INT_T_6   0xc40d0
 
#define USDM_REG_CFC_RSP_START_ADDR   0xc4008
 
#define USDM_REG_CMP_COUNTER_MAX0   0xc401c
 
#define USDM_REG_CMP_COUNTER_MAX1   0xc4020
 
#define USDM_REG_CMP_COUNTER_MAX2   0xc4024
 
#define USDM_REG_CMP_COUNTER_MAX3   0xc4028
 
#define USDM_REG_CMP_COUNTER_START_ADDR   0xc400c
 
#define USDM_REG_ENABLE_IN1   0xc4238
 
#define USDM_REG_ENABLE_IN2   0xc423c
 
#define USDM_REG_ENABLE_OUT1   0xc4240
 
#define USDM_REG_ENABLE_OUT2   0xc4244
 
#define USDM_REG_INIT_CREDIT_PXP_CTRL   0xc44c0
 
#define USDM_REG_NUM_OF_ACK_AFTER_PLACE   0xc4280
 
#define USDM_REG_NUM_OF_PKT_END_MSG   0xc4278
 
#define USDM_REG_NUM_OF_PXP_ASYNC_REQ   0xc427c
 
#define USDM_REG_NUM_OF_Q0_CMD   0xc4248
 
#define USDM_REG_NUM_OF_Q10_CMD   0xc4270
 
#define USDM_REG_NUM_OF_Q11_CMD   0xc4274
 
#define USDM_REG_NUM_OF_Q1_CMD   0xc424c
 
#define USDM_REG_NUM_OF_Q2_CMD   0xc4250
 
#define USDM_REG_NUM_OF_Q3_CMD   0xc4254
 
#define USDM_REG_NUM_OF_Q4_CMD   0xc4258
 
#define USDM_REG_NUM_OF_Q5_CMD   0xc425c
 
#define USDM_REG_NUM_OF_Q6_CMD   0xc4260
 
#define USDM_REG_NUM_OF_Q7_CMD   0xc4264
 
#define USDM_REG_NUM_OF_Q8_CMD   0xc4268
 
#define USDM_REG_NUM_OF_Q9_CMD   0xc426c
 
#define USDM_REG_PCK_END_MSG_START_ADDR   0xc4014
 
#define USDM_REG_Q_COUNTER_START_ADDR   0xc4010
 
#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0xc4550
 
#define USDM_REG_SYNC_PARSER_EMPTY   0xc4558
 
#define USDM_REG_SYNC_SYNC_EMPTY   0xc4560
 
#define USDM_REG_TIMER_TICK   0xc4000
 
#define USDM_REG_USDM_INT_MASK_0   0xc42a0
 
#define USDM_REG_USDM_INT_MASK_1   0xc42b0
 
#define USDM_REG_USDM_INT_STS_0   0xc4294
 
#define USDM_REG_USDM_INT_STS_1   0xc42a4
 
#define USDM_REG_USDM_PRTY_MASK   0xc42c0
 
#define USDM_REG_USDM_PRTY_STS   0xc42b4
 
#define USDM_REG_USDM_PRTY_STS_CLR   0xc42b8
 
#define USEM_REG_ARB_CYCLE_SIZE   0x300034
 
#define USEM_REG_ARB_ELEMENT0   0x300020
 
#define USEM_REG_ARB_ELEMENT1   0x300024
 
#define USEM_REG_ARB_ELEMENT2   0x300028
 
#define USEM_REG_ARB_ELEMENT3   0x30002c
 
#define USEM_REG_ARB_ELEMENT4   0x300030
 
#define USEM_REG_ENABLE_IN   0x3000a4
 
#define USEM_REG_ENABLE_OUT   0x3000a8
 
#define USEM_REG_FAST_MEMORY   0x320000
 
#define USEM_REG_FIC0_DISABLE   0x300224
 
#define USEM_REG_FIC1_DISABLE   0x300234
 
#define USEM_REG_INT_TABLE   0x300400
 
#define USEM_REG_MSG_NUM_FIC0   0x300000
 
#define USEM_REG_MSG_NUM_FIC1   0x300004
 
#define USEM_REG_MSG_NUM_FOC0   0x300008
 
#define USEM_REG_MSG_NUM_FOC1   0x30000c
 
#define USEM_REG_MSG_NUM_FOC2   0x300010
 
#define USEM_REG_MSG_NUM_FOC3   0x300014
 
#define USEM_REG_PAS_DISABLE   0x30024c
 
#define USEM_REG_PASSIVE_BUFFER   0x302000
 
#define USEM_REG_PRAM   0x340000
 
#define USEM_REG_SLEEP_THREADS_VALID   0x30026c
 
#define USEM_REG_SLOW_EXT_STORE_EMPTY   0x3002a0
 
#define USEM_REG_THREADS_LIST   0x3002e4
 
#define USEM_REG_TS_0_AS   0x300038
 
#define USEM_REG_TS_10_AS   0x300060
 
#define USEM_REG_TS_11_AS   0x300064
 
#define USEM_REG_TS_12_AS   0x300068
 
#define USEM_REG_TS_13_AS   0x30006c
 
#define USEM_REG_TS_14_AS   0x300070
 
#define USEM_REG_TS_15_AS   0x300074
 
#define USEM_REG_TS_16_AS   0x300078
 
#define USEM_REG_TS_17_AS   0x30007c
 
#define USEM_REG_TS_18_AS   0x300080
 
#define USEM_REG_TS_1_AS   0x30003c
 
#define USEM_REG_TS_2_AS   0x300040
 
#define USEM_REG_TS_3_AS   0x300044
 
#define USEM_REG_TS_4_AS   0x300048
 
#define USEM_REG_TS_5_AS   0x30004c
 
#define USEM_REG_TS_6_AS   0x300050
 
#define USEM_REG_TS_7_AS   0x300054
 
#define USEM_REG_TS_8_AS   0x300058
 
#define USEM_REG_TS_9_AS   0x30005c
 
#define USEM_REG_USEM_INT_MASK_0   0x300110
 
#define USEM_REG_USEM_INT_MASK_1   0x300120
 
#define USEM_REG_USEM_INT_STS_0   0x300104
 
#define USEM_REG_USEM_INT_STS_1   0x300114
 
#define USEM_REG_USEM_PRTY_MASK_0   0x300130
 
#define USEM_REG_USEM_PRTY_MASK_1   0x300140
 
#define USEM_REG_USEM_PRTY_STS_0   0x300124
 
#define USEM_REG_USEM_PRTY_STS_1   0x300134
 
#define USEM_REG_USEM_PRTY_STS_CLR_0   0x300128
 
#define USEM_REG_USEM_PRTY_STS_CLR_1   0x300138
 
#define USEM_REG_VFPF_ERR_NUM   0x300380
 
#define VFC_MEMORIES_RST_REG_CAM_RST   (0x1<<0)
 
#define VFC_MEMORIES_RST_REG_RAM_RST   (0x1<<1)
 
#define VFC_REG_MEMORIES_RST   0x1943c
 
#define XCM_REG_AG_CTX   0x28000
 
#define XCM_REG_AUX1_Q   0x20134
 
#define XCM_REG_AUX_CNT_FLG_Q_19   0x201b0
 
#define XCM_REG_CAM_OCCUP   0x20244
 
#define XCM_REG_CDU_AG_RD_IFEN   0x20044
 
#define XCM_REG_CDU_AG_WR_IFEN   0x20040
 
#define XCM_REG_CDU_SM_RD_IFEN   0x2004c
 
#define XCM_REG_CDU_SM_WR_IFEN   0x20048
 
#define XCM_REG_CFC_INIT_CRD   0x20404
 
#define XCM_REG_CP_WEIGHT   0x200dc
 
#define XCM_REG_CSEM_IFEN   0x20028
 
#define XCM_REG_CSEM_LENGTH_MIS   0x20228
 
#define XCM_REG_CSEM_WEIGHT   0x200c4
 
#define XCM_REG_DORQ_IFEN   0x20030
 
#define XCM_REG_DORQ_LENGTH_MIS   0x20230
 
#define XCM_REG_DORQ_WEIGHT   0x200cc
 
#define XCM_REG_ERR_EVNT_ID   0x200b0
 
#define XCM_REG_ERR_XCM_HDR   0x200ac
 
#define XCM_REG_EXPR_EVNT_ID   0x200b4
 
#define XCM_REG_FIC0_INIT_CRD   0x2040c
 
#define XCM_REG_FIC1_INIT_CRD   0x20410
 
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0   0x20118
 
#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1   0x2011c
 
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0   0x20108
 
#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1   0x2010c
 
#define XCM_REG_GR_ARB_TYPE   0x2020c
 
#define XCM_REG_GR_LD0_PR   0x20214
 
#define XCM_REG_GR_LD1_PR   0x20218
 
#define XCM_REG_NIG0_IFEN   0x20038
 
#define XCM_REG_NIG0_LENGTH_MIS   0x20238
 
#define XCM_REG_NIG0_WEIGHT   0x200d4
 
#define XCM_REG_NIG1_IFEN   0x2003c
 
#define XCM_REG_NIG1_LENGTH_MIS   0x2023c
 
#define XCM_REG_N_SM_CTX_LD_0   0x20060
 
#define XCM_REG_N_SM_CTX_LD_1   0x20064
 
#define XCM_REG_N_SM_CTX_LD_2   0x20068
 
#define XCM_REG_N_SM_CTX_LD_3   0x2006c
 
#define XCM_REG_N_SM_CTX_LD_4   0x20070
 
#define XCM_REG_N_SM_CTX_LD_5   0x20074
 
#define XCM_REG_PBF_IFEN   0x20034
 
#define XCM_REG_PBF_LENGTH_MIS   0x20234
 
#define XCM_REG_PBF_WEIGHT   0x200d0
 
#define XCM_REG_PHYS_QNUM3_0   0x20100
 
#define XCM_REG_PHYS_QNUM3_1   0x20104
 
#define XCM_REG_STOP_EVNT_ID   0x200b8
 
#define XCM_REG_STORM_LENGTH_MIS   0x2021c
 
#define XCM_REG_STORM_WEIGHT   0x200bc
 
#define XCM_REG_STORM_XCM_IFEN   0x20010
 
#define XCM_REG_TM_INIT_CRD   0x2041c
 
#define XCM_REG_TM_WEIGHT   0x200ec
 
#define XCM_REG_TM_XCM_HDR   0x200a8
 
#define XCM_REG_TM_XCM_IFEN   0x2001c
 
#define XCM_REG_TSEM_IFEN   0x20024
 
#define XCM_REG_TSEM_LENGTH_MIS   0x20224
 
#define XCM_REG_TSEM_WEIGHT   0x200c0
 
#define XCM_REG_UNA_GT_NXT_Q   0x20120
 
#define XCM_REG_USEM_IFEN   0x2002c
 
#define XCM_REG_USEM_LENGTH_MIS   0x2022c
 
#define XCM_REG_USEM_WEIGHT   0x200c8
 
#define XCM_REG_WU_DA_CNT_CMD00   0x201d4
 
#define XCM_REG_WU_DA_CNT_CMD01   0x201d8
 
#define XCM_REG_WU_DA_CNT_CMD10   0x201dc
 
#define XCM_REG_WU_DA_CNT_CMD11   0x201e0
 
#define XCM_REG_WU_DA_CNT_UPD_VAL00   0x201e4
 
#define XCM_REG_WU_DA_CNT_UPD_VAL01   0x201e8
 
#define XCM_REG_WU_DA_CNT_UPD_VAL10   0x201ec
 
#define XCM_REG_WU_DA_CNT_UPD_VAL11   0x201f0
 
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00   0x201c4
 
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01   0x201c8
 
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10   0x201cc
 
#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11   0x201d0
 
#define XCM_REG_XCM_CFC_IFEN   0x20050
 
#define XCM_REG_XCM_INT_MASK   0x202b4
 
#define XCM_REG_XCM_INT_STS   0x202a8
 
#define XCM_REG_XCM_PRTY_MASK   0x202c4
 
#define XCM_REG_XCM_PRTY_STS   0x202b8
 
#define XCM_REG_XCM_PRTY_STS_CLR   0x202bc
 
#define XCM_REG_XCM_REG0_SZ   0x200f4
 
#define XCM_REG_XCM_STORM0_IFEN   0x20004
 
#define XCM_REG_XCM_STORM1_IFEN   0x20008
 
#define XCM_REG_XCM_TM_IFEN   0x20020
 
#define XCM_REG_XCM_XQM_IFEN   0x2000c
 
#define XCM_REG_XCM_XQM_USE_Q   0x200f0
 
#define XCM_REG_XQM_BYP_ACT_UPD   0x200fc
 
#define XCM_REG_XQM_INIT_CRD   0x20420
 
#define XCM_REG_XQM_P_WEIGHT   0x200e4
 
#define XCM_REG_XQM_S_WEIGHT   0x200e8
 
#define XCM_REG_XQM_XCM_HDR_P   0x200a0
 
#define XCM_REG_XQM_XCM_HDR_S   0x200a4
 
#define XCM_REG_XQM_XCM_IFEN   0x20014
 
#define XCM_REG_XSDM_IFEN   0x20018
 
#define XCM_REG_XSDM_LENGTH_MIS   0x20220
 
#define XCM_REG_XSDM_WEIGHT   0x200e0
 
#define XCM_REG_XX_DESCR_TABLE   0x20480
 
#define XCM_REG_XX_DESCR_TABLE_SIZE   32
 
#define XCM_REG_XX_FREE   0x20240
 
#define XCM_REG_XX_INIT_CRD   0x20424
 
#define XCM_REG_XX_MSG_NUM   0x20428
 
#define XCM_REG_XX_OVFL_EVNT_ID   0x20058
 
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS   (0x1<<0)
 
#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS   (0x1<<1)
 
#define XMAC_CTRL_REG_LINE_LOCAL_LPBK   (0x1<<2)
 
#define XMAC_CTRL_REG_RX_EN   (0x1<<1)
 
#define XMAC_CTRL_REG_SOFT_RESET   (0x1<<6)
 
#define XMAC_CTRL_REG_TX_EN   (0x1<<0)
 
#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN   (0x1<<18)
 
#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN   (0x1<<17)
 
#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON   (0x1<<1)
 
#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN   (0x1<<0)
 
#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN   (0x1<<3)
 
#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN   (0x1<<4)
 
#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN   (0x1<<5)
 
#define XMAC_REG_CLEAR_RX_LSS_STATUS   0x60
 
#define XMAC_REG_CTRL   0
 
#define XMAC_REG_CTRL_SA_HI   0x2c
 
#define XMAC_REG_CTRL_SA_LO   0x28
 
#define XMAC_REG_EEE_CTRL   0xd8
 
#define XMAC_REG_EEE_TIMERS_HI   0xe4
 
#define XMAC_REG_PAUSE_CTRL   0x68
 
#define XMAC_REG_PFC_CTRL   0x70
 
#define XMAC_REG_PFC_CTRL_HI   0x74
 
#define XMAC_REG_RX_LSS_STATUS   0x58
 
#define XMAC_REG_RX_MAX_SIZE   0x40
 
#define XMAC_REG_TX_CTRL   0x20
 
#define XCM_REG_XX_TABLE   0x20500
 
#define XSDM_REG_AGG_INT_EVENT_0   0x166038
 
#define XSDM_REG_AGG_INT_EVENT_1   0x16603c
 
#define XSDM_REG_AGG_INT_EVENT_10   0x166060
 
#define XSDM_REG_AGG_INT_EVENT_11   0x166064
 
#define XSDM_REG_AGG_INT_EVENT_12   0x166068
 
#define XSDM_REG_AGG_INT_EVENT_13   0x16606c
 
#define XSDM_REG_AGG_INT_EVENT_14   0x166070
 
#define XSDM_REG_AGG_INT_EVENT_2   0x166040
 
#define XSDM_REG_AGG_INT_EVENT_3   0x166044
 
#define XSDM_REG_AGG_INT_EVENT_4   0x166048
 
#define XSDM_REG_AGG_INT_EVENT_5   0x16604c
 
#define XSDM_REG_AGG_INT_EVENT_6   0x166050
 
#define XSDM_REG_AGG_INT_EVENT_7   0x166054
 
#define XSDM_REG_AGG_INT_EVENT_8   0x166058
 
#define XSDM_REG_AGG_INT_EVENT_9   0x16605c
 
#define XSDM_REG_AGG_INT_MODE_0   0x1661b8
 
#define XSDM_REG_AGG_INT_MODE_1   0x1661bc
 
#define XSDM_REG_CFC_RSP_START_ADDR   0x166008
 
#define XSDM_REG_CMP_COUNTER_MAX0   0x16601c
 
#define XSDM_REG_CMP_COUNTER_MAX1   0x166020
 
#define XSDM_REG_CMP_COUNTER_MAX2   0x166024
 
#define XSDM_REG_CMP_COUNTER_MAX3   0x166028
 
#define XSDM_REG_CMP_COUNTER_START_ADDR   0x16600c
 
#define XSDM_REG_ENABLE_IN1   0x166238
 
#define XSDM_REG_ENABLE_IN2   0x16623c
 
#define XSDM_REG_ENABLE_OUT1   0x166240
 
#define XSDM_REG_ENABLE_OUT2   0x166244
 
#define XSDM_REG_INIT_CREDIT_PXP_CTRL   0x1664bc
 
#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE   0x16627c
 
#define XSDM_REG_NUM_OF_PKT_END_MSG   0x166274
 
#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ   0x166278
 
#define XSDM_REG_NUM_OF_Q0_CMD   0x166248
 
#define XSDM_REG_NUM_OF_Q10_CMD   0x16626c
 
#define XSDM_REG_NUM_OF_Q11_CMD   0x166270
 
#define XSDM_REG_NUM_OF_Q1_CMD   0x16624c
 
#define XSDM_REG_NUM_OF_Q3_CMD   0x166250
 
#define XSDM_REG_NUM_OF_Q4_CMD   0x166254
 
#define XSDM_REG_NUM_OF_Q5_CMD   0x166258
 
#define XSDM_REG_NUM_OF_Q6_CMD   0x16625c
 
#define XSDM_REG_NUM_OF_Q7_CMD   0x166260
 
#define XSDM_REG_NUM_OF_Q8_CMD   0x166264
 
#define XSDM_REG_NUM_OF_Q9_CMD   0x166268
 
#define XSDM_REG_Q_COUNTER_START_ADDR   0x166010
 
#define XSDM_REG_OPERATION_GEN   0x1664c4
 
#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0x166548
 
#define XSDM_REG_SYNC_PARSER_EMPTY   0x166550
 
#define XSDM_REG_SYNC_SYNC_EMPTY   0x166558
 
#define XSDM_REG_TIMER_TICK   0x166000
 
#define XSDM_REG_XSDM_INT_MASK_0   0x16629c
 
#define XSDM_REG_XSDM_INT_MASK_1   0x1662ac
 
#define XSDM_REG_XSDM_INT_STS_0   0x166290
 
#define XSDM_REG_XSDM_INT_STS_1   0x1662a0
 
#define XSDM_REG_XSDM_PRTY_MASK   0x1662bc
 
#define XSDM_REG_XSDM_PRTY_STS   0x1662b0
 
#define XSDM_REG_XSDM_PRTY_STS_CLR   0x1662b4
 
#define XSEM_REG_ARB_CYCLE_SIZE   0x280034
 
#define XSEM_REG_ARB_ELEMENT0   0x280020
 
#define XSEM_REG_ARB_ELEMENT1   0x280024
 
#define XSEM_REG_ARB_ELEMENT2   0x280028
 
#define XSEM_REG_ARB_ELEMENT3   0x28002c
 
#define XSEM_REG_ARB_ELEMENT4   0x280030
 
#define XSEM_REG_ENABLE_IN   0x2800a4
 
#define XSEM_REG_ENABLE_OUT   0x2800a8
 
#define XSEM_REG_FAST_MEMORY   0x2a0000
 
#define XSEM_REG_FIC0_DISABLE   0x280224
 
#define XSEM_REG_FIC1_DISABLE   0x280234
 
#define XSEM_REG_INT_TABLE   0x280400
 
#define XSEM_REG_MSG_NUM_FIC0   0x280000
 
#define XSEM_REG_MSG_NUM_FIC1   0x280004
 
#define XSEM_REG_MSG_NUM_FOC0   0x280008
 
#define XSEM_REG_MSG_NUM_FOC1   0x28000c
 
#define XSEM_REG_MSG_NUM_FOC2   0x280010
 
#define XSEM_REG_MSG_NUM_FOC3   0x280014
 
#define XSEM_REG_PAS_DISABLE   0x28024c
 
#define XSEM_REG_PASSIVE_BUFFER   0x282000
 
#define XSEM_REG_PRAM   0x2c0000
 
#define XSEM_REG_SLEEP_THREADS_VALID   0x28026c
 
#define XSEM_REG_SLOW_EXT_STORE_EMPTY   0x2802a0
 
#define XSEM_REG_THREADS_LIST   0x2802e4
 
#define XSEM_REG_TS_0_AS   0x280038
 
#define XSEM_REG_TS_10_AS   0x280060
 
#define XSEM_REG_TS_11_AS   0x280064
 
#define XSEM_REG_TS_12_AS   0x280068
 
#define XSEM_REG_TS_13_AS   0x28006c
 
#define XSEM_REG_TS_14_AS   0x280070
 
#define XSEM_REG_TS_15_AS   0x280074
 
#define XSEM_REG_TS_16_AS   0x280078
 
#define XSEM_REG_TS_17_AS   0x28007c
 
#define XSEM_REG_TS_18_AS   0x280080
 
#define XSEM_REG_TS_1_AS   0x28003c
 
#define XSEM_REG_TS_2_AS   0x280040
 
#define XSEM_REG_TS_3_AS   0x280044
 
#define XSEM_REG_TS_4_AS   0x280048
 
#define XSEM_REG_TS_5_AS   0x28004c
 
#define XSEM_REG_TS_6_AS   0x280050
 
#define XSEM_REG_TS_7_AS   0x280054
 
#define XSEM_REG_TS_8_AS   0x280058
 
#define XSEM_REG_TS_9_AS   0x28005c
 
#define XSEM_REG_VFPF_ERR_NUM   0x280380
 
#define XSEM_REG_XSEM_INT_MASK_0   0x280110
 
#define XSEM_REG_XSEM_INT_MASK_1   0x280120
 
#define XSEM_REG_XSEM_INT_STS_0   0x280104
 
#define XSEM_REG_XSEM_INT_STS_1   0x280114
 
#define XSEM_REG_XSEM_PRTY_MASK_0   0x280130
 
#define XSEM_REG_XSEM_PRTY_MASK_1   0x280140
 
#define XSEM_REG_XSEM_PRTY_STS_0   0x280124
 
#define XSEM_REG_XSEM_PRTY_STS_1   0x280134
 
#define XSEM_REG_XSEM_PRTY_STS_CLR_0   0x280128
 
#define XSEM_REG_XSEM_PRTY_STS_CLR_1   0x280138
 
#define MCPR_ACCESS_LOCK_LOCK   (1L<<31)
 
#define MCPR_NVM_ACCESS_ENABLE_EN   (1L<<0)
 
#define MCPR_NVM_ACCESS_ENABLE_WR_EN   (1L<<1)
 
#define MCPR_NVM_ADDR_NVM_ADDR_VALUE   (0xffffffL<<0)
 
#define MCPR_NVM_CFG4_FLASH_SIZE   (0x7L<<0)
 
#define MCPR_NVM_COMMAND_DOIT   (1L<<4)
 
#define MCPR_NVM_COMMAND_DONE   (1L<<3)
 
#define MCPR_NVM_COMMAND_FIRST   (1L<<7)
 
#define MCPR_NVM_COMMAND_LAST   (1L<<8)
 
#define MCPR_NVM_COMMAND_WR   (1L<<5)
 
#define MCPR_NVM_SW_ARB_ARB_ARB1   (1L<<9)
 
#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1   (1L<<5)
 
#define MCPR_NVM_SW_ARB_ARB_REQ_SET1   (1L<<1)
 
#define BIGMAC_REGISTER_BMAC_CONTROL   (0x00<<3)
 
#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL   (0x01<<3)
 
#define BIGMAC_REGISTER_CNT_MAX_SIZE   (0x05<<3)
 
#define BIGMAC_REGISTER_RX_CONTROL   (0x21<<3)
 
#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS   (0x46<<3)
 
#define BIGMAC_REGISTER_RX_LSS_STATUS   (0x43<<3)
 
#define BIGMAC_REGISTER_RX_MAX_SIZE   (0x23<<3)
 
#define BIGMAC_REGISTER_RX_STAT_GR64   (0x26<<3)
 
#define BIGMAC_REGISTER_RX_STAT_GRIPJ   (0x42<<3)
 
#define BIGMAC_REGISTER_TX_CONTROL   (0x07<<3)
 
#define BIGMAC_REGISTER_TX_MAX_SIZE   (0x09<<3)
 
#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD   (0x0A<<3)
 
#define BIGMAC_REGISTER_TX_SOURCE_ADDR   (0x08<<3)
 
#define BIGMAC_REGISTER_TX_STAT_GTBYT   (0x20<<3)
 
#define BIGMAC_REGISTER_TX_STAT_GTPKT   (0x0C<<3)
 
#define BIGMAC2_REGISTER_BMAC_CONTROL   (0x00<<3)
 
#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL   (0x01<<3)
 
#define BIGMAC2_REGISTER_CNT_MAX_SIZE   (0x05<<3)
 
#define BIGMAC2_REGISTER_PFC_CONTROL   (0x06<<3)
 
#define BIGMAC2_REGISTER_RX_CONTROL   (0x3A<<3)
 
#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS   (0x62<<3)
 
#define BIGMAC2_REGISTER_RX_LSS_STAT   (0x3E<<3)
 
#define BIGMAC2_REGISTER_RX_MAX_SIZE   (0x3C<<3)
 
#define BIGMAC2_REGISTER_RX_STAT_GR64   (0x40<<3)
 
#define BIGMAC2_REGISTER_RX_STAT_GRIPJ   (0x5f<<3)
 
#define BIGMAC2_REGISTER_RX_STAT_GRPP   (0x51<<3)
 
#define BIGMAC2_REGISTER_TX_CONTROL   (0x1C<<3)
 
#define BIGMAC2_REGISTER_TX_MAX_SIZE   (0x1E<<3)
 
#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL   (0x20<<3)
 
#define BIGMAC2_REGISTER_TX_SOURCE_ADDR   (0x1D<<3)
 
#define BIGMAC2_REGISTER_TX_STAT_GTBYT   (0x39<<3)
 
#define BIGMAC2_REGISTER_TX_STAT_GTPOK   (0x22<<3)
 
#define BIGMAC2_REGISTER_TX_STAT_GTPP   (0x24<<3)
 
#define EMAC_LED_1000MB_OVERRIDE   (1L<<1)
 
#define EMAC_LED_100MB_OVERRIDE   (1L<<2)
 
#define EMAC_LED_10MB_OVERRIDE   (1L<<3)
 
#define EMAC_LED_2500MB_OVERRIDE   (1L<<12)
 
#define EMAC_LED_OVERRIDE   (1L<<0)
 
#define EMAC_LED_TRAFFIC   (1L<<6)
 
#define EMAC_MDIO_COMM_COMMAND_ADDRESS   (0L<<26)
 
#define EMAC_MDIO_COMM_COMMAND_READ_22   (2L<<26)
 
#define EMAC_MDIO_COMM_COMMAND_READ_45   (3L<<26)
 
#define EMAC_MDIO_COMM_COMMAND_WRITE_22   (1L<<26)
 
#define EMAC_MDIO_COMM_COMMAND_WRITE_45   (1L<<26)
 
#define EMAC_MDIO_COMM_DATA   (0xffffL<<0)
 
#define EMAC_MDIO_COMM_START_BUSY   (1L<<29)
 
#define EMAC_MDIO_MODE_AUTO_POLL   (1L<<4)
 
#define EMAC_MDIO_MODE_CLAUSE_45   (1L<<31)
 
#define EMAC_MDIO_MODE_CLOCK_CNT   (0x3ffL<<16)
 
#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT   16
 
#define EMAC_MDIO_STATUS_10MB   (1L<<1)
 
#define EMAC_MODE_25G_MODE   (1L<<5)
 
#define EMAC_MODE_HALF_DUPLEX   (1L<<1)
 
#define EMAC_MODE_PORT_GMII   (2L<<2)
 
#define EMAC_MODE_PORT_MII   (1L<<2)
 
#define EMAC_MODE_PORT_MII_10M   (3L<<2)
 
#define EMAC_MODE_RESET   (1L<<0)
 
#define EMAC_REG_EMAC_LED   0xc
 
#define EMAC_REG_EMAC_MAC_MATCH   0x10
 
#define EMAC_REG_EMAC_MDIO_COMM   0xac
 
#define EMAC_REG_EMAC_MDIO_MODE   0xb4
 
#define EMAC_REG_EMAC_MDIO_STATUS   0xb0
 
#define EMAC_REG_EMAC_MODE   0x0
 
#define EMAC_REG_EMAC_RX_MODE   0xc8
 
#define EMAC_REG_EMAC_RX_MTU_SIZE   0x9c
 
#define EMAC_REG_EMAC_RX_STAT_AC   0x180
 
#define EMAC_REG_EMAC_RX_STAT_AC_28   0x1f4
 
#define EMAC_REG_EMAC_RX_STAT_AC_COUNT   23
 
#define EMAC_REG_EMAC_TX_MODE   0xbc
 
#define EMAC_REG_EMAC_TX_STAT_AC   0x280
 
#define EMAC_REG_EMAC_TX_STAT_AC_COUNT   22
 
#define EMAC_REG_RX_PFC_MODE   0x320
 
#define EMAC_REG_RX_PFC_MODE_PRIORITIES   (1L<<2)
 
#define EMAC_REG_RX_PFC_MODE_RX_EN   (1L<<1)
 
#define EMAC_REG_RX_PFC_MODE_TX_EN   (1L<<0)
 
#define EMAC_REG_RX_PFC_PARAM   0x324
 
#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT   0
 
#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT   16
 
#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD   0x328
 
#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT   (0xffff<<0)
 
#define EMAC_REG_RX_PFC_STATS_XOFF_SENT   0x330
 
#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT   (0xffff<<0)
 
#define EMAC_REG_RX_PFC_STATS_XON_RCVD   0x32c
 
#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT   (0xffff<<0)
 
#define EMAC_REG_RX_PFC_STATS_XON_SENT   0x334
 
#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT   (0xffff<<0)
 
#define EMAC_RX_MODE_FLOW_EN   (1L<<2)
 
#define EMAC_RX_MODE_KEEP_MAC_CONTROL   (1L<<3)
 
#define EMAC_RX_MODE_KEEP_VLAN_TAG   (1L<<10)
 
#define EMAC_RX_MODE_PROMISCUOUS   (1L<<8)
 
#define EMAC_RX_MODE_RESET   (1L<<0)
 
#define EMAC_RX_MTU_SIZE_JUMBO_ENA   (1L<<31)
 
#define EMAC_TX_MODE_EXT_PAUSE_EN   (1L<<3)
 
#define EMAC_TX_MODE_FLOW_EN   (1L<<4)
 
#define EMAC_TX_MODE_RESET   (1L<<0)
 
#define MISC_REGISTERS_GPIO_0   0
 
#define MISC_REGISTERS_GPIO_1   1
 
#define MISC_REGISTERS_GPIO_2   2
 
#define MISC_REGISTERS_GPIO_3   3
 
#define MISC_REGISTERS_GPIO_CLR_POS   16
 
#define MISC_REGISTERS_GPIO_FLOAT   (0xffL<<24)
 
#define MISC_REGISTERS_GPIO_FLOAT_POS   24
 
#define MISC_REGISTERS_GPIO_HIGH   1
 
#define MISC_REGISTERS_GPIO_INPUT_HI_Z   2
 
#define MISC_REGISTERS_GPIO_INT_CLR_POS   24
 
#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR   0
 
#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET   1
 
#define MISC_REGISTERS_GPIO_INT_SET_POS   16
 
#define MISC_REGISTERS_GPIO_LOW   0
 
#define MISC_REGISTERS_GPIO_OUTPUT_HIGH   1
 
#define MISC_REGISTERS_GPIO_OUTPUT_LOW   0
 
#define MISC_REGISTERS_GPIO_PORT_SHIFT   4
 
#define MISC_REGISTERS_GPIO_SET_POS   8
 
#define MISC_REGISTERS_RESET_REG_1_CLEAR   0x588
 
#define MISC_REGISTERS_RESET_REG_1_RST_BRB1   (0x1<<0)
 
#define MISC_REGISTERS_RESET_REG_1_RST_DORQ   (0x1<<19)
 
#define MISC_REGISTERS_RESET_REG_1_RST_HC   (0x1<<29)
 
#define MISC_REGISTERS_RESET_REG_1_RST_NIG   (0x1<<7)
 
#define MISC_REGISTERS_RESET_REG_1_RST_PXP   (0x1<<26)
 
#define MISC_REGISTERS_RESET_REG_1_RST_PXPV   (0x1<<27)
 
#define MISC_REGISTERS_RESET_REG_1_SET   0x584
 
#define MISC_REGISTERS_RESET_REG_2_CLEAR   0x598
 
#define MISC_REGISTERS_RESET_REG_2_MSTAT0   (0x1<<24)
 
#define MISC_REGISTERS_RESET_REG_2_MSTAT1   (0x1<<25)
 
#define MISC_REGISTERS_RESET_REG_2_PGLC   (0x1<<19)
 
#define MISC_REGISTERS_RESET_REG_2_RST_ATC   (0x1<<17)
 
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0   (0x1<<0)
 
#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1   (0x1<<1)
 
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0   (0x1<<2)
 
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE   (0x1<<14)
 
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1   (0x1<<3)
 
#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE   (0x1<<15)
 
#define MISC_REGISTERS_RESET_REG_2_RST_GRC   (0x1<<4)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B   (0x1<<6)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE   (0x1<<8)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU   (0x1<<7)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE   (0x1<<5)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MDIO   (0x1<<13)
 
#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE   (0x1<<11)
 
#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO   (0x1<<13)
 
#define MISC_REGISTERS_RESET_REG_2_RST_RBCN   (0x1<<9)
 
#define MISC_REGISTERS_RESET_REG_2_SET   0x594
 
#define MISC_REGISTERS_RESET_REG_2_UMAC0   (0x1<<20)
 
#define MISC_REGISTERS_RESET_REG_2_UMAC1   (0x1<<21)
 
#define MISC_REGISTERS_RESET_REG_2_XMAC   (0x1<<22)
 
#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT   (0x1<<23)
 
#define MISC_REGISTERS_RESET_REG_3_CLEAR   0x5a8
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ   (0x1<<1)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN   (0x1<<2)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD   (0x1<<3)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW   (0x1<<0)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ   (0x1<<5)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN   (0x1<<6)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD   (0x1<<7)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW   (0x1<<4)
 
#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB   (0x1<<8)
 
#define MISC_REGISTERS_RESET_REG_3_SET   0x5a4
 
#define MISC_REGISTERS_SPIO_4   4
 
#define MISC_REGISTERS_SPIO_5   5
 
#define MISC_REGISTERS_SPIO_7   7
 
#define MISC_REGISTERS_SPIO_CLR_POS   16
 
#define MISC_REGISTERS_SPIO_FLOAT   (0xffL<<24)
 
#define MISC_REGISTERS_SPIO_FLOAT_POS   24
 
#define MISC_REGISTERS_SPIO_INPUT_HI_Z   2
 
#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS   16
 
#define MISC_REGISTERS_SPIO_OUTPUT_HIGH   1
 
#define MISC_REGISTERS_SPIO_OUTPUT_LOW   0
 
#define MISC_REGISTERS_SPIO_SET_POS   8
 
#define HW_LOCK_MAX_RESOURCE_VALUE   31
 
#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB   13
 
#define HW_LOCK_RESOURCE_DRV_FLAGS   10
 
#define HW_LOCK_RESOURCE_GPIO   1
 
#define HW_LOCK_RESOURCE_MDIO   0
 
#define HW_LOCK_RESOURCE_NVRAM   12
 
#define HW_LOCK_RESOURCE_PORT0_ATT_MASK   3
 
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0   8
 
#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1   9
 
#define HW_LOCK_RESOURCE_RECOVERY_REG   11
 
#define HW_LOCK_RESOURCE_RESET   5
 
#define HW_LOCK_RESOURCE_SPIO   2
 
#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT   (0x1<<4)
 
#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR   (0x1<<5)
 
#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR   (0x1<<18)
 
#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT   (0x1<<31)
 
#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR   (0x1<<30)
 
#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT   (0x1<<9)
 
#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR   (0x1<<8)
 
#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT   (0x1<<7)
 
#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR   (0x1<<6)
 
#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT   (0x1<<29)
 
#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR   (0x1<<28)
 
#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT   (0x1<<1)
 
#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR   (0x1<<0)
 
#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR   (0x1<<18)
 
#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT   (0x1<<11)
 
#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR   (0x1<<10)
 
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT   (0x1<<13)
 
#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR   (0x1<<12)
 
#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0   (0x1<<2)
 
#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR   (0x1<<12)
 
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY   (0x1<<28)
 
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY   (0x1<<31)
 
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY   (0x1<<29)
 
#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY   (0x1<<30)
 
#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT   (0x1<<15)
 
#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR   (0x1<<14)
 
#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR   (0x1<<14)
 
#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR   (0x1<<20)
 
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT   (0x1<<31)
 
#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR   (0x1<<30)
 
#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR   (0x1<<0)
 
#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT   (0x1<<2)
 
#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR   (0x1<<3)
 
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT   (0x1<<5)
 
#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR   (0x1<<4)
 
#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT   (0x1<<3)
 
#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR   (0x1<<2)
 
#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT   (0x1<<3)
 
#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR   (0x1<<2)
 
#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR   (0x1<<22)
 
#define AEU_INPUTS_ATTN_BITS_SPIO5   (0x1<<15)
 
#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT   (0x1<<27)
 
#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR   (0x1<<26)
 
#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT   (0x1<<5)
 
#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR   (0x1<<4)
 
#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT   (0x1<<25)
 
#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR   (0x1<<24)
 
#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT   (0x1<<29)
 
#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR   (0x1<<28)
 
#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT   (0x1<<23)
 
#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR   (0x1<<22)
 
#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT   (0x1<<27)
 
#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR   (0x1<<26)
 
#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT   (0x1<<21)
 
#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR   (0x1<<20)
 
#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT   (0x1<<25)
 
#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR   (0x1<<24)
 
#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR   (0x1<<16)
 
#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT   (0x1<<9)
 
#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR   (0x1<<8)
 
#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT   (0x1<<7)
 
#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR   (0x1<<6)
 
#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT   (0x1<<11)
 
#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR   (0x1<<10)
 
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0   (0x1<<5)
 
#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1   (0x1<<9)
 
#define RESERVED_GENERAL_ATTENTION_BIT_0   0
 
#define EVEREST_GEN_ATTN_IN_USE_MASK   0x7ffe0
 
#define EVEREST_LATCHED_ATTN_IN_USE_MASK   0xffe00000
 
#define RESERVED_GENERAL_ATTENTION_BIT_6   6
 
#define RESERVED_GENERAL_ATTENTION_BIT_7   7
 
#define RESERVED_GENERAL_ATTENTION_BIT_8   8
 
#define RESERVED_GENERAL_ATTENTION_BIT_9   9
 
#define RESERVED_GENERAL_ATTENTION_BIT_10   10
 
#define RESERVED_GENERAL_ATTENTION_BIT_11   11
 
#define RESERVED_GENERAL_ATTENTION_BIT_12   12
 
#define RESERVED_GENERAL_ATTENTION_BIT_13   13
 
#define RESERVED_GENERAL_ATTENTION_BIT_14   14
 
#define RESERVED_GENERAL_ATTENTION_BIT_15   15
 
#define RESERVED_GENERAL_ATTENTION_BIT_16   16
 
#define RESERVED_GENERAL_ATTENTION_BIT_17   17
 
#define RESERVED_GENERAL_ATTENTION_BIT_18   18
 
#define RESERVED_GENERAL_ATTENTION_BIT_19   19
 
#define RESERVED_GENERAL_ATTENTION_BIT_20   20
 
#define RESERVED_GENERAL_ATTENTION_BIT_21   21
 
#define TSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_7
 
#define USTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_8
 
#define CSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_9
 
#define XSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_10
 
#define MCP_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_11
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_0   RESERVED_GENERAL_ATTENTION_BIT_12
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_1   RESERVED_GENERAL_ATTENTION_BIT_13
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_2   RESERVED_GENERAL_ATTENTION_BIT_14
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_3   RESERVED_GENERAL_ATTENTION_BIT_15
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_4   RESERVED_GENERAL_ATTENTION_BIT_16
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_5   RESERVED_GENERAL_ATTENTION_BIT_17
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_6   RESERVED_GENERAL_ATTENTION_BIT_18
 
#define LINK_SYNC_ATTENTION_BIT_FUNC_7   RESERVED_GENERAL_ATTENTION_BIT_19
 
#define LATCHED_ATTN_RBCR   23
 
#define LATCHED_ATTN_RBCT   24
 
#define LATCHED_ATTN_RBCN   25
 
#define LATCHED_ATTN_RBCU   26
 
#define LATCHED_ATTN_RBCP   27
 
#define LATCHED_ATTN_TIMEOUT_GRC   28
 
#define LATCHED_ATTN_RSVD_GRC   29
 
#define LATCHED_ATTN_ROM_PARITY_MCP   30
 
#define LATCHED_ATTN_UM_RX_PARITY_MCP   31
 
#define LATCHED_ATTN_UM_TX_PARITY_MCP   32
 
#define LATCHED_ATTN_SCPAD_PARITY_MCP   33
 
#define GENERAL_ATTEN_WORD(atten_name)   ((94 + atten_name) / 32)
 
#define GENERAL_ATTEN_OFFSET(atten_name)   (1UL << ((94 + atten_name) % 32))
 
#define GRCBASE_PXPCS   0x000000
 
#define GRCBASE_PCICONFIG   0x002000
 
#define GRCBASE_PCIREG   0x002400
 
#define GRCBASE_EMAC0   0x008000
 
#define GRCBASE_EMAC1   0x008400
 
#define GRCBASE_DBU   0x008800
 
#define GRCBASE_MISC   0x00A000
 
#define GRCBASE_DBG   0x00C000
 
#define GRCBASE_NIG   0x010000
 
#define GRCBASE_XCM   0x020000
 
#define GRCBASE_PRS   0x040000
 
#define GRCBASE_SRCH   0x040400
 
#define GRCBASE_TSDM   0x042000
 
#define GRCBASE_TCM   0x050000
 
#define GRCBASE_BRB1   0x060000
 
#define GRCBASE_MCP   0x080000
 
#define GRCBASE_UPB   0x0C1000
 
#define GRCBASE_CSDM   0x0C2000
 
#define GRCBASE_USDM   0x0C4000
 
#define GRCBASE_CCM   0x0D0000
 
#define GRCBASE_UCM   0x0E0000
 
#define GRCBASE_CDU   0x101000
 
#define GRCBASE_DMAE   0x102000
 
#define GRCBASE_PXP   0x103000
 
#define GRCBASE_CFC   0x104000
 
#define GRCBASE_HC   0x108000
 
#define GRCBASE_PXP2   0x120000
 
#define GRCBASE_PBF   0x140000
 
#define GRCBASE_UMAC0   0x160000
 
#define GRCBASE_UMAC1   0x160400
 
#define GRCBASE_XPB   0x161000
 
#define GRCBASE_MSTAT0   0x162000
 
#define GRCBASE_MSTAT1   0x162800
 
#define GRCBASE_XMAC0   0x163000
 
#define GRCBASE_XMAC1   0x163800
 
#define GRCBASE_TIMERS   0x164000
 
#define GRCBASE_XSDM   0x166000
 
#define GRCBASE_QM   0x168000
 
#define GRCBASE_DQ   0x170000
 
#define GRCBASE_TSEM   0x180000
 
#define GRCBASE_CSEM   0x200000
 
#define GRCBASE_XSEM   0x280000
 
#define GRCBASE_USEM   0x300000
 
#define GRCBASE_MISC_AEU   GRCBASE_MISC
 
#define PCICFG_OFFSET   0x2000
 
#define PCICFG_VENDOR_ID_OFFSET   0x00
 
#define PCICFG_DEVICE_ID_OFFSET   0x02
 
#define PCICFG_COMMAND_OFFSET   0x04
 
#define PCICFG_COMMAND_IO_SPACE   (1<<0)
 
#define PCICFG_COMMAND_MEM_SPACE   (1<<1)
 
#define PCICFG_COMMAND_BUS_MASTER   (1<<2)
 
#define PCICFG_COMMAND_SPECIAL_CYCLES   (1<<3)
 
#define PCICFG_COMMAND_MWI_CYCLES   (1<<4)
 
#define PCICFG_COMMAND_VGA_SNOOP   (1<<5)
 
#define PCICFG_COMMAND_PERR_ENA   (1<<6)
 
#define PCICFG_COMMAND_STEPPING   (1<<7)
 
#define PCICFG_COMMAND_SERR_ENA   (1<<8)
 
#define PCICFG_COMMAND_FAST_B2B   (1<<9)
 
#define PCICFG_COMMAND_INT_DISABLE   (1<<10)
 
#define PCICFG_COMMAND_RESERVED   (0x1f<<11)
 
#define PCICFG_STATUS_OFFSET   0x06
 
#define PCICFG_REVESION_ID_OFFSET   0x08
 
#define PCICFG_CACHE_LINE_SIZE   0x0c
 
#define PCICFG_LATENCY_TIMER   0x0d
 
#define PCICFG_BAR_1_LOW   0x10
 
#define PCICFG_BAR_1_HIGH   0x14
 
#define PCICFG_BAR_2_LOW   0x18
 
#define PCICFG_BAR_2_HIGH   0x1c
 
#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET   0x2c
 
#define PCICFG_SUBSYSTEM_ID_OFFSET   0x2e
 
#define PCICFG_INT_LINE   0x3c
 
#define PCICFG_INT_PIN   0x3d
 
#define PCICFG_PM_CAPABILITY   0x48
 
#define PCICFG_PM_CAPABILITY_VERSION   (0x3<<16)
 
#define PCICFG_PM_CAPABILITY_CLOCK   (1<<19)
 
#define PCICFG_PM_CAPABILITY_RESERVED   (1<<20)
 
#define PCICFG_PM_CAPABILITY_DSI   (1<<21)
 
#define PCICFG_PM_CAPABILITY_AUX_CURRENT   (0x7<<22)
 
#define PCICFG_PM_CAPABILITY_D1_SUPPORT   (1<<25)
 
#define PCICFG_PM_CAPABILITY_D2_SUPPORT   (1<<26)
 
#define PCICFG_PM_CAPABILITY_PME_IN_D0   (1<<27)
 
#define PCICFG_PM_CAPABILITY_PME_IN_D1   (1<<28)
 
#define PCICFG_PM_CAPABILITY_PME_IN_D2   (1<<29)
 
#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT   (1<<30)
 
#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD   (1<<31)
 
#define PCICFG_PM_CSR_OFFSET   0x4c
 
#define PCICFG_PM_CSR_STATE   (0x3<<0)
 
#define PCICFG_PM_CSR_PME_ENABLE   (1<<8)
 
#define PCICFG_PM_CSR_PME_STATUS   (1<<15)
 
#define PCICFG_MSI_CAP_ID_OFFSET   0x58
 
#define PCICFG_MSI_CONTROL_ENABLE   (0x1<<16)
 
#define PCICFG_MSI_CONTROL_MCAP   (0x7<<17)
 
#define PCICFG_MSI_CONTROL_MENA   (0x7<<20)
 
#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP   (0x1<<23)
 
#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE   (0x1<<24)
 
#define PCICFG_GRC_ADDRESS   0x78
 
#define PCICFG_GRC_DATA   0x80
 
#define PCICFG_ME_REGISTER   0x98
 
#define PCICFG_MSIX_CAP_ID_OFFSET   0xa0
 
#define PCICFG_MSIX_CONTROL_TABLE_SIZE   (0x7ff<<16)
 
#define PCICFG_MSIX_CONTROL_RESERVED   (0x7<<27)
 
#define PCICFG_MSIX_CONTROL_FUNC_MASK   (0x1<<30)
 
#define PCICFG_MSIX_CONTROL_MSIX_ENABLE   (0x1<<31)
 
#define PCICFG_DEVICE_CONTROL   0xb4
 
#define PCICFG_DEVICE_STATUS   0xb6
 
#define PCICFG_DEVICE_STATUS_CORR_ERR_DET   (1<<0)
 
#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET   (1<<1)
 
#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET   (1<<2)
 
#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET   (1<<3)
 
#define PCICFG_DEVICE_STATUS_AUX_PWR_DET   (1<<4)
 
#define PCICFG_DEVICE_STATUS_NO_PEND   (1<<5)
 
#define PCICFG_LINK_CONTROL   0xbc
 
#define BAR_USTRORM_INTMEM   0x400000
 
#define BAR_CSTRORM_INTMEM   0x410000
 
#define BAR_XSTRORM_INTMEM   0x420000
 
#define BAR_TSTRORM_INTMEM   0x430000
 
#define BAR_IGU_INTMEM   0x440000
 
#define BAR_DOORBELL_OFFSET   0x800000
 
#define BAR_ME_REGISTER   0x450000
 
#define GRC_CONFIG_2_SIZE_REG   0x408
 
#define PCI_CONFIG_2_BAR1_SIZE   (0xfL<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_DISABLED   (0L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_64K   (1L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_128K   (2L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_256K   (3L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_512K   (4L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_1M   (5L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_2M   (6L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_4M   (7L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_8M   (8L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_16M   (9L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_32M   (10L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_64M   (11L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_128M   (12L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_256M   (13L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_512M   (14L<<0)
 
#define PCI_CONFIG_2_BAR1_SIZE_1G   (15L<<0)
 
#define PCI_CONFIG_2_BAR1_64ENA   (1L<<4)
 
#define PCI_CONFIG_2_EXP_ROM_RETRY   (1L<<5)
 
#define PCI_CONFIG_2_CFG_CYCLE_RETRY   (1L<<6)
 
#define PCI_CONFIG_2_FIRST_CFG_DONE   (1L<<7)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE   (0xffL<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED   (0L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_2K   (1L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_4K   (2L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_8K   (3L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_16K   (4L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_32K   (5L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_64K   (6L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_128K   (7L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_256K   (8L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_512K   (9L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_1M   (10L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_2M   (11L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_4M   (12L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_8M   (13L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_16M   (14L<<8)
 
#define PCI_CONFIG_2_EXP_ROM_SIZE_32M   (15L<<8)
 
#define PCI_CONFIG_2_BAR_PREFETCH   (1L<<16)
 
#define PCI_CONFIG_2_RESERVED0   (0x7fffL<<17)
 
#define GRC_CONFIG_3_SIZE_REG   0x40c
 
#define PCI_CONFIG_3_STICKY_BYTE   (0xffL<<0)
 
#define PCI_CONFIG_3_FORCE_PME   (1L<<24)
 
#define PCI_CONFIG_3_PME_STATUS   (1L<<25)
 
#define PCI_CONFIG_3_PME_ENABLE   (1L<<26)
 
#define PCI_CONFIG_3_PM_STATE   (0x3L<<27)
 
#define PCI_CONFIG_3_VAUX_PRESET   (1L<<30)
 
#define PCI_CONFIG_3_PCI_POWER   (1L<<31)
 
#define GRC_BAR2_CONFIG   0x4e0
 
#define PCI_CONFIG_2_BAR2_SIZE   (0xfL<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_DISABLED   (0L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_64K   (1L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_128K   (2L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_256K   (3L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_512K   (4L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_1M   (5L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_2M   (6L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_4M   (7L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_8M   (8L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_16M   (9L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_32M   (10L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_64M   (11L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_128M   (12L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_256M   (13L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_512M   (14L<<0)
 
#define PCI_CONFIG_2_BAR2_SIZE_1G   (15L<<0)
 
#define PCI_CONFIG_2_BAR2_64ENA   (1L<<4)
 
#define PCI_PM_DATA_A   0x410
 
#define PCI_PM_DATA_B   0x414
 
#define PCI_ID_VAL1   0x434
 
#define PCI_ID_VAL2   0x438
 
#define PXPCS_TL_CONTROL_5   0x814
 
#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN   (1 << 29) /*WC*/
 
#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN   (1 << 28) /*WC*/
 
#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN   (1 << 27) /*WC*/
 
#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN   (1 << 26) /*WC*/
 
#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR   (1 << 25) /*WC*/
 
#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW   (1 << 24) /*WC*/
 
#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN   (1 << 23) /*RO*/
 
#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN   (1 << 22) /*RO*/
 
#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE   (1 << 21) /*WC*/
 
#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG   (1 << 20) /*WC*/
 
#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1   (1 << 19) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1   (1 << 18) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_ECRC1   (1 << 17) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1   (1 << 16) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1   (1 << 15) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1   (1 << 14) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1   (1 << 13) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1   (1 << 12) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1   (1 << 11) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1   (1 << 10) /*WC*/
 
#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT   (1 << 9) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT   (1 << 8) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_ECRC   (1 << 7) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP   (1 << 6) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW   (1 << 5) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL   (1 << 4) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT   (1 << 3) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT   (1 << 2) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL   (1 << 1) /*WC*/
 
#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP   (1 << 0) /*WC*/
 
#define PXPCS_TL_FUNC345_STAT   0x854
 
#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4   (1 << 29) /* WC */
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
 
#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4
 
#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4
 
#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4
 
#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4
 
#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4
 
#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4
 
#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4
 
#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3   (1 << 19) /* WC */
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
 
#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3
 
#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3
 
#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3
 
#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3
 
#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3
 
#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3
 
#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3
 
#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2   (1 << 9) /* WC */
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
 
#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2
 
#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2
 
#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2
 
#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2
 
#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2
 
#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2
 
#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2
 
#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2
 
#define PXPCS_TL_FUNC678_STAT   0x85C
 
#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7   (1 << 29) /* WC */
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
 
#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7
 
#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7
 
#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7
 
#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7
 
#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7
 
#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7
 
#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7
 
#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6   (1 << 19) /* WC */
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
 
#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6
 
#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6
 
#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6
 
#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6
 
#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6
 
#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6
 
#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6
 
#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5   (1 << 9) /* WC */
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
 
#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5
 
#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5
 
#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5
 
#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5
 
#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5
 
#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5
 
#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5
 
#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5
 
#define BAR_USTRORM_INTMEM   0x400000
 
#define BAR_CSTRORM_INTMEM   0x410000
 
#define BAR_XSTRORM_INTMEM   0x420000
 
#define BAR_TSTRORM_INTMEM   0x430000
 
#define BAR_IGU_INTMEM   0x440000
 
#define BAR_DOORBELL_OFFSET   0x800000
 
#define BAR_ME_REGISTER   0x450000
 
#define ME_REG_PF_NUM_SHIFT   0
 
#define ME_REG_PF_NUM   (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
 
#define ME_REG_VF_VALID   (1<<8)
 
#define ME_REG_VF_NUM_SHIFT   9
 
#define ME_REG_VF_NUM_MASK   (0x3f<<ME_REG_VF_NUM_SHIFT)
 
#define ME_REG_VF_ERR   (0x1<<3)
 
#define ME_REG_ABS_PF_NUM_SHIFT   16
 
#define ME_REG_ABS_PF_NUM   (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
 
#define MDIO_REG_BANK_CL73_IEEEB0   0x0
 
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL   0x0
 
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN   0x0200
 
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN   0x1000
 
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST   0x8000
 
#define MDIO_REG_BANK_CL73_IEEEB1   0x10
 
#define MDIO_CL73_IEEEB1_AN_ADV1   0x00
 
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE   0x0400
 
#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC   0x0800
 
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH   0x0C00
 
#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK   0x0C00
 
#define MDIO_CL73_IEEEB1_AN_ADV2   0x01
 
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M   0x0000
 
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX   0x0020
 
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4   0x0040
 
#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR   0x0080
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV1   0x03
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE   0x0400
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC   0x0800
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH   0x0C00
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK   0x0C00
 
#define MDIO_CL73_IEEEB1_AN_LP_ADV2   0x04
 
#define MDIO_REG_BANK_RX0   0x80b0
 
#define MDIO_RX0_RX_STATUS   0x10
 
#define MDIO_RX0_RX_STATUS_SIGDET   0x8000
 
#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE   0x1000
 
#define MDIO_RX0_RX_EQ_BOOST   0x1c
 
#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7
 
#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL   0x10
 
#define MDIO_REG_BANK_RX1   0x80c0
 
#define MDIO_RX1_RX_EQ_BOOST   0x1c
 
#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7
 
#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL   0x10
 
#define MDIO_REG_BANK_RX2   0x80d0
 
#define MDIO_RX2_RX_EQ_BOOST   0x1c
 
#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7
 
#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL   0x10
 
#define MDIO_REG_BANK_RX3   0x80e0
 
#define MDIO_RX3_RX_EQ_BOOST   0x1c
 
#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7
 
#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL   0x10
 
#define MDIO_REG_BANK_RX_ALL   0x80f0
 
#define MDIO_RX_ALL_RX_EQ_BOOST   0x1c
 
#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7
 
#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL   0x10
 
#define MDIO_REG_BANK_TX0   0x8060
 
#define MDIO_TX0_TX_DRIVER   0x17
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1
 
#define MDIO_TX0_TX_DRIVER_ICBUF1T   1
 
#define MDIO_REG_BANK_TX1   0x8070
 
#define MDIO_TX1_TX_DRIVER   0x17
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1
 
#define MDIO_TX0_TX_DRIVER_ICBUF1T   1
 
#define MDIO_REG_BANK_TX2   0x8080
 
#define MDIO_TX2_TX_DRIVER   0x17
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1
 
#define MDIO_TX0_TX_DRIVER_ICBUF1T   1
 
#define MDIO_REG_BANK_TX3   0x8090
 
#define MDIO_TX3_TX_DRIVER   0x17
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000
 
#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00
 
#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0
 
#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e
 
#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1
 
#define MDIO_TX0_TX_DRIVER_ICBUF1T   1
 
#define MDIO_REG_BANK_XGXS_BLOCK0   0x8000
 
#define MDIO_BLOCK0_XGXS_CONTROL   0x10
 
#define MDIO_REG_BANK_XGXS_BLOCK1   0x8010
 
#define MDIO_BLOCK1_LANE_CTRL0   0x15
 
#define MDIO_BLOCK1_LANE_CTRL1   0x16
 
#define MDIO_BLOCK1_LANE_CTRL2   0x17
 
#define MDIO_BLOCK1_LANE_PRBS   0x19
 
#define MDIO_REG_BANK_XGXS_BLOCK2   0x8100
 
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP   0x10
 
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE   0x8000
 
#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE   0x4000
 
#define MDIO_XGXS_BLOCK2_TX_LN_SWAP   0x11
 
#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE   0x8000
 
#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G   0x14
 
#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS   0x0001
 
#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS   0x0010
 
#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE   0x15
 
#define MDIO_REG_BANK_GP_STATUS   0x8120
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1   0x1B
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE   0x0001
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE   0x0002
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS   0x0004
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS   0x0008
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE   0x0010
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE   0x0020
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE   0x0040
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE   0x0080
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK   0x3f00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M   0x0000
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M   0x0100
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G   0x0200
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G   0x0300
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G   0x0400
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G   0x0500
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG   0x0600
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4   0x0700
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG   0x0800
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G   0x0900
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G   0x0A00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G   0x0B00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G   0x0C00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX   0x0D00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4   0x0E00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR   0x0F00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI   0x1B00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS   0x1E00
 
#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI   0x1F00
 
#define MDIO_REG_BANK_10G_PARALLEL_DETECT   0x8130
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS   0x10
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK   0x8000
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL   0x11
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN   0x1
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK   0x13
 
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT   (0xb71<<1)
 
#define MDIO_REG_BANK_SERDES_DIGITAL   0x8300
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1   0x10
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE   0x0001
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF   0x0002
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN   0x0004
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT   0x0008
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET   0x0010
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE   0x0020
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2   0x11
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN   0x0001
 
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR   0x0040
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1   0x14
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII   0x0001
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK   0x0002
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX   0x0004
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK   0x0018
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT   3
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G   0x0018
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G   0x0010
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M   0x0008
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M   0x0000
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2   0x15
 
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED   0x0002
 
#define MDIO_SERDES_DIGITAL_MISC1   0x18
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK   0xE000
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M   0x0000
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M   0x2000
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M   0x4000
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M   0x6000
 
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M   0x8000
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL   0x0010
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK   0x000f
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G   0x0000
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G   0x0001
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G   0x0002
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG   0x0003
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4   0x0004
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G   0x0005
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G   0x0006
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G   0x0007
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G   0x0008
 
#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G   0x0009
 
#define MDIO_REG_BANK_OVER_1G   0x8320
 
#define MDIO_OVER_1G_DIGCTL_3_4   0x14
 
#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK   0xffe0
 
#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT   5
 
#define MDIO_OVER_1G_UP1   0x19
 
#define MDIO_OVER_1G_UP1_2_5G   0x0001
 
#define MDIO_OVER_1G_UP1_5G   0x0002
 
#define MDIO_OVER_1G_UP1_6G   0x0004
 
#define MDIO_OVER_1G_UP1_10G   0x0010
 
#define MDIO_OVER_1G_UP1_10GH   0x0008
 
#define MDIO_OVER_1G_UP1_12G   0x0020
 
#define MDIO_OVER_1G_UP1_12_5G   0x0040
 
#define MDIO_OVER_1G_UP1_13G   0x0080
 
#define MDIO_OVER_1G_UP1_15G   0x0100
 
#define MDIO_OVER_1G_UP1_16G   0x0200
 
#define MDIO_OVER_1G_UP2   0x1A
 
#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK   0x0007
 
#define MDIO_OVER_1G_UP2_IDRIVER_MASK   0x0038
 
#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK   0x03C0
 
#define MDIO_OVER_1G_UP3   0x1B
 
#define MDIO_OVER_1G_UP3_HIGIG2   0x0001
 
#define MDIO_OVER_1G_LP_UP1   0x1C
 
#define MDIO_OVER_1G_LP_UP2   0x1D
 
#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK   0x03ff
 
#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK   0x0780
 
#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT   7
 
#define MDIO_OVER_1G_LP_UP3   0x1E
 
#define MDIO_REG_BANK_REMOTE_PHY   0x8330
 
#define MDIO_REMOTE_PHY_MISC_RX_STATUS   0x10
 
#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG   0x0010
 
#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG   0x0600
 
#define MDIO_REG_BANK_BAM_NEXT_PAGE   0x8350
 
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL   0x10
 
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE   0x0001
 
#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN   0x0002
 
#define MDIO_REG_BANK_CL73_USERB0   0x8370
 
#define MDIO_CL73_USERB0_CL73_UCTRL   0x10
 
#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL   0x0002
 
#define MDIO_CL73_USERB0_CL73_USTAT1   0x11
 
#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK   0x0100
 
#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37   0x0400
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1   0x12
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN   0x8000
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN   0x4000
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN   0x2000
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL3   0x14
 
#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR   0x0001
 
#define MDIO_REG_BANK_AER_BLOCK   0xFFD0
 
#define MDIO_AER_BLOCK_AER_REG   0x1E
 
#define MDIO_REG_BANK_COMBO_IEEE0   0xFFE0
 
#define MDIO_COMBO_IEEE0_MII_CONTROL   0x10
 
#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK   0x2040
 
#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10   0x0000
 
#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100   0x2000
 
#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000   0x0040
 
#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX   0x0100
 
#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN   0x0200
 
#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN   0x1000
 
#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK   0x4000
 
#define MDIO_COMBO_IEEO_MII_CONTROL_RESET   0x8000
 
#define MDIO_COMBO_IEEE0_MII_STATUS   0x11
 
#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS   0x0004
 
#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE   0x0020
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV   0x14
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX   0x0020
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX   0x0040
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK   0x0180
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE   0x0000
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC   0x0080
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC   0x0100
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH   0x0180
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE   0x8000
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1   0x15
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE   0x8000
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK   0x4000
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK   0x0180
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE   0x0000
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH   0x0180
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP   0x0040
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP   0x0020
 
#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE   0x0001
 
#define MDIO_PMA_DEVAD   0x1
 
#define MDIO_PMA_REG_CTRL   0x0
 
#define MDIO_PMA_REG_STATUS   0x1
 
#define MDIO_PMA_REG_10G_CTRL2   0x7
 
#define MDIO_PMA_REG_TX_DISABLE   0x0009
 
#define MDIO_PMA_REG_RX_SD   0xa
 
#define MDIO_PMA_REG_BCM_CTRL   0x0096
 
#define MDIO_PMA_REG_FEC_CTRL   0x00ab
 
#define MDIO_PMA_REG_PHY_IDENTIFIER   0xc800
 
#define MDIO_PMA_REG_DIGITAL_CTRL   0xc808
 
#define MDIO_PMA_REG_DIGITAL_STATUS   0xc809
 
#define MDIO_PMA_REG_TX_POWER_DOWN   0xca02
 
#define MDIO_PMA_REG_CMU_PLL_BYPASS   0xca09
 
#define MDIO_PMA_REG_MISC_CTRL   0xca0a
 
#define MDIO_PMA_REG_GEN_CTRL   0xca10
 
#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP   0x0188
 
#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET   0x018a
 
#define MDIO_PMA_REG_M8051_MSGIN_REG   0xca12
 
#define MDIO_PMA_REG_M8051_MSGOUT_REG   0xca13
 
#define MDIO_PMA_REG_ROM_VER1   0xca19
 
#define MDIO_PMA_REG_ROM_VER2   0xca1a
 
#define MDIO_PMA_REG_EDC_FFE_MAIN   0xca1b
 
#define MDIO_PMA_REG_PLL_BANDWIDTH   0xca1d
 
#define MDIO_PMA_REG_PLL_CTRL   0xca1e
 
#define MDIO_PMA_REG_MISC_CTRL0   0xca23
 
#define MDIO_PMA_REG_LRM_MODE   0xca3f
 
#define MDIO_PMA_REG_CDR_BANDWIDTH   0xca46
 
#define MDIO_PMA_REG_MISC_CTRL1   0xca85
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL   0x8000
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK   0x000c
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE   0x0000
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE   0x0004
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS   0x0008
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED   0x000c
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT   0x8002
 
#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR   0x8003
 
#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF   0xc820
 
#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK   0xff
 
#define MDIO_PMA_REG_8726_TX_CTRL1   0xca01
 
#define MDIO_PMA_REG_8726_TX_CTRL2   0xca05
 
#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005
 
#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF   0x8007
 
#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK   0xff
 
#define MDIO_PMA_REG_8727_TX_CTRL1   0xca02
 
#define MDIO_PMA_REG_8727_TX_CTRL2   0xca05
 
#define MDIO_PMA_REG_8727_PCS_OPT_CTRL   0xc808
 
#define MDIO_PMA_REG_8727_GPIO_CTRL   0xc80e
 
#define MDIO_PMA_REG_8727_PCS_GP   0xc842
 
#define MDIO_PMA_REG_8727_OPT_CFG_REG   0xc8e4
 
#define MDIO_AN_REG_8727_MISC_CTRL   0x8309
 
#define MDIO_PMA_REG_8073_CHIP_REV   0xc801
 
#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS   0xc820
 
#define MDIO_PMA_REG_8073_XAUI_WA   0xc841
 
#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL   0xcd08
 
#define MDIO_PMA_REG_7101_RESET   0xc000
 
#define MDIO_PMA_REG_7107_LED_CNTL   0xc007
 
#define MDIO_PMA_REG_7107_LINK_LED_CNTL   0xc009
 
#define MDIO_PMA_REG_7101_VER1   0xc026
 
#define MDIO_PMA_REG_7101_VER2   0xc027
 
#define MDIO_PMA_REG_8481_PMD_SIGNAL   0xa811
 
#define MDIO_PMA_REG_8481_LED1_MASK   0xa82c
 
#define MDIO_PMA_REG_8481_LED2_MASK   0xa82f
 
#define MDIO_PMA_REG_8481_LED3_MASK   0xa832
 
#define MDIO_PMA_REG_8481_LED3_BLINK   0xa834
 
#define MDIO_PMA_REG_8481_LED5_MASK   0xa838
 
#define MDIO_PMA_REG_8481_SIGNAL_MASK   0xa835
 
#define MDIO_PMA_REG_8481_LINK_SIGNAL   0xa83b
 
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK   0x800
 
#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT   11
 
#define MDIO_WIS_DEVAD   0x2
 
#define MDIO_WIS_REG_LASI_CNTL   0x9002
 
#define MDIO_WIS_REG_LASI_STATUS   0x9005
 
#define MDIO_PCS_DEVAD   0x3
 
#define MDIO_PCS_REG_STATUS   0x0020
 
#define MDIO_PCS_REG_LASI_STATUS   0x9005
 
#define MDIO_PCS_REG_7101_DSP_ACCESS   0xD000
 
#define MDIO_PCS_REG_7101_SPI_MUX   0xD008
 
#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR   0xE12A
 
#define MDIO_PCS_REG_7101_SPI_RESET_BIT   (5)
 
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR   0xE02A
 
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD   (6)
 
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)
 
#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD   (2)
 
#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR   0xE028
 
#define MDIO_XS_DEVAD   0x4
 
#define MDIO_XS_PLL_SEQUENCER   0x8000
 
#define MDIO_XS_SFX7101_XGXS_TEST1   0xc00a
 
#define MDIO_XS_8706_REG_BANK_RX0   0x80bc
 
#define MDIO_XS_8706_REG_BANK_RX1   0x80cc
 
#define MDIO_XS_8706_REG_BANK_RX2   0x80dc
 
#define MDIO_XS_8706_REG_BANK_RX3   0x80ec
 
#define MDIO_XS_8706_REG_BANK_RXA   0x80fc
 
#define MDIO_XS_REG_8073_RX_CTRL_PCIE   0x80FA
 
#define MDIO_AN_DEVAD   0x7
 
#define MDIO_AN_REG_CTRL   0x0000
 
#define MDIO_AN_REG_STATUS   0x0001
 
#define MDIO_AN_REG_STATUS_AN_COMPLETE   0x0020
 
#define MDIO_AN_REG_ADV_PAUSE   0x0010
 
#define MDIO_AN_REG_ADV_PAUSE_PAUSE   0x0400
 
#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC   0x0800
 
#define MDIO_AN_REG_ADV_PAUSE_BOTH   0x0C00
 
#define MDIO_AN_REG_ADV_PAUSE_MASK   0x0C00
 
#define MDIO_AN_REG_ADV   0x0011
 
#define MDIO_AN_REG_ADV2   0x0012
 
#define MDIO_AN_REG_LP_AUTO_NEG   0x0013
 
#define MDIO_AN_REG_LP_AUTO_NEG2   0x0014
 
#define MDIO_AN_REG_MASTER_STATUS   0x0021
 
#define MDIO_AN_REG_EEE_ADV   0x003c
 
#define MDIO_AN_REG_LP_EEE_ADV   0x003d
 
#define MDIO_AN_REG_LINK_STATUS   0x8304
 
#define MDIO_AN_REG_CL37_CL73   0x8370
 
#define MDIO_AN_REG_CL37_AN   0xffe0
 
#define MDIO_AN_REG_CL37_FC_LD   0xffe4
 
#define MDIO_AN_REG_CL37_FC_LP   0xffe5
 
#define MDIO_AN_REG_1000T_STATUS   0xffea
 
#define MDIO_AN_REG_8073_2_5G   0x8329
 
#define MDIO_AN_REG_8073_BAM   0x8350
 
#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL   0x0020
 
#define MDIO_AN_REG_8481_LEGACY_MII_CTRL   0xffe0
 
#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G   0x40
 
#define MDIO_AN_REG_8481_LEGACY_MII_STATUS   0xffe1
 
#define MDIO_AN_REG_8481_LEGACY_AN_ADV   0xffe4
 
#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION   0xffe6
 
#define MDIO_AN_REG_8481_1000T_CTRL   0xffe9
 
#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL   0xfff0
 
#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF   0x0008
 
#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW   0xfff5
 
#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS   0xfff7
 
#define MDIO_AN_REG_8481_AUX_CTRL   0xfff8
 
#define MDIO_AN_REG_8481_LEGACY_SHADOW   0xfffc
 
#define MDIO_CTL_DEVAD   0x1e
 
#define MDIO_CTL_REG_84823_MEDIA   0x401a
 
#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK   0x0018
 
#define MDIO_CTL_REG_84823_CTRL_MAC_XFI   0x0008
 
#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M   0x0010
 
#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK   0x0060
 
#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L   0x0020
 
#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI   0x0040
 
#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN   0x0080
 
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK   0x0100
 
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER   0x0000
 
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER   0x0100
 
#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G   0x1000
 
#define MDIO_CTL_REG_84823_USER_CTRL_REG   0x4005
 
#define MDIO_CTL_REG_84823_USER_CTRL_CMS   0x0080
 
#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH   0xa82b
 
#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ   0x2f
 
#define MDIO_PMA_REG_84823_CTL_LED_CTL_1   0xa8e3
 
#define MDIO_PMA_REG_84833_CTL_LED_CTL_1   0xa8ec
 
#define MDIO_PMA_REG_84823_LED3_STRETCH_EN   0x0080
 
#define MDIO_84833_TOP_CFG_FW_REV   0x400f
 
#define MDIO_84833_TOP_CFG_FW_EEE   0x10b1
 
#define MDIO_84833_TOP_CFG_FW_NO_EEE   0x1f81
 
#define MDIO_84833_TOP_CFG_XGPHY_STRAP1   0x401a
 
#define MDIO_84833_SUPER_ISOLATE   0x8000
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG0   0x4005
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG1   0x4006
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG2   0x4007
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG3   0x4008
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG4   0x4009
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG26   0x4037
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG27   0x4038
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG28   0x4039
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG29   0x403a
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG30   0x403b
 
#define MDIO_84833_TOP_CFG_SCRATCH_REG31   0x403c
 
#define MDIO_84833_CMD_HDLR_COMMAND   MDIO_84833_TOP_CFG_SCRATCH_REG0
 
#define MDIO_84833_CMD_HDLR_STATUS   MDIO_84833_TOP_CFG_SCRATCH_REG26
 
#define MDIO_84833_CMD_HDLR_DATA1   MDIO_84833_TOP_CFG_SCRATCH_REG27
 
#define MDIO_84833_CMD_HDLR_DATA2   MDIO_84833_TOP_CFG_SCRATCH_REG28
 
#define MDIO_84833_CMD_HDLR_DATA3   MDIO_84833_TOP_CFG_SCRATCH_REG29
 
#define MDIO_84833_CMD_HDLR_DATA4   MDIO_84833_TOP_CFG_SCRATCH_REG30
 
#define MDIO_84833_CMD_HDLR_DATA5   MDIO_84833_TOP_CFG_SCRATCH_REG31
 
#define PHY84833_CMD_SET_PAIR_SWAP   0x8001
 
#define PHY84833_CMD_GET_EEE_MODE   0x8008
 
#define PHY84833_CMD_SET_EEE_MODE   0x8009
 
#define PHY84833_STATUS_CMD_RECEIVED   0x0001
 
#define PHY84833_STATUS_CMD_IN_PROGRESS   0x0002
 
#define PHY84833_STATUS_CMD_COMPLETE_PASS   0x0004
 
#define PHY84833_STATUS_CMD_COMPLETE_ERROR   0x0008
 
#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS   0x0010
 
#define PHY84833_STATUS_CMD_SYSTEM_BOOT   0x0020
 
#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS   0x0040
 
#define PHY84833_STATUS_CMD_CLEAR_COMPLETE   0x0080
 
#define PHY84833_STATUS_CMD_OPEN_OVERRIDE   0xa5a5
 
#define MDIO_WC_DEVAD   0x3
 
#define MDIO_WC_REG_IEEE0BLK_MIICNTL   0x0
 
#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP   0x7
 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0   0x10
 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1   0x11
 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2   0x12
 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY   0x4000
 
#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ   0x8000
 
#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150   0x96
 
#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL   0x8000
 
#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1   0x800e
 
#define MDIO_WC_REG_XGXSBLK1_DESKEW   0x8010
 
#define MDIO_WC_REG_XGXSBLK1_LANECTRL0   0x8015
 
#define MDIO_WC_REG_XGXSBLK1_LANECTRL1   0x8016
 
#define MDIO_WC_REG_XGXSBLK1_LANECTRL2   0x8017
 
#define MDIO_WC_REG_TX0_ANA_CTRL0   0x8061
 
#define MDIO_WC_REG_TX1_ANA_CTRL0   0x8071
 
#define MDIO_WC_REG_TX2_ANA_CTRL0   0x8081
 
#define MDIO_WC_REG_TX3_ANA_CTRL0   0x8091
 
#define MDIO_WC_REG_TX0_TX_DRIVER   0x8067
 
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET   0x04
 
#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK   0x00f0
 
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET   0x08
 
#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00
 
#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET   0x0c
 
#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK   0x7000
 
#define MDIO_WC_REG_TX1_TX_DRIVER   0x8077
 
#define MDIO_WC_REG_TX2_TX_DRIVER   0x8087
 
#define MDIO_WC_REG_TX3_TX_DRIVER   0x8097
 
#define MDIO_WC_REG_RX0_ANARXCONTROL1G   0x80b9
 
#define MDIO_WC_REG_RX2_ANARXCONTROL1G   0x80d9
 
#define MDIO_WC_REG_RX0_PCI_CTRL   0x80ba
 
#define MDIO_WC_REG_RX1_PCI_CTRL   0x80ca
 
#define MDIO_WC_REG_RX2_PCI_CTRL   0x80da
 
#define MDIO_WC_REG_RX3_PCI_CTRL   0x80ea
 
#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G   0x8104
 
#define MDIO_WC_REG_XGXS_STATUS3   0x8129
 
#define MDIO_WC_REG_PAR_DET_10G_STATUS   0x8130
 
#define MDIO_WC_REG_PAR_DET_10G_CTRL   0x8131
 
#define MDIO_WC_REG_XGXS_X2_CONTROL2   0x8141
 
#define MDIO_WC_REG_XGXS_RX_LN_SWAP1   0x816B
 
#define MDIO_WC_REG_XGXS_TX_LN_SWAP1   0x8169
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_0   0x81d0
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_1   0x81d1
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_2   0x81d2
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_3   0x81d3
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_4   0x81d4
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL   0x1000
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL   0x0100
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP   0x0010
 
#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP   0x1
 
#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP   0x81EE
 
#define MDIO_WC_REG_UC_INFO_B1_VERSION   0x81F0
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE   0x81F2
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET   0x0
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT   0x0
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR   0x1
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC   0x2
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI   0x3
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G   0x4
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET   0x4
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET   0x8
 
#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET   0xc
 
#define MDIO_WC_REG_UC_INFO_B1_CRC   0x81FE
 
#define MDIO_WC_REG_DSC_SMC   0x8213
 
#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0   0x821e
 
#define MDIO_WC_REG_TX_FIR_TAP   0x82e2
 
#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET   0x00
 
#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK   0x000f
 
#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET   0x04
 
#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK   0x03f0
 
#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET   0x0a
 
#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK   0x7c00
 
#define MDIO_WC_REG_TX_FIR_TAP_ENABLE   0x8000
 
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL   0x82e3
 
#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL   0x82e6
 
#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL   0x82e7
 
#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL   0x82e8
 
#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL   0x82ec
 
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1   0x8300
 
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2   0x8301
 
#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3   0x8302
 
#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1   0x8304
 
#define MDIO_WC_REG_SERDESDIGITAL_MISC1   0x8308
 
#define MDIO_WC_REG_SERDESDIGITAL_MISC2   0x8309
 
#define MDIO_WC_REG_DIGITAL3_UP1   0x8329
 
#define MDIO_WC_REG_DIGITAL3_LP_UP1   0x832c
 
#define MDIO_WC_REG_DIGITAL4_MISC3   0x833c
 
#define MDIO_WC_REG_DIGITAL4_MISC5   0x833e
 
#define MDIO_WC_REG_DIGITAL5_MISC6   0x8345
 
#define MDIO_WC_REG_DIGITAL5_MISC7   0x8349
 
#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED   0x834e
 
#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL   0x8350
 
#define MDIO_WC_REG_CL49_USERB0_CTRL   0x8368
 
#define MDIO_WC_REG_EEE_COMBO_CONTROL0   0x8390
 
#define MDIO_WC_REG_TX66_CONTROL   0x83b0
 
#define MDIO_WC_REG_RX66_CONTROL   0x83c0
 
#define MDIO_WC_REG_RX66_SCW0   0x83c2
 
#define MDIO_WC_REG_RX66_SCW1   0x83c3
 
#define MDIO_WC_REG_RX66_SCW2   0x83c4
 
#define MDIO_WC_REG_RX66_SCW3   0x83c5
 
#define MDIO_WC_REG_RX66_SCW0_MASK   0x83c6
 
#define MDIO_WC_REG_RX66_SCW1_MASK   0x83c7
 
#define MDIO_WC_REG_RX66_SCW2_MASK   0x83c8
 
#define MDIO_WC_REG_RX66_SCW3_MASK   0x83c9
 
#define MDIO_WC_REG_FX100_CTRL1   0x8400
 
#define MDIO_WC_REG_FX100_CTRL3   0x8402
 
#define MDIO_WC_REG_MICROBLK_CMD   0xffc2
 
#define MDIO_WC_REG_MICROBLK_DL_STATUS   0xffc5
 
#define MDIO_WC_REG_MICROBLK_CMD3   0xffcc
 
#define MDIO_WC_REG_AERBLK_AER   0xffde
 
#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL   0xffe0
 
#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT   0xffe1
 
#define MDIO_WC0_XGXS_BLK2_LANE_RESET   0x810A
 
#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT   0
 
#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT   4
 
#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2   0x8141
 
#define DIGITAL5_ACTUAL_SPEED_TX_MASK   0x003f
 
#define MDIO_REG_GPHY_PHYID_LSB   0x3
 
#define MDIO_REG_GPHY_ID_54618SE   0x5cd5
 
#define MDIO_REG_GPHY_CL45_ADDR_REG   0xd
 
#define MDIO_REG_GPHY_CL45_DATA_REG   0xe
 
#define MDIO_REG_GPHY_EEE_RESOLVED   0x803e
 
#define MDIO_REG_GPHY_EXP_ACCESS_GATE   0x15
 
#define MDIO_REG_GPHY_EXP_ACCESS   0x17
 
#define MDIO_REG_GPHY_EXP_ACCESS_TOP   0xd00
 
#define MDIO_REG_GPHY_EXP_TOP_2K_BUF   0x40
 
#define MDIO_REG_GPHY_AUX_STATUS   0x19
 
#define MDIO_REG_INTR_STATUS   0x1a
 
#define MDIO_REG_INTR_MASK   0x1b
 
#define MDIO_REG_INTR_MASK_LINK_STATUS   (0x1 << 1)
 
#define MDIO_REG_GPHY_SHADOW   0x1c
 
#define MDIO_REG_GPHY_SHADOW_LED_SEL1   (0x0d << 10)
 
#define MDIO_REG_GPHY_SHADOW_LED_SEL2   (0x0e << 10)
 
#define MDIO_REG_GPHY_SHADOW_WR_ENA   (0x1 << 15)
 
#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED   (0x1e << 10)
 
#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD   (0x1 << 8)
 
#define IGU_FUNC_BASE   0x0400
 
#define IGU_ADDR_MSIX   0x0000
 
#define IGU_ADDR_INT_ACK   0x0200
 
#define IGU_ADDR_PROD_UPD   0x0201
 
#define IGU_ADDR_ATTN_BITS_UPD   0x0202
 
#define IGU_ADDR_ATTN_BITS_SET   0x0203
 
#define IGU_ADDR_ATTN_BITS_CLR   0x0204
 
#define IGU_ADDR_COALESCE_NOW   0x0205
 
#define IGU_ADDR_SIMD_MASK   0x0206
 
#define IGU_ADDR_SIMD_NOMASK   0x0207
 
#define IGU_ADDR_MSI_CTL   0x0210
 
#define IGU_ADDR_MSI_ADDR_LO   0x0211
 
#define IGU_ADDR_MSI_ADDR_HI   0x0212
 
#define IGU_ADDR_MSI_DATA   0x0213
 
#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup   0
 
#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup   1
 
#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup   2
 
#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup   3
 
#define COMMAND_REG_INT_ACK   0x0
 
#define COMMAND_REG_PROD_UPD   0x4
 
#define COMMAND_REG_ATTN_BITS_UPD   0x8
 
#define COMMAND_REG_ATTN_BITS_SET   0xc
 
#define COMMAND_REG_ATTN_BITS_CLR   0x10
 
#define COMMAND_REG_COALESCE_NOW   0x14
 
#define COMMAND_REG_SIMD_MASK   0x18
 
#define COMMAND_REG_SIMD_NOMASK   0x1c
 
#define IGU_MEM_BASE   0x0000
 
#define IGU_MEM_MSIX_BASE   0x0000
 
#define IGU_MEM_MSIX_UPPER   0x007f
 
#define IGU_MEM_MSIX_RESERVED_UPPER   0x01ff
 
#define IGU_MEM_PBA_MSIX_BASE   0x0200
 
#define IGU_MEM_PBA_MSIX_UPPER   0x0200
 
#define IGU_CMD_BACKWARD_COMP_PROD_UPD   0x0201
 
#define IGU_MEM_PBA_MSIX_RESERVED_UPPER   0x03ff
 
#define IGU_CMD_INT_ACK_BASE   0x0400
 
#define IGU_CMD_INT_ACK_UPPER   (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
 
#define IGU_CMD_INT_ACK_RESERVED_UPPER   0x04ff
 
#define IGU_CMD_E2_PROD_UPD_BASE   0x0500
 
#define IGU_CMD_E2_PROD_UPD_UPPER   (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
 
#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER   0x059f
 
#define IGU_CMD_ATTN_BIT_UPD_UPPER   0x05a0
 
#define IGU_CMD_ATTN_BIT_SET_UPPER   0x05a1
 
#define IGU_CMD_ATTN_BIT_CLR_UPPER   0x05a2
 
#define IGU_REG_SISR_MDPC_WMASK_UPPER   0x05a3
 
#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER   0x05a4
 
#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER   0x05a5
 
#define IGU_REG_SISR_MDPC_WOMASK_UPPER   0x05a6
 
#define IGU_REG_RESERVED_UPPER   0x05ff
 
#define IGU_PF_CONF_FUNC_EN   (0x1<<0) /* function enable */
 
#define IGU_PF_CONF_MSI_MSIX_EN   (0x1<<1) /* MSI/MSIX enable */
 
#define IGU_PF_CONF_INT_LINE_EN   (0x1<<2) /* INT enable */
 
#define IGU_PF_CONF_ATTN_BIT_EN   (0x1<<3) /* attention enable */
 
#define IGU_PF_CONF_SINGLE_ISR_EN   (0x1<<4) /* single ISR mode enable */
 
#define IGU_PF_CONF_SIMD_MODE   (0x1<<5) /* simd all ones mode */
 
#define IGU_VF_CONF_FUNC_EN   (0x1<<0) /* function enable */
 
#define IGU_VF_CONF_MSI_MSIX_EN   (0x1<<1) /* MSI/MSIX enable */
 
#define IGU_VF_CONF_PARENT_MASK   (0x3<<2) /* Parent PF */
 
#define IGU_VF_CONF_PARENT_SHIFT   2 /* Parent PF */
 
#define IGU_VF_CONF_SINGLE_ISR_EN   (0x1<<4) /* single ISR mode enable */
 
#define IGU_BC_DSB_NUM_SEGS   5
 
#define IGU_BC_NDSB_NUM_SEGS   2
 
#define IGU_NORM_DSB_NUM_SEGS   2
 
#define IGU_NORM_NDSB_NUM_SEGS   1
 
#define IGU_BC_BASE_DSB_PROD   128
 
#define IGU_NORM_BASE_DSB_PROD   136
 
#define IGU_FID_ENCODE_IS_PF   (0x1<<6)
 
#define IGU_FID_ENCODE_IS_PF_SHIFT   6
 
#define IGU_FID_VF_NUM_MASK   (0x3f)
 
#define IGU_FID_PF_NUM_MASK   (0x7)
 
#define IGU_REG_MAPPING_MEMORY_VALID   (1<<0)
 
#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK   (0x3F<<1)
 
#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT   1
 
#define IGU_REG_MAPPING_MEMORY_FID_MASK   (0x7F<<7)
 
#define IGU_REG_MAPPING_MEMORY_FID_SHIFT   7
 
#define CDU_REGION_NUMBER_XCM_AG   2
 
#define CDU_REGION_NUMBER_UCM_AG   4
 
#define CDU_VALID_DATA(_cid, _region, _type)   (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
 
#define CDU_CRC8(_cid, _region, _type)   (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
 
#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)   (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
 
#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)   (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
 
#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val)   ((_val) & ~0x80)
 

Macro Definition Documentation

#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT   (0x1<<4)

Definition at line 5937 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR   (0x1<<5)

Definition at line 5938 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR   (0x1<<18)

Definition at line 5939 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT   (0x1<<31)

Definition at line 5940 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR   (0x1<<30)

Definition at line 5941 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT   (0x1<<9)

Definition at line 5942 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR   (0x1<<8)

Definition at line 5943 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT   (0x1<<7)

Definition at line 5944 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR   (0x1<<6)

Definition at line 5945 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT   (0x1<<29)

Definition at line 5946 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR   (0x1<<28)

Definition at line 5947 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT   (0x1<<1)

Definition at line 5948 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR   (0x1<<0)

Definition at line 5949 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR   (0x1<<18)

Definition at line 5950 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT   (0x1<<11)

Definition at line 5951 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR   (0x1<<10)

Definition at line 5952 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT   (0x1<<13)

Definition at line 5953 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR   (0x1<<12)

Definition at line 5954 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0   (0x1<<2)

Definition at line 5955 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0   (0x1<<5)

Definition at line 6002 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1   (0x1<<9)

Definition at line 6003 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR   (0x1<<12)

Definition at line 5956 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY   (0x1<<28)

Definition at line 5957 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY   (0x1<<31)

Definition at line 5958 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY   (0x1<<29)

Definition at line 5959 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY   (0x1<<30)

Definition at line 5960 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT   (0x1<<15)

Definition at line 5961 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR   (0x1<<14)

Definition at line 5962 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR   (0x1<<14)

Definition at line 5963 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR   (0x1<<20)

Definition at line 5964 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT   (0x1<<31)

Definition at line 5965 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR   (0x1<<30)

Definition at line 5966 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR   (0x1<<0)

Definition at line 5967 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT   (0x1<<2)

Definition at line 5968 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR   (0x1<<3)

Definition at line 5969 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT   (0x1<<3)

Definition at line 5972 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR   (0x1<<2)

Definition at line 5973 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT   (0x1<<5)

Definition at line 5970 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR   (0x1<<4)

Definition at line 5971 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT   (0x1<<3)

Definition at line 5974 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR   (0x1<<2)

Definition at line 5975 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR   (0x1<<22)

Definition at line 5976 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_SPIO5   (0x1<<15)

Definition at line 5977 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT   (0x1<<27)

Definition at line 5978 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR   (0x1<<26)

Definition at line 5979 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT   (0x1<<5)

Definition at line 5980 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR   (0x1<<4)

Definition at line 5981 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT   (0x1<<25)

Definition at line 5982 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR   (0x1<<24)

Definition at line 5983 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT   (0x1<<29)

Definition at line 5984 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR   (0x1<<28)

Definition at line 5985 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT   (0x1<<23)

Definition at line 5986 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR   (0x1<<22)

Definition at line 5987 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT   (0x1<<27)

Definition at line 5988 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR   (0x1<<26)

Definition at line 5989 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT   (0x1<<21)

Definition at line 5990 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR   (0x1<<20)

Definition at line 5991 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT   (0x1<<25)

Definition at line 5992 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR   (0x1<<24)

Definition at line 5993 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR   (0x1<<16)

Definition at line 5994 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT   (0x1<<9)

Definition at line 5995 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR   (0x1<<8)

Definition at line 5996 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT   (0x1<<7)

Definition at line 5997 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR   (0x1<<6)

Definition at line 5998 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT   (0x1<<11)

Definition at line 5999 of file bnx2x_reg.h.

#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR   (0x1<<10)

Definition at line 6000 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR   (0x1<<0)

Definition at line 24 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS   (0x1<<2)

Definition at line 25 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU   (0x1<<5)

Definition at line 26 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT   (0x1<<3)

Definition at line 27 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR   (0x1<<4)

Definition at line 28 of file bnx2x_reg.h.

#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND   (0x1<<1)

Definition at line 29 of file bnx2x_reg.h.

#define ATC_REG_ATC_INIT_ARRAY   0x1100b8

Definition at line 31 of file bnx2x_reg.h.

#define ATC_REG_ATC_INIT_DONE   0x1100bc

Definition at line 33 of file bnx2x_reg.h.

#define ATC_REG_ATC_INT_STS_CLR   0x1101c0

Definition at line 35 of file bnx2x_reg.h.

#define ATC_REG_ATC_PRTY_MASK   0x1101d8

Definition at line 37 of file bnx2x_reg.h.

#define ATC_REG_ATC_PRTY_STS_CLR   0x1101d0

Definition at line 39 of file bnx2x_reg.h.

#define BAR_CSTRORM_INTMEM   0x410000

Definition at line 6431 of file bnx2x_reg.h.

#define BAR_CSTRORM_INTMEM   0x410000

Definition at line 6431 of file bnx2x_reg.h.

#define BAR_DOORBELL_OFFSET   0x800000

Definition at line 6438 of file bnx2x_reg.h.

#define BAR_DOORBELL_OFFSET   0x800000

Definition at line 6438 of file bnx2x_reg.h.

#define BAR_IGU_INTMEM   0x440000

Definition at line 6436 of file bnx2x_reg.h.

#define BAR_IGU_INTMEM   0x440000

Definition at line 6436 of file bnx2x_reg.h.

#define BAR_ME_REGISTER   0x450000

Definition at line 6440 of file bnx2x_reg.h.

#define BAR_ME_REGISTER   0x450000

Definition at line 6440 of file bnx2x_reg.h.

#define BAR_TSTRORM_INTMEM   0x430000

Definition at line 6433 of file bnx2x_reg.h.

#define BAR_TSTRORM_INTMEM   0x430000

Definition at line 6433 of file bnx2x_reg.h.

#define BAR_USTRORM_INTMEM   0x400000

Definition at line 6430 of file bnx2x_reg.h.

#define BAR_USTRORM_INTMEM   0x400000

Definition at line 6430 of file bnx2x_reg.h.

#define BAR_XSTRORM_INTMEM   0x420000

Definition at line 6432 of file bnx2x_reg.h.

#define BAR_XSTRORM_INTMEM   0x420000

Definition at line 6432 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_BMAC_CONTROL   (0x00<<3)

Definition at line 5772 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL   (0x01<<3)

Definition at line 5773 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_CNT_MAX_SIZE   (0x05<<3)

Definition at line 5774 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_PFC_CONTROL   (0x06<<3)

Definition at line 5775 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_CONTROL   (0x3A<<3)

Definition at line 5776 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS   (0x62<<3)

Definition at line 5777 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_LSS_STAT   (0x3E<<3)

Definition at line 5778 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_MAX_SIZE   (0x3C<<3)

Definition at line 5779 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_STAT_GR64   (0x40<<3)

Definition at line 5780 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_STAT_GRIPJ   (0x5f<<3)

Definition at line 5781 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_RX_STAT_GRPP   (0x51<<3)

Definition at line 5782 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_CONTROL   (0x1C<<3)

Definition at line 5783 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_MAX_SIZE   (0x1E<<3)

Definition at line 5784 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL   (0x20<<3)

Definition at line 5785 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_SOURCE_ADDR   (0x1D<<3)

Definition at line 5786 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_STAT_GTBYT   (0x39<<3)

Definition at line 5787 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_STAT_GTPOK   (0x22<<3)

Definition at line 5788 of file bnx2x_reg.h.

#define BIGMAC2_REGISTER_TX_STAT_GTPP   (0x24<<3)

Definition at line 5789 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_BMAC_CONTROL   (0x00<<3)

Definition at line 5757 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL   (0x01<<3)

Definition at line 5758 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_CNT_MAX_SIZE   (0x05<<3)

Definition at line 5759 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_CONTROL   (0x21<<3)

Definition at line 5760 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS   (0x46<<3)

Definition at line 5761 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_LSS_STATUS   (0x43<<3)

Definition at line 5762 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_MAX_SIZE   (0x23<<3)

Definition at line 5763 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_STAT_GR64   (0x26<<3)

Definition at line 5764 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_RX_STAT_GRIPJ   (0x42<<3)

Definition at line 5765 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_CONTROL   (0x07<<3)

Definition at line 5766 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_MAX_SIZE   (0x09<<3)

Definition at line 5767 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD   (0x0A<<3)

Definition at line 5768 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_SOURCE_ADDR   (0x08<<3)

Definition at line 5769 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_STAT_GTBYT   (0x20<<3)

Definition at line 5770 of file bnx2x_reg.h.

#define BIGMAC_REGISTER_TX_STAT_GTPKT   (0x0C<<3)

Definition at line 5771 of file bnx2x_reg.h.

#define BRB1_REG_BRB1_INT_MASK   0x60128

Definition at line 41 of file bnx2x_reg.h.

#define BRB1_REG_BRB1_INT_STS   0x6011c

Definition at line 43 of file bnx2x_reg.h.

#define BRB1_REG_BRB1_PRTY_MASK   0x60138

Definition at line 45 of file bnx2x_reg.h.

#define BRB1_REG_BRB1_PRTY_STS   0x6012c

Definition at line 47 of file bnx2x_reg.h.

#define BRB1_REG_BRB1_PRTY_STS_CLR   0x60130

Definition at line 49 of file bnx2x_reg.h.

#define BRB1_REG_FREE_LIST_PRS_CRDT   0x60200

Definition at line 57 of file bnx2x_reg.h.

#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0   0x601d0

Definition at line 60 of file bnx2x_reg.h.

#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1   0x60230

Definition at line 61 of file bnx2x_reg.h.

#define BRB1_REG_FULL_0_XON_THRESHOLD_0   0x601d4

Definition at line 64 of file bnx2x_reg.h.

#define BRB1_REG_FULL_0_XON_THRESHOLD_1   0x60234

Definition at line 65 of file bnx2x_reg.h.

#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0   0x601d8

Definition at line 68 of file bnx2x_reg.h.

#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1   0x60238

Definition at line 69 of file bnx2x_reg.h.

#define BRB1_REG_FULL_1_XON_THRESHOLD_0   0x601dc

Definition at line 72 of file bnx2x_reg.h.

#define BRB1_REG_FULL_1_XON_THRESHOLD_1   0x6023c

Definition at line 73 of file bnx2x_reg.h.

#define BRB1_REG_FULL_LB_XOFF_THRESHOLD   0x601e0

Definition at line 76 of file bnx2x_reg.h.

#define BRB1_REG_FULL_LB_XON_THRESHOLD   0x601e4

Definition at line 79 of file bnx2x_reg.h.

#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0   0x6014c

Definition at line 82 of file bnx2x_reg.h.

#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0   0x6013c

Definition at line 85 of file bnx2x_reg.h.

#define BRB1_REG_LB_GUARANTIED   0x601ec

Definition at line 87 of file bnx2x_reg.h.

#define BRB1_REG_LB_GUARANTIED_HYST   0x60264

Definition at line 90 of file bnx2x_reg.h.

#define BRB1_REG_LL_RAM   0x61000

Definition at line 92 of file bnx2x_reg.h.

#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0   0x6016c

Definition at line 95 of file bnx2x_reg.h.

#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0   0x6015c

Definition at line 98 of file bnx2x_reg.h.

#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED   0x60244

Definition at line 101 of file bnx2x_reg.h.

#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST   0x60254

Definition at line 105 of file bnx2x_reg.h.

#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED   0x60248

Definition at line 108 of file bnx2x_reg.h.

#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST   0x60258

Definition at line 112 of file bnx2x_reg.h.

#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED   0x6024c

Definition at line 115 of file bnx2x_reg.h.

#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST   0x6025c

Definition at line 119 of file bnx2x_reg.h.

#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED   0x60250

Definition at line 122 of file bnx2x_reg.h.

#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST   0x60260

Definition at line 126 of file bnx2x_reg.h.

#define BRB1_REG_MAC_GUARANTIED_0   0x601e8

Definition at line 129 of file bnx2x_reg.h.

#define BRB1_REG_MAC_GUARANTIED_1   0x60240

Definition at line 130 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_FULL_BLOCKS   0x60090

Definition at line 132 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_FULL_CYCLES_0   0x600c8

Definition at line 135 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_FULL_CYCLES_1   0x600cc

Definition at line 136 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_FULL_CYCLES_4   0x600d8

Definition at line 137 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0   0x600b8

Definition at line 140 of file bnx2x_reg.h.

#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1   0x600bc

Definition at line 141 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0   0x601c0

Definition at line 144 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1   0x60220

Definition at line 145 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0   0x601c4

Definition at line 148 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1   0x60224

Definition at line 149 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0   0x601c8

Definition at line 152 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1   0x60228

Definition at line 153 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0   0x601cc

Definition at line 156 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1   0x6022c

Definition at line 157 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0   0x60078

Definition at line 159 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1   0x6007c

Definition at line 160 of file bnx2x_reg.h.

#define BRB1_REG_PAUSE_LOW_THRESHOLD_0   0x60068

Definition at line 162 of file bnx2x_reg.h.

#define BRB1_REG_PER_CLASS_GUARANTY_MODE   0x60268

Definition at line 166 of file bnx2x_reg.h.

#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0   0x60094

Definition at line 168 of file bnx2x_reg.h.

#define BRB1_REG_SOFT_RESET   0x600dc

Definition at line 170 of file bnx2x_reg.h.

#define CCM_REG_CAM_OCCUP   0xd0188

Definition at line 172 of file bnx2x_reg.h.

#define CCM_REG_CCM_CFC_IFEN   0xd003c

Definition at line 176 of file bnx2x_reg.h.

#define CCM_REG_CCM_CQM_IFEN   0xd000c

Definition at line 180 of file bnx2x_reg.h.

#define CCM_REG_CCM_CQM_USE_Q   0xd00c0

Definition at line 183 of file bnx2x_reg.h.

#define CCM_REG_CCM_INT_MASK   0xd01e4

Definition at line 185 of file bnx2x_reg.h.

#define CCM_REG_CCM_INT_STS   0xd01d8

Definition at line 187 of file bnx2x_reg.h.

#define CCM_REG_CCM_PRTY_MASK   0xd01f4

Definition at line 189 of file bnx2x_reg.h.

#define CCM_REG_CCM_PRTY_STS   0xd01e8

Definition at line 191 of file bnx2x_reg.h.

#define CCM_REG_CCM_PRTY_STS_CLR   0xd01ec

Definition at line 193 of file bnx2x_reg.h.

#define CCM_REG_CCM_REG0_SZ   0xd00c4

Definition at line 198 of file bnx2x_reg.h.

#define CCM_REG_CCM_STORM0_IFEN   0xd0004

Definition at line 202 of file bnx2x_reg.h.

#define CCM_REG_CCM_STORM1_IFEN   0xd0008

Definition at line 206 of file bnx2x_reg.h.

#define CCM_REG_CDU_AG_RD_IFEN   0xd0030

Definition at line 210 of file bnx2x_reg.h.

#define CCM_REG_CDU_AG_WR_IFEN   0xd002c

Definition at line 214 of file bnx2x_reg.h.

#define CCM_REG_CDU_SM_RD_IFEN   0xd0038

Definition at line 218 of file bnx2x_reg.h.

#define CCM_REG_CDU_SM_WR_IFEN   0xd0034

Definition at line 222 of file bnx2x_reg.h.

#define CCM_REG_CFC_INIT_CRD   0xd0204

Definition at line 226 of file bnx2x_reg.h.

#define CCM_REG_CNT_AUX1_Q   0xd00c8

Definition at line 228 of file bnx2x_reg.h.

#define CCM_REG_CNT_AUX2_Q   0xd00cc

Definition at line 230 of file bnx2x_reg.h.

#define CCM_REG_CQM_CCM_HDR_P   0xd008c

Definition at line 232 of file bnx2x_reg.h.

#define CCM_REG_CQM_CCM_HDR_S   0xd0090

Definition at line 234 of file bnx2x_reg.h.

#define CCM_REG_CQM_CCM_IFEN   0xd0014

Definition at line 238 of file bnx2x_reg.h.

#define CCM_REG_CQM_INIT_CRD   0xd020c

Definition at line 242 of file bnx2x_reg.h.

#define CCM_REG_CQM_P_WEIGHT   0xd00b8

Definition at line 246 of file bnx2x_reg.h.

#define CCM_REG_CQM_S_WEIGHT   0xd00bc

Definition at line 250 of file bnx2x_reg.h.

#define CCM_REG_CSDM_IFEN   0xd0018

Definition at line 254 of file bnx2x_reg.h.

#define CCM_REG_CSDM_LENGTH_MIS   0xd0170

Definition at line 257 of file bnx2x_reg.h.

#define CCM_REG_CSDM_WEIGHT   0xd00b4

Definition at line 261 of file bnx2x_reg.h.

#define CCM_REG_ERR_CCM_HDR   0xd0094

Definition at line 264 of file bnx2x_reg.h.

#define CCM_REG_ERR_EVNT_ID   0xd0098

Definition at line 266 of file bnx2x_reg.h.

#define CCM_REG_FIC0_INIT_CRD   0xd0210

Definition at line 270 of file bnx2x_reg.h.

#define CCM_REG_FIC1_INIT_CRD   0xd0214

Definition at line 274 of file bnx2x_reg.h.

#define CCM_REG_GR_ARB_TYPE   0xd015c

Definition at line 280 of file bnx2x_reg.h.

#define CCM_REG_GR_LD0_PR   0xd0164

Definition at line 285 of file bnx2x_reg.h.

#define CCM_REG_GR_LD1_PR   0xd0168

Definition at line 290 of file bnx2x_reg.h.

#define CCM_REG_INV_DONE_Q   0xd0108

Definition at line 292 of file bnx2x_reg.h.

#define CCM_REG_N_SM_CTX_LD_0   0xd004c

Definition at line 298 of file bnx2x_reg.h.

#define CCM_REG_N_SM_CTX_LD_1   0xd0050

Definition at line 299 of file bnx2x_reg.h.

#define CCM_REG_N_SM_CTX_LD_2   0xd0054

Definition at line 300 of file bnx2x_reg.h.

#define CCM_REG_N_SM_CTX_LD_3   0xd0058

Definition at line 301 of file bnx2x_reg.h.

#define CCM_REG_N_SM_CTX_LD_4   0xd005c

Definition at line 302 of file bnx2x_reg.h.

#define CCM_REG_PBF_IFEN   0xd0028

Definition at line 306 of file bnx2x_reg.h.

#define CCM_REG_PBF_LENGTH_MIS   0xd0180

Definition at line 309 of file bnx2x_reg.h.

#define CCM_REG_PBF_WEIGHT   0xd00ac

Definition at line 313 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM1_0   0xd0134

Definition at line 314 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM1_1   0xd0138

Definition at line 315 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM2_0   0xd013c

Definition at line 316 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM2_1   0xd0140

Definition at line 317 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM3_0   0xd0144

Definition at line 318 of file bnx2x_reg.h.

#define CCM_REG_PHYS_QNUM3_1   0xd0148

Definition at line 319 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM0_0   0xd0114

Definition at line 320 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM0_1   0xd0118

Definition at line 321 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM1_0   0xd011c

Definition at line 322 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM1_1   0xd0120

Definition at line 323 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM2_0   0xd0124

Definition at line 324 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM2_1   0xd0128

Definition at line 325 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM3_0   0xd012c

Definition at line 326 of file bnx2x_reg.h.

#define CCM_REG_QOS_PHYS_QNUM3_1   0xd0130

Definition at line 327 of file bnx2x_reg.h.

#define CCM_REG_STORM_CCM_IFEN   0xd0010

Definition at line 331 of file bnx2x_reg.h.

#define CCM_REG_STORM_LENGTH_MIS   0xd016c

Definition at line 334 of file bnx2x_reg.h.

#define CCM_REG_STORM_WEIGHT   0xd009c

Definition at line 339 of file bnx2x_reg.h.

#define CCM_REG_TSEM_IFEN   0xd001c

Definition at line 343 of file bnx2x_reg.h.

#define CCM_REG_TSEM_LENGTH_MIS   0xd0174

Definition at line 346 of file bnx2x_reg.h.

#define CCM_REG_TSEM_WEIGHT   0xd00a0

Definition at line 350 of file bnx2x_reg.h.

#define CCM_REG_USEM_IFEN   0xd0024

Definition at line 354 of file bnx2x_reg.h.

#define CCM_REG_USEM_LENGTH_MIS   0xd017c

Definition at line 357 of file bnx2x_reg.h.

#define CCM_REG_USEM_WEIGHT   0xd00a8

Definition at line 361 of file bnx2x_reg.h.

#define CCM_REG_XSEM_IFEN   0xd0020

Definition at line 365 of file bnx2x_reg.h.

#define CCM_REG_XSEM_LENGTH_MIS   0xd0178

Definition at line 368 of file bnx2x_reg.h.

#define CCM_REG_XSEM_WEIGHT   0xd00a4

Definition at line 372 of file bnx2x_reg.h.

#define CCM_REG_XX_DESCR_TABLE   0xd0300

Definition at line 376 of file bnx2x_reg.h.

#define CCM_REG_XX_DESCR_TABLE_SIZE   24

Definition at line 377 of file bnx2x_reg.h.

#define CCM_REG_XX_FREE   0xd0184

Definition at line 379 of file bnx2x_reg.h.

#define CCM_REG_XX_INIT_CRD   0xd0220

Definition at line 385 of file bnx2x_reg.h.

#define CCM_REG_XX_MSG_NUM   0xd0224

Definition at line 390 of file bnx2x_reg.h.

#define CCM_REG_XX_OVFL_EVNT_ID   0xd0044

Definition at line 392 of file bnx2x_reg.h.

#define CCM_REG_XX_TABLE   0xd0280

Definition at line 396 of file bnx2x_reg.h.

#define CDU_CRC8 (   _cid,
  _region,
  _type 
)    (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))

Definition at line 7224 of file bnx2x_reg.h.

#define CDU_REG_CDU_CHK_MASK0   0x101000

Definition at line 397 of file bnx2x_reg.h.

#define CDU_REG_CDU_CHK_MASK1   0x101004

Definition at line 398 of file bnx2x_reg.h.

#define CDU_REG_CDU_CONTROL0   0x101008

Definition at line 399 of file bnx2x_reg.h.

#define CDU_REG_CDU_DEBUG   0x101010

Definition at line 400 of file bnx2x_reg.h.

#define CDU_REG_CDU_GLOBAL_PARAMS   0x101020

Definition at line 401 of file bnx2x_reg.h.

#define CDU_REG_CDU_INT_MASK   0x10103c

Definition at line 403 of file bnx2x_reg.h.

#define CDU_REG_CDU_INT_STS   0x101030

Definition at line 405 of file bnx2x_reg.h.

#define CDU_REG_CDU_PRTY_MASK   0x10104c

Definition at line 407 of file bnx2x_reg.h.

#define CDU_REG_CDU_PRTY_STS   0x101040

Definition at line 409 of file bnx2x_reg.h.

#define CDU_REG_CDU_PRTY_STS_CLR   0x101044

Definition at line 411 of file bnx2x_reg.h.

#define CDU_REG_ERROR_DATA   0x101014

Definition at line 415 of file bnx2x_reg.h.

#define CDU_REG_L1TT   0x101800

Definition at line 419 of file bnx2x_reg.h.

#define CDU_REG_MATT   0x101100

Definition at line 422 of file bnx2x_reg.h.

#define CDU_REG_MF_MODE   0x101050

Definition at line 424 of file bnx2x_reg.h.

#define CDU_REGION_NUMBER_UCM_AG   4

Definition at line 7215 of file bnx2x_reg.h.

#define CDU_REGION_NUMBER_XCM_AG   2

Definition at line 7214 of file bnx2x_reg.h.

#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE (   _val)    ((_val) & ~0x80)

Definition at line 7230 of file bnx2x_reg.h.

#define CDU_RSRVD_VALUE_TYPE_A (   _cid,
  _region,
  _type 
)    (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))

Definition at line 7226 of file bnx2x_reg.h.

#define CDU_RSRVD_VALUE_TYPE_B (   _crc,
  _type 
)    (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))

Definition at line 7228 of file bnx2x_reg.h.

#define CDU_VALID_DATA (   _cid,
  _region,
  _type 
)    (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))

Definition at line 7222 of file bnx2x_reg.h.

#define CFC_REG_AC_INIT_DONE   0x104078

Definition at line 427 of file bnx2x_reg.h.

#define CFC_REG_ACTIVITY_COUNTER   0x104400

Definition at line 429 of file bnx2x_reg.h.

#define CFC_REG_ACTIVITY_COUNTER_SIZE   256

Definition at line 430 of file bnx2x_reg.h.

#define CFC_REG_CAM_INIT_DONE   0x10407c

Definition at line 432 of file bnx2x_reg.h.

#define CFC_REG_CFC_INT_MASK   0x104108

Definition at line 434 of file bnx2x_reg.h.

#define CFC_REG_CFC_INT_STS   0x1040fc

Definition at line 436 of file bnx2x_reg.h.

#define CFC_REG_CFC_INT_STS_CLR   0x104100

Definition at line 438 of file bnx2x_reg.h.

#define CFC_REG_CFC_PRTY_MASK   0x104118

Definition at line 440 of file bnx2x_reg.h.

#define CFC_REG_CFC_PRTY_STS   0x10410c

Definition at line 442 of file bnx2x_reg.h.

#define CFC_REG_CFC_PRTY_STS_CLR   0x104110

Definition at line 444 of file bnx2x_reg.h.

#define CFC_REG_CID_CAM   0x104800

Definition at line 446 of file bnx2x_reg.h.

#define CFC_REG_CONTROL0   0x104028

Definition at line 447 of file bnx2x_reg.h.

#define CFC_REG_DEBUG0   0x104050

Definition at line 448 of file bnx2x_reg.h.

#define CFC_REG_DISABLE_ON_ERROR   0x104044

Definition at line 451 of file bnx2x_reg.h.

#define CFC_REG_ERROR_VECTOR   0x10403c

Definition at line 455 of file bnx2x_reg.h.

#define CFC_REG_INFO_RAM   0x105000

Definition at line 457 of file bnx2x_reg.h.

#define CFC_REG_INFO_RAM_SIZE   1024

Definition at line 458 of file bnx2x_reg.h.

#define CFC_REG_INIT_REG   0x10404c

Definition at line 459 of file bnx2x_reg.h.

#define CFC_REG_INTERFACES   0x104058

Definition at line 460 of file bnx2x_reg.h.

#define CFC_REG_LCREQ_WEIGHTS   0x104084

Definition at line 464 of file bnx2x_reg.h.

#define CFC_REG_LINK_LIST   0x104c00

Definition at line 466 of file bnx2x_reg.h.

#define CFC_REG_LINK_LIST_SIZE   256

Definition at line 467 of file bnx2x_reg.h.

#define CFC_REG_LL_INIT_DONE   0x104074

Definition at line 469 of file bnx2x_reg.h.

#define CFC_REG_NUM_LCIDS_ALLOC   0x104020

Definition at line 471 of file bnx2x_reg.h.

#define CFC_REG_NUM_LCIDS_ARRIVING   0x104004

Definition at line 473 of file bnx2x_reg.h.

#define CFC_REG_NUM_LCIDS_INSIDE_PF   0x104120

Definition at line 474 of file bnx2x_reg.h.

#define CFC_REG_NUM_LCIDS_LEAVING   0x104018

Definition at line 476 of file bnx2x_reg.h.

#define CFC_REG_WEAK_ENABLE_PF   0x104124

Definition at line 477 of file bnx2x_reg.h.

#define COMMAND_REG_ATTN_BITS_CLR   0x10

Definition at line 7139 of file bnx2x_reg.h.

#define COMMAND_REG_ATTN_BITS_SET   0xc

Definition at line 7138 of file bnx2x_reg.h.

#define COMMAND_REG_ATTN_BITS_UPD   0x8

Definition at line 7137 of file bnx2x_reg.h.

#define COMMAND_REG_COALESCE_NOW   0x14

Definition at line 7140 of file bnx2x_reg.h.

#define COMMAND_REG_INT_ACK   0x0

Definition at line 7135 of file bnx2x_reg.h.

#define COMMAND_REG_PROD_UPD   0x4

Definition at line 7136 of file bnx2x_reg.h.

#define COMMAND_REG_SIMD_MASK   0x18

Definition at line 7141 of file bnx2x_reg.h.

#define COMMAND_REG_SIMD_NOMASK   0x1c

Definition at line 7142 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_0   0xc2038

Definition at line 479 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_10   0xc2060

Definition at line 480 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_11   0xc2064

Definition at line 481 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_12   0xc2068

Definition at line 482 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_13   0xc206c

Definition at line 483 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_14   0xc2070

Definition at line 484 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_15   0xc2074

Definition at line 485 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_16   0xc2078

Definition at line 486 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_2   0xc2040

Definition at line 487 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_3   0xc2044

Definition at line 488 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_4   0xc2048

Definition at line 489 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_5   0xc204c

Definition at line 490 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_6   0xc2050

Definition at line 491 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_7   0xc2054

Definition at line 492 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_8   0xc2058

Definition at line 493 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_EVENT_9   0xc205c

Definition at line 494 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_10   0xc21e0

Definition at line 497 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_11   0xc21e4

Definition at line 498 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_12   0xc21e8

Definition at line 499 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_13   0xc21ec

Definition at line 500 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_14   0xc21f0

Definition at line 501 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_15   0xc21f4

Definition at line 502 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_16   0xc21f8

Definition at line 503 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_6   0xc21d0

Definition at line 504 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_7   0xc21d4

Definition at line 505 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_8   0xc21d8

Definition at line 506 of file bnx2x_reg.h.

#define CSDM_REG_AGG_INT_MODE_9   0xc21dc

Definition at line 507 of file bnx2x_reg.h.

#define CSDM_REG_CFC_RSP_START_ADDR   0xc2008

Definition at line 509 of file bnx2x_reg.h.

#define CSDM_REG_CMP_COUNTER_MAX0   0xc201c

Definition at line 511 of file bnx2x_reg.h.

#define CSDM_REG_CMP_COUNTER_MAX1   0xc2020

Definition at line 513 of file bnx2x_reg.h.

#define CSDM_REG_CMP_COUNTER_MAX2   0xc2024

Definition at line 515 of file bnx2x_reg.h.

#define CSDM_REG_CMP_COUNTER_MAX3   0xc2028

Definition at line 517 of file bnx2x_reg.h.

#define CSDM_REG_CMP_COUNTER_START_ADDR   0xc200c

Definition at line 520 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_INT_MASK_0   0xc229c

Definition at line 522 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_INT_MASK_1   0xc22ac

Definition at line 523 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_INT_STS_0   0xc2290

Definition at line 525 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_INT_STS_1   0xc22a0

Definition at line 526 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_PRTY_MASK   0xc22bc

Definition at line 528 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_PRTY_STS   0xc22b0

Definition at line 530 of file bnx2x_reg.h.

#define CSDM_REG_CSDM_PRTY_STS_CLR   0xc22b4

Definition at line 532 of file bnx2x_reg.h.

#define CSDM_REG_ENABLE_IN1   0xc2238

Definition at line 533 of file bnx2x_reg.h.

#define CSDM_REG_ENABLE_IN2   0xc223c

Definition at line 534 of file bnx2x_reg.h.

#define CSDM_REG_ENABLE_OUT1   0xc2240

Definition at line 535 of file bnx2x_reg.h.

#define CSDM_REG_ENABLE_OUT2   0xc2244

Definition at line 536 of file bnx2x_reg.h.

#define CSDM_REG_INIT_CREDIT_PXP_CTRL   0xc24bc

Definition at line 539 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE   0xc227c

Definition at line 541 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_PKT_END_MSG   0xc2274

Definition at line 543 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ   0xc2278

Definition at line 545 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q0_CMD   0xc2248

Definition at line 547 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q10_CMD   0xc226c

Definition at line 549 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q11_CMD   0xc2270

Definition at line 551 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q1_CMD   0xc224c

Definition at line 553 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q3_CMD   0xc2250

Definition at line 555 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q4_CMD   0xc2254

Definition at line 557 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q5_CMD   0xc2258

Definition at line 559 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q6_CMD   0xc225c

Definition at line 561 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q7_CMD   0xc2260

Definition at line 563 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q8_CMD   0xc2264

Definition at line 565 of file bnx2x_reg.h.

#define CSDM_REG_NUM_OF_Q9_CMD   0xc2268

Definition at line 567 of file bnx2x_reg.h.

#define CSDM_REG_Q_COUNTER_START_ADDR   0xc2010

Definition at line 569 of file bnx2x_reg.h.

#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0xc2548

Definition at line 571 of file bnx2x_reg.h.

#define CSDM_REG_SYNC_PARSER_EMPTY   0xc2550

Definition at line 573 of file bnx2x_reg.h.

#define CSDM_REG_SYNC_SYNC_EMPTY   0xc2558

Definition at line 575 of file bnx2x_reg.h.

#define CSDM_REG_TIMER_TICK   0xc2000

Definition at line 578 of file bnx2x_reg.h.

#define CSEM_REG_ARB_CYCLE_SIZE   0x200034

Definition at line 580 of file bnx2x_reg.h.

#define CSEM_REG_ARB_ELEMENT0   0x200020

Definition at line 584 of file bnx2x_reg.h.

#define CSEM_REG_ARB_ELEMENT1   0x200024

Definition at line 589 of file bnx2x_reg.h.

#define CSEM_REG_ARB_ELEMENT2   0x200028

Definition at line 595 of file bnx2x_reg.h.

#define CSEM_REG_ARB_ELEMENT3   0x20002c

Definition at line 602 of file bnx2x_reg.h.

#define CSEM_REG_ARB_ELEMENT4   0x200030

Definition at line 610 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_INT_MASK_0   0x200110

Definition at line 612 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_INT_MASK_1   0x200120

Definition at line 613 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_INT_STS_0   0x200104

Definition at line 615 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_INT_STS_1   0x200114

Definition at line 616 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_MASK_0   0x200130

Definition at line 618 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_MASK_1   0x200140

Definition at line 619 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_STS_0   0x200124

Definition at line 621 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_STS_1   0x200134

Definition at line 622 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_STS_CLR_0   0x200128

Definition at line 624 of file bnx2x_reg.h.

#define CSEM_REG_CSEM_PRTY_STS_CLR_1   0x200138

Definition at line 625 of file bnx2x_reg.h.

#define CSEM_REG_ENABLE_IN   0x2000a4

Definition at line 626 of file bnx2x_reg.h.

#define CSEM_REG_ENABLE_OUT   0x2000a8

Definition at line 627 of file bnx2x_reg.h.

#define CSEM_REG_FAST_MEMORY   0x220000

Definition at line 632 of file bnx2x_reg.h.

#define CSEM_REG_FIC0_DISABLE   0x200224

Definition at line 635 of file bnx2x_reg.h.

#define CSEM_REG_FIC1_DISABLE   0x200234

Definition at line 638 of file bnx2x_reg.h.

#define CSEM_REG_INT_TABLE   0x200400

Definition at line 641 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FIC0   0x200000

Definition at line 644 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FIC1   0x200004

Definition at line 647 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FOC0   0x200008

Definition at line 650 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FOC1   0x20000c

Definition at line 653 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FOC2   0x200010

Definition at line 656 of file bnx2x_reg.h.

#define CSEM_REG_MSG_NUM_FOC3   0x200014

Definition at line 659 of file bnx2x_reg.h.

#define CSEM_REG_PAS_DISABLE   0x20024c

Definition at line 662 of file bnx2x_reg.h.

#define CSEM_REG_PASSIVE_BUFFER   0x202000

Definition at line 664 of file bnx2x_reg.h.

#define CSEM_REG_PRAM   0x240000

Definition at line 666 of file bnx2x_reg.h.

#define CSEM_REG_SLEEP_THREADS_VALID   0x20026c

Definition at line 668 of file bnx2x_reg.h.

#define CSEM_REG_SLOW_EXT_STORE_EMPTY   0x2002a0

Definition at line 670 of file bnx2x_reg.h.

#define CSEM_REG_THREADS_LIST   0x2002e4

Definition at line 672 of file bnx2x_reg.h.

#define CSEM_REG_TS_0_AS   0x200038

Definition at line 674 of file bnx2x_reg.h.

#define CSEM_REG_TS_10_AS   0x200060

Definition at line 676 of file bnx2x_reg.h.

#define CSEM_REG_TS_11_AS   0x200064

Definition at line 678 of file bnx2x_reg.h.

#define CSEM_REG_TS_12_AS   0x200068

Definition at line 680 of file bnx2x_reg.h.

#define CSEM_REG_TS_13_AS   0x20006c

Definition at line 682 of file bnx2x_reg.h.

#define CSEM_REG_TS_14_AS   0x200070

Definition at line 684 of file bnx2x_reg.h.

#define CSEM_REG_TS_15_AS   0x200074

Definition at line 686 of file bnx2x_reg.h.

#define CSEM_REG_TS_16_AS   0x200078

Definition at line 688 of file bnx2x_reg.h.

#define CSEM_REG_TS_17_AS   0x20007c

Definition at line 690 of file bnx2x_reg.h.

#define CSEM_REG_TS_18_AS   0x200080

Definition at line 692 of file bnx2x_reg.h.

#define CSEM_REG_TS_1_AS   0x20003c

Definition at line 694 of file bnx2x_reg.h.

#define CSEM_REG_TS_2_AS   0x200040

Definition at line 696 of file bnx2x_reg.h.

#define CSEM_REG_TS_3_AS   0x200044

Definition at line 698 of file bnx2x_reg.h.

#define CSEM_REG_TS_4_AS   0x200048

Definition at line 700 of file bnx2x_reg.h.

#define CSEM_REG_TS_5_AS   0x20004c

Definition at line 702 of file bnx2x_reg.h.

#define CSEM_REG_TS_6_AS   0x200050

Definition at line 704 of file bnx2x_reg.h.

#define CSEM_REG_TS_7_AS   0x200054

Definition at line 706 of file bnx2x_reg.h.

#define CSEM_REG_TS_8_AS   0x200058

Definition at line 708 of file bnx2x_reg.h.

#define CSEM_REG_TS_9_AS   0x20005c

Definition at line 710 of file bnx2x_reg.h.

#define CSEM_REG_VFPF_ERR_NUM   0x200380

Definition at line 713 of file bnx2x_reg.h.

#define CSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_9

Definition at line 6030 of file bnx2x_reg.h.

#define DBG_REG_DBG_PRTY_MASK   0xc0a8

Definition at line 715 of file bnx2x_reg.h.

#define DBG_REG_DBG_PRTY_STS   0xc09c

Definition at line 717 of file bnx2x_reg.h.

#define DBG_REG_DBG_PRTY_STS_CLR   0xc0a0

Definition at line 719 of file bnx2x_reg.h.

#define DIGITAL5_ACTUAL_SPEED_TX_MASK   0x003f

Definition at line 7091 of file bnx2x_reg.h.

#define DMAE_REG_BACKWARD_COMP_EN   0x10207c

Definition at line 723 of file bnx2x_reg.h.

#define DMAE_REG_CMD_MEM   0x102400

Definition at line 726 of file bnx2x_reg.h.

#define DMAE_REG_CMD_MEM_SIZE   224

Definition at line 727 of file bnx2x_reg.h.

#define DMAE_REG_CRC16C_INIT   0x10201c

Definition at line 730 of file bnx2x_reg.h.

#define DMAE_REG_CRC16T10_INIT   0x102020

Definition at line 733 of file bnx2x_reg.h.

#define DMAE_REG_DMAE_INT_MASK   0x102054

Definition at line 735 of file bnx2x_reg.h.

#define DMAE_REG_DMAE_PRTY_MASK   0x102064

Definition at line 737 of file bnx2x_reg.h.

#define DMAE_REG_DMAE_PRTY_STS   0x102058

Definition at line 739 of file bnx2x_reg.h.

#define DMAE_REG_DMAE_PRTY_STS_CLR   0x10205c

Definition at line 741 of file bnx2x_reg.h.

#define DMAE_REG_GO_C0   0x102080

Definition at line 743 of file bnx2x_reg.h.

#define DMAE_REG_GO_C1   0x102084

Definition at line 745 of file bnx2x_reg.h.

#define DMAE_REG_GO_C10   0x102088

Definition at line 747 of file bnx2x_reg.h.

#define DMAE_REG_GO_C11   0x10208c

Definition at line 749 of file bnx2x_reg.h.

#define DMAE_REG_GO_C12   0x102090

Definition at line 751 of file bnx2x_reg.h.

#define DMAE_REG_GO_C13   0x102094

Definition at line 753 of file bnx2x_reg.h.

#define DMAE_REG_GO_C14   0x102098

Definition at line 755 of file bnx2x_reg.h.

#define DMAE_REG_GO_C15   0x10209c

Definition at line 757 of file bnx2x_reg.h.

#define DMAE_REG_GO_C2   0x1020a0

Definition at line 759 of file bnx2x_reg.h.

#define DMAE_REG_GO_C3   0x1020a4

Definition at line 761 of file bnx2x_reg.h.

#define DMAE_REG_GO_C4   0x1020a8

Definition at line 763 of file bnx2x_reg.h.

#define DMAE_REG_GO_C5   0x1020ac

Definition at line 765 of file bnx2x_reg.h.

#define DMAE_REG_GO_C6   0x1020b0

Definition at line 767 of file bnx2x_reg.h.

#define DMAE_REG_GO_C7   0x1020b4

Definition at line 769 of file bnx2x_reg.h.

#define DMAE_REG_GO_C8   0x1020b8

Definition at line 771 of file bnx2x_reg.h.

#define DMAE_REG_GO_C9   0x1020bc

Definition at line 773 of file bnx2x_reg.h.

#define DMAE_REG_GRC_IFEN   0x102008

Definition at line 777 of file bnx2x_reg.h.

#define DMAE_REG_PCI_IFEN   0x102004

Definition at line 781 of file bnx2x_reg.h.

#define DMAE_REG_PXP_REQ_INIT_CRD   0x1020c0

Definition at line 785 of file bnx2x_reg.h.

#define DORQ_REG_AGG_CMD0   0x170060

Definition at line 787 of file bnx2x_reg.h.

#define DORQ_REG_AGG_CMD1   0x170064

Definition at line 789 of file bnx2x_reg.h.

#define DORQ_REG_AGG_CMD2   0x170068

Definition at line 791 of file bnx2x_reg.h.

#define DORQ_REG_AGG_CMD3   0x17006c

Definition at line 793 of file bnx2x_reg.h.

#define DORQ_REG_CMHEAD_RX   0x170050

Definition at line 795 of file bnx2x_reg.h.

#define DORQ_REG_DB_ADDR0   0x17008c

Definition at line 797 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_INT_MASK   0x170180

Definition at line 799 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_INT_STS   0x170174

Definition at line 801 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_INT_STS_CLR   0x170178

Definition at line 803 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_PRTY_MASK   0x170190

Definition at line 805 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_PRTY_STS   0x170184

Definition at line 807 of file bnx2x_reg.h.

#define DORQ_REG_DORQ_PRTY_STS_CLR   0x170188

Definition at line 809 of file bnx2x_reg.h.

#define DORQ_REG_DPM_CID_ADDR   0x170044

Definition at line 811 of file bnx2x_reg.h.

#define DORQ_REG_DPM_CID_OFST   0x170030

Definition at line 813 of file bnx2x_reg.h.

#define DORQ_REG_DQ_FIFO_AFULL_TH   0x17007c

Definition at line 815 of file bnx2x_reg.h.

#define DORQ_REG_DQ_FIFO_FULL_TH   0x170078

Definition at line 817 of file bnx2x_reg.h.

#define DORQ_REG_DQ_FILL_LVLF   0x1700a4

Definition at line 821 of file bnx2x_reg.h.

#define DORQ_REG_DQ_FULL_ST   0x1700c0

Definition at line 824 of file bnx2x_reg.h.

#define DORQ_REG_ERR_CMHEAD   0x170058

Definition at line 826 of file bnx2x_reg.h.

#define DORQ_REG_IF_EN   0x170004

Definition at line 827 of file bnx2x_reg.h.

#define DORQ_REG_MODE_ACT   0x170008

Definition at line 828 of file bnx2x_reg.h.

#define DORQ_REG_NORM_CID_OFST   0x17002c

Definition at line 830 of file bnx2x_reg.h.

#define DORQ_REG_NORM_CMHEAD_TX   0x17004c

Definition at line 832 of file bnx2x_reg.h.

#define DORQ_REG_OUTST_REQ   0x17003c

Definition at line 835 of file bnx2x_reg.h.

#define DORQ_REG_PF_USAGE_CNT   0x1701d0

Definition at line 836 of file bnx2x_reg.h.

#define DORQ_REG_REGN   0x170038

Definition at line 837 of file bnx2x_reg.h.

#define DORQ_REG_RSP_INIT_CRD   0x170048

Definition at line 849 of file bnx2x_reg.h.

#define DORQ_REG_RSPA_CRD_CNT   0x1700ac

Definition at line 841 of file bnx2x_reg.h.

#define DORQ_REG_RSPB_CRD_CNT   0x1700b0

Definition at line 845 of file bnx2x_reg.h.

#define DORQ_REG_SHRT_ACT_CNT   0x170070

Definition at line 852 of file bnx2x_reg.h.

#define DORQ_REG_SHRT_CMHEAD   0x170054

Definition at line 854 of file bnx2x_reg.h.

#define EMAC_LED_1000MB_OVERRIDE   (1L<<1)

Definition at line 5790 of file bnx2x_reg.h.

#define EMAC_LED_100MB_OVERRIDE   (1L<<2)

Definition at line 5791 of file bnx2x_reg.h.

#define EMAC_LED_10MB_OVERRIDE   (1L<<3)

Definition at line 5792 of file bnx2x_reg.h.

#define EMAC_LED_2500MB_OVERRIDE   (1L<<12)

Definition at line 5793 of file bnx2x_reg.h.

#define EMAC_LED_OVERRIDE   (1L<<0)

Definition at line 5794 of file bnx2x_reg.h.

#define EMAC_LED_TRAFFIC   (1L<<6)

Definition at line 5795 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_COMMAND_ADDRESS   (0L<<26)

Definition at line 5796 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_COMMAND_READ_22   (2L<<26)

Definition at line 5797 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_COMMAND_READ_45   (3L<<26)

Definition at line 5798 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_COMMAND_WRITE_22   (1L<<26)

Definition at line 5799 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_COMMAND_WRITE_45   (1L<<26)

Definition at line 5800 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_DATA   (0xffffL<<0)

Definition at line 5801 of file bnx2x_reg.h.

#define EMAC_MDIO_COMM_START_BUSY   (1L<<29)

Definition at line 5802 of file bnx2x_reg.h.

#define EMAC_MDIO_MODE_AUTO_POLL   (1L<<4)

Definition at line 5803 of file bnx2x_reg.h.

#define EMAC_MDIO_MODE_CLAUSE_45   (1L<<31)

Definition at line 5804 of file bnx2x_reg.h.

#define EMAC_MDIO_MODE_CLOCK_CNT   (0x3ffL<<16)

Definition at line 5805 of file bnx2x_reg.h.

#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT   16

Definition at line 5806 of file bnx2x_reg.h.

#define EMAC_MDIO_STATUS_10MB   (1L<<1)

Definition at line 5807 of file bnx2x_reg.h.

#define EMAC_MODE_25G_MODE   (1L<<5)

Definition at line 5808 of file bnx2x_reg.h.

#define EMAC_MODE_HALF_DUPLEX   (1L<<1)

Definition at line 5809 of file bnx2x_reg.h.

#define EMAC_MODE_PORT_GMII   (2L<<2)

Definition at line 5810 of file bnx2x_reg.h.

#define EMAC_MODE_PORT_MII   (1L<<2)

Definition at line 5811 of file bnx2x_reg.h.

#define EMAC_MODE_PORT_MII_10M   (3L<<2)

Definition at line 5812 of file bnx2x_reg.h.

#define EMAC_MODE_RESET   (1L<<0)

Definition at line 5813 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_LED   0xc

Definition at line 5814 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_MAC_MATCH   0x10

Definition at line 5815 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_MDIO_COMM   0xac

Definition at line 5816 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_MDIO_MODE   0xb4

Definition at line 5817 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_MDIO_STATUS   0xb0

Definition at line 5818 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_MODE   0x0

Definition at line 5819 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_RX_MODE   0xc8

Definition at line 5820 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_RX_MTU_SIZE   0x9c

Definition at line 5821 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_RX_STAT_AC   0x180

Definition at line 5822 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_RX_STAT_AC_28   0x1f4

Definition at line 5823 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_RX_STAT_AC_COUNT   23

Definition at line 5824 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_TX_MODE   0xbc

Definition at line 5825 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_TX_STAT_AC   0x280

Definition at line 5826 of file bnx2x_reg.h.

#define EMAC_REG_EMAC_TX_STAT_AC_COUNT   22

Definition at line 5827 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_MODE   0x320

Definition at line 5828 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_MODE_PRIORITIES   (1L<<2)

Definition at line 5829 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_MODE_RX_EN   (1L<<1)

Definition at line 5830 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_MODE_TX_EN   (1L<<0)

Definition at line 5831 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_PARAM   0x324

Definition at line 5832 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT   0

Definition at line 5833 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT   16

Definition at line 5834 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD   0x328

Definition at line 5835 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT   (0xffff<<0)

Definition at line 5836 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XOFF_SENT   0x330

Definition at line 5837 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT   (0xffff<<0)

Definition at line 5838 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XON_RCVD   0x32c

Definition at line 5839 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT   (0xffff<<0)

Definition at line 5840 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XON_SENT   0x334

Definition at line 5841 of file bnx2x_reg.h.

#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT   (0xffff<<0)

Definition at line 5842 of file bnx2x_reg.h.

#define EMAC_RX_MODE_FLOW_EN   (1L<<2)

Definition at line 5843 of file bnx2x_reg.h.

#define EMAC_RX_MODE_KEEP_MAC_CONTROL   (1L<<3)

Definition at line 5844 of file bnx2x_reg.h.

#define EMAC_RX_MODE_KEEP_VLAN_TAG   (1L<<10)

Definition at line 5845 of file bnx2x_reg.h.

#define EMAC_RX_MODE_PROMISCUOUS   (1L<<8)

Definition at line 5846 of file bnx2x_reg.h.

#define EMAC_RX_MODE_RESET   (1L<<0)

Definition at line 5847 of file bnx2x_reg.h.

#define EMAC_RX_MTU_SIZE_JUMBO_ENA   (1L<<31)

Definition at line 5848 of file bnx2x_reg.h.

#define EMAC_TX_MODE_EXT_PAUSE_EN   (1L<<3)

Definition at line 5849 of file bnx2x_reg.h.

#define EMAC_TX_MODE_FLOW_EN   (1L<<4)

Definition at line 5850 of file bnx2x_reg.h.

#define EMAC_TX_MODE_RESET   (1L<<0)

Definition at line 5851 of file bnx2x_reg.h.

#define EVEREST_GEN_ATTN_IN_USE_MASK   0x7ffe0

Definition at line 6007 of file bnx2x_reg.h.

#define EVEREST_LATCHED_ATTN_IN_USE_MASK   0xffe00000

Definition at line 6008 of file bnx2x_reg.h.

#define GENERAL_ATTEN_OFFSET (   atten_name)    (1UL << ((94 + atten_name) % 32))

Definition at line 6060 of file bnx2x_reg.h.

#define GENERAL_ATTEN_WORD (   atten_name)    ((94 + atten_name) / 32)

Definition at line 6059 of file bnx2x_reg.h.

#define GRC_BAR2_CONFIG   0x4e0

Definition at line 6252 of file bnx2x_reg.h.

#define GRC_CONFIG_2_SIZE_REG   0x408

Definition at line 6200 of file bnx2x_reg.h.

#define GRC_CONFIG_3_SIZE_REG   0x40c

Definition at line 6243 of file bnx2x_reg.h.

#define GRCBASE_BRB1   0x060000

Definition at line 6083 of file bnx2x_reg.h.

#define GRCBASE_CCM   0x0D0000

Definition at line 6088 of file bnx2x_reg.h.

#define GRCBASE_CDU   0x101000

Definition at line 6090 of file bnx2x_reg.h.

#define GRCBASE_CFC   0x104000

Definition at line 6093 of file bnx2x_reg.h.

#define GRCBASE_CSDM   0x0C2000

Definition at line 6086 of file bnx2x_reg.h.

#define GRCBASE_CSEM   0x200000

Definition at line 6109 of file bnx2x_reg.h.

#define GRCBASE_DBG   0x00C000

Definition at line 6076 of file bnx2x_reg.h.

#define GRCBASE_DBU   0x008800

Definition at line 6074 of file bnx2x_reg.h.

#define GRCBASE_DMAE   0x102000

Definition at line 6091 of file bnx2x_reg.h.

#define GRCBASE_DQ   0x170000

Definition at line 6107 of file bnx2x_reg.h.

#define GRCBASE_EMAC0   0x008000

Definition at line 6072 of file bnx2x_reg.h.

#define GRCBASE_EMAC1   0x008400

Definition at line 6073 of file bnx2x_reg.h.

#define GRCBASE_HC   0x108000

Definition at line 6094 of file bnx2x_reg.h.

#define GRCBASE_MCP   0x080000

Definition at line 6084 of file bnx2x_reg.h.

#define GRCBASE_MISC   0x00A000

Definition at line 6075 of file bnx2x_reg.h.

#define GRCBASE_MISC_AEU   GRCBASE_MISC

Definition at line 6112 of file bnx2x_reg.h.

#define GRCBASE_MSTAT0   0x162000

Definition at line 6100 of file bnx2x_reg.h.

#define GRCBASE_MSTAT1   0x162800

Definition at line 6101 of file bnx2x_reg.h.

#define GRCBASE_NIG   0x010000

Definition at line 6077 of file bnx2x_reg.h.

#define GRCBASE_PBF   0x140000

Definition at line 6096 of file bnx2x_reg.h.

#define GRCBASE_PCICONFIG   0x002000

Definition at line 6070 of file bnx2x_reg.h.

#define GRCBASE_PCIREG   0x002400

Definition at line 6071 of file bnx2x_reg.h.

#define GRCBASE_PRS   0x040000

Definition at line 6079 of file bnx2x_reg.h.

#define GRCBASE_PXP   0x103000

Definition at line 6092 of file bnx2x_reg.h.

#define GRCBASE_PXP2   0x120000

Definition at line 6095 of file bnx2x_reg.h.

#define GRCBASE_PXPCS   0x000000

Definition at line 6069 of file bnx2x_reg.h.

#define GRCBASE_QM   0x168000

Definition at line 6106 of file bnx2x_reg.h.

#define GRCBASE_SRCH   0x040400

Definition at line 6080 of file bnx2x_reg.h.

#define GRCBASE_TCM   0x050000

Definition at line 6082 of file bnx2x_reg.h.

#define GRCBASE_TIMERS   0x164000

Definition at line 6104 of file bnx2x_reg.h.

#define GRCBASE_TSDM   0x042000

Definition at line 6081 of file bnx2x_reg.h.

#define GRCBASE_TSEM   0x180000

Definition at line 6108 of file bnx2x_reg.h.

#define GRCBASE_UCM   0x0E0000

Definition at line 6089 of file bnx2x_reg.h.

#define GRCBASE_UMAC0   0x160000

Definition at line 6097 of file bnx2x_reg.h.

#define GRCBASE_UMAC1   0x160400

Definition at line 6098 of file bnx2x_reg.h.

#define GRCBASE_UPB   0x0C1000

Definition at line 6085 of file bnx2x_reg.h.

#define GRCBASE_USDM   0x0C4000

Definition at line 6087 of file bnx2x_reg.h.

#define GRCBASE_USEM   0x300000

Definition at line 6111 of file bnx2x_reg.h.

#define GRCBASE_XCM   0x020000

Definition at line 6078 of file bnx2x_reg.h.

#define GRCBASE_XMAC0   0x163000

Definition at line 6102 of file bnx2x_reg.h.

#define GRCBASE_XMAC1   0x163800

Definition at line 6103 of file bnx2x_reg.h.

#define GRCBASE_XPB   0x161000

Definition at line 6099 of file bnx2x_reg.h.

#define GRCBASE_XSDM   0x166000

Definition at line 6105 of file bnx2x_reg.h.

#define GRCBASE_XSEM   0x280000

Definition at line 6110 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_ATTN_BIT_EN_0   (0x1<<4)

Definition at line 855 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_BLOCK_DISABLE_0   (0x1<<0)

Definition at line 856 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_INT_LINE_EN_0   (0x1<<3)

Definition at line 857 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_MSI_ATTN_EN_0   (0x1<<7)

Definition at line 858 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0   (0x1<<2)

Definition at line 859 of file bnx2x_reg.h.

#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0   (0x1<<1)

Definition at line 860 of file bnx2x_reg.h.

#define HC_CONFIG_1_REG_BLOCK_DISABLE_1   (0x1<<0)

Definition at line 861 of file bnx2x_reg.h.

#define HC_REG_AGG_INT_0   0x108050

Definition at line 862 of file bnx2x_reg.h.

#define HC_REG_AGG_INT_1   0x108054

Definition at line 863 of file bnx2x_reg.h.

#define HC_REG_ATTN_BIT   0x108120

Definition at line 864 of file bnx2x_reg.h.

#define HC_REG_ATTN_IDX   0x108100

Definition at line 865 of file bnx2x_reg.h.

#define HC_REG_ATTN_MSG0_ADDR_L   0x108018

Definition at line 866 of file bnx2x_reg.h.

#define HC_REG_ATTN_MSG1_ADDR_L   0x108020

Definition at line 867 of file bnx2x_reg.h.

#define HC_REG_ATTN_NUM_P0   0x108038

Definition at line 868 of file bnx2x_reg.h.

#define HC_REG_ATTN_NUM_P1   0x10803c

Definition at line 869 of file bnx2x_reg.h.

#define HC_REG_COMMAND_REG   0x108180

Definition at line 870 of file bnx2x_reg.h.

#define HC_REG_CONFIG_0   0x108000

Definition at line 871 of file bnx2x_reg.h.

#define HC_REG_CONFIG_1   0x108004

Definition at line 872 of file bnx2x_reg.h.

#define HC_REG_FUNC_NUM_P0   0x1080ac

Definition at line 873 of file bnx2x_reg.h.

#define HC_REG_FUNC_NUM_P1   0x1080b0

Definition at line 874 of file bnx2x_reg.h.

#define HC_REG_HC_PRTY_MASK   0x1080a0

Definition at line 876 of file bnx2x_reg.h.

#define HC_REG_HC_PRTY_STS   0x108094

Definition at line 878 of file bnx2x_reg.h.

#define HC_REG_HC_PRTY_STS_CLR   0x108098

Definition at line 880 of file bnx2x_reg.h.

#define HC_REG_INT_MASK   0x108108

Definition at line 881 of file bnx2x_reg.h.

#define HC_REG_LEADING_EDGE_0   0x108040

Definition at line 882 of file bnx2x_reg.h.

#define HC_REG_LEADING_EDGE_1   0x108048

Definition at line 883 of file bnx2x_reg.h.

#define HC_REG_MAIN_MEMORY   0x108800

Definition at line 884 of file bnx2x_reg.h.

#define HC_REG_MAIN_MEMORY_SIZE   152

Definition at line 885 of file bnx2x_reg.h.

#define HC_REG_P0_PROD_CONS   0x108200

Definition at line 886 of file bnx2x_reg.h.

#define HC_REG_P1_PROD_CONS   0x108400

Definition at line 887 of file bnx2x_reg.h.

#define HC_REG_PBA_COMMAND   0x108140

Definition at line 888 of file bnx2x_reg.h.

#define HC_REG_PCI_CONFIG_0   0x108010

Definition at line 889 of file bnx2x_reg.h.

#define HC_REG_PCI_CONFIG_1   0x108014

Definition at line 890 of file bnx2x_reg.h.

#define HC_REG_STATISTIC_COUNTERS   0x109000

Definition at line 891 of file bnx2x_reg.h.

#define HC_REG_TRAILING_EDGE_0   0x108044

Definition at line 892 of file bnx2x_reg.h.

#define HC_REG_TRAILING_EDGE_1   0x10804c

Definition at line 893 of file bnx2x_reg.h.

#define HC_REG_UC_RAM_ADDR_0   0x108028

Definition at line 894 of file bnx2x_reg.h.

#define HC_REG_UC_RAM_ADDR_1   0x108030

Definition at line 895 of file bnx2x_reg.h.

#define HC_REG_USTORM_ADDR_FOR_COALESCE   0x108068

Definition at line 896 of file bnx2x_reg.h.

#define HC_REG_VQID_0   0x108008

Definition at line 897 of file bnx2x_reg.h.

#define HC_REG_VQID_1   0x10800c

Definition at line 898 of file bnx2x_reg.h.

#define HW_LOCK_MAX_RESOURCE_VALUE   31

Definition at line 5925 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB   13

Definition at line 5926 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_DRV_FLAGS   10

Definition at line 5927 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_GPIO   1

Definition at line 5928 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_MDIO   0

Definition at line 5929 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_NVRAM   12

Definition at line 5930 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_PORT0_ATT_MASK   3

Definition at line 5931 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0   8

Definition at line 5932 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1   9

Definition at line 5933 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_RECOVERY_REG   11

Definition at line 5934 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_RESET   5

Definition at line 5935 of file bnx2x_reg.h.

#define HW_LOCK_RESOURCE_SPIO   2

Definition at line 5936 of file bnx2x_reg.h.

#define IGU_ADDR_ATTN_BITS_CLR   0x0204

Definition at line 7121 of file bnx2x_reg.h.

#define IGU_ADDR_ATTN_BITS_SET   0x0203

Definition at line 7120 of file bnx2x_reg.h.

#define IGU_ADDR_ATTN_BITS_UPD   0x0202

Definition at line 7119 of file bnx2x_reg.h.

#define IGU_ADDR_COALESCE_NOW   0x0205

Definition at line 7122 of file bnx2x_reg.h.

#define IGU_ADDR_INT_ACK   0x0200

Definition at line 7117 of file bnx2x_reg.h.

#define IGU_ADDR_MSI_ADDR_HI   0x0212

Definition at line 7127 of file bnx2x_reg.h.

#define IGU_ADDR_MSI_ADDR_LO   0x0211

Definition at line 7126 of file bnx2x_reg.h.

#define IGU_ADDR_MSI_CTL   0x0210

Definition at line 7125 of file bnx2x_reg.h.

#define IGU_ADDR_MSI_DATA   0x0213

Definition at line 7128 of file bnx2x_reg.h.

#define IGU_ADDR_MSIX   0x0000

Definition at line 7116 of file bnx2x_reg.h.

#define IGU_ADDR_PROD_UPD   0x0201

Definition at line 7118 of file bnx2x_reg.h.

#define IGU_ADDR_SIMD_MASK   0x0206

Definition at line 7123 of file bnx2x_reg.h.

#define IGU_ADDR_SIMD_NOMASK   0x0207

Definition at line 7124 of file bnx2x_reg.h.

#define IGU_BC_BASE_DSB_PROD   128

Definition at line 7197 of file bnx2x_reg.h.

#define IGU_BC_DSB_NUM_SEGS   5

Definition at line 7193 of file bnx2x_reg.h.

#define IGU_BC_NDSB_NUM_SEGS   2

Definition at line 7194 of file bnx2x_reg.h.

#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN   (0x1<<1)

Definition at line 899 of file bnx2x_reg.h.

#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE   (0x1<<0)

Definition at line 900 of file bnx2x_reg.h.

#define IGU_CMD_ATTN_BIT_CLR_UPPER   0x05a2

Definition at line 7169 of file bnx2x_reg.h.

#define IGU_CMD_ATTN_BIT_SET_UPPER   0x05a1

Definition at line 7168 of file bnx2x_reg.h.

#define IGU_CMD_ATTN_BIT_UPD_UPPER   0x05a0

Definition at line 7167 of file bnx2x_reg.h.

#define IGU_CMD_BACKWARD_COMP_PROD_UPD   0x0201

Definition at line 7154 of file bnx2x_reg.h.

#define IGU_CMD_E2_PROD_UPD_BASE   0x0500

Definition at line 7162 of file bnx2x_reg.h.

#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER   0x059f

Definition at line 7165 of file bnx2x_reg.h.

#define IGU_CMD_E2_PROD_UPD_UPPER   (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)

Definition at line 7163 of file bnx2x_reg.h.

#define IGU_CMD_INT_ACK_BASE   0x0400

Definition at line 7157 of file bnx2x_reg.h.

#define IGU_CMD_INT_ACK_RESERVED_UPPER   0x04ff

Definition at line 7160 of file bnx2x_reg.h.

#define IGU_CMD_INT_ACK_UPPER   (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)

Definition at line 7158 of file bnx2x_reg.h.

#define IGU_FID_ENCODE_IS_PF   (0x1<<6)

Definition at line 7202 of file bnx2x_reg.h.

#define IGU_FID_ENCODE_IS_PF_SHIFT   6

Definition at line 7203 of file bnx2x_reg.h.

#define IGU_FID_PF_NUM_MASK   (0x7)

Definition at line 7205 of file bnx2x_reg.h.

#define IGU_FID_VF_NUM_MASK   (0x3f)

Definition at line 7204 of file bnx2x_reg.h.

#define IGU_FUNC_BASE   0x0400

Definition at line 7114 of file bnx2x_reg.h.

#define IGU_MEM_BASE   0x0000

Definition at line 7145 of file bnx2x_reg.h.

#define IGU_MEM_MSIX_BASE   0x0000

Definition at line 7147 of file bnx2x_reg.h.

#define IGU_MEM_MSIX_RESERVED_UPPER   0x01ff

Definition at line 7149 of file bnx2x_reg.h.

#define IGU_MEM_MSIX_UPPER   0x007f

Definition at line 7148 of file bnx2x_reg.h.

#define IGU_MEM_PBA_MSIX_BASE   0x0200

Definition at line 7151 of file bnx2x_reg.h.

#define IGU_MEM_PBA_MSIX_RESERVED_UPPER   0x03ff

Definition at line 7155 of file bnx2x_reg.h.

#define IGU_MEM_PBA_MSIX_UPPER   0x0200

Definition at line 7152 of file bnx2x_reg.h.

#define IGU_NORM_BASE_DSB_PROD   136

Definition at line 7198 of file bnx2x_reg.h.

#define IGU_NORM_DSB_NUM_SEGS   2

Definition at line 7195 of file bnx2x_reg.h.

#define IGU_NORM_NDSB_NUM_SEGS   1

Definition at line 7196 of file bnx2x_reg.h.

#define IGU_PF_CONF_ATTN_BIT_EN   (0x1<<3) /* attention enable */

Definition at line 7181 of file bnx2x_reg.h.

#define IGU_PF_CONF_FUNC_EN   (0x1<<0) /* function enable */

Definition at line 7178 of file bnx2x_reg.h.

#define IGU_PF_CONF_INT_LINE_EN   (0x1<<2) /* INT enable */

Definition at line 7180 of file bnx2x_reg.h.

#define IGU_PF_CONF_MSI_MSIX_EN   (0x1<<1) /* MSI/MSIX enable */

Definition at line 7179 of file bnx2x_reg.h.

#define IGU_PF_CONF_SIMD_MODE   (0x1<<5) /* simd all ones mode */

Definition at line 7183 of file bnx2x_reg.h.

#define IGU_PF_CONF_SINGLE_ISR_EN   (0x1<<4) /* single ISR mode enable */

Definition at line 7182 of file bnx2x_reg.h.

#define IGU_REG_ATTENTION_ACK_BITS   0x130108

Definition at line 901 of file bnx2x_reg.h.

#define IGU_REG_ATTN_FSM   0x130054

Definition at line 903 of file bnx2x_reg.h.

#define IGU_REG_ATTN_MSG_ADDR_H   0x13011c

Definition at line 904 of file bnx2x_reg.h.

#define IGU_REG_ATTN_MSG_ADDR_L   0x130120

Definition at line 905 of file bnx2x_reg.h.

#define IGU_REG_ATTN_WRITE_DONE_PENDING   0x130030

Definition at line 909 of file bnx2x_reg.h.

#define IGU_REG_BLOCK_CONFIGURATION   0x130000

Definition at line 910 of file bnx2x_reg.h.

#define IGU_REG_COMMAND_REG_32LSB_DATA   0x130124

Definition at line 911 of file bnx2x_reg.h.

#define IGU_REG_COMMAND_REG_CTRL   0x13012c

Definition at line 912 of file bnx2x_reg.h.

#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP   0x130200

Definition at line 916 of file bnx2x_reg.h.

#define IGU_REG_CTRL_FSM   0x130064

Definition at line 918 of file bnx2x_reg.h.

#define IGU_REG_ERROR_HANDLING_DATA_VALID   0x130130

Definition at line 921 of file bnx2x_reg.h.

#define IGU_REG_IGU_PRTY_MASK   0x1300a8

Definition at line 923 of file bnx2x_reg.h.

#define IGU_REG_IGU_PRTY_STS   0x13009c

Definition at line 925 of file bnx2x_reg.h.

#define IGU_REG_IGU_PRTY_STS_CLR   0x1300a0

Definition at line 927 of file bnx2x_reg.h.

#define IGU_REG_INT_HANDLE_FSM   0x130050

Definition at line 929 of file bnx2x_reg.h.

#define IGU_REG_LEADING_EDGE_LATCH   0x130134

Definition at line 930 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY   0x131000

Definition at line 934 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_FID_MASK   (0x7F<<7)

Definition at line 7210 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_FID_SHIFT   7

Definition at line 7211 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_SIZE   136

Definition at line 935 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_VALID   (1<<0)

Definition at line 7207 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK   (0x3F<<1)

Definition at line 7208 of file bnx2x_reg.h.

#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT   1

Definition at line 7209 of file bnx2x_reg.h.

#define IGU_REG_PBA_STATUS_LSB   0x130138

Definition at line 936 of file bnx2x_reg.h.

#define IGU_REG_PBA_STATUS_MSB   0x13013c

Definition at line 937 of file bnx2x_reg.h.

#define IGU_REG_PCI_PF_MSI_EN   0x130140

Definition at line 938 of file bnx2x_reg.h.

#define IGU_REG_PCI_PF_MSIX_EN   0x130144

Definition at line 939 of file bnx2x_reg.h.

#define IGU_REG_PCI_PF_MSIX_FUNC_MASK   0x130148

Definition at line 940 of file bnx2x_reg.h.

#define IGU_REG_PENDING_BITS_STATUS   0x130300

Definition at line 945 of file bnx2x_reg.h.

#define IGU_REG_PF_CONFIGURATION   0x130154

Definition at line 946 of file bnx2x_reg.h.

#define IGU_REG_PROD_CONS_MEMORY   0x132000

Definition at line 957 of file bnx2x_reg.h.

#define IGU_REG_PXP_ARB_FSM   0x130068

Definition at line 959 of file bnx2x_reg.h.

#define IGU_REG_RESERVED_UPPER   0x05ff

Definition at line 7176 of file bnx2x_reg.h.

#define IGU_REG_RESET_MEMORIES   0x130158

Definition at line 964 of file bnx2x_reg.h.

#define IGU_REG_SB_CTRL_FSM   0x13004c

Definition at line 966 of file bnx2x_reg.h.

#define IGU_REG_SB_INT_BEFORE_MASK_LSB   0x13015c

Definition at line 967 of file bnx2x_reg.h.

#define IGU_REG_SB_INT_BEFORE_MASK_MSB   0x130160

Definition at line 968 of file bnx2x_reg.h.

#define IGU_REG_SB_MASK_LSB   0x130164

Definition at line 969 of file bnx2x_reg.h.

#define IGU_REG_SB_MASK_MSB   0x130168

Definition at line 970 of file bnx2x_reg.h.

#define IGU_REG_SILENT_DROP   0x13016c

Definition at line 975 of file bnx2x_reg.h.

#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER   0x05a4

Definition at line 7172 of file bnx2x_reg.h.

#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER   0x05a5

Definition at line 7173 of file bnx2x_reg.h.

#define IGU_REG_SISR_MDPC_WMASK_UPPER   0x05a3

Definition at line 7171 of file bnx2x_reg.h.

#define IGU_REG_SISR_MDPC_WOMASK_UPPER   0x05a6

Definition at line 7174 of file bnx2x_reg.h.

#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT   0x130800

Definition at line 979 of file bnx2x_reg.h.

#define IGU_REG_TIMER_MASKING_VALUE   0x13003c

Definition at line 982 of file bnx2x_reg.h.

#define IGU_REG_TRAILING_EDGE_LATCH   0x130104

Definition at line 983 of file bnx2x_reg.h.

#define IGU_REG_VF_CONFIGURATION   0x130170

Definition at line 984 of file bnx2x_reg.h.

#define IGU_REG_WRITE_DONE_PENDING   0x130480

Definition at line 988 of file bnx2x_reg.h.

#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup   2

Definition at line 7132 of file bnx2x_reg.h.

#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup   3

Definition at line 7133 of file bnx2x_reg.h.

#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup   0

Definition at line 7130 of file bnx2x_reg.h.

#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup   1

Definition at line 7131 of file bnx2x_reg.h.

#define IGU_VF_CONF_FUNC_EN   (0x1<<0) /* function enable */

Definition at line 7186 of file bnx2x_reg.h.

#define IGU_VF_CONF_MSI_MSIX_EN   (0x1<<1) /* MSI/MSIX enable */

Definition at line 7187 of file bnx2x_reg.h.

#define IGU_VF_CONF_PARENT_MASK   (0x3<<2) /* Parent PF */

Definition at line 7188 of file bnx2x_reg.h.

#define IGU_VF_CONF_PARENT_SHIFT   2 /* Parent PF */

Definition at line 7189 of file bnx2x_reg.h.

#define IGU_VF_CONF_SINGLE_ISR_EN   (0x1<<4) /* single ISR mode enable */

Definition at line 7190 of file bnx2x_reg.h.

#define LATCHED_ATTN_RBCN   25

Definition at line 6049 of file bnx2x_reg.h.

#define LATCHED_ATTN_RBCP   27

Definition at line 6051 of file bnx2x_reg.h.

#define LATCHED_ATTN_RBCR   23

Definition at line 6047 of file bnx2x_reg.h.

#define LATCHED_ATTN_RBCT   24

Definition at line 6048 of file bnx2x_reg.h.

#define LATCHED_ATTN_RBCU   26

Definition at line 6050 of file bnx2x_reg.h.

#define LATCHED_ATTN_ROM_PARITY_MCP   30

Definition at line 6054 of file bnx2x_reg.h.

#define LATCHED_ATTN_RSVD_GRC   29

Definition at line 6053 of file bnx2x_reg.h.

#define LATCHED_ATTN_SCPAD_PARITY_MCP   33

Definition at line 6057 of file bnx2x_reg.h.

#define LATCHED_ATTN_TIMEOUT_GRC   28

Definition at line 6052 of file bnx2x_reg.h.

#define LATCHED_ATTN_UM_RX_PARITY_MCP   31

Definition at line 6055 of file bnx2x_reg.h.

#define LATCHED_ATTN_UM_TX_PARITY_MCP   32

Definition at line 6056 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_0   RESERVED_GENERAL_ATTENTION_BIT_12

Definition at line 6037 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_1   RESERVED_GENERAL_ATTENTION_BIT_13

Definition at line 6038 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_2   RESERVED_GENERAL_ATTENTION_BIT_14

Definition at line 6039 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_3   RESERVED_GENERAL_ATTENTION_BIT_15

Definition at line 6040 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_4   RESERVED_GENERAL_ATTENTION_BIT_16

Definition at line 6041 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_5   RESERVED_GENERAL_ATTENTION_BIT_17

Definition at line 6042 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_6   RESERVED_GENERAL_ATTENTION_BIT_18

Definition at line 6043 of file bnx2x_reg.h.

#define LINK_SYNC_ATTENTION_BIT_FUNC_7   RESERVED_GENERAL_ATTENTION_BIT_19

Definition at line 6044 of file bnx2x_reg.h.

#define MCP_A_REG_MCPR_SCRATCH   0x3a0000

Definition at line 989 of file bnx2x_reg.h.

#define MCP_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_11

Definition at line 6034 of file bnx2x_reg.h.

#define MCP_REG_MCPR_ACCESS_LOCK   0x8009c

Definition at line 990 of file bnx2x_reg.h.

#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER   0x8501c

Definition at line 998 of file bnx2x_reg.h.

#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER   0x8501c

Definition at line 998 of file bnx2x_reg.h.

#define MCP_REG_MCPR_GP_INPUTS   0x800c0

Definition at line 992 of file bnx2x_reg.h.

#define MCP_REG_MCPR_GP_OENABLE   0x800c8

Definition at line 993 of file bnx2x_reg.h.

#define MCP_REG_MCPR_GP_OUTPUTS   0x800c4

Definition at line 994 of file bnx2x_reg.h.

#define MCP_REG_MCPR_IMC_COMMAND   0x85900

Definition at line 995 of file bnx2x_reg.h.

#define MCP_REG_MCPR_IMC_DATAREG0   0x85920

Definition at line 996 of file bnx2x_reg.h.

#define MCP_REG_MCPR_IMC_SLAVE_CONTROL   0x85904

Definition at line 997 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_ACCESS_ENABLE   0x86424

Definition at line 999 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_ADDR   0x8640c

Definition at line 1000 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_CFG4   0x8642c

Definition at line 1001 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_COMMAND   0x86400

Definition at line 1002 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_READ   0x86410

Definition at line 1003 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_SW_ARB   0x86420

Definition at line 1004 of file bnx2x_reg.h.

#define MCP_REG_MCPR_NVM_WRITE   0x86408

Definition at line 1005 of file bnx2x_reg.h.

#define MCP_REG_MCPR_SCRATCH   0xa0000

Definition at line 1006 of file bnx2x_reg.h.

#define MCPR_ACCESS_LOCK_LOCK   (1L<<31)

Definition at line 5744 of file bnx2x_reg.h.

#define MCPR_IMC_COMMAND_ENABLE   (1L<<31)

Definition at line 2153 of file bnx2x_reg.h.

#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT   16

Definition at line 2154 of file bnx2x_reg.h.

#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT   28

Definition at line 2155 of file bnx2x_reg.h.

#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT   8

Definition at line 2156 of file bnx2x_reg.h.

#define MCPR_NVM_ACCESS_ENABLE_EN   (1L<<0)

Definition at line 5745 of file bnx2x_reg.h.

#define MCPR_NVM_ACCESS_ENABLE_WR_EN   (1L<<1)

Definition at line 5746 of file bnx2x_reg.h.

#define MCPR_NVM_ADDR_NVM_ADDR_VALUE   (0xffffffL<<0)

Definition at line 5747 of file bnx2x_reg.h.

#define MCPR_NVM_CFG4_FLASH_SIZE   (0x7L<<0)

Definition at line 5748 of file bnx2x_reg.h.

#define MCPR_NVM_COMMAND_DOIT   (1L<<4)

Definition at line 5749 of file bnx2x_reg.h.

#define MCPR_NVM_COMMAND_DONE   (1L<<3)

Definition at line 5750 of file bnx2x_reg.h.

#define MCPR_NVM_COMMAND_FIRST   (1L<<7)

Definition at line 5751 of file bnx2x_reg.h.

#define MCPR_NVM_COMMAND_LAST   (1L<<8)

Definition at line 5752 of file bnx2x_reg.h.

#define MCPR_NVM_COMMAND_WR   (1L<<5)

Definition at line 5753 of file bnx2x_reg.h.

#define MCPR_NVM_SW_ARB_ARB_ARB1   (1L<<9)

Definition at line 5754 of file bnx2x_reg.h.

#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1   (1L<<5)

Definition at line 5755 of file bnx2x_reg.h.

#define MCPR_NVM_SW_ARB_ARB_REQ_SET1   (1L<<1)

Definition at line 5756 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL   0x11

Definition at line 6608 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN   0x1

Definition at line 6609 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK   0x13

Definition at line 6610 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT   (0xb71<<1)

Definition at line 6611 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS   0x10

Definition at line 6606 of file bnx2x_reg.h.

#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK   0x8000

Definition at line 6607 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_COMMAND   MDIO_84833_TOP_CFG_SCRATCH_REG0

Definition at line 6944 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_DATA1   MDIO_84833_TOP_CFG_SCRATCH_REG27

Definition at line 6946 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_DATA2   MDIO_84833_TOP_CFG_SCRATCH_REG28

Definition at line 6947 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_DATA3   MDIO_84833_TOP_CFG_SCRATCH_REG29

Definition at line 6948 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_DATA4   MDIO_84833_TOP_CFG_SCRATCH_REG30

Definition at line 6949 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_DATA5   MDIO_84833_TOP_CFG_SCRATCH_REG31

Definition at line 6950 of file bnx2x_reg.h.

#define MDIO_84833_CMD_HDLR_STATUS   MDIO_84833_TOP_CFG_SCRATCH_REG26

Definition at line 6945 of file bnx2x_reg.h.

#define MDIO_84833_SUPER_ISOLATE   0x8000

Definition at line 6931 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_FW_EEE   0x10b1

Definition at line 6928 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_FW_NO_EEE   0x1f81

Definition at line 6929 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_FW_REV   0x400f

Definition at line 6927 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG0   0x4005

Definition at line 6933 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG1   0x4006

Definition at line 6934 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG2   0x4007

Definition at line 6935 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG26   0x4037

Definition at line 6938 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG27   0x4038

Definition at line 6939 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG28   0x4039

Definition at line 6940 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG29   0x403a

Definition at line 6941 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG3   0x4008

Definition at line 6936 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG30   0x403b

Definition at line 6942 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG31   0x403c

Definition at line 6943 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_SCRATCH_REG4   0x4009

Definition at line 6937 of file bnx2x_reg.h.

#define MDIO_84833_TOP_CFG_XGPHY_STRAP1   0x401a

Definition at line 6930 of file bnx2x_reg.h.

#define MDIO_AER_BLOCK_AER_REG   0x1E

Definition at line 6708 of file bnx2x_reg.h.

#define MDIO_AN_DEVAD   0x7

Definition at line 6857 of file bnx2x_reg.h.

#define MDIO_AN_REG_1000T_STATUS   0xffea

Definition at line 6880 of file bnx2x_reg.h.

#define MDIO_AN_REG_8073_2_5G   0x8329

Definition at line 6882 of file bnx2x_reg.h.

#define MDIO_AN_REG_8073_BAM   0x8350

Definition at line 6883 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_1000T_CTRL   0xffe9

Definition at line 6891 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL   0x0020

Definition at line 6885 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL   0xfff0

Definition at line 6892 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_AUX_CTRL   0xfff8

Definition at line 6896 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS   0xfff7

Definition at line 6895 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW   0xfff5

Definition at line 6894 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_LEGACY_AN_ADV   0xffe4

Definition at line 6889 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION   0xffe6

Definition at line 6890 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_LEGACY_MII_CTRL   0xffe0

Definition at line 6886 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_LEGACY_MII_STATUS   0xffe1

Definition at line 6888 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_LEGACY_SHADOW   0xfffc

Definition at line 6897 of file bnx2x_reg.h.

#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G   0x40

Definition at line 6887 of file bnx2x_reg.h.

#define MDIO_AN_REG_8727_MISC_CTRL   0x8309

Definition at line 6801 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV   0x0011

Definition at line 6867 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV2   0x0012

Definition at line 6868 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV_PAUSE   0x0010

Definition at line 6862 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC   0x0800

Definition at line 6864 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV_PAUSE_BOTH   0x0C00

Definition at line 6865 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV_PAUSE_MASK   0x0C00

Definition at line 6866 of file bnx2x_reg.h.

#define MDIO_AN_REG_ADV_PAUSE_PAUSE   0x0400

Definition at line 6863 of file bnx2x_reg.h.

#define MDIO_AN_REG_CL37_AN   0xffe0

Definition at line 6877 of file bnx2x_reg.h.

#define MDIO_AN_REG_CL37_CL73   0x8370

Definition at line 6876 of file bnx2x_reg.h.

#define MDIO_AN_REG_CL37_FC_LD   0xffe4

Definition at line 6878 of file bnx2x_reg.h.

#define MDIO_AN_REG_CL37_FC_LP   0xffe5

Definition at line 6879 of file bnx2x_reg.h.

#define MDIO_AN_REG_CTRL   0x0000

Definition at line 6859 of file bnx2x_reg.h.

#define MDIO_AN_REG_EEE_ADV   0x003c

Definition at line 6872 of file bnx2x_reg.h.

#define MDIO_AN_REG_LINK_STATUS   0x8304

Definition at line 6875 of file bnx2x_reg.h.

#define MDIO_AN_REG_LP_AUTO_NEG   0x0013

Definition at line 6869 of file bnx2x_reg.h.

#define MDIO_AN_REG_LP_AUTO_NEG2   0x0014

Definition at line 6870 of file bnx2x_reg.h.

#define MDIO_AN_REG_LP_EEE_ADV   0x003d

Definition at line 6873 of file bnx2x_reg.h.

#define MDIO_AN_REG_MASTER_STATUS   0x0021

Definition at line 6871 of file bnx2x_reg.h.

#define MDIO_AN_REG_STATUS   0x0001

Definition at line 6860 of file bnx2x_reg.h.

#define MDIO_AN_REG_STATUS_AN_COMPLETE   0x0020

Definition at line 6861 of file bnx2x_reg.h.

#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL   0x10

Definition at line 6690 of file bnx2x_reg.h.

#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE   0x0001

Definition at line 6691 of file bnx2x_reg.h.

#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN   0x0002

Definition at line 6692 of file bnx2x_reg.h.

#define MDIO_BLOCK0_XGXS_CONTROL   0x10

Definition at line 6554 of file bnx2x_reg.h.

#define MDIO_BLOCK1_LANE_CTRL0   0x15

Definition at line 6557 of file bnx2x_reg.h.

#define MDIO_BLOCK1_LANE_CTRL1   0x16

Definition at line 6558 of file bnx2x_reg.h.

#define MDIO_BLOCK1_LANE_CTRL2   0x17

Definition at line 6559 of file bnx2x_reg.h.

#define MDIO_BLOCK1_LANE_PRBS   0x19

Definition at line 6560 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL   0x0

Definition at line 6454 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN   0x1000

Definition at line 6456 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST   0x8000

Definition at line 6457 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN   0x0200

Definition at line 6455 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV1   0x00

Definition at line 6460 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC   0x0800

Definition at line 6462 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE   0x0400

Definition at line 6461 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH   0x0C00

Definition at line 6463 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK   0x0C00

Definition at line 6464 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV2   0x01

Definition at line 6465 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M   0x0000

Definition at line 6466 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX   0x0020

Definition at line 6467 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR   0x0080

Definition at line 6469 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4   0x0040

Definition at line 6468 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV1   0x03

Definition at line 6470 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC   0x0800

Definition at line 6472 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE   0x0400

Definition at line 6471 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH   0x0C00

Definition at line 6473 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK   0x0C00

Definition at line 6474 of file bnx2x_reg.h.

#define MDIO_CL73_IEEEB1_AN_LP_ADV2   0x04

Definition at line 6475 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL1   0x12

Definition at line 6700 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN   0x8000

Definition at line 6701 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN   0x2000

Definition at line 6703 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN   0x4000

Definition at line 6702 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL3   0x14

Definition at line 6704 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR   0x0001

Definition at line 6705 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_UCTRL   0x10

Definition at line 6695 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL   0x0002

Definition at line 6696 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_USTAT1   0x11

Definition at line 6697 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37   0x0400

Definition at line 6699 of file bnx2x_reg.h.

#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK   0x0100

Definition at line 6698 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV   0x14

Definition at line 6724 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX   0x0020

Definition at line 6725 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX   0x0040

Definition at line 6726 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE   0x8000

Definition at line 6732 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC   0x0100

Definition at line 6730 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH   0x0180

Definition at line 6731 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK   0x0180

Definition at line 6727 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE   0x0000

Definition at line 6728 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC   0x0080

Definition at line 6729 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1   0x15

Definition at line 6733 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK   0x4000

Definition at line 6735 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP   0x0020

Definition at line 6740 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP   0x0040

Definition at line 6739 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE   0x8000

Definition at line 6734 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH   0x0180

Definition at line 6738 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK   0x0180

Definition at line 6736 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE   0x0000

Definition at line 6737 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE   0x0001

Definition at line 6744 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_MII_CONTROL   0x10

Definition at line 6711 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_MII_STATUS   0x11

Definition at line 6721 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE   0x0020

Definition at line 6723 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS   0x0004

Definition at line 6722 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN   0x1000

Definition at line 6718 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX   0x0100

Definition at line 6716 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK   0x4000

Definition at line 6719 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10   0x0000

Definition at line 6713 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100   0x2000

Definition at line 6714 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000   0x0040

Definition at line 6715 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK   0x2040

Definition at line 6712 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_RESET   0x8000

Definition at line 6720 of file bnx2x_reg.h.

#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN   0x0200

Definition at line 6717 of file bnx2x_reg.h.

#define MDIO_CTL_DEVAD   0x1e

Definition at line 6900 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_CTRL_MAC_XFI   0x0008

Definition at line 6904 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA   0x401a

Definition at line 6901 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN   0x0080

Definition at line 6913 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G   0x1000

Definition at line 6917 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK   0x0060

Definition at line 6907 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L   0x0020

Definition at line 6908 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI   0x0040

Definition at line 6909 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK   0x0018

Definition at line 6902 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M   0x0010

Definition at line 6905 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER   0x0000

Definition at line 6915 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER   0x0100

Definition at line 6916 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK   0x0100

Definition at line 6914 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_USER_CTRL_CMS   0x0080

Definition at line 6919 of file bnx2x_reg.h.

#define MDIO_CTL_REG_84823_USER_CTRL_REG   0x4005

Definition at line 6918 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1   0x1B

Definition at line 6574 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M   0x0100

Definition at line 6585 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4   0x0700

Definition at line 6591 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG   0x0600

Definition at line 6590 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR   0x0F00

Definition at line 6599 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4   0x0E00

Definition at line 6598 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI   0x1F00

Definition at line 6602 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI   0x1B00

Definition at line 6600 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M   0x0000

Definition at line 6584 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G   0x0900

Definition at line 6593 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG   0x0800

Definition at line 6592 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G   0x0A00

Definition at line 6594 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G   0x0B00

Definition at line 6595 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G   0x0C00

Definition at line 6596 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G   0x0200

Definition at line 6586 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX   0x0D00

Definition at line 6597 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS   0x1E00

Definition at line 6601 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G   0x0300

Definition at line 6587 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G   0x0400

Definition at line 6588 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G   0x0500

Definition at line 6589 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK   0x3f00

Definition at line 6583 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE   0x0002

Definition at line 6576 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE   0x0001

Definition at line 6575 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE   0x0020

Definition at line 6580 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE   0x0010

Definition at line 6579 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS   0x0008

Definition at line 6578 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS   0x0004

Definition at line 6577 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE   0x0080

Definition at line 6582 of file bnx2x_reg.h.

#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE   0x0040

Definition at line 6581 of file bnx2x_reg.h.

#define MDIO_OVER_1G_DIGCTL_3_4   0x14

Definition at line 6657 of file bnx2x_reg.h.

#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK   0xffe0

Definition at line 6658 of file bnx2x_reg.h.

#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT   5

Definition at line 6659 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP1   0x1C

Definition at line 6677 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP2   0x1D

Definition at line 6678 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK   0x03ff

Definition at line 6679 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK   0x0780

Definition at line 6680 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT   7

Definition at line 6681 of file bnx2x_reg.h.

#define MDIO_OVER_1G_LP_UP3   0x1E

Definition at line 6682 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1   0x19

Definition at line 6660 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_10G   0x0010

Definition at line 6664 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_10GH   0x0008

Definition at line 6665 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_12_5G   0x0040

Definition at line 6667 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_12G   0x0020

Definition at line 6666 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_13G   0x0080

Definition at line 6668 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_15G   0x0100

Definition at line 6669 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_16G   0x0200

Definition at line 6670 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_2_5G   0x0001

Definition at line 6661 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_5G   0x0002

Definition at line 6662 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP1_6G   0x0004

Definition at line 6663 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP2   0x1A

Definition at line 6671 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP2_IDRIVER_MASK   0x0038

Definition at line 6673 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK   0x0007

Definition at line 6672 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK   0x03C0

Definition at line 6674 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP3   0x1B

Definition at line 6675 of file bnx2x_reg.h.

#define MDIO_OVER_1G_UP3_HIGIG2   0x0001

Definition at line 6676 of file bnx2x_reg.h.

#define MDIO_PCS_DEVAD   0x3

Definition at line 6831 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_DSP_ACCESS   0xD000

Definition at line 6834 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR   0xE028

Definition at line 6842 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR   0xE12A

Definition at line 6836 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR   0xE02A

Definition at line 6838 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)

Definition at line 6840 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD   (2)

Definition at line 6841 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD   (6)

Definition at line 6839 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_MUX   0xD008

Definition at line 6835 of file bnx2x_reg.h.

#define MDIO_PCS_REG_7101_SPI_RESET_BIT   (5)

Definition at line 6837 of file bnx2x_reg.h.

#define MDIO_PCS_REG_LASI_STATUS   0x9005

Definition at line 6833 of file bnx2x_reg.h.

#define MDIO_PCS_REG_STATUS   0x0020

Definition at line 6832 of file bnx2x_reg.h.

#define MDIO_PMA_DEVAD   0x1

Definition at line 6747 of file bnx2x_reg.h.

#define MDIO_PMA_REG_10G_CTRL2   0x7

Definition at line 6751 of file bnx2x_reg.h.

#define MDIO_PMA_REG_7101_RESET   0xc000

Definition at line 6808 of file bnx2x_reg.h.

#define MDIO_PMA_REG_7101_VER1   0xc026

Definition at line 6811 of file bnx2x_reg.h.

#define MDIO_PMA_REG_7101_VER2   0xc027

Definition at line 6812 of file bnx2x_reg.h.

#define MDIO_PMA_REG_7107_LED_CNTL   0xc007

Definition at line 6809 of file bnx2x_reg.h.

#define MDIO_PMA_REG_7107_LINK_LED_CNTL   0xc009

Definition at line 6810 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8073_CHIP_REV   0xc801

Definition at line 6803 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL   0xcd08

Definition at line 6806 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS   0xc820

Definition at line 6804 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8073_XAUI_WA   0xc841

Definition at line 6805 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LED1_MASK   0xa82c

Definition at line 6815 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LED2_MASK   0xa82f

Definition at line 6816 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LED3_BLINK   0xa834

Definition at line 6818 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LED3_MASK   0xa832

Definition at line 6817 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LED5_MASK   0xa838

Definition at line 6819 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LINK_SIGNAL   0xa83b

Definition at line 6821 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK   0x800

Definition at line 6822 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT   11

Definition at line 6823 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_PMD_SIGNAL   0xa811

Definition at line 6814 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8481_SIGNAL_MASK   0xa835

Definition at line 6820 of file bnx2x_reg.h.

#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ   0x2f

Definition at line 6921 of file bnx2x_reg.h.

#define MDIO_PMA_REG_84823_CTL_LED_CTL_1   0xa8e3

Definition at line 6922 of file bnx2x_reg.h.

#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH   0xa82b

Definition at line 6920 of file bnx2x_reg.h.

#define MDIO_PMA_REG_84823_LED3_STRETCH_EN   0x0080

Definition at line 6924 of file bnx2x_reg.h.

#define MDIO_PMA_REG_84833_CTL_LED_CTL_1   0xa8ec

Definition at line 6923 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF   0xc820

Definition at line 6786 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK   0xff

Definition at line 6787 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8726_TX_CTRL1   0xca01

Definition at line 6788 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8726_TX_CTRL2   0xca05

Definition at line 6789 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_GPIO_CTRL   0xc80e

Definition at line 6797 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_OPT_CFG_REG   0xc8e4

Definition at line 6799 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_PCS_GP   0xc842

Definition at line 6798 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_PCS_OPT_CTRL   0xc808

Definition at line 6796 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF   0x8007

Definition at line 6792 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK   0xff

Definition at line 6793 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005

Definition at line 6791 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_TX_CTRL1   0xca02

Definition at line 6794 of file bnx2x_reg.h.

#define MDIO_PMA_REG_8727_TX_CTRL2   0xca05

Definition at line 6795 of file bnx2x_reg.h.

#define MDIO_PMA_REG_BCM_CTRL   0x0096

Definition at line 6755 of file bnx2x_reg.h.

#define MDIO_PMA_REG_CDR_BANDWIDTH   0xca46

Definition at line 6775 of file bnx2x_reg.h.

#define MDIO_PMA_REG_CMU_PLL_BYPASS   0xca09

Definition at line 6761 of file bnx2x_reg.h.

#define MDIO_PMA_REG_CTRL   0x0

Definition at line 6749 of file bnx2x_reg.h.

#define MDIO_PMA_REG_DIGITAL_CTRL   0xc808

Definition at line 6758 of file bnx2x_reg.h.

#define MDIO_PMA_REG_DIGITAL_STATUS   0xc809

Definition at line 6759 of file bnx2x_reg.h.

#define MDIO_PMA_REG_EDC_FFE_MAIN   0xca1b

Definition at line 6770 of file bnx2x_reg.h.

#define MDIO_PMA_REG_FEC_CTRL   0x00ab

Definition at line 6756 of file bnx2x_reg.h.

#define MDIO_PMA_REG_GEN_CTRL   0xca10

Definition at line 6763 of file bnx2x_reg.h.

#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET   0x018a

Definition at line 6765 of file bnx2x_reg.h.

#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP   0x0188

Definition at line 6764 of file bnx2x_reg.h.

#define MDIO_PMA_REG_LRM_MODE   0xca3f

Definition at line 6774 of file bnx2x_reg.h.

#define MDIO_PMA_REG_M8051_MSGIN_REG   0xca12

Definition at line 6766 of file bnx2x_reg.h.

#define MDIO_PMA_REG_M8051_MSGOUT_REG   0xca13

Definition at line 6767 of file bnx2x_reg.h.

#define MDIO_PMA_REG_MISC_CTRL   0xca0a

Definition at line 6762 of file bnx2x_reg.h.

#define MDIO_PMA_REG_MISC_CTRL0   0xca23

Definition at line 6773 of file bnx2x_reg.h.

#define MDIO_PMA_REG_MISC_CTRL1   0xca85

Definition at line 6776 of file bnx2x_reg.h.

#define MDIO_PMA_REG_PHY_IDENTIFIER   0xc800

Definition at line 6757 of file bnx2x_reg.h.

#define MDIO_PMA_REG_PLL_BANDWIDTH   0xca1d

Definition at line 6771 of file bnx2x_reg.h.

#define MDIO_PMA_REG_PLL_CTRL   0xca1e

Definition at line 6772 of file bnx2x_reg.h.

#define MDIO_PMA_REG_ROM_VER1   0xca19

Definition at line 6768 of file bnx2x_reg.h.

#define MDIO_PMA_REG_ROM_VER2   0xca1a

Definition at line 6769 of file bnx2x_reg.h.

#define MDIO_PMA_REG_RX_SD   0xa

Definition at line 6753 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT   0x8002

Definition at line 6784 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL   0x8000

Definition at line 6778 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK   0x000c

Definition at line 6779 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR   0x8003

Definition at line 6785 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE   0x0004

Definition at line 6781 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED   0x000c

Definition at line 6783 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE   0x0000

Definition at line 6780 of file bnx2x_reg.h.

#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS   0x0008

Definition at line 6782 of file bnx2x_reg.h.

#define MDIO_PMA_REG_STATUS   0x1

Definition at line 6750 of file bnx2x_reg.h.

#define MDIO_PMA_REG_TX_DISABLE   0x0009

Definition at line 6752 of file bnx2x_reg.h.

#define MDIO_PMA_REG_TX_POWER_DOWN   0xca02

Definition at line 6760 of file bnx2x_reg.h.

#define MDIO_REG_BANK_10G_PARALLEL_DETECT   0x8130

Definition at line 6605 of file bnx2x_reg.h.

#define MDIO_REG_BANK_AER_BLOCK   0xFFD0

Definition at line 6707 of file bnx2x_reg.h.

#define MDIO_REG_BANK_BAM_NEXT_PAGE   0x8350

Definition at line 6689 of file bnx2x_reg.h.

#define MDIO_REG_BANK_CL73_IEEEB0   0x0

Definition at line 6453 of file bnx2x_reg.h.

#define MDIO_REG_BANK_CL73_IEEEB1   0x10

Definition at line 6459 of file bnx2x_reg.h.

#define MDIO_REG_BANK_CL73_USERB0   0x8370

Definition at line 6694 of file bnx2x_reg.h.

#define MDIO_REG_BANK_COMBO_IEEE0   0xFFE0

Definition at line 6710 of file bnx2x_reg.h.

#define MDIO_REG_BANK_GP_STATUS   0x8120

Definition at line 6573 of file bnx2x_reg.h.

#define MDIO_REG_BANK_OVER_1G   0x8320

Definition at line 6656 of file bnx2x_reg.h.

#define MDIO_REG_BANK_REMOTE_PHY   0x8330

Definition at line 6684 of file bnx2x_reg.h.

#define MDIO_REG_BANK_RX0   0x80b0

Definition at line 6477 of file bnx2x_reg.h.

#define MDIO_REG_BANK_RX1   0x80c0

Definition at line 6485 of file bnx2x_reg.h.

#define MDIO_REG_BANK_RX2   0x80d0

Definition at line 6490 of file bnx2x_reg.h.

#define MDIO_REG_BANK_RX3   0x80e0

Definition at line 6495 of file bnx2x_reg.h.

#define MDIO_REG_BANK_RX_ALL   0x80f0

Definition at line 6500 of file bnx2x_reg.h.

#define MDIO_REG_BANK_SERDES_DIGITAL   0x8300

Definition at line 6613 of file bnx2x_reg.h.

#define MDIO_REG_BANK_TX0   0x8060

Definition at line 6505 of file bnx2x_reg.h.

#define MDIO_REG_BANK_TX1   0x8070

Definition at line 6517 of file bnx2x_reg.h.

#define MDIO_REG_BANK_TX2   0x8080

Definition at line 6529 of file bnx2x_reg.h.

#define MDIO_REG_BANK_TX3   0x8090

Definition at line 6541 of file bnx2x_reg.h.

#define MDIO_REG_BANK_XGXS_BLOCK0   0x8000

Definition at line 6553 of file bnx2x_reg.h.

#define MDIO_REG_BANK_XGXS_BLOCK1   0x8010

Definition at line 6556 of file bnx2x_reg.h.

#define MDIO_REG_BANK_XGXS_BLOCK2   0x8100

Definition at line 6562 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_AUX_STATUS   0x19

Definition at line 7103 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_CL45_ADDR_REG   0xd

Definition at line 7096 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_CL45_DATA_REG   0xe

Definition at line 7097 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_EEE_RESOLVED   0x803e

Definition at line 7098 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_EXP_ACCESS   0x17

Definition at line 7100 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_EXP_ACCESS_GATE   0x15

Definition at line 7099 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_EXP_ACCESS_TOP   0xd00

Definition at line 7101 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_EXP_TOP_2K_BUF   0x40

Definition at line 7102 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_ID_54618SE   0x5cd5

Definition at line 7095 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_PHYID_LSB   0x3

Definition at line 7094 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW   0x1c

Definition at line 7107 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED   (0x1e << 10)

Definition at line 7111 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD   (0x1 << 8)

Definition at line 7112 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW_LED_SEL1   (0x0d << 10)

Definition at line 7108 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW_LED_SEL2   (0x0e << 10)

Definition at line 7109 of file bnx2x_reg.h.

#define MDIO_REG_GPHY_SHADOW_WR_ENA   (0x1 << 15)

Definition at line 7110 of file bnx2x_reg.h.

#define MDIO_REG_INTR_MASK   0x1b

Definition at line 7105 of file bnx2x_reg.h.

#define MDIO_REG_INTR_MASK_LINK_STATUS   (0x1 << 1)

Definition at line 7106 of file bnx2x_reg.h.

#define MDIO_REG_INTR_STATUS   0x1a

Definition at line 7104 of file bnx2x_reg.h.

#define MDIO_REMOTE_PHY_MISC_RX_STATUS   0x10

Definition at line 6685 of file bnx2x_reg.h.

#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG   0x0600

Definition at line 6687 of file bnx2x_reg.h.

#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG   0x0010

Definition at line 6686 of file bnx2x_reg.h.

#define MDIO_RX0_RX_EQ_BOOST   0x1c

Definition at line 6481 of file bnx2x_reg.h.

#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7

Definition at line 6482 of file bnx2x_reg.h.

#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL   0x10

Definition at line 6483 of file bnx2x_reg.h.

#define MDIO_RX0_RX_STATUS   0x10

Definition at line 6478 of file bnx2x_reg.h.

#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE   0x1000

Definition at line 6480 of file bnx2x_reg.h.

#define MDIO_RX0_RX_STATUS_SIGDET   0x8000

Definition at line 6479 of file bnx2x_reg.h.

#define MDIO_RX1_RX_EQ_BOOST   0x1c

Definition at line 6486 of file bnx2x_reg.h.

#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7

Definition at line 6487 of file bnx2x_reg.h.

#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL   0x10

Definition at line 6488 of file bnx2x_reg.h.

#define MDIO_RX2_RX_EQ_BOOST   0x1c

Definition at line 6491 of file bnx2x_reg.h.

#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7

Definition at line 6492 of file bnx2x_reg.h.

#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL   0x10

Definition at line 6493 of file bnx2x_reg.h.

#define MDIO_RX3_RX_EQ_BOOST   0x1c

Definition at line 6496 of file bnx2x_reg.h.

#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7

Definition at line 6497 of file bnx2x_reg.h.

#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL   0x10

Definition at line 6498 of file bnx2x_reg.h.

#define MDIO_RX_ALL_RX_EQ_BOOST   0x1c

Definition at line 6501 of file bnx2x_reg.h.

#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK   0x7

Definition at line 6502 of file bnx2x_reg.h.

#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL   0x10

Definition at line 6503 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1   0x10

Definition at line 6614 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET   0x0010

Definition at line 6619 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE   0x0001

Definition at line 6615 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT   0x0008

Definition at line 6618 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE   0x0020

Definition at line 6620 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN   0x0004

Definition at line 6617 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF   0x0002

Definition at line 6616 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2   0x11

Definition at line 6621 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR   0x0040

Definition at line 6623 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN   0x0001

Definition at line 6622 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1   0x14

Definition at line 6624 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX   0x0004

Definition at line 6627 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK   0x0002

Definition at line 6626 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII   0x0001

Definition at line 6625 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M   0x0008

Definition at line 6632 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M   0x0000

Definition at line 6633 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G   0x0010

Definition at line 6631 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G   0x0018

Definition at line 6630 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK   0x0018

Definition at line 6628 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT   3

Definition at line 6629 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2   0x15

Definition at line 6634 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED   0x0002

Definition at line 6635 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1   0x18

Definition at line 6636 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4   0x0004

Definition at line 6649 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG   0x0003

Definition at line 6648 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G   0x0006

Definition at line 6651 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G   0x0005

Definition at line 6650 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G   0x0007

Definition at line 6652 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G   0x0008

Definition at line 6653 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G   0x0009

Definition at line 6654 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G   0x0000

Definition at line 6645 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G   0x0001

Definition at line 6646 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G   0x0002

Definition at line 6647 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK   0x000f

Definition at line 6644 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL   0x0010

Definition at line 6643 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M   0x2000

Definition at line 6639 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M   0x4000

Definition at line 6640 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M   0x6000

Definition at line 6641 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M   0x8000

Definition at line 6642 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M   0x0000

Definition at line 6638 of file bnx2x_reg.h.

#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK   0xE000

Definition at line 6637 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER   0x17

Definition at line 6506 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_ICBUF1T   1

Definition at line 6551 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_ICBUF1T   1

Definition at line 6551 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_ICBUF1T   1

Definition at line 6551 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_ICBUF1T   1

Definition at line 6551 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00

Definition at line 6545 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00

Definition at line 6545 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00

Definition at line 6545 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00

Definition at line 6545 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8

Definition at line 6546 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8

Definition at line 6546 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8

Definition at line 6546 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT   8

Definition at line 6546 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e

Definition at line 6549 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e

Definition at line 6549 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e

Definition at line 6549 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK   0x000e

Definition at line 6549 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1

Definition at line 6550 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1

Definition at line 6550 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1

Definition at line 6550 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT   1

Definition at line 6550 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0

Definition at line 6547 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0

Definition at line 6547 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0

Definition at line 6547 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK   0x00f0

Definition at line 6547 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4

Definition at line 6548 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4

Definition at line 6548 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4

Definition at line 6548 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT   4

Definition at line 6548 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000

Definition at line 6543 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000

Definition at line 6543 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000

Definition at line 6543 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK   0xf000

Definition at line 6543 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12

Definition at line 6544 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12

Definition at line 6544 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12

Definition at line 6544 of file bnx2x_reg.h.

#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT   12

Definition at line 6544 of file bnx2x_reg.h.

#define MDIO_TX1_TX_DRIVER   0x17

Definition at line 6518 of file bnx2x_reg.h.

#define MDIO_TX2_TX_DRIVER   0x17

Definition at line 6530 of file bnx2x_reg.h.

#define MDIO_TX3_TX_DRIVER   0x17

Definition at line 6542 of file bnx2x_reg.h.

#define MDIO_WC0_XGXS_BLK2_LANE_RESET   0x810A

Definition at line 7085 of file bnx2x_reg.h.

#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT   0

Definition at line 7086 of file bnx2x_reg.h.

#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT   4

Definition at line 7087 of file bnx2x_reg.h.

#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2   0x8141

Definition at line 7089 of file bnx2x_reg.h.

#define MDIO_WC_DEVAD   0x3

Definition at line 6969 of file bnx2x_reg.h.

#define MDIO_WC_REG_AERBLK_AER   0xffde

Definition at line 7081 of file bnx2x_reg.h.

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY   0x4000

Definition at line 6975 of file bnx2x_reg.h.

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ   0x8000

Definition at line 6976 of file bnx2x_reg.h.

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0   0x10

Definition at line 6972 of file bnx2x_reg.h.

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1   0x11

Definition at line 6973 of file bnx2x_reg.h.

#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2   0x12

Definition at line 6974 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL49_USERB0_CTRL   0x8368

Definition at line 7062 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL   0x82e8

Definition at line 7046 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL   0x82e7

Definition at line 7045 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL   0x82e3

Definition at line 7043 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL   0x82ec

Definition at line 7047 of file bnx2x_reg.h.

#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL   0x82e6

Definition at line 7044 of file bnx2x_reg.h.

#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL   0xffe0

Definition at line 7082 of file bnx2x_reg.h.

#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT   0xffe1

Definition at line 7083 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL3_LP_UP1   0x832c

Definition at line 7055 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL3_UP1   0x8329

Definition at line 7054 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL4_MISC3   0x833c

Definition at line 7056 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL4_MISC5   0x833e

Definition at line 7057 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED   0x834e

Definition at line 7060 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL5_MISC6   0x8345

Definition at line 7058 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL5_MISC7   0x8349

Definition at line 7059 of file bnx2x_reg.h.

#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL   0x8350

Definition at line 7061 of file bnx2x_reg.h.

#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0   0x821e

Definition at line 7034 of file bnx2x_reg.h.

#define MDIO_WC_REG_DSC_SMC   0x8213

Definition at line 7033 of file bnx2x_reg.h.

#define MDIO_WC_REG_EEE_COMBO_CONTROL0   0x8390

Definition at line 7063 of file bnx2x_reg.h.

#define MDIO_WC_REG_FX100_CTRL1   0x8400

Definition at line 7074 of file bnx2x_reg.h.

#define MDIO_WC_REG_FX100_CTRL3   0x8402

Definition at line 7075 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_0   0x81d0

Definition at line 7011 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_1   0x81d1

Definition at line 7012 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_2   0x81d2

Definition at line 7013 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_3   0x81d3

Definition at line 7014 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_4   0x81d4

Definition at line 7015 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP   0x1

Definition at line 7019 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL   0x0100

Definition at line 7017 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP   0x0010

Definition at line 7018 of file bnx2x_reg.h.

#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL   0x1000

Definition at line 7016 of file bnx2x_reg.h.

#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP   0x7

Definition at line 6971 of file bnx2x_reg.h.

#define MDIO_WC_REG_IEEE0BLK_MIICNTL   0x0

Definition at line 6970 of file bnx2x_reg.h.

#define MDIO_WC_REG_MICROBLK_CMD   0xffc2

Definition at line 7077 of file bnx2x_reg.h.

#define MDIO_WC_REG_MICROBLK_CMD3   0xffcc

Definition at line 7079 of file bnx2x_reg.h.

#define MDIO_WC_REG_MICROBLK_DL_STATUS   0xffc5

Definition at line 7078 of file bnx2x_reg.h.

#define MDIO_WC_REG_PAR_DET_10G_CTRL   0x8131

Definition at line 7007 of file bnx2x_reg.h.

#define MDIO_WC_REG_PAR_DET_10G_STATUS   0x8130

Definition at line 7006 of file bnx2x_reg.h.

#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150   0x96

Definition at line 6977 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX0_ANARXCONTROL1G   0x80b9

Definition at line 6998 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX0_PCI_CTRL   0x80ba

Definition at line 7000 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX1_PCI_CTRL   0x80ca

Definition at line 7001 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX2_ANARXCONTROL1G   0x80d9

Definition at line 6999 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX2_PCI_CTRL   0x80da

Definition at line 7002 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX3_PCI_CTRL   0x80ea

Definition at line 7003 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_CONTROL   0x83c0

Definition at line 7065 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW0   0x83c2

Definition at line 7066 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW0_MASK   0x83c6

Definition at line 7070 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW1   0x83c3

Definition at line 7067 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW1_MASK   0x83c7

Definition at line 7071 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW2   0x83c4

Definition at line 7068 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW2_MASK   0x83c8

Definition at line 7072 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW3   0x83c5

Definition at line 7069 of file bnx2x_reg.h.

#define MDIO_WC_REG_RX66_SCW3_MASK   0x83c9

Definition at line 7073 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1   0x8300

Definition at line 7048 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2   0x8301

Definition at line 7049 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3   0x8302

Definition at line 7050 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_MISC1   0x8308

Definition at line 7052 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_MISC2   0x8309

Definition at line 7053 of file bnx2x_reg.h.

#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1   0x8304

Definition at line 7051 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_ANA_CTRL0   0x8061

Definition at line 6984 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER   0x8067

Definition at line 6988 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK   0x0f00

Definition at line 6992 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET   0x08

Definition at line 6991 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK   0x00f0

Definition at line 6990 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET   0x04

Definition at line 6989 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK   0x7000

Definition at line 6994 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET   0x0c

Definition at line 6993 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX1_ANA_CTRL0   0x8071

Definition at line 6985 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX1_TX_DRIVER   0x8077

Definition at line 6995 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX2_ANA_CTRL0   0x8081

Definition at line 6986 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX2_TX_DRIVER   0x8087

Definition at line 6996 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX3_ANA_CTRL0   0x8091

Definition at line 6987 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX3_TX_DRIVER   0x8097

Definition at line 6997 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX66_CONTROL   0x83b0

Definition at line 7064 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP   0x82e2

Definition at line 7035 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_ENABLE   0x8000

Definition at line 7042 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK   0x03f0

Definition at line 7039 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET   0x04

Definition at line 7038 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK   0x7c00

Definition at line 7041 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET   0x0a

Definition at line 7040 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK   0x000f

Definition at line 7037 of file bnx2x_reg.h.

#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET   0x00

Definition at line 7036 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP   0x81EE

Definition at line 7020 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_CRC   0x81FE

Definition at line 7032 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET   0x0

Definition at line 7023 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET   0x4

Definition at line 7029 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET   0x8

Definition at line 7030 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET   0xc

Definition at line 7031 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE   0x81F2

Definition at line 7022 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT   0x0

Definition at line 7024 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G   0x4

Definition at line 7028 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC   0x2

Definition at line 7026 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR   0x1

Definition at line 7025 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI   0x3

Definition at line 7027 of file bnx2x_reg.h.

#define MDIO_WC_REG_UC_INFO_B1_VERSION   0x81F0

Definition at line 7021 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXS_RX_LN_SWAP1   0x816B

Definition at line 7009 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXS_STATUS3   0x8129

Definition at line 7005 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXS_TX_LN_SWAP1   0x8169

Definition at line 7010 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXS_X2_CONTROL2   0x8141

Definition at line 7008 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1   0x800e

Definition at line 6979 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL   0x8000

Definition at line 6978 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK1_DESKEW   0x8010

Definition at line 6980 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK1_LANECTRL0   0x8015

Definition at line 6981 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK1_LANECTRL1   0x8016

Definition at line 6982 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK1_LANECTRL2   0x8017

Definition at line 6983 of file bnx2x_reg.h.

#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G   0x8104

Definition at line 7004 of file bnx2x_reg.h.

#define MDIO_WIS_DEVAD   0x2

Definition at line 6826 of file bnx2x_reg.h.

#define MDIO_WIS_REG_LASI_CNTL   0x9002

Definition at line 6828 of file bnx2x_reg.h.

#define MDIO_WIS_REG_LASI_STATUS   0x9005

Definition at line 6829 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_RX_LN_SWAP   0x10

Definition at line 6563 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE   0x8000

Definition at line 6564 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE   0x4000

Definition at line 6565 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE   0x15

Definition at line 6571 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_TX_LN_SWAP   0x11

Definition at line 6566 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE   0x8000

Definition at line 6567 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G   0x14

Definition at line 6568 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS   0x0001

Definition at line 6569 of file bnx2x_reg.h.

#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS   0x0010

Definition at line 6570 of file bnx2x_reg.h.

#define MDIO_XS_8706_REG_BANK_RX0   0x80bc

Definition at line 6849 of file bnx2x_reg.h.

#define MDIO_XS_8706_REG_BANK_RX1   0x80cc

Definition at line 6850 of file bnx2x_reg.h.

#define MDIO_XS_8706_REG_BANK_RX2   0x80dc

Definition at line 6851 of file bnx2x_reg.h.

#define MDIO_XS_8706_REG_BANK_RX3   0x80ec

Definition at line 6852 of file bnx2x_reg.h.

#define MDIO_XS_8706_REG_BANK_RXA   0x80fc

Definition at line 6853 of file bnx2x_reg.h.

#define MDIO_XS_DEVAD   0x4

Definition at line 6845 of file bnx2x_reg.h.

#define MDIO_XS_PLL_SEQUENCER   0x8000

Definition at line 6846 of file bnx2x_reg.h.

#define MDIO_XS_REG_8073_RX_CTRL_PCIE   0x80FA

Definition at line 6855 of file bnx2x_reg.h.

#define MDIO_XS_SFX7101_XGXS_TEST1   0xc00a

Definition at line 6847 of file bnx2x_reg.h.

#define ME_REG_ABS_PF_NUM   (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */

Definition at line 6449 of file bnx2x_reg.h.

#define ME_REG_ABS_PF_NUM_SHIFT   16

Definition at line 6448 of file bnx2x_reg.h.

#define ME_REG_PF_NUM   (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */

Definition at line 6442 of file bnx2x_reg.h.

#define ME_REG_PF_NUM_SHIFT   0

Definition at line 6441 of file bnx2x_reg.h.

#define ME_REG_VF_ERR   (0x1<<3)

Definition at line 6447 of file bnx2x_reg.h.

#define ME_REG_VF_NUM_MASK   (0x3f<<ME_REG_VF_NUM_SHIFT)

Definition at line 6446 of file bnx2x_reg.h.

#define ME_REG_VF_NUM_SHIFT   9

Definition at line 6445 of file bnx2x_reg.h.

#define ME_REG_VF_VALID   (1<<8)

Definition at line 6444 of file bnx2x_reg.h.

#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF   0x0008

Definition at line 6893 of file bnx2x_reg.h.

#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK   (0x1<<1)

Definition at line 1007 of file bnx2x_reg.h.

#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK   (0x1<<0)

Definition at line 1008 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0   0xa42c

Definition at line 1022 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1   0xa430

Definition at line 1023 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_1_MCP   0xa434

Definition at line 1037 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0   0xa438

Definition at line 1051 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1   0xa43c

Definition at line 1052 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_2_MCP   0xa440

Definition at line 1065 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0   0xa444

Definition at line 1079 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1   0xa448

Definition at line 1080 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_3_MCP   0xa44c

Definition at line 1093 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0   0xa450

Definition at line 1106 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1   0xa454

Definition at line 1107 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_4_MCP   0xa458

Definition at line 1120 of file bnx2x_reg.h.

#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0   0xa700

Definition at line 1125 of file bnx2x_reg.h.

#define MISC_REG_AEU_CLR_LATCH_SIGNAL   0xa45c

Definition at line 1136 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0   0xa06c

Definition at line 1150 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1   0xa07c

Definition at line 1151 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2   0xa08c

Definition at line 1152 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3   0xa09c

Definition at line 1153 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5   0xa0bc

Definition at line 1154 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6   0xa0cc

Definition at line 1155 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7   0xa0dc

Definition at line 1156 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0   0xa10c

Definition at line 1170 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1   0xa11c

Definition at line 1171 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2   0xa12c

Definition at line 1172 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3   0xa13c

Definition at line 1173 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5   0xa15c

Definition at line 1174 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6   0xa16c

Definition at line 1175 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7   0xa17c

Definition at line 1176 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_NIG_0   0xa0ec

Definition at line 1190 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_NIG_1   0xa18c

Definition at line 1191 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_PXP_0   0xa0fc

Definition at line 1205 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE1_PXP_1   0xa19c

Definition at line 1206 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0   0xa070

Definition at line 1220 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1   0xa080

Definition at line 1221 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0   0xa110

Definition at line 1235 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1   0xa120

Definition at line 1236 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_NIG_0   0xa0f0

Definition at line 1250 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_NIG_1   0xa190

Definition at line 1251 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_PXP_0   0xa100

Definition at line 1265 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE2_PXP_1   0xa1a0

Definition at line 1266 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0   0xa074

Definition at line 1280 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1   0xa084

Definition at line 1281 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0   0xa114

Definition at line 1295 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1   0xa124

Definition at line 1296 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_NIG_0   0xa0f4

Definition at line 1310 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_NIG_1   0xa194

Definition at line 1311 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_PXP_0   0xa104

Definition at line 1325 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE3_PXP_1   0xa1a4

Definition at line 1326 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0   0xa078

Definition at line 1339 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2   0xa098

Definition at line 1340 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4   0xa0b8

Definition at line 1341 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5   0xa0c8

Definition at line 1342 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6   0xa0d8

Definition at line 1343 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7   0xa0e8

Definition at line 1344 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0   0xa118

Definition at line 1357 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2   0xa138

Definition at line 1358 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4   0xa158

Definition at line 1359 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5   0xa168

Definition at line 1360 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6   0xa178

Definition at line 1361 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7   0xa188

Definition at line 1362 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_NIG_0   0xa0f8

Definition at line 1375 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_NIG_1   0xa198

Definition at line 1376 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_PXP_0   0xa108

Definition at line 1389 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE4_PXP_1   0xa1a8

Definition at line 1390 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0   0xa688

Definition at line 1396 of file bnx2x_reg.h.

#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0   0xa6b0

Definition at line 1402 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_0   0xa000

Definition at line 1405 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_1   0xa004

Definition at line 1406 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_10   0xa028

Definition at line 1407 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_11   0xa02c

Definition at line 1408 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_12   0xa030

Definition at line 1409 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_2   0xa008

Definition at line 1410 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_3   0xa00c

Definition at line 1411 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_4   0xa010

Definition at line 1412 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_5   0xa014

Definition at line 1413 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_6   0xa018

Definition at line 1414 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_7   0xa01c

Definition at line 1415 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_8   0xa020

Definition at line 1416 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_ATTN_9   0xa024

Definition at line 1417 of file bnx2x_reg.h.

#define MISC_REG_AEU_GENERAL_MASK   0xa61c

Definition at line 1418 of file bnx2x_reg.h.

#define MISC_REG_AEU_INVERTER_1_FUNC_0   0xa22c

Definition at line 1432 of file bnx2x_reg.h.

#define MISC_REG_AEU_INVERTER_1_FUNC_1   0xa23c

Definition at line 1433 of file bnx2x_reg.h.

#define MISC_REG_AEU_INVERTER_2_FUNC_0   0xa230

Definition at line 1447 of file bnx2x_reg.h.

#define MISC_REG_AEU_INVERTER_2_FUNC_1   0xa240

Definition at line 1448 of file bnx2x_reg.h.

#define MISC_REG_AEU_MASK_ATTN_FUNC_0   0xa060

Definition at line 1451 of file bnx2x_reg.h.

#define MISC_REG_AEU_MASK_ATTN_FUNC_1   0xa064

Definition at line 1452 of file bnx2x_reg.h.

#define MISC_REG_AEU_SYS_KILL_OCCURRED   0xa610

Definition at line 1454 of file bnx2x_reg.h.

#define MISC_REG_AEU_SYS_KILL_STATUS_0   0xa600

Definition at line 1469 of file bnx2x_reg.h.

#define MISC_REG_AEU_SYS_KILL_STATUS_1   0xa604

Definition at line 1470 of file bnx2x_reg.h.

#define MISC_REG_AEU_SYS_KILL_STATUS_2   0xa608

Definition at line 1471 of file bnx2x_reg.h.

#define MISC_REG_AEU_SYS_KILL_STATUS_3   0xa60c

Definition at line 1472 of file bnx2x_reg.h.

#define MISC_REG_BOND_ID   0xa400

Definition at line 1475 of file bnx2x_reg.h.

#define MISC_REG_CHIP_METAL   0xa404

Definition at line 1479 of file bnx2x_reg.h.

#define MISC_REG_CHIP_NUM   0xa408

Definition at line 1481 of file bnx2x_reg.h.

#define MISC_REG_CHIP_REV   0xa40c

Definition at line 1485 of file bnx2x_reg.h.

#define MISC_REG_CHIP_TYPE   0xac60

Definition at line 1489 of file bnx2x_reg.h.

#define MISC_REG_CHIP_TYPE_57811_MASK   (1<<1)

Definition at line 1490 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_DR_ENABLE   0xa858

Definition at line 1491 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_FW_ENABLE_P0   0xa84c

Definition at line 1495 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_IDLE_THR_P0   0xa8a0

Definition at line 1498 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_MASK_ENT_P0   0xa880

Definition at line 1549 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_MASK_EXT_P0   0xa888

Definition at line 1601 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0   0xa8b8

Definition at line 1605 of file bnx2x_reg.h.

#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1   0xa8bc

Definition at line 1609 of file bnx2x_reg.h.

#define MISC_REG_DRIVER_CONTROL_1   0xa510

Definition at line 1626 of file bnx2x_reg.h.

#define MISC_REG_DRIVER_CONTROL_7   0xa3c8

Definition at line 1627 of file bnx2x_reg.h.

#define MISC_REG_E1HMF_MODE   0xa5f8

Definition at line 1630 of file bnx2x_reg.h.

#define MISC_REG_FOUR_PORT_PATH_SWAP   0xa75c

Definition at line 1632 of file bnx2x_reg.h.

#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR   0xa738

Definition at line 1638 of file bnx2x_reg.h.

#define MISC_REG_FOUR_PORT_PORT_SWAP   0xa754

Definition at line 1640 of file bnx2x_reg.h.

#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR   0xa734

Definition at line 1646 of file bnx2x_reg.h.

#define MISC_REG_GEN_PURP_HWG   0xa9a0

Definition at line 1661 of file bnx2x_reg.h.

#define MISC_REG_GENERIC_CR_0   0xa460

Definition at line 1648 of file bnx2x_reg.h.

#define MISC_REG_GENERIC_CR_1   0xa464

Definition at line 1649 of file bnx2x_reg.h.

#define MISC_REG_GENERIC_POR_1   0xa474

Definition at line 1651 of file bnx2x_reg.h.

#define MISC_REG_GPIO   0xa490

Definition at line 1678 of file bnx2x_reg.h.

#define MISC_REG_GPIO_EVENT_EN   0xa2bc

Definition at line 1683 of file bnx2x_reg.h.

#define MISC_REG_GPIO_INT   0xa494

Definition at line 1701 of file bnx2x_reg.h.

#define MISC_REG_GRC_RSV_ATTN   0xa3c0

Definition at line 1707 of file bnx2x_reg.h.

#define MISC_REG_GRC_TIMEOUT_ATTN   0xa3c4

Definition at line 1713 of file bnx2x_reg.h.

#define MISC_REG_GRC_TIMEOUT_EN   0xa280

Definition at line 1719 of file bnx2x_reg.h.

#define MISC_REG_LCPLL_CTRL_1   0xa2a4

Definition at line 1748 of file bnx2x_reg.h.

#define MISC_REG_LCPLL_CTRL_REG_2   0xa2a8

Definition at line 1749 of file bnx2x_reg.h.

#define MISC_REG_LCPLL_E40_PWRDWN   0xaa74

Definition at line 1752 of file bnx2x_reg.h.

#define MISC_REG_LCPLL_E40_RESETB_ANA   0xaa78

Definition at line 1754 of file bnx2x_reg.h.

#define MISC_REG_LCPLL_E40_RESETB_DIG   0xaa7c

Definition at line 1757 of file bnx2x_reg.h.

#define MISC_REG_MISC_INT_MASK   0xa388

Definition at line 1759 of file bnx2x_reg.h.

#define MISC_REG_MISC_PRTY_MASK   0xa398

Definition at line 1761 of file bnx2x_reg.h.

#define MISC_REG_MISC_PRTY_STS   0xa38c

Definition at line 1763 of file bnx2x_reg.h.

#define MISC_REG_MISC_PRTY_STS_CLR   0xa390

Definition at line 1765 of file bnx2x_reg.h.

#define MISC_REG_NIG_WOL_P0   0xa270

Definition at line 1766 of file bnx2x_reg.h.

#define MISC_REG_NIG_WOL_P1   0xa274

Definition at line 1767 of file bnx2x_reg.h.

#define MISC_REG_PCIE_HOT_RESET   0xa618

Definition at line 1770 of file bnx2x_reg.h.

#define MISC_REG_PLL_STORM_CTRL_1   0xa294

Definition at line 1788 of file bnx2x_reg.h.

#define MISC_REG_PLL_STORM_CTRL_2   0xa298

Definition at line 1789 of file bnx2x_reg.h.

#define MISC_REG_PLL_STORM_CTRL_3   0xa29c

Definition at line 1790 of file bnx2x_reg.h.

#define MISC_REG_PLL_STORM_CTRL_4   0xa2a0

Definition at line 1791 of file bnx2x_reg.h.

#define MISC_REG_PORT4MODE_EN   0xa750

Definition at line 1793 of file bnx2x_reg.h.

#define MISC_REG_PORT4MODE_EN_OVWR   0xa720

Definition at line 1799 of file bnx2x_reg.h.

#define MISC_REG_RESET_REG_1   0xa580

Definition at line 1814 of file bnx2x_reg.h.

#define MISC_REG_RESET_REG_2   0xa590

Definition at line 1815 of file bnx2x_reg.h.

#define MISC_REG_SHARED_MEM_ADDR   0xa2b4

Definition at line 1818 of file bnx2x_reg.h.

#define MISC_REG_SPIO   0xa4fc

Definition at line 1844 of file bnx2x_reg.h.

#define MISC_REG_SPIO_EVENT_EN   0xa2b8

Definition at line 1848 of file bnx2x_reg.h.

#define MISC_REG_SPIO_INT   0xa500

Definition at line 1864 of file bnx2x_reg.h.

#define MISC_REG_SW_TIMER_RELOAD_VAL_4   0xa2fc

Definition at line 1868 of file bnx2x_reg.h.

#define MISC_REG_SW_TIMER_VAL   0xa5c0

Definition at line 1872 of file bnx2x_reg.h.

#define MISC_REG_TWO_PORT_PATH_SWAP   0xa758

Definition at line 1874 of file bnx2x_reg.h.

#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR   0xa72c

Definition at line 1880 of file bnx2x_reg.h.

#define MISC_REG_UNPREPARED   0xa424

Definition at line 1883 of file bnx2x_reg.h.

#define MISC_REG_WC0_CTRL_PHY_ADDR   0xa9cc

Definition at line 1893 of file bnx2x_reg.h.

#define MISC_REG_WC0_RESET   0xac30

Definition at line 1894 of file bnx2x_reg.h.

#define MISC_REG_XMAC_CORE_PORT_MODE   0xa964

Definition at line 1902 of file bnx2x_reg.h.

#define MISC_REG_XMAC_PHY_PORT_MODE   0xa960

Definition at line 1908 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_0   0

Definition at line 5852 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_1   1

Definition at line 5853 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_2   2

Definition at line 5854 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_3   3

Definition at line 5855 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_CLR_POS   16

Definition at line 5856 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_FLOAT   (0xffL<<24)

Definition at line 5857 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_FLOAT_POS   24

Definition at line 5858 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_HIGH   1

Definition at line 5859 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_INPUT_HI_Z   2

Definition at line 5860 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_INT_CLR_POS   24

Definition at line 5861 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR   0

Definition at line 5862 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET   1

Definition at line 5863 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_INT_SET_POS   16

Definition at line 5864 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_LOW   0

Definition at line 5865 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_OUTPUT_HIGH   1

Definition at line 5866 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_OUTPUT_LOW   0

Definition at line 5867 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_PORT_SHIFT   4

Definition at line 5868 of file bnx2x_reg.h.

#define MISC_REGISTERS_GPIO_SET_POS   8

Definition at line 5869 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_CLEAR   0x588

Definition at line 5870 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_BRB1   (0x1<<0)

Definition at line 5871 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_DORQ   (0x1<<19)

Definition at line 5872 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_HC   (0x1<<29)

Definition at line 5873 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_NIG   (0x1<<7)

Definition at line 5874 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_PXP   (0x1<<26)

Definition at line 5875 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_RST_PXPV   (0x1<<27)

Definition at line 5876 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_1_SET   0x584

Definition at line 5877 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_CLEAR   0x598

Definition at line 5878 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_MSTAT0   (0x1<<24)

Definition at line 5879 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_MSTAT1   (0x1<<25)

Definition at line 5880 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_PGLC   (0x1<<19)

Definition at line 5881 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_ATC   (0x1<<17)

Definition at line 5882 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0   (0x1<<0)

Definition at line 5883 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1   (0x1<<1)

Definition at line 5884 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0   (0x1<<2)

Definition at line 5885 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE   (0x1<<14)

Definition at line 5886 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1   (0x1<<3)

Definition at line 5887 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE   (0x1<<15)

Definition at line 5888 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_GRC   (0x1<<4)

Definition at line 5889 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B   (0x1<<6)

Definition at line 5890 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE   (0x1<<8)

Definition at line 5891 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU   (0x1<<7)

Definition at line 5892 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE   (0x1<<5)

Definition at line 5893 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MDIO   (0x1<<13)

Definition at line 5894 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE   (0x1<<11)

Definition at line 5895 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO   (0x1<<13)

Definition at line 5896 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_RST_RBCN   (0x1<<9)

Definition at line 5897 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_SET   0x594

Definition at line 5898 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_UMAC0   (0x1<<20)

Definition at line 5899 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_UMAC1   (0x1<<21)

Definition at line 5900 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_XMAC   (0x1<<22)

Definition at line 5901 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT   (0x1<<23)

Definition at line 5902 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_CLEAR   0x5a8

Definition at line 5903 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ   (0x1<<1)

Definition at line 5904 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN   (0x1<<2)

Definition at line 5905 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD   (0x1<<3)

Definition at line 5906 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW   (0x1<<0)

Definition at line 5907 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ   (0x1<<5)

Definition at line 5908 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN   (0x1<<6)

Definition at line 5909 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD   (0x1<<7)

Definition at line 5910 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW   (0x1<<4)

Definition at line 5911 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB   (0x1<<8)

Definition at line 5912 of file bnx2x_reg.h.

#define MISC_REGISTERS_RESET_REG_3_SET   0x5a4

Definition at line 5913 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_4   4

Definition at line 5914 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_5   5

Definition at line 5915 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_7   7

Definition at line 5916 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_CLR_POS   16

Definition at line 5917 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_FLOAT   (0xffL<<24)

Definition at line 5918 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_FLOAT_POS   24

Definition at line 5919 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_INPUT_HI_Z   2

Definition at line 5920 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS   16

Definition at line 5921 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_OUTPUT_HIGH   1

Definition at line 5922 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_OUTPUT_LOW   0

Definition at line 5923 of file bnx2x_reg.h.

#define MISC_REGISTERS_SPIO_SET_POS   8

Definition at line 5924 of file bnx2x_reg.h.

#define MSTAT_REG_RX_STAT_GR64_LO   0x200

Definition at line 1911 of file bnx2x_reg.h.

#define MSTAT_REG_TX_STAT_GTXPOK_LO   0

Definition at line 1914 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST   (0x1<<0)

Definition at line 1915 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST   (0x1<<0)

Definition at line 1915 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST   (0x1<<1)

Definition at line 1916 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST   (0x1<<1)

Definition at line 1916 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN   (0x1<<4)

Definition at line 1917 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN   (0x1<<4)

Definition at line 1917 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST   (0x1<<2)

Definition at line 1918 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST   (0x1<<2)

Definition at line 1918 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN   (0x1<<3)

Definition at line 1919 of file bnx2x_reg.h.

#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN   (0x1<<3)

Definition at line 1919 of file bnx2x_reg.h.

#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN   (0x1<<0)

Definition at line 1920 of file bnx2x_reg.h.

#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN   (0x1<<0)

Definition at line 1921 of file bnx2x_reg.h.

#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT   (0x1<<0)

Definition at line 1922 of file bnx2x_reg.h.

#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS   (0x1<<9)

Definition at line 1923 of file bnx2x_reg.h.

#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G   (0x1<<15)

Definition at line 1924 of file bnx2x_reg.h.

#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS   (0xf<<18)

Definition at line 1925 of file bnx2x_reg.h.

#define NIG_REG_BMAC0_IN_EN   0x100ac

Definition at line 1927 of file bnx2x_reg.h.

#define NIG_REG_BMAC0_OUT_EN   0x100e0

Definition at line 1929 of file bnx2x_reg.h.

#define NIG_REG_BMAC0_PAUSE_OUT_EN   0x10110

Definition at line 1931 of file bnx2x_reg.h.

#define NIG_REG_BMAC0_REGS_OUT_EN   0x100e8

Definition at line 1933 of file bnx2x_reg.h.

#define NIG_REG_BRB0_OUT_EN   0x100f8

Definition at line 1935 of file bnx2x_reg.h.

#define NIG_REG_BRB0_PAUSE_IN_EN   0x100c4

Definition at line 1937 of file bnx2x_reg.h.

#define NIG_REG_BRB1_OUT_EN   0x100fc

Definition at line 1939 of file bnx2x_reg.h.

#define NIG_REG_BRB1_PAUSE_IN_EN   0x100c8

Definition at line 1941 of file bnx2x_reg.h.

#define NIG_REG_BRB_LB_OUT_EN   0x10100

Definition at line 1943 of file bnx2x_reg.h.

#define NIG_REG_DEBUG_PACKET_LB   0x10800

Definition at line 1947 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_DEBUG_IN_EN   0x100dc

Definition at line 1949 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_DRAIN0_MODE   0x10060

Definition at line 1954 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_EMAC0_OUT_EN   0x10120

Definition at line 1956 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_EMAC0_PORT   0x10058

Definition at line 1959 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_PBF0_IN_EN   0x100cc

Definition at line 1961 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_PBF1_IN_EN   0x100d0

Definition at line 1963 of file bnx2x_reg.h.

#define NIG_REG_EGRESS_UMP0_IN_EN   0x100d4

Definition at line 1965 of file bnx2x_reg.h.

#define NIG_REG_EMAC0_IN_EN   0x100a4

Definition at line 1967 of file bnx2x_reg.h.

#define NIG_REG_EMAC0_PAUSE_OUT_EN   0x10118

Definition at line 1969 of file bnx2x_reg.h.

#define NIG_REG_EMAC0_STATUS_MISC_MI_INT   0x10494

Definition at line 1973 of file bnx2x_reg.h.

#define NIG_REG_INGRESS_BMAC0_MEM   0x10c00

Definition at line 1978 of file bnx2x_reg.h.

#define NIG_REG_INGRESS_BMAC1_MEM   0x11000

Definition at line 1983 of file bnx2x_reg.h.

#define NIG_REG_INGRESS_EOP_LB_EMPTY   0x104e0

Definition at line 1985 of file bnx2x_reg.h.

#define NIG_REG_INGRESS_EOP_LB_FIFO   0x104e4

Definition at line 1988 of file bnx2x_reg.h.

#define NIG_REG_LATCH_BC_0   0x16210

Definition at line 1992 of file bnx2x_reg.h.

#define NIG_REG_LATCH_STATUS_0   0x18000

Definition at line 2006 of file bnx2x_reg.h.

#define NIG_REG_LED_10G_P0   0x10320

Definition at line 2008 of file bnx2x_reg.h.

#define NIG_REG_LED_10G_P1   0x10324

Definition at line 2010 of file bnx2x_reg.h.

#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0   0x10318

Definition at line 2015 of file bnx2x_reg.h.

#define NIG_REG_LED_CONTROL_BLINK_RATE_P0   0x10310

Definition at line 2019 of file bnx2x_reg.h.

#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0   0x10308

Definition at line 2027 of file bnx2x_reg.h.

#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0   0x102f8

Definition at line 2032 of file bnx2x_reg.h.

#define NIG_REG_LED_CONTROL_TRAFFIC_P0   0x10300

Definition at line 2039 of file bnx2x_reg.h.

#define NIG_REG_LED_MODE_P0   0x102f0

Definition at line 2042 of file bnx2x_reg.h.

#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0   0x16070

Definition at line 2045 of file bnx2x_reg.h.

#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1   0x16074

Definition at line 2046 of file bnx2x_reg.h.

#define NIG_REG_LLFC_ENABLE_0   0x16208

Definition at line 2050 of file bnx2x_reg.h.

#define NIG_REG_LLFC_ENABLE_1   0x1620c

Definition at line 2051 of file bnx2x_reg.h.

#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0   0x16058

Definition at line 2053 of file bnx2x_reg.h.

#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1   0x1605c

Definition at line 2054 of file bnx2x_reg.h.

#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0   0x16060

Definition at line 2056 of file bnx2x_reg.h.

#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1   0x16064

Definition at line 2057 of file bnx2x_reg.h.

#define NIG_REG_LLFC_OUT_EN_0   0x160c8

Definition at line 2059 of file bnx2x_reg.h.

#define NIG_REG_LLFC_OUT_EN_1   0x160cc

Definition at line 2060 of file bnx2x_reg.h.

#define NIG_REG_LLH0_ACPI_PAT_0_CRC   0x1015c

Definition at line 2061 of file bnx2x_reg.h.

#define NIG_REG_LLH0_ACPI_PAT_6_LEN   0x10154

Definition at line 2062 of file bnx2x_reg.h.

#define NIG_REG_LLH0_BRB1_DRV_MASK   0x10244

Definition at line 2063 of file bnx2x_reg.h.

#define NIG_REG_LLH0_BRB1_DRV_MASK_MF   0x16048

Definition at line 2064 of file bnx2x_reg.h.

#define NIG_REG_LLH0_BRB1_NOT_MCP   0x1025c

Definition at line 2066 of file bnx2x_reg.h.

#define NIG_REG_LLH0_CLS_TYPE   0x16080

Definition at line 2070 of file bnx2x_reg.h.

#define NIG_REG_LLH0_CM_HEADER   0x1007c

Definition at line 2072 of file bnx2x_reg.h.

#define NIG_REG_LLH0_DEST_IP_0_1   0x101dc

Definition at line 2073 of file bnx2x_reg.h.

#define NIG_REG_LLH0_DEST_MAC_0_0   0x101c0

Definition at line 2074 of file bnx2x_reg.h.

#define NIG_REG_LLH0_DEST_TCP_0   0x10220

Definition at line 2077 of file bnx2x_reg.h.

#define NIG_REG_LLH0_DEST_UDP_0   0x10214

Definition at line 2080 of file bnx2x_reg.h.

#define NIG_REG_LLH0_ERROR_MASK   0x1008c

Definition at line 2081 of file bnx2x_reg.h.

#define NIG_REG_LLH0_EVENT_ID   0x10084

Definition at line 2083 of file bnx2x_reg.h.

#define NIG_REG_LLH0_FUNC_EN   0x160fc

Definition at line 2084 of file bnx2x_reg.h.

#define NIG_REG_LLH0_FUNC_MEM   0x16180

Definition at line 2085 of file bnx2x_reg.h.

#define NIG_REG_LLH0_FUNC_MEM_ENABLE   0x16140

Definition at line 2086 of file bnx2x_reg.h.

#define NIG_REG_LLH0_FUNC_VLAN_ID   0x16100

Definition at line 2087 of file bnx2x_reg.h.

#define NIG_REG_LLH0_IPV4_IPV6_0   0x10208

Definition at line 2090 of file bnx2x_reg.h.

#define NIG_REG_LLH0_T_BIT   0x10074

Definition at line 2092 of file bnx2x_reg.h.

#define NIG_REG_LLH0_VLAN_ID_0   0x1022c

Definition at line 2094 of file bnx2x_reg.h.

#define NIG_REG_LLH0_XCM_INIT_CREDIT   0x10554

Definition at line 2096 of file bnx2x_reg.h.

#define NIG_REG_LLH0_XCM_MASK   0x10130

Definition at line 2097 of file bnx2x_reg.h.

#define NIG_REG_LLH1_BRB1_DRV_MASK   0x10248

Definition at line 2098 of file bnx2x_reg.h.

#define NIG_REG_LLH1_BRB1_NOT_MCP   0x102dc

Definition at line 2100 of file bnx2x_reg.h.

#define NIG_REG_LLH1_CLS_TYPE   0x16084

Definition at line 2104 of file bnx2x_reg.h.

#define NIG_REG_LLH1_CM_HEADER   0x10080

Definition at line 2106 of file bnx2x_reg.h.

#define NIG_REG_LLH1_ERROR_MASK   0x10090

Definition at line 2107 of file bnx2x_reg.h.

#define NIG_REG_LLH1_EVENT_ID   0x10088

Definition at line 2109 of file bnx2x_reg.h.

#define NIG_REG_LLH1_FUNC_MEM   0x161c0

Definition at line 2110 of file bnx2x_reg.h.

#define NIG_REG_LLH1_FUNC_MEM_ENABLE   0x16160

Definition at line 2111 of file bnx2x_reg.h.

#define NIG_REG_LLH1_FUNC_MEM_SIZE   16

Definition at line 2112 of file bnx2x_reg.h.

#define NIG_REG_LLH1_MF_MODE   0x18614

Definition at line 2116 of file bnx2x_reg.h.

#define NIG_REG_LLH1_XCM_INIT_CREDIT   0x10564

Definition at line 2118 of file bnx2x_reg.h.

#define NIG_REG_LLH1_XCM_MASK   0x10134

Definition at line 2119 of file bnx2x_reg.h.

#define NIG_REG_LLH_E1HOV_MODE   0x160d8

Definition at line 2122 of file bnx2x_reg.h.

#define NIG_REG_LLH_MF_MODE   0x16024

Definition at line 2125 of file bnx2x_reg.h.

#define NIG_REG_MASK_INTERRUPT_PORT0   0x10330

Definition at line 2126 of file bnx2x_reg.h.

#define NIG_REG_MASK_INTERRUPT_PORT1   0x10334

Definition at line 2127 of file bnx2x_reg.h.

#define NIG_REG_NIG_EMAC0_EN   0x1003c

Definition at line 2129 of file bnx2x_reg.h.

#define NIG_REG_NIG_EMAC1_EN   0x10040

Definition at line 2131 of file bnx2x_reg.h.

#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC   0x10044

Definition at line 2134 of file bnx2x_reg.h.

#define NIG_REG_NIG_INT_STS_0   0x103b0

Definition at line 2136 of file bnx2x_reg.h.

#define NIG_REG_NIG_INT_STS_1   0x103c0

Definition at line 2137 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_MASK   0x103dc

Definition at line 2139 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_MASK_0   0x183c8

Definition at line 2141 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_MASK_1   0x183d8

Definition at line 2142 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS   0x103d0

Definition at line 2144 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS_0   0x183bc

Definition at line 2146 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS_1   0x183cc

Definition at line 2147 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS_CLR   0x103d4

Definition at line 2149 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS_CLR_0   0x183c0

Definition at line 2151 of file bnx2x_reg.h.

#define NIG_REG_NIG_PRTY_STS_CLR_1   0x183d0

Definition at line 2152 of file bnx2x_reg.h.

#define NIG_REG_P0_HDRS_AFTER_BASIC   0x18038

Definition at line 2159 of file bnx2x_reg.h.

#define NIG_REG_P0_HWPFC_ENABLE   0x18078

Definition at line 2163 of file bnx2x_reg.h.

#define NIG_REG_P0_LLH_FUNC_MEM2   0x18480

Definition at line 2164 of file bnx2x_reg.h.

#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE   0x18440

Definition at line 2165 of file bnx2x_reg.h.

#define NIG_REG_P0_MAC_IN_EN   0x185ac

Definition at line 2167 of file bnx2x_reg.h.

#define NIG_REG_P0_MAC_OUT_EN   0x185b0

Definition at line 2169 of file bnx2x_reg.h.

#define NIG_REG_P0_MAC_PAUSE_OUT_EN   0x185b4

Definition at line 2171 of file bnx2x_reg.h.

#define NIG_REG_P0_PKT_PRIORITY_TO_COS   0x18054

Definition at line 2177 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS0_PRIORITY_MASK   0x18058

Definition at line 2182 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS1_PRIORITY_MASK   0x1805c

Definition at line 2187 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS2_PRIORITY_MASK   0x186b0

Definition at line 2192 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS3_PRIORITY_MASK   0x186b4

Definition at line 2197 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS4_PRIORITY_MASK   0x186b8

Definition at line 2202 of file bnx2x_reg.h.

#define NIG_REG_P0_RX_COS5_PRIORITY_MASK   0x186bc

Definition at line 2207 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP   0x180f0

Definition at line 2213 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB   0x18688

Definition at line 2223 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB   0x1868c

Definition at line 2233 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT   0x180e8

Definition at line 2238 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ   0x180ec

Definition at line 2243 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0   0x1810c

Definition at line 2246 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1   0x18110

Definition at line 2247 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2   0x18114

Definition at line 2248 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3   0x18118

Definition at line 2249 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4   0x1811c

Definition at line 2250 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5   0x186a0

Definition at line 2251 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6   0x186a4

Definition at line 2252 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7   0x186a8

Definition at line 2253 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8   0x186ac

Definition at line 2254 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0   0x180f8

Definition at line 2257 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1   0x180fc

Definition at line 2258 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2   0x18100

Definition at line 2259 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3   0x18104

Definition at line 2260 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4   0x18108

Definition at line 2261 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5   0x18690

Definition at line 2262 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6   0x18694

Definition at line 2263 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7   0x18698

Definition at line 2264 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8   0x1869c

Definition at line 2265 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS   0x180f4

Definition at line 2270 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT   0x180e4

Definition at line 2279 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB   0x18680

Definition at line 2294 of file bnx2x_reg.h.

#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB   0x18684

Definition at line 2304 of file bnx2x_reg.h.

#define NIG_REG_P1_HDRS_AFTER_BASIC   0x1818c

Definition at line 2282 of file bnx2x_reg.h.

#define NIG_REG_P1_HWPFC_ENABLE   0x181d0

Definition at line 2305 of file bnx2x_reg.h.

#define NIG_REG_P1_LLH_FUNC_MEM2   0x184c0

Definition at line 2283 of file bnx2x_reg.h.

#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE   0x18460

Definition at line 2284 of file bnx2x_reg.h.

#define NIG_REG_P1_MAC_IN_EN   0x185c0

Definition at line 2306 of file bnx2x_reg.h.

#define NIG_REG_P1_MAC_OUT_EN   0x185c4

Definition at line 2308 of file bnx2x_reg.h.

#define NIG_REG_P1_MAC_PAUSE_OUT_EN   0x185c8

Definition at line 2310 of file bnx2x_reg.h.

#define NIG_REG_P1_PKT_PRIORITY_TO_COS   0x181a8

Definition at line 2316 of file bnx2x_reg.h.

#define NIG_REG_P1_RX_COS0_PRIORITY_MASK   0x181ac

Definition at line 2321 of file bnx2x_reg.h.

#define NIG_REG_P1_RX_COS1_PRIORITY_MASK   0x181b0

Definition at line 2326 of file bnx2x_reg.h.

#define NIG_REG_P1_RX_COS2_PRIORITY_MASK   0x186f8

Definition at line 2331 of file bnx2x_reg.h.

#define NIG_REG_P1_RX_MACFIFO_EMPTY   0x1858c

Definition at line 2333 of file bnx2x_reg.h.

#define NIG_REG_P1_TLLH_FIFO_EMPTY   0x18338

Definition at line 2335 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB   0x186e8

Definition at line 2348 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB   0x186ec

Definition at line 2361 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT   0x18234

Definition at line 2368 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ   0x18238

Definition at line 2375 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0   0x18258

Definition at line 2376 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1   0x1825c

Definition at line 2377 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2   0x18260

Definition at line 2378 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3   0x18264

Definition at line 2379 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4   0x18268

Definition at line 2380 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5   0x186f4

Definition at line 2381 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0   0x18244

Definition at line 2384 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1   0x18248

Definition at line 2385 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2   0x1824c

Definition at line 2386 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3   0x18250

Definition at line 2387 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4   0x18254

Definition at line 2388 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5   0x186f0

Definition at line 2389 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS   0x18240

Definition at line 2394 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB   0x186e0

Definition at line 2406 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB   0x186e4

Definition at line 2418 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_MACFIFO_EMPTY   0x18594

Definition at line 2420 of file bnx2x_reg.h.

#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY   0x182b8

Definition at line 2423 of file bnx2x_reg.h.

#define NIG_REG_PAUSE_ENABLE_0   0x160c0

Definition at line 2429 of file bnx2x_reg.h.

#define NIG_REG_PAUSE_ENABLE_1   0x160c4

Definition at line 2430 of file bnx2x_reg.h.

#define NIG_REG_PBF_LB_IN_EN   0x100b4

Definition at line 2432 of file bnx2x_reg.h.

#define NIG_REG_PORT_SWAP   0x10394

Definition at line 2435 of file bnx2x_reg.h.

#define NIG_REG_PPP_ENABLE_0   0x160b0

Definition at line 2439 of file bnx2x_reg.h.

#define NIG_REG_PPP_ENABLE_1   0x160b4

Definition at line 2440 of file bnx2x_reg.h.

#define NIG_REG_PRS_EOP_OUT_EN   0x10104

Definition at line 2442 of file bnx2x_reg.h.

#define NIG_REG_PRS_REQ_IN_EN   0x100b8

Definition at line 2444 of file bnx2x_reg.h.

#define NIG_REG_SERDES0_CTRL_MD_DEVAD   0x10370

Definition at line 2446 of file bnx2x_reg.h.

#define NIG_REG_SERDES0_CTRL_MD_ST   0x1036c

Definition at line 2448 of file bnx2x_reg.h.

#define NIG_REG_SERDES0_CTRL_PHY_ADDR   0x10374

Definition at line 2450 of file bnx2x_reg.h.

#define NIG_REG_SERDES0_STATUS_LINK_STATUS   0x10578

Definition at line 2452 of file bnx2x_reg.h.

#define NIG_REG_STAT0_BRB_DISCARD   0x105f0

Definition at line 2455 of file bnx2x_reg.h.

#define NIG_REG_STAT0_BRB_TRUNCATE   0x105f8

Definition at line 2458 of file bnx2x_reg.h.

#define NIG_REG_STAT0_EGRESS_MAC_PKT0   0x10750

Definition at line 2461 of file bnx2x_reg.h.

#define NIG_REG_STAT0_EGRESS_MAC_PKT1   0x10760

Definition at line 2464 of file bnx2x_reg.h.

#define NIG_REG_STAT1_BRB_DISCARD   0x10628

Definition at line 2467 of file bnx2x_reg.h.

#define NIG_REG_STAT1_EGRESS_MAC_PKT0   0x107a0

Definition at line 2470 of file bnx2x_reg.h.

#define NIG_REG_STAT1_EGRESS_MAC_PKT1   0x107b0

Definition at line 2473 of file bnx2x_reg.h.

#define NIG_REG_STAT2_BRB_OCTET   0x107e0

Definition at line 2475 of file bnx2x_reg.h.

#define NIG_REG_STATUS_INTERRUPT_PORT0   0x10328

Definition at line 2476 of file bnx2x_reg.h.

#define NIG_REG_STATUS_INTERRUPT_PORT1   0x1032c

Definition at line 2477 of file bnx2x_reg.h.

#define NIG_REG_STRAP_OVERRIDE   0x10398

Definition at line 2481 of file bnx2x_reg.h.

#define NIG_REG_XCM0_OUT_EN   0x100f0

Definition at line 2483 of file bnx2x_reg.h.

#define NIG_REG_XCM1_OUT_EN   0x100f4

Definition at line 2485 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST   0x10348

Definition at line 2487 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_CTRL_MD_DEVAD   0x1033c

Definition at line 2489 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_CTRL_MD_ST   0x10338

Definition at line 2491 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_CTRL_PHY_ADDR   0x10340

Definition at line 2493 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_STATUS_LINK10G   0x10680

Definition at line 2495 of file bnx2x_reg.h.

#define NIG_REG_XGXS0_STATUS_LINK_STATUS   0x10684

Definition at line 2497 of file bnx2x_reg.h.

#define NIG_REG_XGXS_LANE_SEL_P0   0x102e8

Definition at line 2499 of file bnx2x_reg.h.

#define NIG_REG_XGXS_SERDES0_MODE_SEL   0x102e0

Definition at line 2501 of file bnx2x_reg.h.

#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT   (0x1<<0)

Definition at line 2502 of file bnx2x_reg.h.

#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS   (0x1<<9)

Definition at line 2503 of file bnx2x_reg.h.

#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G   (0x1<<15)

Definition at line 2504 of file bnx2x_reg.h.

#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS   (0xf<<18)

Definition at line 2505 of file bnx2x_reg.h.

#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE   18

Definition at line 2506 of file bnx2x_reg.h.

#define PB_REG_CONTROL   0

Definition at line 2743 of file bnx2x_reg.h.

#define PB_REG_PB_INT_MASK   0x28

Definition at line 2745 of file bnx2x_reg.h.

#define PB_REG_PB_INT_STS   0x1c

Definition at line 2747 of file bnx2x_reg.h.

#define PB_REG_PB_PRTY_MASK   0x38

Definition at line 2749 of file bnx2x_reg.h.

#define PB_REG_PB_PRTY_STS   0x2c

Definition at line 2751 of file bnx2x_reg.h.

#define PB_REG_PB_PRTY_STS_CLR   0x30

Definition at line 2753 of file bnx2x_reg.h.

#define PBF_REG_COS0_UPPER_BOUND   0x15c05c

Definition at line 2508 of file bnx2x_reg.h.

#define PBF_REG_COS0_UPPER_BOUND_P0   0x15c2cc

Definition at line 2511 of file bnx2x_reg.h.

#define PBF_REG_COS0_UPPER_BOUND_P1   0x15c2e4

Definition at line 2514 of file bnx2x_reg.h.

#define PBF_REG_COS0_WEIGHT   0x15c054

Definition at line 2516 of file bnx2x_reg.h.

#define PBF_REG_COS0_WEIGHT_P0   0x15c2a8

Definition at line 2518 of file bnx2x_reg.h.

#define PBF_REG_COS0_WEIGHT_P1   0x15c2c0

Definition at line 2520 of file bnx2x_reg.h.

#define PBF_REG_COS1_UPPER_BOUND   0x15c060

Definition at line 2522 of file bnx2x_reg.h.

#define PBF_REG_COS1_WEIGHT   0x15c058

Definition at line 2524 of file bnx2x_reg.h.

#define PBF_REG_COS1_WEIGHT_P0   0x15c2ac

Definition at line 2526 of file bnx2x_reg.h.

#define PBF_REG_COS1_WEIGHT_P1   0x15c2c4

Definition at line 2528 of file bnx2x_reg.h.

#define PBF_REG_COS2_WEIGHT_P0   0x15c2b0

Definition at line 2530 of file bnx2x_reg.h.

#define PBF_REG_COS2_WEIGHT_P1   0x15c2c8

Definition at line 2532 of file bnx2x_reg.h.

#define PBF_REG_COS3_WEIGHT_P0   0x15c2b4

Definition at line 2534 of file bnx2x_reg.h.

#define PBF_REG_COS4_WEIGHT_P0   0x15c2b8

Definition at line 2536 of file bnx2x_reg.h.

#define PBF_REG_COS5_WEIGHT_P0   0x15c2bc

Definition at line 2538 of file bnx2x_reg.h.

#define PBF_REG_CREDIT_LB_Q   0x140338

Definition at line 2541 of file bnx2x_reg.h.

#define PBF_REG_CREDIT_Q0   0x14033c

Definition at line 2544 of file bnx2x_reg.h.

#define PBF_REG_CREDIT_Q1   0x140340

Definition at line 2547 of file bnx2x_reg.h.

#define PBF_REG_DISABLE_NEW_TASK_PROC_P0   0x14005c

Definition at line 2550 of file bnx2x_reg.h.

#define PBF_REG_DISABLE_NEW_TASK_PROC_P1   0x140060

Definition at line 2553 of file bnx2x_reg.h.

#define PBF_REG_DISABLE_NEW_TASK_PROC_P4   0x14006c

Definition at line 2556 of file bnx2x_reg.h.

#define PBF_REG_DISABLE_PF   0x1402e8

Definition at line 2557 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0   0x15c288

Definition at line 2562 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1   0x15c28c

Definition at line 2567 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0   0x15c278

Definition at line 2572 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1   0x15c27c

Definition at line 2577 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0   0x15c280

Definition at line 2580 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1   0x15c284

Definition at line 2583 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0   0x15c2a0

Definition at line 2588 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1   0x15c2a4

Definition at line 2593 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0   0x15c270

Definition at line 2598 of file bnx2x_reg.h.

#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1   0x15c274

Definition at line 2603 of file bnx2x_reg.h.

#define PBF_REG_ETS_ENABLED   0x15c050

Definition at line 2607 of file bnx2x_reg.h.

#define PBF_REG_HDRS_AFTER_BASIC   0x15c0a8

Definition at line 2610 of file bnx2x_reg.h.

#define PBF_REG_HDRS_AFTER_TAG_0   0x15c0b8

Definition at line 2612 of file bnx2x_reg.h.

#define PBF_REG_HIGH_PRIORITY_COS_NUM   0x15c04c

Definition at line 2615 of file bnx2x_reg.h.

#define PBF_REG_IF_ENABLE_REG   0x140044

Definition at line 2616 of file bnx2x_reg.h.

#define PBF_REG_INIT   0x140000

Definition at line 2620 of file bnx2x_reg.h.

#define PBF_REG_INIT_CRD_LB_Q   0x15c248

Definition at line 2623 of file bnx2x_reg.h.

#define PBF_REG_INIT_CRD_Q0   0x15c230

Definition at line 2626 of file bnx2x_reg.h.

#define PBF_REG_INIT_CRD_Q1   0x15c234

Definition at line 2629 of file bnx2x_reg.h.

#define PBF_REG_INIT_P0   0x140004

Definition at line 2633 of file bnx2x_reg.h.

#define PBF_REG_INIT_P1   0x140008

Definition at line 2637 of file bnx2x_reg.h.

#define PBF_REG_INIT_P4   0x14000c

Definition at line 2641 of file bnx2x_reg.h.

#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q   0x140354

Definition at line 2644 of file bnx2x_reg.h.

#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0   0x140358

Definition at line 2647 of file bnx2x_reg.h.

#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1   0x14035c

Definition at line 2650 of file bnx2x_reg.h.

#define PBF_REG_MAC_IF0_ENABLE   0x140030

Definition at line 2652 of file bnx2x_reg.h.

#define PBF_REG_MAC_IF1_ENABLE   0x140034

Definition at line 2654 of file bnx2x_reg.h.

#define PBF_REG_MAC_LB_ENABLE   0x140040

Definition at line 2656 of file bnx2x_reg.h.

#define PBF_REG_MUST_HAVE_HDRS   0x15c0c4

Definition at line 2658 of file bnx2x_reg.h.

#define PBF_REG_NUM_STRICT_ARB_SLOTS   0x15c064

Definition at line 2662 of file bnx2x_reg.h.

#define PBF_REG_P0_ARB_THRSH   0x1400e4

Definition at line 2665 of file bnx2x_reg.h.

#define PBF_REG_P0_CREDIT   0x140200

Definition at line 2667 of file bnx2x_reg.h.

#define PBF_REG_P0_INIT_CRD   0x1400d0

Definition at line 2670 of file bnx2x_reg.h.

#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT   0x140308

Definition at line 2673 of file bnx2x_reg.h.

#define PBF_REG_P0_PAUSE_ENABLE   0x140014

Definition at line 2675 of file bnx2x_reg.h.

#define PBF_REG_P0_TASK_CNT   0x140204

Definition at line 2677 of file bnx2x_reg.h.

#define PBF_REG_P0_TQ_LINES_FREED_CNT   0x1402f0

Definition at line 2680 of file bnx2x_reg.h.

#define PBF_REG_P0_TQ_OCCUPANCY   0x1402fc

Definition at line 2682 of file bnx2x_reg.h.

#define PBF_REG_P1_CREDIT   0x140208

Definition at line 2685 of file bnx2x_reg.h.

#define PBF_REG_P1_INIT_CRD   0x1400d4

Definition at line 2688 of file bnx2x_reg.h.

#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT   0x14030c

Definition at line 2691 of file bnx2x_reg.h.

#define PBF_REG_P1_TASK_CNT   0x14020c

Definition at line 2693 of file bnx2x_reg.h.

#define PBF_REG_P1_TQ_LINES_FREED_CNT   0x1402f4

Definition at line 2696 of file bnx2x_reg.h.

#define PBF_REG_P1_TQ_OCCUPANCY   0x140300

Definition at line 2698 of file bnx2x_reg.h.

#define PBF_REG_P4_CREDIT   0x140210

Definition at line 2700 of file bnx2x_reg.h.

#define PBF_REG_P4_INIT_CRD   0x1400e0

Definition at line 2703 of file bnx2x_reg.h.

#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT   0x140310

Definition at line 2706 of file bnx2x_reg.h.

#define PBF_REG_P4_TASK_CNT   0x140214

Definition at line 2708 of file bnx2x_reg.h.

#define PBF_REG_P4_TQ_LINES_FREED_CNT   0x1402f8

Definition at line 2711 of file bnx2x_reg.h.

#define PBF_REG_P4_TQ_OCCUPANCY   0x140304

Definition at line 2713 of file bnx2x_reg.h.

#define PBF_REG_PBF_INT_MASK   0x1401d4

Definition at line 2715 of file bnx2x_reg.h.

#define PBF_REG_PBF_INT_STS   0x1401c8

Definition at line 2717 of file bnx2x_reg.h.

#define PBF_REG_PBF_PRTY_MASK   0x1401e4

Definition at line 2719 of file bnx2x_reg.h.

#define PBF_REG_PBF_PRTY_STS_CLR   0x1401dc

Definition at line 2721 of file bnx2x_reg.h.

#define PBF_REG_TAG_ETHERTYPE_0   0x15c090

Definition at line 2723 of file bnx2x_reg.h.

#define PBF_REG_TAG_LEN_0   0x15c09c

Definition at line 2726 of file bnx2x_reg.h.

#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q   0x14038c

Definition at line 2729 of file bnx2x_reg.h.

#define PBF_REG_TQ_LINES_FREED_CNT_Q0   0x140390

Definition at line 2732 of file bnx2x_reg.h.

#define PBF_REG_TQ_LINES_FREED_CNT_Q1   0x140394

Definition at line 2735 of file bnx2x_reg.h.

#define PBF_REG_TQ_OCCUPANCY_LB_Q   0x1403a8

Definition at line 2738 of file bnx2x_reg.h.

#define PBF_REG_TQ_OCCUPANCY_Q0   0x1403ac

Definition at line 2740 of file bnx2x_reg.h.

#define PBF_REG_TQ_OCCUPANCY_Q1   0x1403b0

Definition at line 2742 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_64ENA   (1L<<4)

Definition at line 6218 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE   (0xfL<<0)

Definition at line 6201 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_128K   (2L<<0)

Definition at line 6204 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_128M   (12L<<0)

Definition at line 6214 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_16M   (9L<<0)

Definition at line 6211 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_1G   (15L<<0)

Definition at line 6217 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_1M   (5L<<0)

Definition at line 6207 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_256K   (3L<<0)

Definition at line 6205 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_256M   (13L<<0)

Definition at line 6215 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_2M   (6L<<0)

Definition at line 6208 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_32M   (10L<<0)

Definition at line 6212 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_4M   (7L<<0)

Definition at line 6209 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_512K   (4L<<0)

Definition at line 6206 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_512M   (14L<<0)

Definition at line 6216 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_64K   (1L<<0)

Definition at line 6203 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_64M   (11L<<0)

Definition at line 6213 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_8M   (8L<<0)

Definition at line 6210 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR1_SIZE_DISABLED   (0L<<0)

Definition at line 6202 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_64ENA   (1L<<4)

Definition at line 6270 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE   (0xfL<<0)

Definition at line 6253 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_128K   (2L<<0)

Definition at line 6256 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_128M   (12L<<0)

Definition at line 6266 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_16M   (9L<<0)

Definition at line 6263 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_1G   (15L<<0)

Definition at line 6269 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_1M   (5L<<0)

Definition at line 6259 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_256K   (3L<<0)

Definition at line 6257 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_256M   (13L<<0)

Definition at line 6267 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_2M   (6L<<0)

Definition at line 6260 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_32M   (10L<<0)

Definition at line 6264 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_4M   (7L<<0)

Definition at line 6261 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_512K   (4L<<0)

Definition at line 6258 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_512M   (14L<<0)

Definition at line 6268 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_64K   (1L<<0)

Definition at line 6255 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_64M   (11L<<0)

Definition at line 6265 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_8M   (8L<<0)

Definition at line 6262 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR2_SIZE_DISABLED   (0L<<0)

Definition at line 6254 of file bnx2x_reg.h.

#define PCI_CONFIG_2_BAR_PREFETCH   (1L<<16)

Definition at line 6239 of file bnx2x_reg.h.

#define PCI_CONFIG_2_CFG_CYCLE_RETRY   (1L<<6)

Definition at line 6220 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_RETRY   (1L<<5)

Definition at line 6219 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE   (0xffL<<8)

Definition at line 6222 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_128K   (7L<<8)

Definition at line 6230 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_16K   (4L<<8)

Definition at line 6227 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_16M   (14L<<8)

Definition at line 6237 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_1M   (10L<<8)

Definition at line 6233 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_256K   (8L<<8)

Definition at line 6231 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_2K   (1L<<8)

Definition at line 6224 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_2M   (11L<<8)

Definition at line 6234 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_32K   (5L<<8)

Definition at line 6228 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_32M   (15L<<8)

Definition at line 6238 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_4K   (2L<<8)

Definition at line 6225 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_4M   (12L<<8)

Definition at line 6235 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_512K   (9L<<8)

Definition at line 6232 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_64K   (6L<<8)

Definition at line 6229 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_8K   (3L<<8)

Definition at line 6226 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_8M   (13L<<8)

Definition at line 6236 of file bnx2x_reg.h.

#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED   (0L<<8)

Definition at line 6223 of file bnx2x_reg.h.

#define PCI_CONFIG_2_FIRST_CFG_DONE   (1L<<7)

Definition at line 6221 of file bnx2x_reg.h.

#define PCI_CONFIG_2_RESERVED0   (0x7fffL<<17)

Definition at line 6240 of file bnx2x_reg.h.

#define PCI_CONFIG_3_FORCE_PME   (1L<<24)

Definition at line 6245 of file bnx2x_reg.h.

#define PCI_CONFIG_3_PCI_POWER   (1L<<31)

Definition at line 6250 of file bnx2x_reg.h.

#define PCI_CONFIG_3_PM_STATE   (0x3L<<27)

Definition at line 6248 of file bnx2x_reg.h.

#define PCI_CONFIG_3_PME_ENABLE   (1L<<26)

Definition at line 6247 of file bnx2x_reg.h.

#define PCI_CONFIG_3_PME_STATUS   (1L<<25)

Definition at line 6246 of file bnx2x_reg.h.

#define PCI_CONFIG_3_STICKY_BYTE   (0xffL<<0)

Definition at line 6244 of file bnx2x_reg.h.

#define PCI_CONFIG_3_VAUX_PRESET   (1L<<30)

Definition at line 6249 of file bnx2x_reg.h.

#define PCI_ID_VAL1   0x434

Definition at line 6274 of file bnx2x_reg.h.

#define PCI_ID_VAL2   0x438

Definition at line 6275 of file bnx2x_reg.h.

#define PCI_PM_DATA_A   0x410

Definition at line 6272 of file bnx2x_reg.h.

#define PCI_PM_DATA_B   0x414

Definition at line 6273 of file bnx2x_reg.h.

#define PCICFG_BAR_1_HIGH   0x14

Definition at line 6137 of file bnx2x_reg.h.

#define PCICFG_BAR_1_LOW   0x10

Definition at line 6136 of file bnx2x_reg.h.

#define PCICFG_BAR_2_HIGH   0x1c

Definition at line 6139 of file bnx2x_reg.h.

#define PCICFG_BAR_2_LOW   0x18

Definition at line 6138 of file bnx2x_reg.h.

#define PCICFG_CACHE_LINE_SIZE   0x0c

Definition at line 6134 of file bnx2x_reg.h.

#define PCICFG_COMMAND_BUS_MASTER   (1<<2)

Definition at line 6122 of file bnx2x_reg.h.

#define PCICFG_COMMAND_FAST_B2B   (1<<9)

Definition at line 6129 of file bnx2x_reg.h.

#define PCICFG_COMMAND_INT_DISABLE   (1<<10)

Definition at line 6130 of file bnx2x_reg.h.

#define PCICFG_COMMAND_IO_SPACE   (1<<0)

Definition at line 6120 of file bnx2x_reg.h.

#define PCICFG_COMMAND_MEM_SPACE   (1<<1)

Definition at line 6121 of file bnx2x_reg.h.

#define PCICFG_COMMAND_MWI_CYCLES   (1<<4)

Definition at line 6124 of file bnx2x_reg.h.

#define PCICFG_COMMAND_OFFSET   0x04

Definition at line 6119 of file bnx2x_reg.h.

#define PCICFG_COMMAND_PERR_ENA   (1<<6)

Definition at line 6126 of file bnx2x_reg.h.

#define PCICFG_COMMAND_RESERVED   (0x1f<<11)

Definition at line 6131 of file bnx2x_reg.h.

#define PCICFG_COMMAND_SERR_ENA   (1<<8)

Definition at line 6128 of file bnx2x_reg.h.

#define PCICFG_COMMAND_SPECIAL_CYCLES   (1<<3)

Definition at line 6123 of file bnx2x_reg.h.

#define PCICFG_COMMAND_STEPPING   (1<<7)

Definition at line 6127 of file bnx2x_reg.h.

#define PCICFG_COMMAND_VGA_SNOOP   (1<<5)

Definition at line 6125 of file bnx2x_reg.h.

#define PCICFG_DEVICE_CONTROL   0xb4

Definition at line 6176 of file bnx2x_reg.h.

#define PCICFG_DEVICE_ID_OFFSET   0x02

Definition at line 6118 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS   0xb6

Definition at line 6177 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_AUX_PWR_DET   (1<<4)

Definition at line 6182 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_CORR_ERR_DET   (1<<0)

Definition at line 6178 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET   (1<<2)

Definition at line 6180 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_NO_PEND   (1<<5)

Definition at line 6183 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET   (1<<1)

Definition at line 6179 of file bnx2x_reg.h.

#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET   (1<<3)

Definition at line 6181 of file bnx2x_reg.h.

#define PCICFG_GRC_ADDRESS   0x78

Definition at line 6167 of file bnx2x_reg.h.

#define PCICFG_GRC_DATA   0x80

Definition at line 6168 of file bnx2x_reg.h.

#define PCICFG_INT_LINE   0x3c

Definition at line 6142 of file bnx2x_reg.h.

#define PCICFG_INT_PIN   0x3d

Definition at line 6143 of file bnx2x_reg.h.

#define PCICFG_LATENCY_TIMER   0x0d

Definition at line 6135 of file bnx2x_reg.h.

#define PCICFG_LINK_CONTROL   0xbc

Definition at line 6184 of file bnx2x_reg.h.

#define PCICFG_ME_REGISTER   0x98

Definition at line 6169 of file bnx2x_reg.h.

#define PCICFG_MSI_CAP_ID_OFFSET   0x58

Definition at line 6161 of file bnx2x_reg.h.

#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP   (0x1<<23)

Definition at line 6165 of file bnx2x_reg.h.

#define PCICFG_MSI_CONTROL_ENABLE   (0x1<<16)

Definition at line 6162 of file bnx2x_reg.h.

#define PCICFG_MSI_CONTROL_MCAP   (0x7<<17)

Definition at line 6163 of file bnx2x_reg.h.

#define PCICFG_MSI_CONTROL_MENA   (0x7<<20)

Definition at line 6164 of file bnx2x_reg.h.

#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE   (0x1<<24)

Definition at line 6166 of file bnx2x_reg.h.

#define PCICFG_MSIX_CAP_ID_OFFSET   0xa0

Definition at line 6170 of file bnx2x_reg.h.

#define PCICFG_MSIX_CONTROL_FUNC_MASK   (0x1<<30)

Definition at line 6173 of file bnx2x_reg.h.

#define PCICFG_MSIX_CONTROL_MSIX_ENABLE   (0x1<<31)

Definition at line 6174 of file bnx2x_reg.h.

#define PCICFG_MSIX_CONTROL_RESERVED   (0x7<<27)

Definition at line 6172 of file bnx2x_reg.h.

#define PCICFG_MSIX_CONTROL_TABLE_SIZE   (0x7ff<<16)

Definition at line 6171 of file bnx2x_reg.h.

#define PCICFG_OFFSET   0x2000

Definition at line 6116 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY   0x48

Definition at line 6144 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_AUX_CURRENT   (0x7<<22)

Definition at line 6149 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_CLOCK   (1<<19)

Definition at line 6146 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_D1_SUPPORT   (1<<25)

Definition at line 6150 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_D2_SUPPORT   (1<<26)

Definition at line 6151 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_DSI   (1<<21)

Definition at line 6148 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_PME_IN_D0   (1<<27)

Definition at line 6152 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_PME_IN_D1   (1<<28)

Definition at line 6153 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_PME_IN_D2   (1<<29)

Definition at line 6154 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD   (1<<31)

Definition at line 6156 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT   (1<<30)

Definition at line 6155 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_RESERVED   (1<<20)

Definition at line 6147 of file bnx2x_reg.h.

#define PCICFG_PM_CAPABILITY_VERSION   (0x3<<16)

Definition at line 6145 of file bnx2x_reg.h.

#define PCICFG_PM_CSR_OFFSET   0x4c

Definition at line 6157 of file bnx2x_reg.h.

#define PCICFG_PM_CSR_PME_ENABLE   (1<<8)

Definition at line 6159 of file bnx2x_reg.h.

#define PCICFG_PM_CSR_PME_STATUS   (1<<15)

Definition at line 6160 of file bnx2x_reg.h.

#define PCICFG_PM_CSR_STATE   (0x3<<0)

Definition at line 6158 of file bnx2x_reg.h.

#define PCICFG_REVESION_ID_OFFSET   0x08

Definition at line 6133 of file bnx2x_reg.h.

#define PCICFG_STATUS_OFFSET   0x06

Definition at line 6132 of file bnx2x_reg.h.

#define PCICFG_SUBSYSTEM_ID_OFFSET   0x2e

Definition at line 6141 of file bnx2x_reg.h.

#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET   0x2c

Definition at line 6140 of file bnx2x_reg.h.

#define PCICFG_VENDOR_ID_OFFSET   0x00

Definition at line 6117 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR   (0x1<<0)

Definition at line 2754 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW   (0x1<<8)

Definition at line 2755 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR   (0x1<<1)

Definition at line 2756 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN   (0x1<<6)

Definition at line 2757 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN   (0x1<<7)

Definition at line 2758 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN   (0x1<<4)

Definition at line 2759 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN   (0x1<<3)

Definition at line 2760 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN   (0x1<<5)

Definition at line 2761 of file bnx2x_reg.h.

#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN   (0x1<<2)

Definition at line 2762 of file bnx2x_reg.h.

#define PGLUE_B_REG_CFG_SPACE_A_REQUEST   0x9010

Definition at line 2767 of file bnx2x_reg.h.

#define PGLUE_B_REG_CFG_SPACE_B_REQUEST   0x9014

Definition at line 2772 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE   0x9194

Definition at line 2775 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_INB_INT_B_VF   0x916c

Definition at line 2778 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE   0x919c

Definition at line 2781 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_START_OFFSET_A   0x9100

Definition at line 2783 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_START_OFFSET_B   0x9108

Definition at line 2785 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_VF_SHIFT_B   0x9110

Definition at line 2787 of file bnx2x_reg.h.

#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF   0x91ac

Definition at line 2789 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_PF_7_0   0x9028

Definition at line 2794 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR   0x9418

Definition at line 2799 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_VF_127_96   0x9024

Definition at line 2803 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_VF_31_0   0x9018

Definition at line 2807 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_VF_63_32   0x901c

Definition at line 2811 of file bnx2x_reg.h.

#define PGLUE_B_REG_FLR_REQUEST_VF_95_64   0x9020

Definition at line 2815 of file bnx2x_reg.h.

#define PGLUE_B_REG_INCORRECT_RCV_DETAILS   0x9068

Definition at line 2825 of file bnx2x_reg.h.

#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER   0x942c

Definition at line 2826 of file bnx2x_reg.h.

#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ   0x9430

Definition at line 2827 of file bnx2x_reg.h.

#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE   0x9434

Definition at line 2828 of file bnx2x_reg.h.

#define PGLUE_B_REG_INTERNAL_VFID_ENABLE   0x9438

Definition at line 2829 of file bnx2x_reg.h.

#define PGLUE_B_REG_PGLUE_B_INT_STS   0x9298

Definition at line 2831 of file bnx2x_reg.h.

#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR   0x929c

Definition at line 2833 of file bnx2x_reg.h.

#define PGLUE_B_REG_PGLUE_B_PRTY_MASK   0x92b4

Definition at line 2835 of file bnx2x_reg.h.

#define PGLUE_B_REG_PGLUE_B_PRTY_STS   0x92a8

Definition at line 2837 of file bnx2x_reg.h.

#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR   0x92ac

Definition at line 2839 of file bnx2x_reg.h.

#define PGLUE_B_REG_RX_ERR_DETAILS   0x9080

Definition at line 2846 of file bnx2x_reg.h.

#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS   0x9084

Definition at line 2853 of file bnx2x_reg.h.

#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR   0x9458

Definition at line 2858 of file bnx2x_reg.h.

#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST   0x9030

Definition at line 2864 of file bnx2x_reg.h.

#define PGLUE_B_REG_TAGS_63_32   0x9244

Definition at line 2868 of file bnx2x_reg.h.

#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE   0x9170

Definition at line 2871 of file bnx2x_reg.h.

#define PGLUE_B_REG_TSDM_START_OFFSET_A   0x90c4

Definition at line 2873 of file bnx2x_reg.h.

#define PGLUE_B_REG_TSDM_START_OFFSET_B   0x90cc

Definition at line 2875 of file bnx2x_reg.h.

#define PGLUE_B_REG_TSDM_VF_SHIFT_B   0x90d4

Definition at line 2877 of file bnx2x_reg.h.

#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF   0x91a0

Definition at line 2879 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0   0x9098

Definition at line 2881 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32   0x909c

Definition at line 2883 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_RD_DETAILS   0x90a0

Definition at line 2888 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_RD_DETAILS2   0x90a4

Definition at line 2896 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0   0x9088

Definition at line 2898 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32   0x908c

Definition at line 2900 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_WR_DETAILS   0x9090

Definition at line 2904 of file bnx2x_reg.h.

#define PGLUE_B_REG_TX_ERR_WR_DETAILS2   0x9094

Definition at line 2912 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_0   0x9128

Definition at line 2916 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_1   0x912c

Definition at line 2917 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_2   0x9130

Definition at line 2918 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_3   0x9134

Definition at line 2919 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_4   0x9138

Definition at line 2920 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_5   0x913c

Definition at line 2921 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_6   0x9140

Definition at line 2922 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE   0x917c

Definition at line 2925 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE   0x9180

Definition at line 2928 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE   0x9184

Definition at line 2931 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_START_OFFSET_A   0x90d8

Definition at line 2933 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_START_OFFSET_B   0x90e0

Definition at line 2935 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_VF_SHIFT_B   0x90e8

Definition at line 2937 of file bnx2x_reg.h.

#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF   0x91a4

Definition at line 2939 of file bnx2x_reg.h.

#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS   0x9234

Definition at line 2946 of file bnx2x_reg.h.

#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS   0x9230

Definition at line 2954 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_PF_7_0   0x907c

Definition at line 2959 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR   0x9470

Definition at line 2963 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_127_96   0x9078

Definition at line 2968 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR   0x9474

Definition at line 2972 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_31_0   0x906c

Definition at line 2977 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR   0x9478

Definition at line 2981 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_63_32   0x9070

Definition at line 2986 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR   0x947c

Definition at line 2990 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_95_64   0x9074

Definition at line 2995 of file bnx2x_reg.h.

#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR   0x9480

Definition at line 2999 of file bnx2x_reg.h.

#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE   0x9188

Definition at line 3002 of file bnx2x_reg.h.

#define PGLUE_B_REG_XSDM_START_OFFSET_A   0x90ec

Definition at line 3004 of file bnx2x_reg.h.

#define PGLUE_B_REG_XSDM_START_OFFSET_B   0x90f4

Definition at line 3006 of file bnx2x_reg.h.

#define PGLUE_B_REG_XSDM_VF_SHIFT_B   0x90fc

Definition at line 3008 of file bnx2x_reg.h.

#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF   0x91a8

Definition at line 3010 of file bnx2x_reg.h.

#define PHY84833_CMD_GET_EEE_MODE   0x8008

Definition at line 6954 of file bnx2x_reg.h.

#define PHY84833_CMD_SET_EEE_MODE   0x8009

Definition at line 6955 of file bnx2x_reg.h.

#define PHY84833_CMD_SET_PAIR_SWAP   0x8001

Definition at line 6953 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_CLEAR_COMPLETE   0x0080

Definition at line 6964 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_COMPLETE_ERROR   0x0008

Definition at line 6960 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_COMPLETE_PASS   0x0004

Definition at line 6959 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_IN_PROGRESS   0x0002

Definition at line 6958 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS   0x0040

Definition at line 6963 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS   0x0010

Definition at line 6961 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_OPEN_OVERRIDE   0xa5a5

Definition at line 6965 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_RECEIVED   0x0001

Definition at line 6957 of file bnx2x_reg.h.

#define PHY84833_STATUS_CMD_SYSTEM_BOOT   0x0020

Definition at line 6962 of file bnx2x_reg.h.

#define PRS_REG_A_PRSU_20   0x40134

Definition at line 3011 of file bnx2x_reg.h.

#define PRS_REG_CFC_LD_CURRENT_CREDIT   0x40164

Definition at line 3013 of file bnx2x_reg.h.

#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT   0x40168

Definition at line 3015 of file bnx2x_reg.h.

#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT   0x4011c

Definition at line 3018 of file bnx2x_reg.h.

#define PRS_REG_CID_PORT_0   0x400fc

Definition at line 3020 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0   0x400dc

Definition at line 3024 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1   0x400e0

Definition at line 3025 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2   0x400e4

Definition at line 3026 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3   0x400e8

Definition at line 3027 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4   0x400ec

Definition at line 3028 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5   0x400f0

Definition at line 3029 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0   0x400bc

Definition at line 3033 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1   0x400c0

Definition at line 3034 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2   0x400c4

Definition at line 3035 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3   0x400c8

Definition at line 3036 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4   0x400cc

Definition at line 3037 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5   0x400d0

Definition at line 3038 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1   0x4009c

Definition at line 3041 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2   0x400a0

Definition at line 3042 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3   0x400a4

Definition at line 3043 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4   0x400a8

Definition at line 3044 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_TYPE_0   0x40078

Definition at line 3047 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_TYPE_1   0x4007c

Definition at line 3048 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_TYPE_2   0x40080

Definition at line 3049 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_TYPE_3   0x40084

Definition at line 3050 of file bnx2x_reg.h.

#define PRS_REG_CM_HDR_TYPE_4   0x40088

Definition at line 3051 of file bnx2x_reg.h.

#define PRS_REG_CM_NO_MATCH_HDR   0x400b8

Definition at line 3053 of file bnx2x_reg.h.

#define PRS_REG_E1HOV_MODE   0x401c8

Definition at line 3055 of file bnx2x_reg.h.

#define PRS_REG_EVENT_ID_1   0x40054

Definition at line 3058 of file bnx2x_reg.h.

#define PRS_REG_EVENT_ID_2   0x40058

Definition at line 3059 of file bnx2x_reg.h.

#define PRS_REG_EVENT_ID_3   0x4005c

Definition at line 3060 of file bnx2x_reg.h.

#define PRS_REG_FCOE_TYPE   0x401d0

Definition at line 3062 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_0   0x40004

Definition at line 3065 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_1   0x40008

Definition at line 3066 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_2   0x4000c

Definition at line 3067 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_3   0x40010

Definition at line 3068 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_4   0x40014

Definition at line 3069 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_5   0x40018

Definition at line 3070 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_6   0x4001c

Definition at line 3071 of file bnx2x_reg.h.

#define PRS_REG_FLUSH_REGIONS_TYPE_7   0x40020

Definition at line 3072 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_BASIC   0x40238

Definition at line 3075 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_BASIC_PORT_0   0x40270

Definition at line 3078 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_BASIC_PORT_1   0x40290

Definition at line 3079 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_TAG_0   0x40248

Definition at line 3081 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0   0x40280

Definition at line 3084 of file bnx2x_reg.h.

#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1   0x402a0

Definition at line 3085 of file bnx2x_reg.h.

#define PRS_REG_INC_VALUE   0x40048

Definition at line 3087 of file bnx2x_reg.h.

#define PRS_REG_MUST_HAVE_HDRS   0x40254

Definition at line 3089 of file bnx2x_reg.h.

#define PRS_REG_MUST_HAVE_HDRS_PORT_0   0x4028c

Definition at line 3092 of file bnx2x_reg.h.

#define PRS_REG_MUST_HAVE_HDRS_PORT_1   0x402ac

Definition at line 3093 of file bnx2x_reg.h.

#define PRS_REG_NIC_MODE   0x40138

Definition at line 3094 of file bnx2x_reg.h.

#define PRS_REG_NO_MATCH_EVENT_ID   0x40070

Definition at line 3097 of file bnx2x_reg.h.

#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES   0x40128

Definition at line 3099 of file bnx2x_reg.h.

#define PRS_REG_NUM_OF_DEAD_CYCLES   0x40130

Definition at line 3102 of file bnx2x_reg.h.

#define PRS_REG_NUM_OF_PACKETS   0x40124

Definition at line 3104 of file bnx2x_reg.h.

#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES   0x4012c

Definition at line 3106 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_0   0x40028

Definition at line 3109 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_1   0x4002c

Definition at line 3110 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_2   0x40030

Definition at line 3111 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_3   0x40034

Definition at line 3112 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_4   0x40038

Definition at line 3113 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_5   0x4003c

Definition at line 3114 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_6   0x40040

Definition at line 3115 of file bnx2x_reg.h.

#define PRS_REG_PACKET_REGIONS_TYPE_7   0x40044

Definition at line 3116 of file bnx2x_reg.h.

#define PRS_REG_PENDING_BRB_CAC0_RQ   0x40174

Definition at line 3118 of file bnx2x_reg.h.

#define PRS_REG_PENDING_BRB_PRS_RQ   0x40170

Definition at line 3120 of file bnx2x_reg.h.

#define PRS_REG_PRS_INT_STS   0x40188

Definition at line 3122 of file bnx2x_reg.h.

#define PRS_REG_PRS_PRTY_MASK   0x401a4

Definition at line 3124 of file bnx2x_reg.h.

#define PRS_REG_PRS_PRTY_STS   0x40198

Definition at line 3126 of file bnx2x_reg.h.

#define PRS_REG_PRS_PRTY_STS_CLR   0x4019c

Definition at line 3128 of file bnx2x_reg.h.

#define PRS_REG_PURE_REGIONS   0x40024

Definition at line 3131 of file bnx2x_reg.h.

#define PRS_REG_SERIAL_NUM_STATUS_LSB   0x40154

Definition at line 3135 of file bnx2x_reg.h.

#define PRS_REG_SERIAL_NUM_STATUS_MSB   0x40158

Definition at line 3139 of file bnx2x_reg.h.

#define PRS_REG_SRC_CURRENT_CREDIT   0x4016c

Definition at line 3141 of file bnx2x_reg.h.

#define PRS_REG_TAG_ETHERTYPE_0   0x401d4

Definition at line 3143 of file bnx2x_reg.h.

#define PRS_REG_TAG_LEN_0   0x4022c

Definition at line 3146 of file bnx2x_reg.h.

#define PRS_REG_TCM_CURRENT_CREDIT   0x40160

Definition at line 3148 of file bnx2x_reg.h.

#define PRS_REG_TSDM_CURRENT_CREDIT   0x4015c

Definition at line 3150 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT   (0x1<<19)

Definition at line 3151 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF   (0x1<<20)

Definition at line 3152 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN   (0x1<<22)

Definition at line 3153 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED   (0x1<<23)

Definition at line 3154 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED   (0x1<<24)

Definition at line 3155 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR   (0x1<<7)

Definition at line 3156 of file bnx2x_reg.h.

#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR   (0x1<<7)

Definition at line 3157 of file bnx2x_reg.h.

#define PXP2_REG_HST_DATA_FIFO_STATUS   0x12047c

Definition at line 3159 of file bnx2x_reg.h.

#define PXP2_REG_HST_HEADER_FIFO_STATUS   0x120478

Definition at line 3161 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_88_F0   0x120534

Definition at line 3162 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_88_F1   0x120544

Definition at line 3166 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_8C_F0   0x120538

Definition at line 3167 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_8C_F1   0x120548

Definition at line 3171 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_90_F0   0x12053c

Definition at line 3172 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_90_F1   0x12054c

Definition at line 3176 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_94_F0   0x120540

Definition at line 3177 of file bnx2x_reg.h.

#define PXP2_REG_PGL_ADDR_94_F1   0x120550

Definition at line 3181 of file bnx2x_reg.h.

#define PXP2_REG_PGL_CONTROL0   0x120490

Definition at line 3182 of file bnx2x_reg.h.

#define PXP2_REG_PGL_CONTROL1   0x120514

Definition at line 3183 of file bnx2x_reg.h.

#define PXP2_REG_PGL_DEBUG   0x120520

Definition at line 3184 of file bnx2x_reg.h.

#define PXP2_REG_PGL_EXP_ROM2   0x120808

Definition at line 3189 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_0   0x1204f4

Definition at line 3192 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_1   0x1204f8

Definition at line 3193 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_2   0x1204fc

Definition at line 3194 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_3   0x120500

Definition at line 3195 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_4   0x120504

Definition at line 3196 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_5   0x120508

Definition at line 3197 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_6   0x12050c

Definition at line 3198 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_CSDM_7   0x120510

Definition at line 3199 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_0   0x120494

Definition at line 3202 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_1   0x120498

Definition at line 3203 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_2   0x12049c

Definition at line 3204 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_3   0x1204a0

Definition at line 3205 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_4   0x1204a4

Definition at line 3206 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_5   0x1204a8

Definition at line 3207 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_6   0x1204ac

Definition at line 3208 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_TSDM_7   0x1204b0

Definition at line 3209 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_0   0x1204b4

Definition at line 3212 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_1   0x1204b8

Definition at line 3213 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_2   0x1204bc

Definition at line 3214 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_3   0x1204c0

Definition at line 3215 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_4   0x1204c4

Definition at line 3216 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_5   0x1204c8

Definition at line 3217 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_6   0x1204cc

Definition at line 3218 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_USDM_7   0x1204d0

Definition at line 3219 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_0   0x1204d4

Definition at line 3222 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_1   0x1204d8

Definition at line 3223 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_2   0x1204dc

Definition at line 3224 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_3   0x1204e0

Definition at line 3225 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_4   0x1204e4

Definition at line 3226 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_5   0x1204e8

Definition at line 3227 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_6   0x1204ec

Definition at line 3228 of file bnx2x_reg.h.

#define PXP2_REG_PGL_INT_XSDM_7   0x1204f0

Definition at line 3229 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F0   0x120674

Definition at line 3235 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F1   0x120678

Definition at line 3236 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F2   0x12067c

Definition at line 3237 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F3   0x120680

Definition at line 3238 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F4   0x120684

Definition at line 3239 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F5   0x120688

Definition at line 3240 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F6   0x12068c

Definition at line 3241 of file bnx2x_reg.h.

#define PXP2_REG_PGL_PRETEND_FUNC_F7   0x120690

Definition at line 3242 of file bnx2x_reg.h.

#define PXP2_REG_PGL_READ_BLOCKED   0x120568

Definition at line 3245 of file bnx2x_reg.h.

#define PXP2_REG_PGL_TAGS_LIMIT   0x1205a8

Definition at line 3246 of file bnx2x_reg.h.

#define PXP2_REG_PGL_TXW_CDTS   0x12052c

Definition at line 3248 of file bnx2x_reg.h.

#define PXP2_REG_PGL_WRITE_BLOCKED   0x120564

Definition at line 3251 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD1   0x1201c0

Definition at line 3252 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD10   0x1201e4

Definition at line 3253 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD11   0x1201e8

Definition at line 3254 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD2   0x1201c4

Definition at line 3255 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD28   0x120228

Definition at line 3256 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD3   0x1201c8

Definition at line 3257 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD6   0x1201d4

Definition at line 3258 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD7   0x1201d8

Definition at line 3259 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD8   0x1201dc

Definition at line 3260 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_ADD9   0x1201e0

Definition at line 3261 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_CREDIT   0x12032c

Definition at line 3262 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L1   0x1202b0

Definition at line 3263 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L10   0x1202d4

Definition at line 3264 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L11   0x1202d8

Definition at line 3265 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L2   0x1202b4

Definition at line 3266 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L28   0x120318

Definition at line 3267 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L3   0x1202b8

Definition at line 3268 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L6   0x1202c4

Definition at line 3269 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L7   0x1202c8

Definition at line 3270 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L8   0x1202cc

Definition at line 3271 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_L9   0x1202d0

Definition at line 3272 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_RD   0x120324

Definition at line 3273 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB1   0x120238

Definition at line 3274 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB10   0x12025c

Definition at line 3275 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB11   0x120260

Definition at line 3276 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB2   0x12023c

Definition at line 3277 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB28   0x1202a0

Definition at line 3278 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB3   0x120240

Definition at line 3279 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB6   0x12024c

Definition at line 3280 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB7   0x120250

Definition at line 3281 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB8   0x120254

Definition at line 3282 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_UB9   0x120258

Definition at line 3283 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_BW_WR   0x120328

Definition at line 3284 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_CDU0_L2P   0x120000

Definition at line 3285 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_QM0_L2P   0x120038

Definition at line 3286 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_SRC0_L2P   0x120054

Definition at line 3287 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_TM0_L2P   0x12001c

Definition at line 3288 of file bnx2x_reg.h.

#define PXP2_REG_PSWRQ_TSDM0_L2P   0x1200e0

Definition at line 3289 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_INT_MASK_0   0x120578

Definition at line 3291 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_INT_STS_0   0x12056c

Definition at line 3293 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_INT_STS_1   0x120608

Definition at line 3294 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_INT_STS_CLR_0   0x120570

Definition at line 3296 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_MASK_0   0x120588

Definition at line 3298 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_MASK_1   0x120598

Definition at line 3299 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_STS_0   0x12057c

Definition at line 3301 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_STS_1   0x12058c

Definition at line 3302 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_STS_CLR_0   0x120580

Definition at line 3304 of file bnx2x_reg.h.

#define PXP2_REG_PXP2_PRTY_STS_CLR_1   0x120590

Definition at line 3305 of file bnx2x_reg.h.

#define PXP2_REG_RD_ALMOST_FULL_0   0x120424

Definition at line 3308 of file bnx2x_reg.h.

#define PXP2_REG_RD_BLK_CNT   0x120418

Definition at line 3310 of file bnx2x_reg.h.

#define PXP2_REG_RD_BLK_NUM_CFG   0x12040c

Definition at line 3313 of file bnx2x_reg.h.

#define PXP2_REG_RD_CDURD_SWAP_MODE   0x120404

Definition at line 3315 of file bnx2x_reg.h.

#define PXP2_REG_RD_DISABLE_INPUTS   0x120374

Definition at line 3317 of file bnx2x_reg.h.

#define PXP2_REG_RD_INIT_DONE   0x120370

Definition at line 3319 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ10   0x1203a0

Definition at line 3322 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ11   0x1203a4

Definition at line 3325 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ17   0x1203bc

Definition at line 3328 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ18   0x1203c0

Definition at line 3331 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ19   0x1203c4

Definition at line 3334 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ22   0x1203d0

Definition at line 3337 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ25   0x1203dc

Definition at line 3340 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ6   0x120390

Definition at line 3343 of file bnx2x_reg.h.

#define PXP2_REG_RD_MAX_BLKS_VQ9   0x12039c

Definition at line 3346 of file bnx2x_reg.h.

#define PXP2_REG_RD_PBF_SWAP_MODE   0x1203f4

Definition at line 3348 of file bnx2x_reg.h.

#define PXP2_REG_RD_PORT_IS_IDLE_0   0x12041c

Definition at line 3350 of file bnx2x_reg.h.

#define PXP2_REG_RD_PORT_IS_IDLE_1   0x120420

Definition at line 3351 of file bnx2x_reg.h.

#define PXP2_REG_RD_QM_SWAP_MODE   0x1203f8

Definition at line 3353 of file bnx2x_reg.h.

#define PXP2_REG_RD_SR_CNT   0x120414

Definition at line 3355 of file bnx2x_reg.h.

#define PXP2_REG_RD_SR_NUM_CFG   0x120408

Definition at line 3360 of file bnx2x_reg.h.

#define PXP2_REG_RD_SRC_SWAP_MODE   0x120400

Definition at line 3357 of file bnx2x_reg.h.

#define PXP2_REG_RD_START_INIT   0x12036c

Definition at line 3362 of file bnx2x_reg.h.

#define PXP2_REG_RD_TM_SWAP_MODE   0x1203fc

Definition at line 3364 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD0   0x1201bc

Definition at line 3366 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD12   0x1201ec

Definition at line 3368 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD13   0x1201f0

Definition at line 3370 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD14   0x1201f4

Definition at line 3372 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD15   0x1201f8

Definition at line 3374 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD16   0x1201fc

Definition at line 3376 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD17   0x120200

Definition at line 3378 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD18   0x120204

Definition at line 3380 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD19   0x120208

Definition at line 3382 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD20   0x12020c

Definition at line 3384 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD22   0x120210

Definition at line 3386 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD23   0x120214

Definition at line 3388 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD24   0x120218

Definition at line 3390 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD25   0x12021c

Definition at line 3392 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD26   0x120220

Definition at line 3394 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD27   0x120224

Definition at line 3396 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD4   0x1201cc

Definition at line 3398 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_ADD5   0x1201d0

Definition at line 3400 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L0   0x1202ac

Definition at line 3402 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L12   0x1202dc

Definition at line 3404 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L13   0x1202e0

Definition at line 3406 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L14   0x1202e4

Definition at line 3408 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L15   0x1202e8

Definition at line 3410 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L16   0x1202ec

Definition at line 3412 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L17   0x1202f0

Definition at line 3414 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L18   0x1202f4

Definition at line 3416 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L19   0x1202f8

Definition at line 3418 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L20   0x1202fc

Definition at line 3420 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L22   0x120300

Definition at line 3422 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L23   0x120304

Definition at line 3424 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L24   0x120308

Definition at line 3426 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L25   0x12030c

Definition at line 3428 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L26   0x120310

Definition at line 3430 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L27   0x120314

Definition at line 3432 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L4   0x1202bc

Definition at line 3434 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_L5   0x1202c0

Definition at line 3436 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND0   0x120234

Definition at line 3438 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND12   0x120264

Definition at line 3440 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND13   0x120268

Definition at line 3442 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND14   0x12026c

Definition at line 3444 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND15   0x120270

Definition at line 3446 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND16   0x120274

Definition at line 3448 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND17   0x120278

Definition at line 3450 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND18   0x12027c

Definition at line 3452 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND19   0x120280

Definition at line 3454 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND20   0x120284

Definition at line 3456 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND22   0x120288

Definition at line 3458 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND23   0x12028c

Definition at line 3460 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND24   0x120290

Definition at line 3462 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND25   0x120294

Definition at line 3464 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND26   0x120298

Definition at line 3466 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND27   0x12029c

Definition at line 3468 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND4   0x120244

Definition at line 3470 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_RD_UBOUND5   0x120248

Definition at line 3472 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_ADD29   0x12022c

Definition at line 3474 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_ADD30   0x120230

Definition at line 3476 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_L29   0x12031c

Definition at line 3478 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_L30   0x120320

Definition at line 3480 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_UBOUND29   0x1202a4

Definition at line 3482 of file bnx2x_reg.h.

#define PXP2_REG_RQ_BW_WR_UBOUND30   0x1202a8

Definition at line 3484 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR   0x120008

Definition at line 3486 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CDU_ENDIAN_M   0x1201a0

Definition at line 3488 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CDU_FIRST_ILT   0x12061c

Definition at line 3489 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CDU_LAST_ILT   0x120620

Definition at line 3490 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CDU_P_SIZE   0x120018

Definition at line 3493 of file bnx2x_reg.h.

#define PXP2_REG_RQ_CFG_DONE   0x1201b4

Definition at line 3496 of file bnx2x_reg.h.

#define PXP2_REG_RQ_DBG_ENDIAN_M   0x1201a4

Definition at line 3498 of file bnx2x_reg.h.

#define PXP2_REG_RQ_DISABLE_INPUTS   0x120330

Definition at line 3501 of file bnx2x_reg.h.

#define PXP2_REG_RQ_DRAM_ALIGN   0x1205b0

Definition at line 3505 of file bnx2x_reg.h.

#define PXP2_REG_RQ_DRAM_ALIGN_RD   0x12092c

Definition at line 3509 of file bnx2x_reg.h.

#define PXP2_REG_RQ_DRAM_ALIGN_SEL   0x120930

Definition at line 3512 of file bnx2x_reg.h.

#define PXP2_REG_RQ_ELT_DISABLE   0x12066c

Definition at line 3515 of file bnx2x_reg.h.

#define PXP2_REG_RQ_HC_ENDIAN_M   0x1201a8

Definition at line 3517 of file bnx2x_reg.h.

#define PXP2_REG_RQ_ILT_MODE   0x1205b4

Definition at line 3520 of file bnx2x_reg.h.

#define PXP2_REG_RQ_ONCHIP_AT   0x122000

Definition at line 3522 of file bnx2x_reg.h.

#define PXP2_REG_RQ_ONCHIP_AT_B0   0x128000

Definition at line 3524 of file bnx2x_reg.h.

#define PXP2_REG_RQ_PDR_LIMIT   0x12033c

Definition at line 3526 of file bnx2x_reg.h.

#define PXP2_REG_RQ_QM_ENDIAN_M   0x120194

Definition at line 3528 of file bnx2x_reg.h.

#define PXP2_REG_RQ_QM_FIRST_ILT   0x120634

Definition at line 3529 of file bnx2x_reg.h.

#define PXP2_REG_RQ_QM_LAST_ILT   0x120638

Definition at line 3530 of file bnx2x_reg.h.

#define PXP2_REG_RQ_QM_P_SIZE   0x120050

Definition at line 3533 of file bnx2x_reg.h.

#define PXP2_REG_RQ_RBC_DONE   0x1201b0

Definition at line 3535 of file bnx2x_reg.h.

#define PXP2_REG_RQ_RD_MBS0   0x120160

Definition at line 3538 of file bnx2x_reg.h.

#define PXP2_REG_RQ_RD_MBS1   0x120168

Definition at line 3541 of file bnx2x_reg.h.

#define PXP2_REG_RQ_SRC_ENDIAN_M   0x12019c

Definition at line 3543 of file bnx2x_reg.h.

#define PXP2_REG_RQ_SRC_FIRST_ILT   0x12063c

Definition at line 3544 of file bnx2x_reg.h.

#define PXP2_REG_RQ_SRC_LAST_ILT   0x120640

Definition at line 3545 of file bnx2x_reg.h.

#define PXP2_REG_RQ_SRC_P_SIZE   0x12006c

Definition at line 3548 of file bnx2x_reg.h.

#define PXP2_REG_RQ_TM_ENDIAN_M   0x120198

Definition at line 3550 of file bnx2x_reg.h.

#define PXP2_REG_RQ_TM_FIRST_ILT   0x120644

Definition at line 3551 of file bnx2x_reg.h.

#define PXP2_REG_RQ_TM_LAST_ILT   0x120648

Definition at line 3552 of file bnx2x_reg.h.

#define PXP2_REG_RQ_TM_P_SIZE   0x120034

Definition at line 3555 of file bnx2x_reg.h.

#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY   0x12080c

Definition at line 3557 of file bnx2x_reg.h.

#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR   0x120094

Definition at line 3559 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ0_ENTRY_CNT   0x120810

Definition at line 3561 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ10_ENTRY_CNT   0x120818

Definition at line 3563 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ11_ENTRY_CNT   0x120820

Definition at line 3565 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ12_ENTRY_CNT   0x120828

Definition at line 3567 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ13_ENTRY_CNT   0x120830

Definition at line 3569 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ14_ENTRY_CNT   0x120838

Definition at line 3571 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ15_ENTRY_CNT   0x120840

Definition at line 3573 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ16_ENTRY_CNT   0x120848

Definition at line 3575 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ17_ENTRY_CNT   0x120850

Definition at line 3577 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ18_ENTRY_CNT   0x120858

Definition at line 3579 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ19_ENTRY_CNT   0x120860

Definition at line 3581 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ1_ENTRY_CNT   0x120868

Definition at line 3583 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ20_ENTRY_CNT   0x120870

Definition at line 3585 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ21_ENTRY_CNT   0x120878

Definition at line 3587 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ22_ENTRY_CNT   0x120880

Definition at line 3589 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ23_ENTRY_CNT   0x120888

Definition at line 3591 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ24_ENTRY_CNT   0x120890

Definition at line 3593 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ25_ENTRY_CNT   0x120898

Definition at line 3595 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ26_ENTRY_CNT   0x1208a0

Definition at line 3597 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ27_ENTRY_CNT   0x1208a8

Definition at line 3599 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ28_ENTRY_CNT   0x1208b0

Definition at line 3601 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ29_ENTRY_CNT   0x1208b8

Definition at line 3603 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ2_ENTRY_CNT   0x1208c0

Definition at line 3605 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ30_ENTRY_CNT   0x1208c8

Definition at line 3607 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ31_ENTRY_CNT   0x1208d0

Definition at line 3609 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ3_ENTRY_CNT   0x1208d8

Definition at line 3611 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ4_ENTRY_CNT   0x1208e0

Definition at line 3613 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ5_ENTRY_CNT   0x1208e8

Definition at line 3615 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ6_ENTRY_CNT   0x1208f0

Definition at line 3617 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ7_ENTRY_CNT   0x1208f8

Definition at line 3619 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ8_ENTRY_CNT   0x120900

Definition at line 3621 of file bnx2x_reg.h.

#define PXP2_REG_RQ_VQ9_ENTRY_CNT   0x120908

Definition at line 3623 of file bnx2x_reg.h.

#define PXP2_REG_RQ_WR_MBS0   0x12015c

Definition at line 3626 of file bnx2x_reg.h.

#define PXP2_REG_RQ_WR_MBS1   0x120164

Definition at line 3629 of file bnx2x_reg.h.

#define PXP2_REG_WR_CDU_MPS   0x1205f0

Definition at line 3632 of file bnx2x_reg.h.

#define PXP2_REG_WR_CSDM_MPS   0x1205d0

Definition at line 3635 of file bnx2x_reg.h.

#define PXP2_REG_WR_DBG_MPS   0x1205e8

Definition at line 3638 of file bnx2x_reg.h.

#define PXP2_REG_WR_DMAE_MPS   0x1205ec

Definition at line 3641 of file bnx2x_reg.h.

#define PXP2_REG_WR_DMAE_TH   0x120368

Definition at line 3645 of file bnx2x_reg.h.

#define PXP2_REG_WR_HC_MPS   0x1205c8

Definition at line 3648 of file bnx2x_reg.h.

#define PXP2_REG_WR_QM_MPS   0x1205dc

Definition at line 3651 of file bnx2x_reg.h.

#define PXP2_REG_WR_REV_MODE   0x120670

Definition at line 3653 of file bnx2x_reg.h.

#define PXP2_REG_WR_SRC_MPS   0x1205e4

Definition at line 3656 of file bnx2x_reg.h.

#define PXP2_REG_WR_TM_MPS   0x1205e0

Definition at line 3659 of file bnx2x_reg.h.

#define PXP2_REG_WR_TSDM_MPS   0x1205d4

Definition at line 3662 of file bnx2x_reg.h.

#define PXP2_REG_WR_USDM_MPS   0x1205cc

Definition at line 3669 of file bnx2x_reg.h.

#define PXP2_REG_WR_USDMDP_TH   0x120348

Definition at line 3666 of file bnx2x_reg.h.

#define PXP2_REG_WR_XSDM_MPS   0x1205d8

Definition at line 3672 of file bnx2x_reg.h.

#define PXP_REG_HST_ARB_IS_IDLE   0x103004

Definition at line 3674 of file bnx2x_reg.h.

#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB   0x103008

Definition at line 3677 of file bnx2x_reg.h.

#define PXP_REG_HST_DISCARD_DOORBELLS   0x1030a4

Definition at line 3680 of file bnx2x_reg.h.

#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS   0x1030a0

Definition at line 3684 of file bnx2x_reg.h.

#define PXP_REG_HST_DISCARD_INTERNAL_WRITES   0x1030a8

Definition at line 3687 of file bnx2x_reg.h.

#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS   0x10309c

Definition at line 3692 of file bnx2x_reg.h.

#define PXP_REG_HST_INBOUND_INT   0x103800

Definition at line 3694 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_MASK_0   0x103074

Definition at line 3696 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_MASK_1   0x103084

Definition at line 3697 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_STS_0   0x103068

Definition at line 3699 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_STS_1   0x103078

Definition at line 3700 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_STS_CLR_0   0x10306c

Definition at line 3702 of file bnx2x_reg.h.

#define PXP_REG_PXP_INT_STS_CLR_1   0x10307c

Definition at line 3703 of file bnx2x_reg.h.

#define PXP_REG_PXP_PRTY_MASK   0x103094

Definition at line 3705 of file bnx2x_reg.h.

#define PXP_REG_PXP_PRTY_STS   0x103088

Definition at line 3707 of file bnx2x_reg.h.

#define PXP_REG_PXP_PRTY_STS_CLR   0x10308c

Definition at line 3709 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5   0x814

Definition at line 6277 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN   (1 << 28) /*WC*/

Definition at line 6279 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN   (1 << 22) /*RO*/

Definition at line 6285 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT   (1 << 2) /*WC*/

Definition at line 6305 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1   (1 << 12) /*WC*/

Definition at line 6295 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_ECRC   (1 << 7) /*WC*/

Definition at line 6300 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_ECRC1   (1 << 17) /*WC*/

Definition at line 6290 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL   (1 << 1) /*WC*/

Definition at line 6306 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1   (1 << 11) /*WC*/

Definition at line 6296 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP   (1 << 6) /*WC*/

Definition at line 6301 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1   (1 << 16) /*WC*/

Definition at line 6291 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT   (1 << 3) /*WC*/

Definition at line 6304 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1   (1 << 13) /*WC*/

Definition at line 6294 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP   (1 << 0) /*WC*/

Definition at line 6307 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1   (1 << 10) /*WC*/

Definition at line 6297 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW   (1 << 5) /*WC*/

Definition at line 6302 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1   (1 << 15) /*WC*/

Definition at line 6292 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL   (1 << 4) /*WC*/

Definition at line 6303 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1   (1 << 14) /*WC*/

Definition at line 6293 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT   (1 << 8) /*WC*/

Definition at line 6299 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1   (1 << 18) /*WC*/

Definition at line 6289 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN   (1 << 26) /*WC*/

Definition at line 6281 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN   (1 << 27) /*WC*/

Definition at line 6280 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN   (1 << 23) /*RO*/

Definition at line 6284 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT   (1 << 9) /*WC*/

Definition at line 6298 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1   (1 << 19) /*WC*/

Definition at line 6288 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG   (1 << 20) /*WC*/

Definition at line 6287 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR   (1 << 25) /*WC*/

Definition at line 6282 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE   (1 << 21) /*WC*/

Definition at line 6286 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW   (1 << 24) /*WC*/

Definition at line 6283 of file bnx2x_reg.h.

#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN   (1 << 29) /*WC*/

Definition at line 6278 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT   0x854

Definition at line 6310 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2
Value:
(1 << 2) /* Completer Timeout Status Status for Function 2, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6362 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3
Value:
(1 << 12) /* Completer Timeout Status Status in function 3, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6343 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4
Value:
(1 << 22) /* Completer Timeout Status Status in function 4, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6324 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2
Value:
(1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6352 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3
Value:
(1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6333 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4
Value:
(1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6314 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2
Value:
(1 << 1) /* Flow Control Protocol Error Status Status for \
Function 2, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6364 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3
Value:
(1 << 11) /* Flow Control Protocol Error Status Status in \
function 3, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6345 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4
Value:
(1 << 21) /* Flow Control Protocol Error Status Status in \
function 4, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6326 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2
Value:
(1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6354 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3
Value:
(1 << 16) /* Malformed TLP Status Status in function 3, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6335 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4
Value:
(1 << 26) /* Malformed TLP Status Status in function 4, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6316 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2
Value:
(1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6360 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3
Value:
(1 << 13) /* Receive UR Statusin function 3. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6341 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4
Value:
(1 << 23) /* Receive UR Statusin function 4. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6322 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2
Value:
(1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6366 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3
Value:
(1 << 10) /* Poisoned Error Status Status in function 3, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6347 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4
Value:
(1 << 20) /* Poisoned Error Status Status in function 4, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6328 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2
Value:
(1 << 5) /* Receiver Overflow Status Status for Function 2, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6356 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3
Value:
(1 << 15) /* Receiver Overflow Status Status in function 3, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6337 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4
Value:
(1 << 25) /* Receiver Overflow Status Status in function 4, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6318 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2
Value:
(1 << 4) /* Unexpected Completion Status Status for Function 2, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6358 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3
Value:
(1 << 14) /* Unexpected Completion Status Status in function 3, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6339 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4
Value:
(1 << 24) /* Unexpected Completion Status Status in function 4, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6320 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
Value:
(1 << 8) /* Unsupported Request Error Status for Function 2, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6350 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
Value:
(1 << 18) /* Unsupported Request Error Status in function3, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6331 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
Value:
(1 << 28) /* Unsupported Request Error Status in function4, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6312 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2   (1 << 9) /* WC */

Definition at line 6349 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3   (1 << 19) /* WC */

Definition at line 6330 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4   (1 << 29) /* WC */

Definition at line 6311 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT   0x85C

Definition at line 6370 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5
Value:
(1 << 2) /* Completer Timeout Status Status for Function 5, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6422 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6
Value:
(1 << 12) /* Completer Timeout Status Status in function 6, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6403 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7
Value:
(1 << 22) /* Completer Timeout Status Status in function 7, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6384 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5
Value:
(1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6412 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6
Value:
(1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6393 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7
Value:
(1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6374 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5
Value:
(1 << 1) /* Flow Control Protocol Error Status Status for \
Function 5, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6424 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6
Value:
(1 << 11) /* Flow Control Protocol Error Status Status in \
function 6, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6405 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7
Value:
(1 << 21) /* Flow Control Protocol Error Status Status in \
function 7, if set, generate pcie_err_attn output when this error \
is seen. WC */

Definition at line 6386 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5
Value:
(1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6414 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6
Value:
(1 << 16) /* Malformed TLP Status Status in function 6, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6395 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7
Value:
(1 << 26) /* Malformed TLP Status Status in function 7, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6376 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5
Value:
(1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6420 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6
Value:
(1 << 13) /* Receive UR Statusin function 6. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6401 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7
Value:
(1 << 23) /* Receive UR Statusin function 7. If set, generate \
pcie_err_attn output when this error is seen. WC */

Definition at line 6382 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5
Value:
(1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6426 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6
Value:
(1 << 10) /* Poisoned Error Status Status in function 6, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6407 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7
Value:
(1 << 20) /* Poisoned Error Status Status in function 7, if set, \
generate pcie_err_attn output when this error is seen.. WC */

Definition at line 6388 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5
Value:
(1 << 5) /* Receiver Overflow Status Status for Function 5, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6416 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6
Value:
(1 << 15) /* Receiver Overflow Status Status in function 6, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6397 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7
Value:
(1 << 25) /* Receiver Overflow Status Status in function 7, if \
set, generate pcie_err_attn output when this error is seen.. WC \
*/

Definition at line 6378 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5
Value:
(1 << 4) /* Unexpected Completion Status Status for Function 5, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6418 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6
Value:
(1 << 14) /* Unexpected Completion Status Status in function 6, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6399 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7
Value:
(1 << 24) /* Unexpected Completion Status Status in function 7, \
if set, generate pcie_err_attn output when this error is seen. WC \
*/

Definition at line 6380 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
Value:
(1 << 8) /* Unsupported Request Error Status for Function 5, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6410 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
Value:
(1 << 18) /* Unsupported Request Error Status in function6, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6391 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
Value:
(1 << 28) /* Unsupported Request Error Status in function7, if \
set, generate pcie_err_attn output when this error is seen. WC */

Definition at line 6372 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5   (1 << 9) /* WC */

Definition at line 6409 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6   (1 << 19) /* WC */

Definition at line 6390 of file bnx2x_reg.h.

#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7   (1 << 29) /* WC */

Definition at line 6371 of file bnx2x_reg.h.

#define QM_REG_ACTCTRINITVAL_0   0x168040

Definition at line 3712 of file bnx2x_reg.h.

#define QM_REG_ACTCTRINITVAL_1   0x168044

Definition at line 3713 of file bnx2x_reg.h.

#define QM_REG_ACTCTRINITVAL_2   0x168048

Definition at line 3714 of file bnx2x_reg.h.

#define QM_REG_ACTCTRINITVAL_3   0x16804c

Definition at line 3715 of file bnx2x_reg.h.

#define QM_REG_BASEADDR   0x168900

Definition at line 3720 of file bnx2x_reg.h.

#define QM_REG_BASEADDR_EXT_A   0x16e100

Definition at line 3725 of file bnx2x_reg.h.

#define QM_REG_BYTECRDCMDQ_0   0x16e6e8

Definition at line 3747 of file bnx2x_reg.h.

#define QM_REG_BYTECRDCOST   0x168234

Definition at line 3727 of file bnx2x_reg.h.

#define QM_REG_BYTECRDINITVAL   0x168238

Definition at line 3729 of file bnx2x_reg.h.

#define QM_REG_BYTECRDPORT_LSB   0x168228

Definition at line 3732 of file bnx2x_reg.h.

#define QM_REG_BYTECRDPORT_LSB_EXT_A   0x16e520

Definition at line 3735 of file bnx2x_reg.h.

#define QM_REG_BYTECRDPORT_MSB   0x168224

Definition at line 3738 of file bnx2x_reg.h.

#define QM_REG_BYTECRDPORT_MSB_EXT_A   0x16e51c

Definition at line 3741 of file bnx2x_reg.h.

#define QM_REG_BYTECREDITAFULLTHR   0x168094

Definition at line 3744 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_0   0x1680cc

Definition at line 3746 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_1   0x1680d0

Definition at line 3748 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_2   0x1680d4

Definition at line 3749 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_3   0x1680d8

Definition at line 3750 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_4   0x1680dc

Definition at line 3751 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_5   0x1680e0

Definition at line 3752 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_6   0x1680e4

Definition at line 3753 of file bnx2x_reg.h.

#define QM_REG_CMINITCRD_7   0x1680e8

Definition at line 3754 of file bnx2x_reg.h.

#define QM_REG_CMINTEN   0x1680ec

Definition at line 3757 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_0   0x1681f4

Definition at line 3760 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_1   0x1681f8

Definition at line 3761 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_2   0x1681fc

Definition at line 3762 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_3   0x168200

Definition at line 3763 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_4   0x168204

Definition at line 3764 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_5   0x168208

Definition at line 3765 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_6   0x16820c

Definition at line 3766 of file bnx2x_reg.h.

#define QM_REG_CMINTVOQMASK_7   0x168210

Definition at line 3767 of file bnx2x_reg.h.

#define QM_REG_CONNNUM_0   0x168020

Definition at line 3770 of file bnx2x_reg.h.

#define QM_REG_CQM_WRC_FIFOLVL   0x168018

Definition at line 3772 of file bnx2x_reg.h.

#define QM_REG_CTXREG_0   0x168030

Definition at line 3774 of file bnx2x_reg.h.

#define QM_REG_CTXREG_1   0x168034

Definition at line 3775 of file bnx2x_reg.h.

#define QM_REG_CTXREG_2   0x168038

Definition at line 3776 of file bnx2x_reg.h.

#define QM_REG_CTXREG_3   0x16803c

Definition at line 3777 of file bnx2x_reg.h.

#define QM_REG_ENBYPVOQMASK   0x16823c

Definition at line 3780 of file bnx2x_reg.h.

#define QM_REG_ENBYTECRD_LSB   0x168220

Definition at line 3783 of file bnx2x_reg.h.

#define QM_REG_ENBYTECRD_LSB_EXT_A   0x16e518

Definition at line 3786 of file bnx2x_reg.h.

#define QM_REG_ENBYTECRD_MSB   0x16821c

Definition at line 3789 of file bnx2x_reg.h.

#define QM_REG_ENBYTECRD_MSB_EXT_A   0x16e514

Definition at line 3792 of file bnx2x_reg.h.

#define QM_REG_ENSEC   0x1680f0

Definition at line 3795 of file bnx2x_reg.h.

#define QM_REG_FUNCNUMSEL_LSB   0x168230

Definition at line 3797 of file bnx2x_reg.h.

#define QM_REG_FUNCNUMSEL_MSB   0x16822c

Definition at line 3799 of file bnx2x_reg.h.

#define QM_REG_HWAEMPTYMASK_LSB   0x168218

Definition at line 3802 of file bnx2x_reg.h.

#define QM_REG_HWAEMPTYMASK_LSB_EXT_A   0x16e510

Definition at line 3805 of file bnx2x_reg.h.

#define QM_REG_HWAEMPTYMASK_MSB   0x168214

Definition at line 3808 of file bnx2x_reg.h.

#define QM_REG_HWAEMPTYMASK_MSB_EXT_A   0x16e50c

Definition at line 3811 of file bnx2x_reg.h.

#define QM_REG_OUTLDREQ   0x168804

Definition at line 3813 of file bnx2x_reg.h.

#define QM_REG_OVFERROR   0x16805c

Definition at line 3816 of file bnx2x_reg.h.

#define QM_REG_OVFQNUM   0x168058

Definition at line 3818 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE0   0x168410

Definition at line 3820 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE1   0x168414

Definition at line 3822 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE2   0x16e684

Definition at line 3824 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE3   0x16e688

Definition at line 3826 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE4   0x16e68c

Definition at line 3828 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE5   0x16e690

Definition at line 3830 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE6   0x16e694

Definition at line 3832 of file bnx2x_reg.h.

#define QM_REG_PAUSESTATE7   0x16e698

Definition at line 3834 of file bnx2x_reg.h.

#define QM_REG_PCIREQAT   0x168054

Definition at line 3836 of file bnx2x_reg.h.

#define QM_REG_PF_EN   0x16e70c

Definition at line 3837 of file bnx2x_reg.h.

#define QM_REG_PF_USG_CNT_0   0x16e040

Definition at line 3840 of file bnx2x_reg.h.

#define QM_REG_PORT0BYTECRD   0x168300

Definition at line 3842 of file bnx2x_reg.h.

#define QM_REG_PORT1BYTECRD   0x168304

Definition at line 3844 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_0   0x16e6bc

Definition at line 3846 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_1   0x16e6c0

Definition at line 3847 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_2   0x16e6c4

Definition at line 3848 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_3   0x16e6c8

Definition at line 3849 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_4   0x16e6cc

Definition at line 3850 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_5   0x16e6d0

Definition at line 3851 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_6   0x16e6d4

Definition at line 3852 of file bnx2x_reg.h.

#define QM_REG_PQ2PCIFUNC_7   0x16e6d8

Definition at line 3853 of file bnx2x_reg.h.

#define QM_REG_PTRTBL   0x168a00

Definition at line 3857 of file bnx2x_reg.h.

#define QM_REG_PTRTBL_EXT_A   0x16e200

Definition at line 3861 of file bnx2x_reg.h.

#define QM_REG_QM_INT_MASK   0x168444

Definition at line 3863 of file bnx2x_reg.h.

#define QM_REG_QM_INT_STS   0x168438

Definition at line 3865 of file bnx2x_reg.h.

#define QM_REG_QM_PRTY_MASK   0x168454

Definition at line 3867 of file bnx2x_reg.h.

#define QM_REG_QM_PRTY_STS   0x168448

Definition at line 3869 of file bnx2x_reg.h.

#define QM_REG_QM_PRTY_STS_CLR   0x16844c

Definition at line 3871 of file bnx2x_reg.h.

#define QM_REG_QSTATUS_HIGH   0x16802c

Definition at line 3873 of file bnx2x_reg.h.

#define QM_REG_QSTATUS_HIGH_EXT_A   0x16e408

Definition at line 3875 of file bnx2x_reg.h.

#define QM_REG_QSTATUS_LOW   0x168028

Definition at line 3877 of file bnx2x_reg.h.

#define QM_REG_QSTATUS_LOW_EXT_A   0x16e404

Definition at line 3879 of file bnx2x_reg.h.

#define QM_REG_QTASKCTR_0   0x168308

Definition at line 3881 of file bnx2x_reg.h.

#define QM_REG_QTASKCTR_EXT_A_0   0x16e584

Definition at line 3883 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_0   0x1680f4

Definition at line 3885 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_10   0x16811c

Definition at line 3886 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_100   0x16e49c

Definition at line 3887 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_101   0x16e4a0

Definition at line 3888 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_102   0x16e4a4

Definition at line 3889 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_103   0x16e4a8

Definition at line 3890 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_104   0x16e4ac

Definition at line 3891 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_105   0x16e4b0

Definition at line 3892 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_106   0x16e4b4

Definition at line 3893 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_107   0x16e4b8

Definition at line 3894 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_108   0x16e4bc

Definition at line 3895 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_109   0x16e4c0

Definition at line 3896 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_11   0x168120

Definition at line 3897 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_110   0x16e4c4

Definition at line 3898 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_111   0x16e4c8

Definition at line 3899 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_112   0x16e4cc

Definition at line 3900 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_113   0x16e4d0

Definition at line 3901 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_114   0x16e4d4

Definition at line 3902 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_115   0x16e4d8

Definition at line 3903 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_116   0x16e4dc

Definition at line 3904 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_117   0x16e4e0

Definition at line 3905 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_118   0x16e4e4

Definition at line 3906 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_119   0x16e4e8

Definition at line 3907 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_12   0x168124

Definition at line 3908 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_120   0x16e4ec

Definition at line 3909 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_121   0x16e4f0

Definition at line 3910 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_122   0x16e4f4

Definition at line 3911 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_123   0x16e4f8

Definition at line 3912 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_124   0x16e4fc

Definition at line 3913 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_125   0x16e500

Definition at line 3914 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_126   0x16e504

Definition at line 3915 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_127   0x16e508

Definition at line 3916 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_13   0x168128

Definition at line 3917 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_14   0x16812c

Definition at line 3918 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_15   0x168130

Definition at line 3919 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_16   0x168134

Definition at line 3920 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_17   0x168138

Definition at line 3921 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_21   0x168148

Definition at line 3922 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_22   0x16814c

Definition at line 3923 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_23   0x168150

Definition at line 3924 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_24   0x168154

Definition at line 3925 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_25   0x168158

Definition at line 3926 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_26   0x16815c

Definition at line 3927 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_27   0x168160

Definition at line 3928 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_28   0x168164

Definition at line 3929 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_29   0x168168

Definition at line 3930 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_30   0x16816c

Definition at line 3931 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_31   0x168170

Definition at line 3932 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_32   0x168174

Definition at line 3933 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_33   0x168178

Definition at line 3934 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_34   0x16817c

Definition at line 3935 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_35   0x168180

Definition at line 3936 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_36   0x168184

Definition at line 3937 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_37   0x168188

Definition at line 3938 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_38   0x16818c

Definition at line 3939 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_39   0x168190

Definition at line 3940 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_40   0x168194

Definition at line 3941 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_41   0x168198

Definition at line 3942 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_42   0x16819c

Definition at line 3943 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_43   0x1681a0

Definition at line 3944 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_44   0x1681a4

Definition at line 3945 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_45   0x1681a8

Definition at line 3946 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_46   0x1681ac

Definition at line 3947 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_47   0x1681b0

Definition at line 3948 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_48   0x1681b4

Definition at line 3949 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_49   0x1681b8

Definition at line 3950 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_5   0x168108

Definition at line 3951 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_50   0x1681bc

Definition at line 3952 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_51   0x1681c0

Definition at line 3953 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_52   0x1681c4

Definition at line 3954 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_53   0x1681c8

Definition at line 3955 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_54   0x1681cc

Definition at line 3956 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_55   0x1681d0

Definition at line 3957 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_56   0x1681d4

Definition at line 3958 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_57   0x1681d8

Definition at line 3959 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_58   0x1681dc

Definition at line 3960 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_59   0x1681e0

Definition at line 3961 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_6   0x16810c

Definition at line 3962 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_60   0x1681e4

Definition at line 3963 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_61   0x1681e8

Definition at line 3964 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_62   0x1681ec

Definition at line 3965 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_63   0x1681f0

Definition at line 3966 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_64   0x16e40c

Definition at line 3967 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_65   0x16e410

Definition at line 3968 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_69   0x16e420

Definition at line 3969 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_7   0x168110

Definition at line 3970 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_70   0x16e424

Definition at line 3971 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_71   0x16e428

Definition at line 3972 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_72   0x16e42c

Definition at line 3973 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_73   0x16e430

Definition at line 3974 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_74   0x16e434

Definition at line 3975 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_75   0x16e438

Definition at line 3976 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_76   0x16e43c

Definition at line 3977 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_77   0x16e440

Definition at line 3978 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_78   0x16e444

Definition at line 3979 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_79   0x16e448

Definition at line 3980 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_8   0x168114

Definition at line 3981 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_80   0x16e44c

Definition at line 3982 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_81   0x16e450

Definition at line 3983 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_85   0x16e460

Definition at line 3984 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_86   0x16e464

Definition at line 3985 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_87   0x16e468

Definition at line 3986 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_88   0x16e46c

Definition at line 3987 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_89   0x16e470

Definition at line 3988 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_9   0x168118

Definition at line 3989 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_90   0x16e474

Definition at line 3990 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_91   0x16e478

Definition at line 3991 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_92   0x16e47c

Definition at line 3992 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_93   0x16e480

Definition at line 3993 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_94   0x16e484

Definition at line 3994 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_95   0x16e488

Definition at line 3995 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_96   0x16e48c

Definition at line 3996 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_97   0x16e490

Definition at line 3997 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_98   0x16e494

Definition at line 3998 of file bnx2x_reg.h.

#define QM_REG_QVOQIDX_99   0x16e498

Definition at line 3999 of file bnx2x_reg.h.

#define QM_REG_SOFT_RESET   0x168428

Definition at line 4001 of file bnx2x_reg.h.

#define QM_REG_TASKCRDCOST_0   0x16809c

Definition at line 4003 of file bnx2x_reg.h.

#define QM_REG_TASKCRDCOST_1   0x1680a0

Definition at line 4004 of file bnx2x_reg.h.

#define QM_REG_TASKCRDCOST_2   0x1680a4

Definition at line 4005 of file bnx2x_reg.h.

#define QM_REG_TASKCRDCOST_4   0x1680ac

Definition at line 4006 of file bnx2x_reg.h.

#define QM_REG_TASKCRDCOST_5   0x1680b0

Definition at line 4007 of file bnx2x_reg.h.

#define QM_REG_TQM_WRC_FIFOLVL   0x168010

Definition at line 4009 of file bnx2x_reg.h.

#define QM_REG_UQM_WRC_FIFOLVL   0x168008

Definition at line 4011 of file bnx2x_reg.h.

#define QM_REG_VOQCRDERRREG   0x168408

Definition at line 4013 of file bnx2x_reg.h.

#define QM_REG_VOQCREDIT_0   0x1682d0

Definition at line 4015 of file bnx2x_reg.h.

#define QM_REG_VOQCREDIT_1   0x1682d4

Definition at line 4016 of file bnx2x_reg.h.

#define QM_REG_VOQCREDIT_4   0x1682e0

Definition at line 4017 of file bnx2x_reg.h.

#define QM_REG_VOQCREDITAFULLTHR   0x168090

Definition at line 4019 of file bnx2x_reg.h.

#define QM_REG_VOQINITCREDIT_0   0x168060

Definition at line 4021 of file bnx2x_reg.h.

#define QM_REG_VOQINITCREDIT_1   0x168064

Definition at line 4022 of file bnx2x_reg.h.

#define QM_REG_VOQINITCREDIT_2   0x168068

Definition at line 4023 of file bnx2x_reg.h.

#define QM_REG_VOQINITCREDIT_4   0x168070

Definition at line 4024 of file bnx2x_reg.h.

#define QM_REG_VOQINITCREDIT_5   0x168074

Definition at line 4025 of file bnx2x_reg.h.

#define QM_REG_VOQPORT_0   0x1682a0

Definition at line 4027 of file bnx2x_reg.h.

#define QM_REG_VOQPORT_1   0x1682a4

Definition at line 4028 of file bnx2x_reg.h.

#define QM_REG_VOQPORT_2   0x1682a8

Definition at line 4029 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_0_LSB   0x168240

Definition at line 4031 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_0_LSB_EXT_A   0x16e524

Definition at line 4033 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_0_MSB   0x168244

Definition at line 4035 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_0_MSB_EXT_A   0x16e528

Definition at line 4037 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_10_LSB   0x168290

Definition at line 4039 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_10_LSB_EXT_A   0x16e574

Definition at line 4041 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_10_MSB   0x168294

Definition at line 4043 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_10_MSB_EXT_A   0x16e578

Definition at line 4045 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_11_LSB   0x168298

Definition at line 4047 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_11_LSB_EXT_A   0x16e57c

Definition at line 4049 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_11_MSB   0x16829c

Definition at line 4051 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_11_MSB_EXT_A   0x16e580

Definition at line 4053 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_1_LSB   0x168248

Definition at line 4055 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_1_LSB_EXT_A   0x16e52c

Definition at line 4057 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_1_MSB   0x16824c

Definition at line 4059 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_1_MSB_EXT_A   0x16e530

Definition at line 4061 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_2_LSB   0x168250

Definition at line 4063 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_2_LSB_EXT_A   0x16e534

Definition at line 4065 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_2_MSB   0x168254

Definition at line 4067 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_2_MSB_EXT_A   0x16e538

Definition at line 4069 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_3_LSB   0x168258

Definition at line 4071 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_3_LSB_EXT_A   0x16e53c

Definition at line 4073 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_3_MSB_EXT_A   0x16e540

Definition at line 4075 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_4_LSB   0x168260

Definition at line 4077 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_4_LSB_EXT_A   0x16e544

Definition at line 4079 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_4_MSB   0x168264

Definition at line 4081 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_4_MSB_EXT_A   0x16e548

Definition at line 4083 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_5_LSB   0x168268

Definition at line 4085 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_5_LSB_EXT_A   0x16e54c

Definition at line 4087 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_5_MSB   0x16826c

Definition at line 4089 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_5_MSB_EXT_A   0x16e550

Definition at line 4091 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_6_LSB   0x168270

Definition at line 4093 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_6_LSB_EXT_A   0x16e554

Definition at line 4095 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_6_MSB   0x168274

Definition at line 4097 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_6_MSB_EXT_A   0x16e558

Definition at line 4099 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_7_LSB   0x168278

Definition at line 4101 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_7_LSB_EXT_A   0x16e55c

Definition at line 4103 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_7_MSB   0x16827c

Definition at line 4105 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_7_MSB_EXT_A   0x16e560

Definition at line 4107 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_8_LSB   0x168280

Definition at line 4109 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_8_LSB_EXT_A   0x16e564

Definition at line 4111 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_8_MSB   0x168284

Definition at line 4113 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_8_MSB_EXT_A   0x16e568

Definition at line 4115 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_9_LSB   0x168288

Definition at line 4117 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_9_LSB_EXT_A   0x16e56c

Definition at line 4119 of file bnx2x_reg.h.

#define QM_REG_VOQQMASK_9_MSB_EXT_A   0x16e570

Definition at line 4121 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_0   0x16880c

Definition at line 4123 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_1   0x168810

Definition at line 4124 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_10   0x168814

Definition at line 4125 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_11   0x168818

Definition at line 4126 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_12   0x16881c

Definition at line 4127 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_13   0x168820

Definition at line 4128 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_14   0x168824

Definition at line 4129 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_15   0x168828

Definition at line 4130 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_16   0x16e000

Definition at line 4131 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_17   0x16e004

Definition at line 4132 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_18   0x16e008

Definition at line 4133 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_19   0x16e00c

Definition at line 4134 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_2   0x16882c

Definition at line 4135 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_20   0x16e010

Definition at line 4136 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_21   0x16e014

Definition at line 4137 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_22   0x16e018

Definition at line 4138 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_23   0x16e01c

Definition at line 4139 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_24   0x16e020

Definition at line 4140 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_25   0x16e024

Definition at line 4141 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_26   0x16e028

Definition at line 4142 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_27   0x16e02c

Definition at line 4143 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_28   0x16e030

Definition at line 4144 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_29   0x16e034

Definition at line 4145 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_3   0x168830

Definition at line 4146 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_30   0x16e038

Definition at line 4147 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_31   0x16e03c

Definition at line 4148 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_4   0x168834

Definition at line 4149 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_5   0x168838

Definition at line 4150 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_6   0x16883c

Definition at line 4151 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_7   0x168840

Definition at line 4152 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_8   0x168844

Definition at line 4153 of file bnx2x_reg.h.

#define QM_REG_WRRWEIGHTS_9   0x168848

Definition at line 4154 of file bnx2x_reg.h.

#define QM_REG_XQM_WRC_FIFOLVL   0x168000

Definition at line 4156 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_0   0

Definition at line 6005 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_10   10

Definition at line 6014 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_11   11

Definition at line 6015 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_12   12

Definition at line 6016 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_13   13

Definition at line 6017 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_14   14

Definition at line 6018 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_15   15

Definition at line 6019 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_16   16

Definition at line 6020 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_17   17

Definition at line 6021 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_18   18

Definition at line 6022 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_19   19

Definition at line 6023 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_20   20

Definition at line 6024 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_21   21

Definition at line 6025 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_6   6

Definition at line 6010 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_7   7

Definition at line 6011 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_8   8

Definition at line 6012 of file bnx2x_reg.h.

#define RESERVED_GENERAL_ATTENTION_BIT_9   9

Definition at line 6013 of file bnx2x_reg.h.

#define SEM_FAST_REG_PARITY_RST   0x18840

Definition at line 4158 of file bnx2x_reg.h.

#define SRC_REG_COUNTFREE0   0x40500

Definition at line 4159 of file bnx2x_reg.h.

#define SRC_REG_E1HMF_ENABLE   0x404cc

Definition at line 4162 of file bnx2x_reg.h.

#define SRC_REG_FIRSTFREE0   0x40510

Definition at line 4163 of file bnx2x_reg.h.

#define SRC_REG_KEYRSS0_0   0x40408

Definition at line 4164 of file bnx2x_reg.h.

#define SRC_REG_KEYRSS0_7   0x40424

Definition at line 4165 of file bnx2x_reg.h.

#define SRC_REG_KEYRSS1_9   0x40454

Definition at line 4166 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_0   0x40458

Definition at line 4167 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_1   0x4045c

Definition at line 4168 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_2   0x40460

Definition at line 4169 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_3   0x40464

Definition at line 4170 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_4   0x40468

Definition at line 4171 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_5   0x4046c

Definition at line 4172 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_6   0x40470

Definition at line 4173 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_7   0x40474

Definition at line 4174 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_8   0x40478

Definition at line 4175 of file bnx2x_reg.h.

#define SRC_REG_KEYSEARCH_9   0x4047c

Definition at line 4176 of file bnx2x_reg.h.

#define SRC_REG_LASTFREE0   0x40530

Definition at line 4177 of file bnx2x_reg.h.

#define SRC_REG_NUMBER_HASH_BITS0   0x40400

Definition at line 4178 of file bnx2x_reg.h.

#define SRC_REG_SOFT_RST   0x4049c

Definition at line 4180 of file bnx2x_reg.h.

#define SRC_REG_SRC_INT_STS   0x404ac

Definition at line 4182 of file bnx2x_reg.h.

#define SRC_REG_SRC_PRTY_MASK   0x404c8

Definition at line 4184 of file bnx2x_reg.h.

#define SRC_REG_SRC_PRTY_STS   0x404bc

Definition at line 4186 of file bnx2x_reg.h.

#define SRC_REG_SRC_PRTY_STS_CLR   0x404c0

Definition at line 4188 of file bnx2x_reg.h.

#define TCM_REG_CAM_OCCUP   0x5017c

Definition at line 4190 of file bnx2x_reg.h.

#define TCM_REG_CDU_AG_RD_IFEN   0x50034

Definition at line 4194 of file bnx2x_reg.h.

#define TCM_REG_CDU_AG_WR_IFEN   0x50030

Definition at line 4198 of file bnx2x_reg.h.

#define TCM_REG_CDU_SM_RD_IFEN   0x5003c

Definition at line 4202 of file bnx2x_reg.h.

#define TCM_REG_CDU_SM_WR_IFEN   0x50038

Definition at line 4206 of file bnx2x_reg.h.

#define TCM_REG_CFC_INIT_CRD   0x50204

Definition at line 4210 of file bnx2x_reg.h.

#define TCM_REG_CP_WEIGHT   0x500c0

Definition at line 4214 of file bnx2x_reg.h.

#define TCM_REG_CSEM_IFEN   0x5002c

Definition at line 4218 of file bnx2x_reg.h.

#define TCM_REG_CSEM_LENGTH_MIS   0x50174

Definition at line 4221 of file bnx2x_reg.h.

#define TCM_REG_CSEM_WEIGHT   0x500bc

Definition at line 4225 of file bnx2x_reg.h.

#define TCM_REG_ERR_EVNT_ID   0x500a0

Definition at line 4227 of file bnx2x_reg.h.

#define TCM_REG_ERR_TCM_HDR   0x5009c

Definition at line 4229 of file bnx2x_reg.h.

#define TCM_REG_EXPR_EVNT_ID   0x500a4

Definition at line 4231 of file bnx2x_reg.h.

#define TCM_REG_FIC0_INIT_CRD   0x5020c

Definition at line 4235 of file bnx2x_reg.h.

#define TCM_REG_FIC1_INIT_CRD   0x50210

Definition at line 4239 of file bnx2x_reg.h.

#define TCM_REG_GR_ARB_TYPE   0x50114

Definition at line 4244 of file bnx2x_reg.h.

#define TCM_REG_GR_LD0_PR   0x5011c

Definition at line 4248 of file bnx2x_reg.h.

#define TCM_REG_GR_LD1_PR   0x50120

Definition at line 4252 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_0   0x50050

Definition at line 4258 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_1   0x50054

Definition at line 4259 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_2   0x50058

Definition at line 4260 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_3   0x5005c

Definition at line 4261 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_4   0x50060

Definition at line 4262 of file bnx2x_reg.h.

#define TCM_REG_N_SM_CTX_LD_5   0x50064

Definition at line 4263 of file bnx2x_reg.h.

#define TCM_REG_PBF_IFEN   0x50024

Definition at line 4267 of file bnx2x_reg.h.

#define TCM_REG_PBF_LENGTH_MIS   0x5016c

Definition at line 4270 of file bnx2x_reg.h.

#define TCM_REG_PBF_WEIGHT   0x500b4

Definition at line 4274 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM0_0   0x500e0

Definition at line 4275 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM0_1   0x500e4

Definition at line 4276 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM1_0   0x500e8

Definition at line 4277 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM1_1   0x500ec

Definition at line 4278 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM2_0   0x500f0

Definition at line 4279 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM2_1   0x500f4

Definition at line 4280 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM3_0   0x500f8

Definition at line 4281 of file bnx2x_reg.h.

#define TCM_REG_PHYS_QNUM3_1   0x500fc

Definition at line 4282 of file bnx2x_reg.h.

#define TCM_REG_PRS_IFEN   0x50020

Definition at line 4286 of file bnx2x_reg.h.

#define TCM_REG_PRS_LENGTH_MIS   0x50168

Definition at line 4289 of file bnx2x_reg.h.

#define TCM_REG_PRS_WEIGHT   0x500b0

Definition at line 4293 of file bnx2x_reg.h.

#define TCM_REG_STOP_EVNT_ID   0x500a8

Definition at line 4295 of file bnx2x_reg.h.

#define TCM_REG_STORM_LENGTH_MIS   0x50160

Definition at line 4298 of file bnx2x_reg.h.

#define TCM_REG_STORM_TCM_IFEN   0x50010

Definition at line 4302 of file bnx2x_reg.h.

#define TCM_REG_STORM_WEIGHT   0x500ac

Definition at line 4306 of file bnx2x_reg.h.

#define TCM_REG_TCM_CFC_IFEN   0x50040

Definition at line 4310 of file bnx2x_reg.h.

#define TCM_REG_TCM_INT_MASK   0x501dc

Definition at line 4312 of file bnx2x_reg.h.

#define TCM_REG_TCM_INT_STS   0x501d0

Definition at line 4314 of file bnx2x_reg.h.

#define TCM_REG_TCM_PRTY_MASK   0x501ec

Definition at line 4316 of file bnx2x_reg.h.

#define TCM_REG_TCM_PRTY_STS   0x501e0

Definition at line 4318 of file bnx2x_reg.h.

#define TCM_REG_TCM_PRTY_STS_CLR   0x501e4

Definition at line 4320 of file bnx2x_reg.h.

#define TCM_REG_TCM_REG0_SZ   0x500d8

Definition at line 4325 of file bnx2x_reg.h.

#define TCM_REG_TCM_STORM0_IFEN   0x50004

Definition at line 4329 of file bnx2x_reg.h.

#define TCM_REG_TCM_STORM1_IFEN   0x50008

Definition at line 4333 of file bnx2x_reg.h.

#define TCM_REG_TCM_TQM_IFEN   0x5000c

Definition at line 4337 of file bnx2x_reg.h.

#define TCM_REG_TCM_TQM_USE_Q   0x500d4

Definition at line 4339 of file bnx2x_reg.h.

#define TCM_REG_TM_TCM_HDR   0x50098

Definition at line 4341 of file bnx2x_reg.h.

#define TCM_REG_TM_TCM_IFEN   0x5001c

Definition at line 4345 of file bnx2x_reg.h.

#define TCM_REG_TM_WEIGHT   0x500d0

Definition at line 4349 of file bnx2x_reg.h.

#define TCM_REG_TQM_INIT_CRD   0x5021c

Definition at line 4353 of file bnx2x_reg.h.

#define TCM_REG_TQM_P_WEIGHT   0x500c8

Definition at line 4357 of file bnx2x_reg.h.

#define TCM_REG_TQM_S_WEIGHT   0x500cc

Definition at line 4361 of file bnx2x_reg.h.

#define TCM_REG_TQM_TCM_HDR_P   0x50090

Definition at line 4363 of file bnx2x_reg.h.

#define TCM_REG_TQM_TCM_HDR_S   0x50094

Definition at line 4365 of file bnx2x_reg.h.

#define TCM_REG_TQM_TCM_IFEN   0x50014

Definition at line 4369 of file bnx2x_reg.h.

#define TCM_REG_TSDM_IFEN   0x50018

Definition at line 4373 of file bnx2x_reg.h.

#define TCM_REG_TSDM_LENGTH_MIS   0x50164

Definition at line 4376 of file bnx2x_reg.h.

#define TCM_REG_TSDM_WEIGHT   0x500c4

Definition at line 4380 of file bnx2x_reg.h.

#define TCM_REG_USEM_IFEN   0x50028

Definition at line 4384 of file bnx2x_reg.h.

#define TCM_REG_USEM_LENGTH_MIS   0x50170

Definition at line 4387 of file bnx2x_reg.h.

#define TCM_REG_USEM_WEIGHT   0x500b8

Definition at line 4391 of file bnx2x_reg.h.

#define TCM_REG_XX_DESCR_TABLE   0x50280

Definition at line 4395 of file bnx2x_reg.h.

#define TCM_REG_XX_DESCR_TABLE_SIZE   29

Definition at line 4396 of file bnx2x_reg.h.

#define TCM_REG_XX_FREE   0x50178

Definition at line 4398 of file bnx2x_reg.h.

#define TCM_REG_XX_INIT_CRD   0x50220

Definition at line 4404 of file bnx2x_reg.h.

#define TCM_REG_XX_MAX_LL_SZ   0x50044

Definition at line 4407 of file bnx2x_reg.h.

#define TCM_REG_XX_MSG_NUM   0x50224

Definition at line 4410 of file bnx2x_reg.h.

#define TCM_REG_XX_OVFL_EVNT_ID   0x50048

Definition at line 4412 of file bnx2x_reg.h.

#define TCM_REG_XX_TABLE   0x50240

Definition at line 4416 of file bnx2x_reg.h.

#define TM_REG_CFC_AC_CRDCNT_VAL   0x164208

Definition at line 4418 of file bnx2x_reg.h.

#define TM_REG_CFC_CLD_CRDCNT_VAL   0x164210

Definition at line 4420 of file bnx2x_reg.h.

#define TM_REG_CL0_CONT_REGION   0x164030

Definition at line 4422 of file bnx2x_reg.h.

#define TM_REG_CL1_CONT_REGION   0x164034

Definition at line 4424 of file bnx2x_reg.h.

#define TM_REG_CL2_CONT_REGION   0x164038

Definition at line 4426 of file bnx2x_reg.h.

#define TM_REG_CLIN_PRIOR0_CLIENT   0x164024

Definition at line 4428 of file bnx2x_reg.h.

#define TM_REG_CLOUT_CRDCNT0_VAL   0x164220

Definition at line 4430 of file bnx2x_reg.h.

#define TM_REG_CLOUT_CRDCNT1_VAL   0x164228

Definition at line 4432 of file bnx2x_reg.h.

#define TM_REG_CLOUT_CRDCNT2_VAL   0x164230

Definition at line 4434 of file bnx2x_reg.h.

#define TM_REG_EN_CL0_INPUT   0x164008

Definition at line 4436 of file bnx2x_reg.h.

#define TM_REG_EN_CL1_INPUT   0x16400c

Definition at line 4438 of file bnx2x_reg.h.

#define TM_REG_EN_CL2_INPUT   0x164010

Definition at line 4440 of file bnx2x_reg.h.

#define TM_REG_EN_LINEAR0_TIMER   0x164014

Definition at line 4441 of file bnx2x_reg.h.

#define TM_REG_EN_REAL_TIME_CNT   0x1640d8

Definition at line 4443 of file bnx2x_reg.h.

#define TM_REG_EN_TIMERS   0x164000

Definition at line 4445 of file bnx2x_reg.h.

#define TM_REG_EXP_CRDCNT_VAL   0x164238

Definition at line 4448 of file bnx2x_reg.h.

#define TM_REG_LIN0_LOGIC_ADDR   0x164240

Definition at line 4450 of file bnx2x_reg.h.

#define TM_REG_LIN0_MAX_ACTIVE_CID   0x164048

Definition at line 4452 of file bnx2x_reg.h.

#define TM_REG_LIN0_NUM_SCANS   0x1640a0

Definition at line 4454 of file bnx2x_reg.h.

#define TM_REG_LIN0_PHY_ADDR   0x164270

Definition at line 4456 of file bnx2x_reg.h.

#define TM_REG_LIN0_PHY_ADDR_VALID   0x164248

Definition at line 4458 of file bnx2x_reg.h.

#define TM_REG_LIN0_SCAN_ON   0x1640d0

Definition at line 4459 of file bnx2x_reg.h.

#define TM_REG_LIN0_SCAN_TIME   0x16403c

Definition at line 4461 of file bnx2x_reg.h.

#define TM_REG_LIN0_VNIC_UC   0x164128

Definition at line 4462 of file bnx2x_reg.h.

#define TM_REG_LIN1_LOGIC_ADDR   0x164250

Definition at line 4464 of file bnx2x_reg.h.

#define TM_REG_LIN1_PHY_ADDR   0x164280

Definition at line 4466 of file bnx2x_reg.h.

#define TM_REG_LIN1_PHY_ADDR_VALID   0x164258

Definition at line 4468 of file bnx2x_reg.h.

#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR   0x164070

Definition at line 4470 of file bnx2x_reg.h.

#define TM_REG_PCIARB_CRDCNT_VAL   0x164260

Definition at line 4472 of file bnx2x_reg.h.

#define TM_REG_TIMER_TICK_SIZE   0x16401c

Definition at line 4474 of file bnx2x_reg.h.

#define TM_REG_TM_CONTEXT_REGION   0x164044

Definition at line 4476 of file bnx2x_reg.h.

#define TM_REG_TM_INT_MASK   0x1640fc

Definition at line 4478 of file bnx2x_reg.h.

#define TM_REG_TM_INT_STS   0x1640f0

Definition at line 4480 of file bnx2x_reg.h.

#define TM_REG_TM_PRTY_MASK   0x16410c

Definition at line 4482 of file bnx2x_reg.h.

#define TM_REG_TM_PRTY_STS_CLR   0x164104

Definition at line 4484 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_EVENT_0   0x42038

Definition at line 4486 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_EVENT_1   0x4203c

Definition at line 4487 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_EVENT_2   0x42040

Definition at line 4488 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_EVENT_3   0x42044

Definition at line 4489 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_EVENT_4   0x42048

Definition at line 4490 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_T_0   0x420b8

Definition at line 4492 of file bnx2x_reg.h.

#define TSDM_REG_AGG_INT_T_1   0x420bc

Definition at line 4493 of file bnx2x_reg.h.

#define TSDM_REG_CFC_RSP_START_ADDR   0x42008

Definition at line 4495 of file bnx2x_reg.h.

#define TSDM_REG_CMP_COUNTER_MAX0   0x4201c

Definition at line 4497 of file bnx2x_reg.h.

#define TSDM_REG_CMP_COUNTER_MAX1   0x42020

Definition at line 4499 of file bnx2x_reg.h.

#define TSDM_REG_CMP_COUNTER_MAX2   0x42024

Definition at line 4501 of file bnx2x_reg.h.

#define TSDM_REG_CMP_COUNTER_MAX3   0x42028

Definition at line 4503 of file bnx2x_reg.h.

#define TSDM_REG_CMP_COUNTER_START_ADDR   0x4200c

Definition at line 4506 of file bnx2x_reg.h.

#define TSDM_REG_ENABLE_IN1   0x42238

Definition at line 4507 of file bnx2x_reg.h.

#define TSDM_REG_ENABLE_IN2   0x4223c

Definition at line 4508 of file bnx2x_reg.h.

#define TSDM_REG_ENABLE_OUT1   0x42240

Definition at line 4509 of file bnx2x_reg.h.

#define TSDM_REG_ENABLE_OUT2   0x42244

Definition at line 4510 of file bnx2x_reg.h.

#define TSDM_REG_INIT_CREDIT_PXP_CTRL   0x424bc

Definition at line 4513 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE   0x4227c

Definition at line 4515 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_PKT_END_MSG   0x42274

Definition at line 4517 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ   0x42278

Definition at line 4519 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q0_CMD   0x42248

Definition at line 4521 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q10_CMD   0x4226c

Definition at line 4523 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q11_CMD   0x42270

Definition at line 4525 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q1_CMD   0x4224c

Definition at line 4527 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q3_CMD   0x42250

Definition at line 4529 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q4_CMD   0x42254

Definition at line 4531 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q5_CMD   0x42258

Definition at line 4533 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q6_CMD   0x4225c

Definition at line 4535 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q7_CMD   0x42260

Definition at line 4537 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q8_CMD   0x42264

Definition at line 4539 of file bnx2x_reg.h.

#define TSDM_REG_NUM_OF_Q9_CMD   0x42268

Definition at line 4541 of file bnx2x_reg.h.

#define TSDM_REG_PCK_END_MSG_START_ADDR   0x42014

Definition at line 4543 of file bnx2x_reg.h.

#define TSDM_REG_Q_COUNTER_START_ADDR   0x42010

Definition at line 4545 of file bnx2x_reg.h.

#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0x42548

Definition at line 4547 of file bnx2x_reg.h.

#define TSDM_REG_SYNC_PARSER_EMPTY   0x42550

Definition at line 4549 of file bnx2x_reg.h.

#define TSDM_REG_SYNC_SYNC_EMPTY   0x42558

Definition at line 4551 of file bnx2x_reg.h.

#define TSDM_REG_TIMER_TICK   0x42000

Definition at line 4554 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_INT_MASK_0   0x4229c

Definition at line 4556 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_INT_MASK_1   0x422ac

Definition at line 4557 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_INT_STS_0   0x42290

Definition at line 4559 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_INT_STS_1   0x422a0

Definition at line 4560 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_PRTY_MASK   0x422bc

Definition at line 4562 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_PRTY_STS   0x422b0

Definition at line 4564 of file bnx2x_reg.h.

#define TSDM_REG_TSDM_PRTY_STS_CLR   0x422b4

Definition at line 4566 of file bnx2x_reg.h.

#define TSEM_REG_ARB_CYCLE_SIZE   0x180034

Definition at line 4568 of file bnx2x_reg.h.

#define TSEM_REG_ARB_ELEMENT0   0x180020

Definition at line 4572 of file bnx2x_reg.h.

#define TSEM_REG_ARB_ELEMENT1   0x180024

Definition at line 4577 of file bnx2x_reg.h.

#define TSEM_REG_ARB_ELEMENT2   0x180028

Definition at line 4583 of file bnx2x_reg.h.

#define TSEM_REG_ARB_ELEMENT3   0x18002c

Definition at line 4590 of file bnx2x_reg.h.

#define TSEM_REG_ARB_ELEMENT4   0x180030

Definition at line 4598 of file bnx2x_reg.h.

#define TSEM_REG_ENABLE_IN   0x1800a4

Definition at line 4599 of file bnx2x_reg.h.

#define TSEM_REG_ENABLE_OUT   0x1800a8

Definition at line 4600 of file bnx2x_reg.h.

#define TSEM_REG_FAST_MEMORY   0x1a0000

Definition at line 4605 of file bnx2x_reg.h.

#define TSEM_REG_FIC0_DISABLE   0x180224

Definition at line 4608 of file bnx2x_reg.h.

#define TSEM_REG_FIC1_DISABLE   0x180234

Definition at line 4611 of file bnx2x_reg.h.

#define TSEM_REG_INT_TABLE   0x180400

Definition at line 4614 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FIC0   0x180000

Definition at line 4617 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FIC1   0x180004

Definition at line 4620 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FOC0   0x180008

Definition at line 4623 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FOC1   0x18000c

Definition at line 4626 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FOC2   0x180010

Definition at line 4629 of file bnx2x_reg.h.

#define TSEM_REG_MSG_NUM_FOC3   0x180014

Definition at line 4632 of file bnx2x_reg.h.

#define TSEM_REG_PAS_DISABLE   0x18024c

Definition at line 4635 of file bnx2x_reg.h.

#define TSEM_REG_PASSIVE_BUFFER   0x181000

Definition at line 4637 of file bnx2x_reg.h.

#define TSEM_REG_PRAM   0x1c0000

Definition at line 4639 of file bnx2x_reg.h.

#define TSEM_REG_SLEEP_THREADS_VALID   0x18026c

Definition at line 4641 of file bnx2x_reg.h.

#define TSEM_REG_SLOW_EXT_STORE_EMPTY   0x1802a0

Definition at line 4643 of file bnx2x_reg.h.

#define TSEM_REG_THREADS_LIST   0x1802e4

Definition at line 4645 of file bnx2x_reg.h.

#define TSEM_REG_TS_0_AS   0x180038

Definition at line 4650 of file bnx2x_reg.h.

#define TSEM_REG_TS_10_AS   0x180060

Definition at line 4652 of file bnx2x_reg.h.

#define TSEM_REG_TS_11_AS   0x180064

Definition at line 4654 of file bnx2x_reg.h.

#define TSEM_REG_TS_12_AS   0x180068

Definition at line 4656 of file bnx2x_reg.h.

#define TSEM_REG_TS_13_AS   0x18006c

Definition at line 4658 of file bnx2x_reg.h.

#define TSEM_REG_TS_14_AS   0x180070

Definition at line 4660 of file bnx2x_reg.h.

#define TSEM_REG_TS_15_AS   0x180074

Definition at line 4662 of file bnx2x_reg.h.

#define TSEM_REG_TS_16_AS   0x180078

Definition at line 4664 of file bnx2x_reg.h.

#define TSEM_REG_TS_17_AS   0x18007c

Definition at line 4666 of file bnx2x_reg.h.

#define TSEM_REG_TS_18_AS   0x180080

Definition at line 4668 of file bnx2x_reg.h.

#define TSEM_REG_TS_1_AS   0x18003c

Definition at line 4670 of file bnx2x_reg.h.

#define TSEM_REG_TS_2_AS   0x180040

Definition at line 4672 of file bnx2x_reg.h.

#define TSEM_REG_TS_3_AS   0x180044

Definition at line 4674 of file bnx2x_reg.h.

#define TSEM_REG_TS_4_AS   0x180048

Definition at line 4676 of file bnx2x_reg.h.

#define TSEM_REG_TS_5_AS   0x18004c

Definition at line 4678 of file bnx2x_reg.h.

#define TSEM_REG_TS_6_AS   0x180050

Definition at line 4680 of file bnx2x_reg.h.

#define TSEM_REG_TS_7_AS   0x180054

Definition at line 4682 of file bnx2x_reg.h.

#define TSEM_REG_TS_8_AS   0x180058

Definition at line 4684 of file bnx2x_reg.h.

#define TSEM_REG_TS_9_AS   0x18005c

Definition at line 4686 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_INT_MASK_0   0x180100

Definition at line 4688 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_INT_MASK_1   0x180110

Definition at line 4689 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_INT_STS_0   0x1800f4

Definition at line 4691 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_INT_STS_1   0x180104

Definition at line 4692 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_MASK_0   0x180120

Definition at line 4694 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_MASK_1   0x180130

Definition at line 4695 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_STS_0   0x180114

Definition at line 4697 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_STS_1   0x180124

Definition at line 4698 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_STS_CLR_0   0x180118

Definition at line 4647 of file bnx2x_reg.h.

#define TSEM_REG_TSEM_PRTY_STS_CLR_1   0x180128

Definition at line 4648 of file bnx2x_reg.h.

#define TSEM_REG_VFPF_ERR_NUM   0x180380

Definition at line 4701 of file bnx2x_reg.h.

#define TSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_7

Definition at line 6028 of file bnx2x_reg.h.

#define UCM_REG_AG_CTX   0xe2000

Definition at line 4706 of file bnx2x_reg.h.

#define UCM_REG_CAM_OCCUP   0xe0170

Definition at line 4708 of file bnx2x_reg.h.

#define UCM_REG_CDU_AG_RD_IFEN   0xe0038

Definition at line 4712 of file bnx2x_reg.h.

#define UCM_REG_CDU_AG_WR_IFEN   0xe0034

Definition at line 4716 of file bnx2x_reg.h.

#define UCM_REG_CDU_SM_RD_IFEN   0xe0040

Definition at line 4720 of file bnx2x_reg.h.

#define UCM_REG_CDU_SM_WR_IFEN   0xe003c

Definition at line 4724 of file bnx2x_reg.h.

#define UCM_REG_CFC_INIT_CRD   0xe0204

Definition at line 4728 of file bnx2x_reg.h.

#define UCM_REG_CP_WEIGHT   0xe00c4

Definition at line 4732 of file bnx2x_reg.h.

#define UCM_REG_CSEM_IFEN   0xe0028

Definition at line 4736 of file bnx2x_reg.h.

#define UCM_REG_CSEM_LENGTH_MIS   0xe0160

Definition at line 4739 of file bnx2x_reg.h.

#define UCM_REG_CSEM_WEIGHT   0xe00b8

Definition at line 4743 of file bnx2x_reg.h.

#define UCM_REG_DORQ_IFEN   0xe0030

Definition at line 4747 of file bnx2x_reg.h.

#define UCM_REG_DORQ_LENGTH_MIS   0xe0168

Definition at line 4750 of file bnx2x_reg.h.

#define UCM_REG_DORQ_WEIGHT   0xe00c0

Definition at line 4754 of file bnx2x_reg.h.

#define UCM_REG_ERR_EVNT_ID   0xe00a4

Definition at line 4756 of file bnx2x_reg.h.

#define UCM_REG_ERR_UCM_HDR   0xe00a0

Definition at line 4758 of file bnx2x_reg.h.

#define UCM_REG_EXPR_EVNT_ID   0xe00a8

Definition at line 4760 of file bnx2x_reg.h.

#define UCM_REG_FIC0_INIT_CRD   0xe020c

Definition at line 4764 of file bnx2x_reg.h.

#define UCM_REG_FIC1_INIT_CRD   0xe0210

Definition at line 4768 of file bnx2x_reg.h.

#define UCM_REG_GR_ARB_TYPE   0xe0144

Definition at line 4773 of file bnx2x_reg.h.

#define UCM_REG_GR_LD0_PR   0xe014c

Definition at line 4777 of file bnx2x_reg.h.

#define UCM_REG_GR_LD1_PR   0xe0150

Definition at line 4781 of file bnx2x_reg.h.

#define UCM_REG_INV_CFLG_Q   0xe00e4

Definition at line 4783 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_0   0xe0054

Definition at line 4789 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_1   0xe0058

Definition at line 4790 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_2   0xe005c

Definition at line 4791 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_3   0xe0060

Definition at line 4792 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_4   0xe0064

Definition at line 4793 of file bnx2x_reg.h.

#define UCM_REG_N_SM_CTX_LD_5   0xe0068

Definition at line 4794 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM0_0   0xe0110

Definition at line 4795 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM0_1   0xe0114

Definition at line 4796 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM1_0   0xe0118

Definition at line 4797 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM1_1   0xe011c

Definition at line 4798 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM2_0   0xe0120

Definition at line 4799 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM2_1   0xe0124

Definition at line 4800 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM3_0   0xe0128

Definition at line 4801 of file bnx2x_reg.h.

#define UCM_REG_PHYS_QNUM3_1   0xe012c

Definition at line 4802 of file bnx2x_reg.h.

#define UCM_REG_STOP_EVNT_ID   0xe00ac

Definition at line 4804 of file bnx2x_reg.h.

#define UCM_REG_STORM_LENGTH_MIS   0xe0154

Definition at line 4807 of file bnx2x_reg.h.

#define UCM_REG_STORM_UCM_IFEN   0xe0010

Definition at line 4811 of file bnx2x_reg.h.

#define UCM_REG_STORM_WEIGHT   0xe00b0

Definition at line 4815 of file bnx2x_reg.h.

#define UCM_REG_TM_INIT_CRD   0xe021c

Definition at line 4819 of file bnx2x_reg.h.

#define UCM_REG_TM_UCM_HDR   0xe009c

Definition at line 4821 of file bnx2x_reg.h.

#define UCM_REG_TM_UCM_IFEN   0xe001c

Definition at line 4825 of file bnx2x_reg.h.

#define UCM_REG_TM_WEIGHT   0xe00d4

Definition at line 4829 of file bnx2x_reg.h.

#define UCM_REG_TSEM_IFEN   0xe0024

Definition at line 4833 of file bnx2x_reg.h.

#define UCM_REG_TSEM_LENGTH_MIS   0xe015c

Definition at line 4836 of file bnx2x_reg.h.

#define UCM_REG_TSEM_WEIGHT   0xe00b4

Definition at line 4840 of file bnx2x_reg.h.

#define UCM_REG_UCM_CFC_IFEN   0xe0044

Definition at line 4844 of file bnx2x_reg.h.

#define UCM_REG_UCM_INT_MASK   0xe01d4

Definition at line 4846 of file bnx2x_reg.h.

#define UCM_REG_UCM_INT_STS   0xe01c8

Definition at line 4848 of file bnx2x_reg.h.

#define UCM_REG_UCM_PRTY_MASK   0xe01e4

Definition at line 4850 of file bnx2x_reg.h.

#define UCM_REG_UCM_PRTY_STS   0xe01d8

Definition at line 4852 of file bnx2x_reg.h.

#define UCM_REG_UCM_PRTY_STS_CLR   0xe01dc

Definition at line 4854 of file bnx2x_reg.h.

#define UCM_REG_UCM_REG0_SZ   0xe00dc

Definition at line 4859 of file bnx2x_reg.h.

#define UCM_REG_UCM_STORM0_IFEN   0xe0004

Definition at line 4863 of file bnx2x_reg.h.

#define UCM_REG_UCM_STORM1_IFEN   0xe0008

Definition at line 4867 of file bnx2x_reg.h.

#define UCM_REG_UCM_TM_IFEN   0xe0020

Definition at line 4871 of file bnx2x_reg.h.

#define UCM_REG_UCM_UQM_IFEN   0xe000c

Definition at line 4875 of file bnx2x_reg.h.

#define UCM_REG_UCM_UQM_USE_Q   0xe00d8

Definition at line 4877 of file bnx2x_reg.h.

#define UCM_REG_UQM_INIT_CRD   0xe0220

Definition at line 4881 of file bnx2x_reg.h.

#define UCM_REG_UQM_P_WEIGHT   0xe00cc

Definition at line 4885 of file bnx2x_reg.h.

#define UCM_REG_UQM_S_WEIGHT   0xe00d0

Definition at line 4889 of file bnx2x_reg.h.

#define UCM_REG_UQM_UCM_HDR_P   0xe0094

Definition at line 4891 of file bnx2x_reg.h.

#define UCM_REG_UQM_UCM_HDR_S   0xe0098

Definition at line 4893 of file bnx2x_reg.h.

#define UCM_REG_UQM_UCM_IFEN   0xe0014

Definition at line 4897 of file bnx2x_reg.h.

#define UCM_REG_USDM_IFEN   0xe0018

Definition at line 4901 of file bnx2x_reg.h.

#define UCM_REG_USDM_LENGTH_MIS   0xe0158

Definition at line 4904 of file bnx2x_reg.h.

#define UCM_REG_USDM_WEIGHT   0xe00c8

Definition at line 4908 of file bnx2x_reg.h.

#define UCM_REG_XSEM_IFEN   0xe002c

Definition at line 4912 of file bnx2x_reg.h.

#define UCM_REG_XSEM_LENGTH_MIS   0xe0164

Definition at line 4915 of file bnx2x_reg.h.

#define UCM_REG_XSEM_WEIGHT   0xe00bc

Definition at line 4919 of file bnx2x_reg.h.

#define UCM_REG_XX_DESCR_TABLE   0xe0280

Definition at line 4923 of file bnx2x_reg.h.

#define UCM_REG_XX_DESCR_TABLE_SIZE   27

Definition at line 4924 of file bnx2x_reg.h.

#define UCM_REG_XX_FREE   0xe016c

Definition at line 4926 of file bnx2x_reg.h.

#define UCM_REG_XX_INIT_CRD   0xe0224

Definition at line 4931 of file bnx2x_reg.h.

#define UCM_REG_XX_MSG_NUM   0xe0228

Definition at line 4934 of file bnx2x_reg.h.

#define UCM_REG_XX_OVFL_EVNT_ID   0xe004c

Definition at line 4936 of file bnx2x_reg.h.

#define UCM_REG_XX_TABLE   0xe0300

Definition at line 4940 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_HD_ENA   (0x1<<10)

Definition at line 4941 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE   (0x1<<28)

Definition at line 4942 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA   (0x1<<15)

Definition at line 4943 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK   (0x1<<24)

Definition at line 4944 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_PAD_EN   (0x1<<5)

Definition at line 4945 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE   (0x1<<8)

Definition at line 4946 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN   (0x1<<4)

Definition at line 4947 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_RX_ENA   (0x1<<1)

Definition at line 4948 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_SW_RESET   (0x1<<13)

Definition at line 4949 of file bnx2x_reg.h.

#define UMAC_COMMAND_CONFIG_REG_TX_ENA   (0x1<<0)

Definition at line 4950 of file bnx2x_reg.h.

#define UMAC_REG_COMMAND_CONFIG   0x8

Definition at line 4951 of file bnx2x_reg.h.

#define UMAC_REG_EEE_WAKE_TIMER   0x6c

Definition at line 4955 of file bnx2x_reg.h.

#define UMAC_REG_MAC_ADDR0   0xc

Definition at line 4958 of file bnx2x_reg.h.

#define UMAC_REG_MAC_ADDR1   0x10

Definition at line 4961 of file bnx2x_reg.h.

#define UMAC_REG_MAXFR   0x14

Definition at line 4964 of file bnx2x_reg.h.

#define UMAC_REG_UMAC_EEE_CTRL   0x64

Definition at line 4965 of file bnx2x_reg.h.

#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN   (0x1<<3)

Definition at line 4966 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_0   0xc4038

Definition at line 4968 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_1   0xc403c

Definition at line 4969 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_2   0xc4040

Definition at line 4970 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_4   0xc4048

Definition at line 4971 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_5   0xc404c

Definition at line 4972 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_EVENT_6   0xc4050

Definition at line 4973 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_MODE_0   0xc41b8

Definition at line 4976 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_MODE_1   0xc41bc

Definition at line 4977 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_MODE_4   0xc41c8

Definition at line 4978 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_MODE_5   0xc41cc

Definition at line 4979 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_MODE_6   0xc41d0

Definition at line 4980 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_T_5   0xc40cc

Definition at line 4982 of file bnx2x_reg.h.

#define USDM_REG_AGG_INT_T_6   0xc40d0

Definition at line 4983 of file bnx2x_reg.h.

#define USDM_REG_CFC_RSP_START_ADDR   0xc4008

Definition at line 4985 of file bnx2x_reg.h.

#define USDM_REG_CMP_COUNTER_MAX0   0xc401c

Definition at line 4987 of file bnx2x_reg.h.

#define USDM_REG_CMP_COUNTER_MAX1   0xc4020

Definition at line 4989 of file bnx2x_reg.h.

#define USDM_REG_CMP_COUNTER_MAX2   0xc4024

Definition at line 4991 of file bnx2x_reg.h.

#define USDM_REG_CMP_COUNTER_MAX3   0xc4028

Definition at line 4993 of file bnx2x_reg.h.

#define USDM_REG_CMP_COUNTER_START_ADDR   0xc400c

Definition at line 4996 of file bnx2x_reg.h.

#define USDM_REG_ENABLE_IN1   0xc4238

Definition at line 4997 of file bnx2x_reg.h.

#define USDM_REG_ENABLE_IN2   0xc423c

Definition at line 4998 of file bnx2x_reg.h.

#define USDM_REG_ENABLE_OUT1   0xc4240

Definition at line 4999 of file bnx2x_reg.h.

#define USDM_REG_ENABLE_OUT2   0xc4244

Definition at line 5000 of file bnx2x_reg.h.

#define USDM_REG_INIT_CREDIT_PXP_CTRL   0xc44c0

Definition at line 5003 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_ACK_AFTER_PLACE   0xc4280

Definition at line 5005 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_PKT_END_MSG   0xc4278

Definition at line 5007 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_PXP_ASYNC_REQ   0xc427c

Definition at line 5009 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q0_CMD   0xc4248

Definition at line 5011 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q10_CMD   0xc4270

Definition at line 5013 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q11_CMD   0xc4274

Definition at line 5015 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q1_CMD   0xc424c

Definition at line 5017 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q2_CMD   0xc4250

Definition at line 5019 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q3_CMD   0xc4254

Definition at line 5021 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q4_CMD   0xc4258

Definition at line 5023 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q5_CMD   0xc425c

Definition at line 5025 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q6_CMD   0xc4260

Definition at line 5027 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q7_CMD   0xc4264

Definition at line 5029 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q8_CMD   0xc4268

Definition at line 5031 of file bnx2x_reg.h.

#define USDM_REG_NUM_OF_Q9_CMD   0xc426c

Definition at line 5033 of file bnx2x_reg.h.

#define USDM_REG_PCK_END_MSG_START_ADDR   0xc4014

Definition at line 5035 of file bnx2x_reg.h.

#define USDM_REG_Q_COUNTER_START_ADDR   0xc4010

Definition at line 5037 of file bnx2x_reg.h.

#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0xc4550

Definition at line 5039 of file bnx2x_reg.h.

#define USDM_REG_SYNC_PARSER_EMPTY   0xc4558

Definition at line 5041 of file bnx2x_reg.h.

#define USDM_REG_SYNC_SYNC_EMPTY   0xc4560

Definition at line 5043 of file bnx2x_reg.h.

#define USDM_REG_TIMER_TICK   0xc4000

Definition at line 5046 of file bnx2x_reg.h.

#define USDM_REG_USDM_INT_MASK_0   0xc42a0

Definition at line 5048 of file bnx2x_reg.h.

#define USDM_REG_USDM_INT_MASK_1   0xc42b0

Definition at line 5049 of file bnx2x_reg.h.

#define USDM_REG_USDM_INT_STS_0   0xc4294

Definition at line 5051 of file bnx2x_reg.h.

#define USDM_REG_USDM_INT_STS_1   0xc42a4

Definition at line 5052 of file bnx2x_reg.h.

#define USDM_REG_USDM_PRTY_MASK   0xc42c0

Definition at line 5054 of file bnx2x_reg.h.

#define USDM_REG_USDM_PRTY_STS   0xc42b4

Definition at line 5056 of file bnx2x_reg.h.

#define USDM_REG_USDM_PRTY_STS_CLR   0xc42b8

Definition at line 5058 of file bnx2x_reg.h.

#define USEM_REG_ARB_CYCLE_SIZE   0x300034

Definition at line 5060 of file bnx2x_reg.h.

#define USEM_REG_ARB_ELEMENT0   0x300020

Definition at line 5064 of file bnx2x_reg.h.

#define USEM_REG_ARB_ELEMENT1   0x300024

Definition at line 5069 of file bnx2x_reg.h.

#define USEM_REG_ARB_ELEMENT2   0x300028

Definition at line 5075 of file bnx2x_reg.h.

#define USEM_REG_ARB_ELEMENT3   0x30002c

Definition at line 5082 of file bnx2x_reg.h.

#define USEM_REG_ARB_ELEMENT4   0x300030

Definition at line 5090 of file bnx2x_reg.h.

#define USEM_REG_ENABLE_IN   0x3000a4

Definition at line 5091 of file bnx2x_reg.h.

#define USEM_REG_ENABLE_OUT   0x3000a8

Definition at line 5092 of file bnx2x_reg.h.

#define USEM_REG_FAST_MEMORY   0x320000

Definition at line 5097 of file bnx2x_reg.h.

#define USEM_REG_FIC0_DISABLE   0x300224

Definition at line 5100 of file bnx2x_reg.h.

#define USEM_REG_FIC1_DISABLE   0x300234

Definition at line 5103 of file bnx2x_reg.h.

#define USEM_REG_INT_TABLE   0x300400

Definition at line 5106 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FIC0   0x300000

Definition at line 5109 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FIC1   0x300004

Definition at line 5112 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FOC0   0x300008

Definition at line 5115 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FOC1   0x30000c

Definition at line 5118 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FOC2   0x300010

Definition at line 5121 of file bnx2x_reg.h.

#define USEM_REG_MSG_NUM_FOC3   0x300014

Definition at line 5124 of file bnx2x_reg.h.

#define USEM_REG_PAS_DISABLE   0x30024c

Definition at line 5127 of file bnx2x_reg.h.

#define USEM_REG_PASSIVE_BUFFER   0x302000

Definition at line 5129 of file bnx2x_reg.h.

#define USEM_REG_PRAM   0x340000

Definition at line 5131 of file bnx2x_reg.h.

#define USEM_REG_SLEEP_THREADS_VALID   0x30026c

Definition at line 5133 of file bnx2x_reg.h.

#define USEM_REG_SLOW_EXT_STORE_EMPTY   0x3002a0

Definition at line 5135 of file bnx2x_reg.h.

#define USEM_REG_THREADS_LIST   0x3002e4

Definition at line 5137 of file bnx2x_reg.h.

#define USEM_REG_TS_0_AS   0x300038

Definition at line 5139 of file bnx2x_reg.h.

#define USEM_REG_TS_10_AS   0x300060

Definition at line 5141 of file bnx2x_reg.h.

#define USEM_REG_TS_11_AS   0x300064

Definition at line 5143 of file bnx2x_reg.h.

#define USEM_REG_TS_12_AS   0x300068

Definition at line 5145 of file bnx2x_reg.h.

#define USEM_REG_TS_13_AS   0x30006c

Definition at line 5147 of file bnx2x_reg.h.

#define USEM_REG_TS_14_AS   0x300070

Definition at line 5149 of file bnx2x_reg.h.

#define USEM_REG_TS_15_AS   0x300074

Definition at line 5151 of file bnx2x_reg.h.

#define USEM_REG_TS_16_AS   0x300078

Definition at line 5153 of file bnx2x_reg.h.

#define USEM_REG_TS_17_AS   0x30007c

Definition at line 5155 of file bnx2x_reg.h.

#define USEM_REG_TS_18_AS   0x300080

Definition at line 5157 of file bnx2x_reg.h.

#define USEM_REG_TS_1_AS   0x30003c

Definition at line 5159 of file bnx2x_reg.h.

#define USEM_REG_TS_2_AS   0x300040

Definition at line 5161 of file bnx2x_reg.h.

#define USEM_REG_TS_3_AS   0x300044

Definition at line 5163 of file bnx2x_reg.h.

#define USEM_REG_TS_4_AS   0x300048

Definition at line 5165 of file bnx2x_reg.h.

#define USEM_REG_TS_5_AS   0x30004c

Definition at line 5167 of file bnx2x_reg.h.

#define USEM_REG_TS_6_AS   0x300050

Definition at line 5169 of file bnx2x_reg.h.

#define USEM_REG_TS_7_AS   0x300054

Definition at line 5171 of file bnx2x_reg.h.

#define USEM_REG_TS_8_AS   0x300058

Definition at line 5173 of file bnx2x_reg.h.

#define USEM_REG_TS_9_AS   0x30005c

Definition at line 5175 of file bnx2x_reg.h.

#define USEM_REG_USEM_INT_MASK_0   0x300110

Definition at line 5177 of file bnx2x_reg.h.

#define USEM_REG_USEM_INT_MASK_1   0x300120

Definition at line 5178 of file bnx2x_reg.h.

#define USEM_REG_USEM_INT_STS_0   0x300104

Definition at line 5180 of file bnx2x_reg.h.

#define USEM_REG_USEM_INT_STS_1   0x300114

Definition at line 5181 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_MASK_0   0x300130

Definition at line 5183 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_MASK_1   0x300140

Definition at line 5184 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_STS_0   0x300124

Definition at line 5186 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_STS_1   0x300134

Definition at line 5187 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_STS_CLR_0   0x300128

Definition at line 5189 of file bnx2x_reg.h.

#define USEM_REG_USEM_PRTY_STS_CLR_1   0x300138

Definition at line 5190 of file bnx2x_reg.h.

#define USEM_REG_VFPF_ERR_NUM   0x300380

Definition at line 5193 of file bnx2x_reg.h.

#define USTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_8

Definition at line 6029 of file bnx2x_reg.h.

#define VFC_MEMORIES_RST_REG_CAM_RST   (0x1<<0)

Definition at line 5194 of file bnx2x_reg.h.

#define VFC_MEMORIES_RST_REG_RAM_RST   (0x1<<1)

Definition at line 5195 of file bnx2x_reg.h.

#define VFC_REG_MEMORIES_RST   0x1943c

Definition at line 5196 of file bnx2x_reg.h.

#define XCM_REG_AG_CTX   0x28000

Definition at line 5201 of file bnx2x_reg.h.

#define XCM_REG_AUX1_Q   0x20134

Definition at line 5203 of file bnx2x_reg.h.

#define XCM_REG_AUX_CNT_FLG_Q_19   0x201b0

Definition at line 5205 of file bnx2x_reg.h.

#define XCM_REG_CAM_OCCUP   0x20244

Definition at line 5207 of file bnx2x_reg.h.

#define XCM_REG_CDU_AG_RD_IFEN   0x20044

Definition at line 5211 of file bnx2x_reg.h.

#define XCM_REG_CDU_AG_WR_IFEN   0x20040

Definition at line 5215 of file bnx2x_reg.h.

#define XCM_REG_CDU_SM_RD_IFEN   0x2004c

Definition at line 5219 of file bnx2x_reg.h.

#define XCM_REG_CDU_SM_WR_IFEN   0x20048

Definition at line 5223 of file bnx2x_reg.h.

#define XCM_REG_CFC_INIT_CRD   0x20404

Definition at line 5227 of file bnx2x_reg.h.

#define XCM_REG_CP_WEIGHT   0x200dc

Definition at line 5231 of file bnx2x_reg.h.

#define XCM_REG_CSEM_IFEN   0x20028

Definition at line 5235 of file bnx2x_reg.h.

#define XCM_REG_CSEM_LENGTH_MIS   0x20228

Definition at line 5238 of file bnx2x_reg.h.

#define XCM_REG_CSEM_WEIGHT   0x200c4

Definition at line 5242 of file bnx2x_reg.h.

#define XCM_REG_DORQ_IFEN   0x20030

Definition at line 5246 of file bnx2x_reg.h.

#define XCM_REG_DORQ_LENGTH_MIS   0x20230

Definition at line 5249 of file bnx2x_reg.h.

#define XCM_REG_DORQ_WEIGHT   0x200cc

Definition at line 5253 of file bnx2x_reg.h.

#define XCM_REG_ERR_EVNT_ID   0x200b0

Definition at line 5255 of file bnx2x_reg.h.

#define XCM_REG_ERR_XCM_HDR   0x200ac

Definition at line 5257 of file bnx2x_reg.h.

#define XCM_REG_EXPR_EVNT_ID   0x200b4

Definition at line 5259 of file bnx2x_reg.h.

#define XCM_REG_FIC0_INIT_CRD   0x2040c

Definition at line 5263 of file bnx2x_reg.h.

#define XCM_REG_FIC1_INIT_CRD   0x20410

Definition at line 5267 of file bnx2x_reg.h.

#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0   0x20118

Definition at line 5268 of file bnx2x_reg.h.

#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1   0x2011c

Definition at line 5269 of file bnx2x_reg.h.

#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0   0x20108

Definition at line 5270 of file bnx2x_reg.h.

#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1   0x2010c

Definition at line 5271 of file bnx2x_reg.h.

#define XCM_REG_GR_ARB_TYPE   0x2020c

Definition at line 5276 of file bnx2x_reg.h.

#define XCM_REG_GR_LD0_PR   0x20214

Definition at line 5280 of file bnx2x_reg.h.

#define XCM_REG_GR_LD1_PR   0x20218

Definition at line 5284 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_0   0x20060

Definition at line 5308 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_1   0x20064

Definition at line 5309 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_2   0x20068

Definition at line 5310 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_3   0x2006c

Definition at line 5311 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_4   0x20070

Definition at line 5312 of file bnx2x_reg.h.

#define XCM_REG_N_SM_CTX_LD_5   0x20074

Definition at line 5313 of file bnx2x_reg.h.

#define XCM_REG_NIG0_IFEN   0x20038

Definition at line 5288 of file bnx2x_reg.h.

#define XCM_REG_NIG0_LENGTH_MIS   0x20238

Definition at line 5291 of file bnx2x_reg.h.

#define XCM_REG_NIG0_WEIGHT   0x200d4

Definition at line 5295 of file bnx2x_reg.h.

#define XCM_REG_NIG1_IFEN   0x2003c

Definition at line 5299 of file bnx2x_reg.h.

#define XCM_REG_NIG1_LENGTH_MIS   0x2023c

Definition at line 5302 of file bnx2x_reg.h.

#define XCM_REG_PBF_IFEN   0x20034

Definition at line 5317 of file bnx2x_reg.h.

#define XCM_REG_PBF_LENGTH_MIS   0x20234

Definition at line 5320 of file bnx2x_reg.h.

#define XCM_REG_PBF_WEIGHT   0x200d0

Definition at line 5324 of file bnx2x_reg.h.

#define XCM_REG_PHYS_QNUM3_0   0x20100

Definition at line 5325 of file bnx2x_reg.h.

#define XCM_REG_PHYS_QNUM3_1   0x20104

Definition at line 5326 of file bnx2x_reg.h.

#define XCM_REG_STOP_EVNT_ID   0x200b8

Definition at line 5328 of file bnx2x_reg.h.

#define XCM_REG_STORM_LENGTH_MIS   0x2021c

Definition at line 5331 of file bnx2x_reg.h.

#define XCM_REG_STORM_WEIGHT   0x200bc

Definition at line 5335 of file bnx2x_reg.h.

#define XCM_REG_STORM_XCM_IFEN   0x20010

Definition at line 5339 of file bnx2x_reg.h.

#define XCM_REG_TM_INIT_CRD   0x2041c

Definition at line 5343 of file bnx2x_reg.h.

#define XCM_REG_TM_WEIGHT   0x200ec

Definition at line 5347 of file bnx2x_reg.h.

#define XCM_REG_TM_XCM_HDR   0x200a8

Definition at line 5349 of file bnx2x_reg.h.

#define XCM_REG_TM_XCM_IFEN   0x2001c

Definition at line 5353 of file bnx2x_reg.h.

#define XCM_REG_TSEM_IFEN   0x20024

Definition at line 5357 of file bnx2x_reg.h.

#define XCM_REG_TSEM_LENGTH_MIS   0x20224

Definition at line 5360 of file bnx2x_reg.h.

#define XCM_REG_TSEM_WEIGHT   0x200c0

Definition at line 5364 of file bnx2x_reg.h.

#define XCM_REG_UNA_GT_NXT_Q   0x20120

Definition at line 5366 of file bnx2x_reg.h.

#define XCM_REG_USEM_IFEN   0x2002c

Definition at line 5370 of file bnx2x_reg.h.

#define XCM_REG_USEM_LENGTH_MIS   0x2022c

Definition at line 5373 of file bnx2x_reg.h.

#define XCM_REG_USEM_WEIGHT   0x200c8

Definition at line 5377 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_CMD00   0x201d4

Definition at line 5378 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_CMD01   0x201d8

Definition at line 5379 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_CMD10   0x201dc

Definition at line 5380 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_CMD11   0x201e0

Definition at line 5381 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_UPD_VAL00   0x201e4

Definition at line 5382 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_UPD_VAL01   0x201e8

Definition at line 5383 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_UPD_VAL10   0x201ec

Definition at line 5384 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_CNT_UPD_VAL11   0x201f0

Definition at line 5385 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00   0x201c4

Definition at line 5386 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01   0x201c8

Definition at line 5387 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10   0x201cc

Definition at line 5388 of file bnx2x_reg.h.

#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11   0x201d0

Definition at line 5389 of file bnx2x_reg.h.

#define XCM_REG_XCM_CFC_IFEN   0x20050

Definition at line 5393 of file bnx2x_reg.h.

#define XCM_REG_XCM_INT_MASK   0x202b4

Definition at line 5395 of file bnx2x_reg.h.

#define XCM_REG_XCM_INT_STS   0x202a8

Definition at line 5397 of file bnx2x_reg.h.

#define XCM_REG_XCM_PRTY_MASK   0x202c4

Definition at line 5399 of file bnx2x_reg.h.

#define XCM_REG_XCM_PRTY_STS   0x202b8

Definition at line 5401 of file bnx2x_reg.h.

#define XCM_REG_XCM_PRTY_STS_CLR   0x202bc

Definition at line 5403 of file bnx2x_reg.h.

#define XCM_REG_XCM_REG0_SZ   0x200f4

Definition at line 5409 of file bnx2x_reg.h.

#define XCM_REG_XCM_STORM0_IFEN   0x20004

Definition at line 5413 of file bnx2x_reg.h.

#define XCM_REG_XCM_STORM1_IFEN   0x20008

Definition at line 5417 of file bnx2x_reg.h.

#define XCM_REG_XCM_TM_IFEN   0x20020

Definition at line 5421 of file bnx2x_reg.h.

#define XCM_REG_XCM_XQM_IFEN   0x2000c

Definition at line 5425 of file bnx2x_reg.h.

#define XCM_REG_XCM_XQM_USE_Q   0x200f0

Definition at line 5427 of file bnx2x_reg.h.

#define XCM_REG_XQM_BYP_ACT_UPD   0x200fc

Definition at line 5429 of file bnx2x_reg.h.

#define XCM_REG_XQM_INIT_CRD   0x20420

Definition at line 5433 of file bnx2x_reg.h.

#define XCM_REG_XQM_P_WEIGHT   0x200e4

Definition at line 5437 of file bnx2x_reg.h.

#define XCM_REG_XQM_S_WEIGHT   0x200e8

Definition at line 5441 of file bnx2x_reg.h.

#define XCM_REG_XQM_XCM_HDR_P   0x200a0

Definition at line 5443 of file bnx2x_reg.h.

#define XCM_REG_XQM_XCM_HDR_S   0x200a4

Definition at line 5445 of file bnx2x_reg.h.

#define XCM_REG_XQM_XCM_IFEN   0x20014

Definition at line 5449 of file bnx2x_reg.h.

#define XCM_REG_XSDM_IFEN   0x20018

Definition at line 5453 of file bnx2x_reg.h.

#define XCM_REG_XSDM_LENGTH_MIS   0x20220

Definition at line 5456 of file bnx2x_reg.h.

#define XCM_REG_XSDM_WEIGHT   0x200e0

Definition at line 5460 of file bnx2x_reg.h.

#define XCM_REG_XX_DESCR_TABLE   0x20480

Definition at line 5464 of file bnx2x_reg.h.

#define XCM_REG_XX_DESCR_TABLE_SIZE   32

Definition at line 5465 of file bnx2x_reg.h.

#define XCM_REG_XX_FREE   0x20240

Definition at line 5467 of file bnx2x_reg.h.

#define XCM_REG_XX_INIT_CRD   0x20424

Definition at line 5473 of file bnx2x_reg.h.

#define XCM_REG_XX_MSG_NUM   0x20428

Definition at line 5476 of file bnx2x_reg.h.

#define XCM_REG_XX_OVFL_EVNT_ID   0x20058

Definition at line 5478 of file bnx2x_reg.h.

#define XCM_REG_XX_TABLE   0x20500

Definition at line 5513 of file bnx2x_reg.h.

#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS   (0x1<<0)

Definition at line 5479 of file bnx2x_reg.h.

#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS   (0x1<<1)

Definition at line 5480 of file bnx2x_reg.h.

#define XMAC_CTRL_REG_LINE_LOCAL_LPBK   (0x1<<2)

Definition at line 5481 of file bnx2x_reg.h.

#define XMAC_CTRL_REG_RX_EN   (0x1<<1)

Definition at line 5482 of file bnx2x_reg.h.

#define XMAC_CTRL_REG_SOFT_RESET   (0x1<<6)

Definition at line 5483 of file bnx2x_reg.h.

#define XMAC_CTRL_REG_TX_EN   (0x1<<0)

Definition at line 5484 of file bnx2x_reg.h.

#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN   (0x1<<18)

Definition at line 5485 of file bnx2x_reg.h.

#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN   (0x1<<17)

Definition at line 5486 of file bnx2x_reg.h.

#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON   (0x1<<1)

Definition at line 5487 of file bnx2x_reg.h.

#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN   (0x1<<0)

Definition at line 5488 of file bnx2x_reg.h.

#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN   (0x1<<3)

Definition at line 5489 of file bnx2x_reg.h.

#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN   (0x1<<4)

Definition at line 5490 of file bnx2x_reg.h.

#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN   (0x1<<5)

Definition at line 5491 of file bnx2x_reg.h.

#define XMAC_REG_CLEAR_RX_LSS_STATUS   0x60

Definition at line 5492 of file bnx2x_reg.h.

#define XMAC_REG_CTRL   0

Definition at line 5493 of file bnx2x_reg.h.

#define XMAC_REG_CTRL_SA_HI   0x2c

Definition at line 5496 of file bnx2x_reg.h.

#define XMAC_REG_CTRL_SA_LO   0x28

Definition at line 5499 of file bnx2x_reg.h.

#define XMAC_REG_EEE_CTRL   0xd8

Definition at line 5500 of file bnx2x_reg.h.

#define XMAC_REG_EEE_TIMERS_HI   0xe4

Definition at line 5501 of file bnx2x_reg.h.

#define XMAC_REG_PAUSE_CTRL   0x68

Definition at line 5502 of file bnx2x_reg.h.

#define XMAC_REG_PFC_CTRL   0x70

Definition at line 5503 of file bnx2x_reg.h.

#define XMAC_REG_PFC_CTRL_HI   0x74

Definition at line 5504 of file bnx2x_reg.h.

#define XMAC_REG_RX_LSS_STATUS   0x58

Definition at line 5505 of file bnx2x_reg.h.

#define XMAC_REG_RX_MAX_SIZE   0x40

Definition at line 5508 of file bnx2x_reg.h.

#define XMAC_REG_TX_CTRL   0x20

Definition at line 5509 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_0   0x166038

Definition at line 5515 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_1   0x16603c

Definition at line 5516 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_10   0x166060

Definition at line 5517 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_11   0x166064

Definition at line 5518 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_12   0x166068

Definition at line 5519 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_13   0x16606c

Definition at line 5520 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_14   0x166070

Definition at line 5521 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_2   0x166040

Definition at line 5522 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_3   0x166044

Definition at line 5523 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_4   0x166048

Definition at line 5524 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_5   0x16604c

Definition at line 5525 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_6   0x166050

Definition at line 5526 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_7   0x166054

Definition at line 5527 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_8   0x166058

Definition at line 5528 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_EVENT_9   0x16605c

Definition at line 5529 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_MODE_0   0x1661b8

Definition at line 5532 of file bnx2x_reg.h.

#define XSDM_REG_AGG_INT_MODE_1   0x1661bc

Definition at line 5533 of file bnx2x_reg.h.

#define XSDM_REG_CFC_RSP_START_ADDR   0x166008

Definition at line 5535 of file bnx2x_reg.h.

#define XSDM_REG_CMP_COUNTER_MAX0   0x16601c

Definition at line 5537 of file bnx2x_reg.h.

#define XSDM_REG_CMP_COUNTER_MAX1   0x166020

Definition at line 5539 of file bnx2x_reg.h.

#define XSDM_REG_CMP_COUNTER_MAX2   0x166024

Definition at line 5541 of file bnx2x_reg.h.

#define XSDM_REG_CMP_COUNTER_MAX3   0x166028

Definition at line 5543 of file bnx2x_reg.h.

#define XSDM_REG_CMP_COUNTER_START_ADDR   0x16600c

Definition at line 5546 of file bnx2x_reg.h.

#define XSDM_REG_ENABLE_IN1   0x166238

Definition at line 5547 of file bnx2x_reg.h.

#define XSDM_REG_ENABLE_IN2   0x16623c

Definition at line 5548 of file bnx2x_reg.h.

#define XSDM_REG_ENABLE_OUT1   0x166240

Definition at line 5549 of file bnx2x_reg.h.

#define XSDM_REG_ENABLE_OUT2   0x166244

Definition at line 5550 of file bnx2x_reg.h.

#define XSDM_REG_INIT_CREDIT_PXP_CTRL   0x1664bc

Definition at line 5553 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE   0x16627c

Definition at line 5555 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_PKT_END_MSG   0x166274

Definition at line 5557 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ   0x166278

Definition at line 5559 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q0_CMD   0x166248

Definition at line 5561 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q10_CMD   0x16626c

Definition at line 5563 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q11_CMD   0x166270

Definition at line 5565 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q1_CMD   0x16624c

Definition at line 5567 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q3_CMD   0x166250

Definition at line 5569 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q4_CMD   0x166254

Definition at line 5571 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q5_CMD   0x166258

Definition at line 5573 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q6_CMD   0x16625c

Definition at line 5575 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q7_CMD   0x166260

Definition at line 5577 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q8_CMD   0x166264

Definition at line 5579 of file bnx2x_reg.h.

#define XSDM_REG_NUM_OF_Q9_CMD   0x166268

Definition at line 5581 of file bnx2x_reg.h.

#define XSDM_REG_OPERATION_GEN   0x1664c4

Definition at line 5587 of file bnx2x_reg.h.

#define XSDM_REG_Q_COUNTER_START_ADDR   0x166010

Definition at line 5583 of file bnx2x_reg.h.

#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY   0x166548

Definition at line 5589 of file bnx2x_reg.h.

#define XSDM_REG_SYNC_PARSER_EMPTY   0x166550

Definition at line 5591 of file bnx2x_reg.h.

#define XSDM_REG_SYNC_SYNC_EMPTY   0x166558

Definition at line 5593 of file bnx2x_reg.h.

#define XSDM_REG_TIMER_TICK   0x166000

Definition at line 5596 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_INT_MASK_0   0x16629c

Definition at line 5598 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_INT_MASK_1   0x1662ac

Definition at line 5599 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_INT_STS_0   0x166290

Definition at line 5601 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_INT_STS_1   0x1662a0

Definition at line 5602 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_PRTY_MASK   0x1662bc

Definition at line 5604 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_PRTY_STS   0x1662b0

Definition at line 5606 of file bnx2x_reg.h.

#define XSDM_REG_XSDM_PRTY_STS_CLR   0x1662b4

Definition at line 5608 of file bnx2x_reg.h.

#define XSEM_REG_ARB_CYCLE_SIZE   0x280034

Definition at line 5610 of file bnx2x_reg.h.

#define XSEM_REG_ARB_ELEMENT0   0x280020

Definition at line 5614 of file bnx2x_reg.h.

#define XSEM_REG_ARB_ELEMENT1   0x280024

Definition at line 5619 of file bnx2x_reg.h.

#define XSEM_REG_ARB_ELEMENT2   0x280028

Definition at line 5625 of file bnx2x_reg.h.

#define XSEM_REG_ARB_ELEMENT3   0x28002c

Definition at line 5632 of file bnx2x_reg.h.

#define XSEM_REG_ARB_ELEMENT4   0x280030

Definition at line 5640 of file bnx2x_reg.h.

#define XSEM_REG_ENABLE_IN   0x2800a4

Definition at line 5641 of file bnx2x_reg.h.

#define XSEM_REG_ENABLE_OUT   0x2800a8

Definition at line 5642 of file bnx2x_reg.h.

#define XSEM_REG_FAST_MEMORY   0x2a0000

Definition at line 5647 of file bnx2x_reg.h.

#define XSEM_REG_FIC0_DISABLE   0x280224

Definition at line 5650 of file bnx2x_reg.h.

#define XSEM_REG_FIC1_DISABLE   0x280234

Definition at line 5653 of file bnx2x_reg.h.

#define XSEM_REG_INT_TABLE   0x280400

Definition at line 5656 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FIC0   0x280000

Definition at line 5659 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FIC1   0x280004

Definition at line 5662 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FOC0   0x280008

Definition at line 5665 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FOC1   0x28000c

Definition at line 5668 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FOC2   0x280010

Definition at line 5671 of file bnx2x_reg.h.

#define XSEM_REG_MSG_NUM_FOC3   0x280014

Definition at line 5674 of file bnx2x_reg.h.

#define XSEM_REG_PAS_DISABLE   0x28024c

Definition at line 5677 of file bnx2x_reg.h.

#define XSEM_REG_PASSIVE_BUFFER   0x282000

Definition at line 5679 of file bnx2x_reg.h.

#define XSEM_REG_PRAM   0x2c0000

Definition at line 5681 of file bnx2x_reg.h.

#define XSEM_REG_SLEEP_THREADS_VALID   0x28026c

Definition at line 5683 of file bnx2x_reg.h.

#define XSEM_REG_SLOW_EXT_STORE_EMPTY   0x2802a0

Definition at line 5685 of file bnx2x_reg.h.

#define XSEM_REG_THREADS_LIST   0x2802e4

Definition at line 5687 of file bnx2x_reg.h.

#define XSEM_REG_TS_0_AS   0x280038

Definition at line 5689 of file bnx2x_reg.h.

#define XSEM_REG_TS_10_AS   0x280060

Definition at line 5691 of file bnx2x_reg.h.

#define XSEM_REG_TS_11_AS   0x280064

Definition at line 5693 of file bnx2x_reg.h.

#define XSEM_REG_TS_12_AS   0x280068

Definition at line 5695 of file bnx2x_reg.h.

#define XSEM_REG_TS_13_AS   0x28006c

Definition at line 5697 of file bnx2x_reg.h.

#define XSEM_REG_TS_14_AS   0x280070

Definition at line 5699 of file bnx2x_reg.h.

#define XSEM_REG_TS_15_AS   0x280074

Definition at line 5701 of file bnx2x_reg.h.

#define XSEM_REG_TS_16_AS   0x280078

Definition at line 5703 of file bnx2x_reg.h.

#define XSEM_REG_TS_17_AS   0x28007c

Definition at line 5705 of file bnx2x_reg.h.

#define XSEM_REG_TS_18_AS   0x280080

Definition at line 5707 of file bnx2x_reg.h.

#define XSEM_REG_TS_1_AS   0x28003c

Definition at line 5709 of file bnx2x_reg.h.

#define XSEM_REG_TS_2_AS   0x280040

Definition at line 5711 of file bnx2x_reg.h.

#define XSEM_REG_TS_3_AS   0x280044

Definition at line 5713 of file bnx2x_reg.h.

#define XSEM_REG_TS_4_AS   0x280048

Definition at line 5715 of file bnx2x_reg.h.

#define XSEM_REG_TS_5_AS   0x28004c

Definition at line 5717 of file bnx2x_reg.h.

#define XSEM_REG_TS_6_AS   0x280050

Definition at line 5719 of file bnx2x_reg.h.

#define XSEM_REG_TS_7_AS   0x280054

Definition at line 5721 of file bnx2x_reg.h.

#define XSEM_REG_TS_8_AS   0x280058

Definition at line 5723 of file bnx2x_reg.h.

#define XSEM_REG_TS_9_AS   0x28005c

Definition at line 5725 of file bnx2x_reg.h.

#define XSEM_REG_VFPF_ERR_NUM   0x280380

Definition at line 5728 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_INT_MASK_0   0x280110

Definition at line 5730 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_INT_MASK_1   0x280120

Definition at line 5731 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_INT_STS_0   0x280104

Definition at line 5733 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_INT_STS_1   0x280114

Definition at line 5734 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_MASK_0   0x280130

Definition at line 5736 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_MASK_1   0x280140

Definition at line 5737 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_STS_0   0x280124

Definition at line 5739 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_STS_1   0x280134

Definition at line 5740 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_STS_CLR_0   0x280128

Definition at line 5742 of file bnx2x_reg.h.

#define XSEM_REG_XSEM_PRTY_STS_CLR_1   0x280138

Definition at line 5743 of file bnx2x_reg.h.

#define XSTORM_FATAL_ASSERT_ATTENTION_BIT   RESERVED_GENERAL_ATTENTION_BIT_10

Definition at line 6031 of file bnx2x_reg.h.

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