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board-trout-panel.c
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1 /* linux/arch/arm/mach-msm/board-trout-mddi.c
2 ** Author: Brian Swetland <[email protected]>
3 */
4 #include <linux/gpio.h>
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/delay.h>
9 #include <linux/leds.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 
13 #include <asm/io.h>
14 #include <asm/mach-types.h>
15 #include <asm/system_info.h>
16 
17 #include <linux/platform_data/video-msm_fb.h>
18 #include <mach/vreg.h>
19 
20 #include "board-trout.h"
21 #include "proc_comm.h"
22 #include "devices.h"
23 
24 #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
25 
26 #define MDDI_CLIENT_CORE_BASE 0x108000
27 #define LCD_CONTROL_BLOCK_BASE 0x110000
28 #define SPI_BLOCK_BASE 0x120000
29 #define I2C_BLOCK_BASE 0x130000
30 #define PWM_BLOCK_BASE 0x140000
31 #define GPIO_BLOCK_BASE 0x150000
32 #define SYSTEM_BLOCK1_BASE 0x160000
33 #define SYSTEM_BLOCK2_BASE 0x170000
34 
35 
36 #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
37 #define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
38 #define PWM0OFF (PWM_BLOCK_BASE|0x1C)
39 
40 #define V_VDDE2E_VDD2_GPIO 0
41 #define MDDI_RST_N 82
42 
43 #define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
44 #define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
45 #define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
46 #define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
47 #define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
48 #define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
49 #define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
50 #define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
51 #define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
52 #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
53 #define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
54 #define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
55 #define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
56 #define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
57 #define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
58 #define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
59 #define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
60 #define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
61 #define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
62 #define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
63 #define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
64 #define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
65 
66 #define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
67 #define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
68 #define START (LCD_CONTROL_BLOCK_BASE|0x08)
69 #define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
70 #define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
71 #define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
72 #define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
73 #define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
74 #define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
75 #define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
76 #define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
77 #define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
78 #define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
79 #define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
80 #define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
81 #define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
82 #define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
83 #define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
84 #define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
85 #define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
86 #define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
87 #define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
88 #define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
89 #define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
90 #define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
91 #define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
92 #define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
93 #define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
94 #define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
95 #define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
96 #define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
97 #define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
98 #define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
99 #define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
100 #define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
101 
102 #define SSICTL (SPI_BLOCK_BASE|0x00)
103 #define SSITIME (SPI_BLOCK_BASE|0x04)
104 #define SSITX (SPI_BLOCK_BASE|0x08)
105 #define SSIRX (SPI_BLOCK_BASE|0x0C)
106 #define SSIINTC (SPI_BLOCK_BASE|0x10)
107 #define SSIINTS (SPI_BLOCK_BASE|0x14)
108 #define SSIDBG1 (SPI_BLOCK_BASE|0x18)
109 #define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
110 #define SSIID (SPI_BLOCK_BASE|0x20)
111 
112 #define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
113 #define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
114 #define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
115 #define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
116 #define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
117 
118 #define GPIODATA (GPIO_BLOCK_BASE|0x00)
119 #define GPIODIR (GPIO_BLOCK_BASE|0x04)
120 #define GPIOIS (GPIO_BLOCK_BASE|0x08)
121 #define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
122 #define GPIOIEV (GPIO_BLOCK_BASE|0x10)
123 #define GPIOIE (GPIO_BLOCK_BASE|0x14)
124 #define GPIORIS (GPIO_BLOCK_BASE|0x18)
125 #define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
126 #define GPIOIC (GPIO_BLOCK_BASE|0x20)
127 #define GPIOOMS (GPIO_BLOCK_BASE|0x24)
128 #define GPIOPC (GPIO_BLOCK_BASE|0x28)
129 #define GPIOID (GPIO_BLOCK_BASE|0x30)
130 
131 #define SPI_WRITE(reg, val) \
132  { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
133  { 0, 5 },
134 
135 #define SPI_WRITE1(reg) \
136  { SSITX, (reg) & 0xff }, \
137  { 0, 5 },
138 
139 struct mddi_table {
140  uint32_t reg;
141  uint32_t value;
142 };
143 static struct mddi_table mddi_toshiba_init_table[] = {
144  { DPSET0, 0x09e90046 },
145  { DPSET1, 0x00000118 },
146  { DPSUS, 0x00000000 },
147  { DPRUN, 0x00000001 },
148  { 1, 14 }, /* msleep 14 */
149  { SYSCKENA, 0x00000001 },
150  { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
151 
152  { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
153  { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
154  { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
155  { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
156  { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
157 
158  { GPIOIBE, 0x000003FF },
159  { GPIOIS, 0x00000000 },
160  { GPIOIC, 0x000003FF },
161  { GPIOIE, 0x00000000 },
162 
163  { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
164  { 1, 1 }, /* msleep 1 */
165  { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
166  { DRAMPWR, 0x00000001 }, /* eDRAM power */
167 };
168 
169 #define GPIOSEL_VWAKEINT (1U << 0)
170 #define INTMASK_VWAKEOUT (1U << 0)
171 
172 
173 static struct clk *gp_clk;
174 static int trout_new_backlight = 1;
175 static struct vreg *vreg_mddi_1v5;
176 static struct vreg *vreg_lcm_2v85;
177 
178 static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
179  struct mddi_table *table, size_t count)
180 {
181  int i;
182  for (i = 0; i < count; i++) {
183  uint32_t reg = table[i].reg;
184  uint32_t value = table[i].value;
185 
186  if (reg == 0)
187  udelay(value);
188  else if (reg == 1)
189  msleep(value);
190  else
191  client_data->remote_write(client_data, value, reg);
192  }
193 }
194 
195 static int trout_mddi_toshiba_client_init(
196  struct msm_mddi_bridge_platform_data *bridge_data,
197  struct msm_mddi_client_data *client_data)
198 {
199  int panel_id;
200 
201  client_data->auto_hibernate(client_data, 0);
202  trout_process_mddi_table(client_data, mddi_toshiba_init_table,
203  ARRAY_SIZE(mddi_toshiba_init_table));
204  client_data->auto_hibernate(client_data, 1);
205  panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
206  if (panel_id > 1) {
207  printk(KERN_WARNING "unknown panel id at mddi_enable\n");
208  return -1;
209  }
210  return 0;
211 }
212 
213 static int trout_mddi_toshiba_client_uninit(
214  struct msm_mddi_bridge_platform_data *bridge_data,
215  struct msm_mddi_client_data *client_data)
216 {
217  return 0;
218 }
219 
220 static struct resource resources_msm_fb[] = {
221  {
222  .start = MSM_FB_BASE,
223  .end = MSM_FB_BASE + MSM_FB_SIZE,
224  .flags = IORESOURCE_MEM,
225  },
226 };
227 
228 struct msm_mddi_bridge_platform_data toshiba_client_data = {
229  .init = trout_mddi_toshiba_client_init,
230  .uninit = trout_mddi_toshiba_client_uninit,
231  .fb_data = {
232  .xres = 320,
233  .yres = 480,
234  .width = 45,
235  .height = 67,
236  .output_format = 0,
237  },
238 };
239 
240 static struct msm_mddi_platform_data mddi_pdata = {
241  .clk_rate = 122880000,
242  .fb_resource = resources_msm_fb,
243  .num_clients = 1,
244  .client_platform_data = {
245  {
246  .product_id = (0xd263 << 16 | 0),
247  .name = "mddi_c_d263_0000",
248  .id = 0,
249  .client_data = &toshiba_client_data,
250  .clk_rate = 0,
251  },
252  },
253 };
254 
255 int __init trout_init_panel(void)
256 {
257  int rc;
258 
259  if (!machine_is_trout())
260  return 0;
261  vreg_mddi_1v5 = vreg_get(0, "gp2");
262  if (IS_ERR(vreg_mddi_1v5))
263  return PTR_ERR(vreg_mddi_1v5);
264  vreg_lcm_2v85 = vreg_get(0, "gp4");
265  if (IS_ERR(vreg_lcm_2v85))
266  return PTR_ERR(vreg_lcm_2v85);
267 
268  trout_new_backlight = system_rev >= 5;
269  if (trout_new_backlight) {
270  uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
271  GPIO_NO_PULL, GPIO_8MA);
272  msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
273  } else {
274  uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
275  GPIO_NO_PULL, GPIO_8MA);
276  msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
277 
278  gp_clk = clk_get(NULL, "gp_clk");
279  if (IS_ERR(gp_clk)) {
280  printk(KERN_ERR "trout_init_panel: could not get gp"
281  "clock\n");
282  gp_clk = NULL;
283  }
284  rc = clk_set_rate(gp_clk, 19200000);
285  if (rc)
286  printk(KERN_ERR "trout_init_panel: set clock rate "
287  "failed\n");
288  }
289 
290  rc = platform_device_register(&msm_device_mdp);
291  if (rc)
292  return rc;
293  msm_device_mddi0.dev.platform_data = &mddi_pdata;
294  return platform_device_register(&msm_device_mddi0);
295 }
296 
297 device_initcall(trout_init_panel);
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