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cassini.h
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1 /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
2  * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
3  *
4  * Copyright (C) 2004 Sun Microsystems Inc.
5  * Copyright (c) 2003 Adrian Sun ([email protected])
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of the
10  * License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20  * 02111-1307, USA.
21  *
22  * vendor id: 0x108E (Sun Microsystems, Inc.)
23  * device id: 0xabba (Cassini)
24  * revision ids: 0x01 = Cassini
25  * 0x02 = Cassini rev 2
26  * 0x10 = Cassini+
27  * 0x11 = Cassini+ 0.2u
28  *
29  * vendor id: 0x100b (National Semiconductor)
30  * device id: 0x0035 (DP83065/Saturn)
31  * revision ids: 0x30 = Saturn B2
32  *
33  * rings are all offset from 0.
34  *
35  * there are two clock domains:
36  * PCI: 33/66MHz clock
37  * chip: 125MHz clock
38  */
39 
40 #ifndef _CASSINI_H
41 #define _CASSINI_H
42 
43 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
44  * 32-bit words. there is no i/o port access. REG_ addresses are
45  * shared between cassini and cassini+. REG_PLUS_ addresses only
46  * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
47  */
48 #define CAS_ID_REV2 0x02
49 #define CAS_ID_REVPLUS 0x10
50 #define CAS_ID_REVPLUS02u 0x11
51 #define CAS_ID_REVSATURNB2 0x30
52 
55 /* this register sets the weights for the weighted round robin arbiter. e.g.,
56  * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
57  * for its next turn to access the pci bus.
58  * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
59  * DEFAULT: 0x0, SIZE: 5 bits
60  */
61 #define REG_CAWR 0x0004 /* core arbitration weight */
62 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
63 #define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */
64 #define CAWR_TX_DMA_WEIGHT_SHIFT 2
65 #define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */
66 #define CAWR_RR_DIS 0x10 /* [4] */
67 
68 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
69  * sizes determined by length of packet or descriptor transfer and the
70  * max length allowed by the target.
71  * DEFAULT: 0x0, SIZE: 1 bit
72  */
73 #define REG_INF_BURST 0x0008 /* infinite burst enable reg */
74 #define INF_BURST_EN 0x1 /* enable */
75 
76 /* top level interrupts [0-9] are auto-cleared to 0 when the status
77  * register is read. second level interrupts [13 - 18] are cleared at
78  * the source. tx completion register 3 is replicated in [19 - 31]
79  * DEFAULT: 0x00000000, SIZE: 29 bits
80  */
81 #define REG_INTR_STATUS 0x000C /* interrupt status register */
82 #define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
83  xferred from host queue to
84  TX FIFO */
85 #define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
86  TX FIFO. i.e.,
87  TX Kick == TX complete. if
88  PACED_MODE set, then TX FIFO
89  also empty */
90 #define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
91  FIFO */
92 #define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
93  corrupted. FATAL ERROR */
94 #define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
95  from RX FIFO to host mem.
96  RX completion reg updated.
97  may be delayed by recv
98  intr blanking. */
99 #define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
100  RX Kick == RX complete */
101 #define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
102  corrupted. FATAL ERROR */
103 #define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
104  ring to post descriptors.
105  RX complete head incr to
106  almost reach RX complete
107  tail */
108 #define INTR_RX_BUF_AE 0x00000100 /* less than the
109  programmable threshold #
110  of free descr avail for
111  hw use */
112 #define INTR_RX_COMP_AF 0x00000200 /* less than the
113  programmable threshold #
114  of descr spaces for hw
115  use in completion descr
116  ring */
117 #define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC !=
118  len of non-reassembly pkt
119  from fifo during DMA or
120  header parser provides TCP
121  header and payload size >
122  MAC packet size.
123  FATAL ERROR */
124 #define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
125  bit will be set if an interrupt
126  generated on the pci bus. useful
127  when driver is polling for
128  interrupts */
129 #define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
130 #define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
131  least 1 unmasked interrupt set */
132 #define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
133  least 1 unmasked interrupt set */
134 #define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
135  at least 1 unmasked interrupt
136  set */
137 #define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
138  1 unmasked interrupt set */
139 #define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
140  BIF has at least 1 unmasked
141  interrupt set */
142 #define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
143  3 reg data */
144 #define INTR_TX_COMP_3_SHIFT 19
145 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
146  INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
147  INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
148  INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
149  INTR_MAC_CTRL_STATUS)
150 
151 /* determines which status events will cause an interrupt. layout same
152  * as REG_INTR_STATUS.
153  * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
154  */
155 #define REG_INTR_MASK 0x0010 /* Interrupt mask */
156 
157 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
158  * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
159  * DEFAULT: 0x00000000, SIZE: 12 bits
160  */
161 #define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
162  (used w/ status alias) */
163 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
164  * REG_ALIAS_CLEAR
165  * DEFAULT: 0x00000000, SIZE: 29 bits
166  */
167 #define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
168  (selective clear) */
169 
170 /* DEFAULT: 0x0, SIZE: 3 bits */
171 #define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
172 #define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
173  set if no ACK64# during ABS64 cycle
174  in Cassini. */
175 #define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
176  no read retry after 2^15 clocks */
177 #define PCI_ERR_OTHER 0x04 /* other PCI errors */
178 #define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req.
179  unused in Cassini. */
180 #define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
181  unused in Cassini. */
182 #define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
183  DMA. unused in cassini. */
184 
185 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
186  * causes an interrupt to be generated.
187  * DEFAULT: 0x7, SIZE: 3 bits
188  */
189 #define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
190 
191 /* used to configure PCI related parameters that are not in PCI config space.
192  * DEFAULT: 0bxx000, SIZE: 5 bits
193  */
194 #define REG_BIM_CFG 0x1008 /* BIM Configuration */
195 #define BIM_CFG_RESERVED0 0x001 /* reserved */
196 #define BIM_CFG_RESERVED1 0x002 /* reserved */
197 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
198 #define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
199 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
200 #define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */
201 #define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
202 #define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
203 #define BIM_CFG_RESERVED2 0x100 /* reserved */
204 #define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
205  reset. reserved in Cassini. */
206 #define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
207  reserved in Cassini. */
208 #define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0.
209  reserved in Cassini. */
210 
211 /* DEFAULT: 0x00000000, SIZE: 32 bits */
212 #define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
213 #define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
214  machine bits [21:0] */
215 #define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
216  machine bits [6:0] */
217 
218 /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
219  * reset. poll until TX and RX read back as 0's for completion.
220  */
221 #define REG_SW_RESET 0x1010 /* Software reset */
222 #define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until
223  cleared to 0. */
224 #define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
225  cleared to 0. */
226 #define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
227  resets PHY and anything else
228  connected to RSTOUT#. RSTOUT#
229  is also activated by local PCI
230  reset when hot-swap is being
231  done. */
232 #define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
233  this bit set, PCS and SLINK
234  modules won't be reset.
235  i.e., link won't drop. */
236 #define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
237 #define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
238  0b000: ARB_IDLE1
239  0b001: ARB_IDLE2
240  0b010: ARB_WB_ACK
241  0b011: ARB_WB_WAT
242  0b100: ARB_RB_ACK
243  0b101: ARB_RB_WAT
244  0b110: ARB_RB_END
245  0b111: ARB_WB_END */
246 #define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
247  0b00: RD_PCI_WAT
248  0b01: RD_PCI_RDY
249  0b11: RD_PCI_ACK */
250 #define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
251  0b00: AD_IDL_RX
252  0b01: AD_ACK_RX
253  0b10: AD_ACK_TX
254  0b11: AD_IDL_TX */
255 #define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
256  0b00: WR_PCI_WAT
257  0b01: WR_PCI_RDY
258  0b11: WR_PCI_ACK */
259 #define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits:
260  0b000: ARB_IDLE1
261  0b001: ARB_IDLE2
262  0b010: ARB_TX_ACK
263  0b011: ARB_TX_WAT
264  0b100: ARB_RX_ACK
265  0b110: ARB_RX_WAT */
266 
267 /* Cassini only. 64-bit register used to check PCI datapath. when read,
268  * value written has both lower and upper 32-bit halves rotated to the right
269  * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
270  */
271 #define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
272  Cassini+: reserved */
273 
274 /* output enables are provided for each device's chip select and for the rest
275  * of the outputs from cassini to its local bus devices. two sw programmable
276  * bits are connected to general purpus control/status bits.
277  * DEFAULT: 0x7
278  */
279 #define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
280  output EN. default: 0x7 */
281 #define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
282  OE signal output enable on the
283  local bus interface. these
284  are shared between both local
285  bus devices. tristate when 0. */
286 #define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
287 #define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
288  select output enable */
289 #define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */
290 #define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */
291 #define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
292 
293 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
294  * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
295  * _DATA_HI should be the last access of the sequence.
296  * DEFAULT: undefined
297  */
298 #define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
299  purposes. */
300 #define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
301 #define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1
302  read buffer access = 0 */
303 /* DEFAULT: undefined */
304 #define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
305 #define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
306 
307 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
308  * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
309  */
310 #define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
311  control/status */
312 #define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
313 #define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
314  Cassini only. reserved in
315  Cassini+. */
316 #define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
317  buffer. */
318 #define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write
319  buffer. Cassini only. reserved
320  in Cassini+. */
321 #define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
322 #define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
323 #define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
324  Cassini only. reserved in
325  Cassini+. */
326 #define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
327  Cassini only. reserved in
328  Cassini+. */
329 
330 /* ASUN: i'm not sure what this does as it's not in the spec.
331  * DEFAULT: 0xFC
332  */
333 #define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
334  select register */
335 
336 /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
337  * values for _SEL_HI_MASK and _SEL_LOW_MASK:
338  * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
339  * wtc empty r, post pci)
340  * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
341  * pci rpkt comp, txdma wr req, txdma wr ack,
342  * txdma wr rdy, txdma wr xfr done)
343  * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
344  * rd arb state, rd pci state)
345  * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
346  * wrpci state)
347  * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
348  * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
349  * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
350  * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
351  * the following are not available in Cassini:
352  * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
353  * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
354  */
355 #define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
356 #define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
357  driven on local bus P_A[15:0]
358  for debugging */
359 #define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
360  0x03 = mac[1:0]
361  0x0C = rx[1:0]
362  0x30 = tx[1:0]
363  0xC0 = hp[1:0] */
364 #define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
365  on P_A[15:8]. see above for
366  values. */
367 #define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
368  on P_A[7:0]. see above for
369  values. */
370 
371 /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
372  DEFAULT: 0x1F */
373 #define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
374  register 2 for INTB */
375 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
376 /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
377  * all of the alternate (2-4) INTR registers while _1 corresponds to only
378  * _MASK_1 and _STATUS_1 registers.
379  * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
380  */
381 #define INTR_RX_DONE_ALT 0x01
382 #define INTR_RX_COMP_FULL_ALT 0x02
383 #define INTR_RX_COMP_AF_ALT 0x04
384 #define INTR_RX_BUF_UNAVAIL_1 0x08
385 #define INTR_RX_BUF_AE_1 0x10 /* almost empty */
386 #define INTRN_MASK_RX_EN 0x80
387 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
388  INTR_RX_COMP_FULL_ALT | \
389  INTR_RX_COMP_AF_ALT | \
390  INTR_RX_BUF_UNAVAIL_1 | \
391  INTR_RX_BUF_AE_1)
392 #define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status
393  register 2 for INTB. default: 0x1F */
394 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
395 #define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the
396  flags are set. enables desc ring. */
397 
398 #define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
399  register 2 for INTB */
400 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
401 
402 #define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
403  register alias 2 for INTB */
404 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
405 
406 #define REG_SATURN_PCFG 0x106c /* pin configuration register for
407  integrated macphy */
408 
409 #define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */
410 #define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */
411 #define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
412 #define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
413 #define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
414 #define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
415  0 = normal */
416 #define SATURN_PCFG_MTP 0x00000080 /* test point select */
417 #define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
418  GMII on SERDES pins for
419  monitoring. */
420 #define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
421  pins configed as outputs.
422  for power saving when using
423  internal phy. */
424 #define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
425  polarity from strapping
426  value.
427  1 = mac core led ctrl
428  polarity active low. */
429 
430 
432 #define MAX_TX_RINGS_SHIFT 2
433 #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
434 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
435 
436 /* TX configuration.
437  * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
438  * DEFAULT: 0x3F000001
439  */
440 #define REG_TX_CFG 0x2004 /* TX config */
441 #define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
442  will stop after xfer of current
443  buffer has been completed. */
444 #define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
445  accessed w/ FIFO addr
446  and data registers.
447  TX DMA should be
448  disabled. */
449 #define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
450  ring 1. */
451 #define TX_CFG_DESC_RING0_SHIFT 2
452 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
453 #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
454 #define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
455  TX FIFO becomes empty.
456  if 0, TX_ALL set
457  if descr queue empty. */
458 #define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
459 #define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at
460  the end of every packet kicked
461  through Q1. */
462 #define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at
463  the end of every packet kicked
464  through Q2. */
465 #define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at
466  the end of every packet kicked
467  through Q3 */
468 #define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at
469  the end of every packet kicked
470  through Q4 */
471 #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
472  writeback */
473 #define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
474  connection
475  0b00: tx mac req,
476  tx mac retry req,
477  tx ack and tx tag.
478  0b01: txdma rd req,
479  txdma rd ack,
480  txdma rd rdy,
481  txdma rd type0
482  0b11: txdma wr req,
483  txdma wr ack,
484  txdma wr rdy,
485  txdma wr xfr done. */
486 #define TX_CFG_CTX_SEL_SHIFT 30
487 
488 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
489  * used for diagnostics only.
490  */
491 #define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
492 #define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
493  pointer. temp hold reg.
494  diagnostics only. */
495 #define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
496 #define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
497  pointer */
498 
499 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
500 #define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */
501 
502 /* current state of all state machines in TX */
503 #define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */
504 #define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */
505 #define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */
506 #define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine.
507  = 0x01 when TX disabled. */
508 #define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */
509 #define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
510  state machine */
511 #define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
512 
513 #define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
514 #define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
515 #define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
516 #define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */
517 
518 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
519  * while the upper 23 bits are taken from the TX descriptor
520  */
521 #define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
522 #define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
523 
524 /* 13 bit registers written by driver w/ descriptor value that follows
525  * last valid xmit descriptor. kick # and complete # values are used by
526  * the xmit dma engine to control tx descr fetching. if > 1 valid
527  * tx descr is available within the cache line being read, cassini will
528  * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
529  */
530 #define REG_TX_KICK0 0x2038 /* TX kick reg #1 */
531 #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
532 #define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
533 #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
534 
535 /* values of TX_COMPLETE_1-4 are written. each completion register
536  * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
537  * NOTE: completion reg values are only written back prior to TX_INTME and
538  * TX_ALL interrupts. at all other times, the most up-to-date index values
539  * should be obtained from the REG_TX_COMPLETE_# registers.
540  * here's the layout:
541  * offset from base addr completion # byte
542  * 0 TX_COMPLETE_1_MSB
543  * 1 TX_COMPLETE_1_LSB
544  * 2 TX_COMPLETE_2_MSB
545  * 3 TX_COMPLETE_2_LSB
546  * 4 TX_COMPLETE_3_MSB
547  * 5 TX_COMPLETE_3_LSB
548  * 6 TX_COMPLETE_4_MSB
549  * 7 TX_COMPLETE_4_LSB
550  */
551 #define TX_COMPWB_SIZE 8
552 #define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back
553  base low */
554 #define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back
555  base high */
556 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
557 #define TX_COMPWB_MSB_SHIFT 0
558 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
559 #define TX_COMPWB_LSB_SHIFT 8
560 #define TX_COMPWB_NEXT(x) ((x) >> 16)
561 
562 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
563  * be 2KB-aligned. */
564 #define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
565 #define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */
566 #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
567 #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
568 
569 /* 16-bit registers hold weights for the weighted round-robin of the
570  * four CBQ TX descr rings. weights correspond to # bytes xferred from
571  * host to TXFIFO in a round of WRR arbitration. can be set
572  * dynamically with new weights set upon completion of the current
573  * packet transfer from host memory to TXFIFO. a dummy write to any of
574  * these registers causes a queue1 pre-emption with all historical bw
575  * deficit data reset to 0 (useful when congestion requires a
576  * pre-emption/re-allocation of network bandwidth
577  */
578 #define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */
579 #define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */
580 #define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */
581 #define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */
582 
583 /* diagnostics access to any TX FIFO location. every access is 65
584  * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
585  * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
586  * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
587  * TX FIFO data integrity is desired, TX DMA should be
588  * disabled. _DATA_HI_Tx should be the last access of the sequence.
589  */
590 #define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
591 #define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
592 #define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */
593 #define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */
594 #define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
595 #define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
596 
597 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
598  * passed for the specified memory
599  */
600 #define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
601 #define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
602  controller state machine */
603 #define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
604 #define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
605 #define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */
606 #define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */
607 #define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */
608 #define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self
609  clears on completion. */
610 
612 #define MAX_RX_DESC_RINGS 2
613 #define MAX_RX_COMP_RINGS 4
614 
615 /* receive DMA channel configuration. default: 0x80910
616  * free ring size = (1 << n)*32 -> [32 - 8k]
617  * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
618  * DEFAULT: 0x80910
619  */
620 #define REG_RX_CFG 0x4000 /* RX config */
621 #define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
622  channel as soon as current
623  frame xfer has completed.
624  driver should disable MAC
625  for 200ms before disabling
626  RX */
627 #define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
628  free desc ring.
629  def: 0x8 = 8k */
630 #define RX_CFG_DESC_RING_SHIFT 1
631 #define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
632  ring. def: 0x8 = 32k */
633 #define RX_CFG_COMP_RING_SHIFT 5
634 #define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
635  batching. def: 0x0 =
636  enabled */
637 #define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
638  data byte of the packet
639  w/in 8 byte boundares.
640  this swivels the data
641  DMA'ed to header
642  buffers, jumbo buffers
643  when header split is not
644  requested and MTU sized
645  buffers. def: 0x2 */
646 #define RX_CFG_SWIVEL_SHIFT 10
647 
648 /* cassini+ only */
649 #define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
650  RX free desc ring 2.
651  def: 0x8 = 8k */
652 #define RX_CFG_DESC_RING1_SHIFT 16
653 
654 
655 /* the page size register allows cassini chips to do the following with
656  * received data:
657  * [--------------------------------------------------------------] page
658  * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
659  * |--------------| = PAGE_SIZE_BUFFER_STRIDE
660  * page = PAGE_SIZE
661  * offset = PAGE_SIZE_MTU_OFF
662  * for the above example, MTU_BUFFER_COUNT = 4.
663  * NOTE: as is apparent, you need to ensure that the following holds:
664  * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
665  * DEFAULT: 0x48002002 (8k pages)
666  */
667 #define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
668 #define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
669  by receive descriptors.
670  if jumbo buffers are
671  supported the page size
672  should not be < 8k.
673  0b00 = 2k, 0b01 = 4k
674  0b10 = 8k, 0b11 = 16k
675  DEFAULT: 8k */
676 #define RX_PAGE_SIZE_SHIFT 0
677 #define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
678  packs into a page.
679  DEFAULT: 4 */
680 #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
681 #define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
682  each MTU buffer +
683  offset from each
684  other.
685  0b00 = 1k, 0b01 = 2k
686  0b10 = 4k, 0b11 = 8k
687  DEFAULT: 0x1 */
688 #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
689 #define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
690  hw writes the MTU buffer
691  into.
692  0b00 = 0,
693  0b01 = 64 bytes
694  0b10 = 96, 0b11 = 128
695  DEFAULT: 0x1 */
696 #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
697 
698 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
699  * shadow write pointers enable retries in case of early receive aborts.
700  * DEFAULT: 0x0. generated on 64-bit boundaries.
701  */
702 #define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
703 #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
704 #define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
705  pointer */
706 #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
707  pointer */
708 #define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
709  pointer. (8-bit counter) */
710 
711 /* current state of RX DMA state engines + other info
712  * DEFAULT: 0x0
713  */
714 #define REG_RX_DEBUG 0x401C /* RX debug */
715 #define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC:
716  0x0 = idle, 0x1 = load_bop
717  0x2 = load 1, 0x3 = load 2
718  0x4 = load 3, 0x5 = load 4
719  0x6 = last detect
720  0x7 = wait req
721  0x8 = wait req statuss 1st
722  0x9 = load st
723  0xa = bubble mac
724  0xb = error */
725 #define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and
726  RX FIFO:
727  0x0 = idle, 0x1 = hp xfr
728  0x2 = wait hp ready
729  0x3 = wait flow code
730  0x4 = fifo xfer
731  0x5 = make status
732  0x6 = csum ready
733  0x7 = error */
734 #define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine
735  w/ MAC:
736  0x0 = idle
737  0x1 = wait xoff ack
738  0x2 = wait xon
739  0x3 = wait xon ack */
740 #define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
741  states:
742  0x0 = idle data
743  0x1 = header begin
744  0x2 = xfer header
745  0x3 = xfer header ld
746  0x4 = mtu begin
747  0x5 = xfer mtu
748  0x6 = xfer mtu ld
749  0x7 = jumbo begin
750  0x8 = xfer jumbo
751  0x9 = xfer jumbo ld
752  0xa = reas begin
753  0xb = xfer reas
754  0xc = flush tag
755  0xd = xfer reas ld
756  0xe = error
757  0xf = bubble idle */
758 #define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine
759  states:
760  0x0 = idle desc
761  0x1 = wait ack
762  0x9 = wait ack 2
763  0x2 = fetch desc 1
764  0xa = fetch desc 2
765  0x3 = load ptrs
766  0x4 = wait dma
767  0x5 = wait ack batch
768  0x6 = post batch
769  0x7 = xfr done */
770 #define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
771  interrupt queue */
772 #define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer
773  of the interrupt queue */
774 
775 /* flow control frames are emitted using two PAUSE thresholds:
776  * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
777  * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
778  * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
779  * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
780  * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
781  * value is is 0x6F.
782  * DEFAULT: 0x00078
783  */
784 #define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
785 #define RX_PAUSE_THRESH_QUANTUM 64
786 #define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
787  RX FIFO occupancy >
788  value*64B */
789 #define RX_PAUSE_THRESH_OFF_SHIFT 0
790 #define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
791  emitting XOFF PAUSE when RX
792  FIFO occupancy falls below
793  this value*64B. must be
794  < XOFF threshold. if =
795  RX_FIFO_SIZE< XON frames are
796  never emitted. */
797 #define RX_PAUSE_THRESH_ON_SHIFT 12
798 
799 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
800  * valid RX descriptors are available, Cassini will read 4 at a time.
801  * writing N means that all desc up to *but* excluding N are available. N must
802  * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
803  * DEFAULT: 0 on reset
804  */
805 #define REG_RX_KICK 0x4024 /* RX kick reg */
806 
807 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
808  * lower 13 bits of the low register are hard-wired to 0.
809  */
810 #define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
811  base low */
812 #define REG_RX_DB_HI 0x402C /* RX descriptor ring
813  base hi */
814 #define REG_RX_CB_LOW 0x4030 /* RX completion ring
815  base low */
816 #define REG_RX_CB_HI 0x4034 /* RX completion ring
817  base hi */
818 /* 13-bit register indicate desc used by cassini for receive frames. used
819  * for diagnostic purposes.
820  * DEFAULT: 0 on reset
821  */
822 #define REG_RX_COMP 0x4038 /* (ro) RX completion */
823 
824 /* HEAD and TAIL are used to control RX desc posting and interrupt
825  * generation. hw moves the head register to pass ownership to sw. sw
826  * moves the tail register to pass ownership back to hw. to give all
827  * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
828  * more entries are available, DMA will pause and an interrupt will be
829  * generated to indicate no more entries are available. sw can use
830  * this interrupt to reduce the # of times it must update the
831  * completion tail register.
832  * DEFAULT: 0 on reset
833  */
834 #define REG_RX_COMP_HEAD 0x403C /* RX completion head */
835 #define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
836 
837 /* values used for receive interrupt blanking. loaded each time the ISR is read
838  * DEFAULT: 0x00000000
839  */
840 #define REG_RX_BLANK 0x4044 /* RX blanking register
841  for ISR read */
842 #define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
843  this many sets of completion
844  writebacks (up to 2 packets)
845  occur since the last time
846  the ISR was read. 0 = no
847  packet blanking */
848 #define RX_BLANK_INTR_PKT_SHIFT 0
849 #define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted
850  if that many clocks were
851  counted since last time the
852  ISR was read.
853  each count is 512 core
854  clocks (125MHz). 0 = no
855  time blanking */
856 #define RX_BLANK_INTR_TIME_SHIFT 12
857 
858 /* values used for interrupt generation based on threshold values of how
859  * many free desc and completion entries are available for hw use.
860  * DEFAULT: 0x00000000
861  */
862 #define REG_RX_AE_THRESH 0x4048 /* RX almost empty
863  thresholds */
864 #define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be
865  generated if # desc
866  avail for hw use <=
867  # */
868 #define RX_AE_THRESH_FREE_SHIFT 0
869 #define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be
870  generated if # of
871  completion entries
872  avail for hw use <=
873  # */
874 #define RX_AE_THRESH_COMP_SHIFT 13
875 
876 /* probabilities for random early drop (RED) thresholds on a FIFO threshold
877  * basis. probability should increase when the FIFO level increases. control
878  * packets are never dropped and not counted in stats. probability programmed
879  * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
880  * DEFAULT: 0x00000000
881  */
882 #define REG_RX_RED 0x404C /* RX random early detect enable */
883 #define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */
884 #define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */
885 #define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */
886 #define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */
887 
888 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
889  * RX control FIFO = # of packets in RX FIFO.
890  * DEFAULT: 0x0
891  */
892 #define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
893 #define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */
894 #define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */
895 #define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
896 #define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
897 #define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
898 #define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
899  high */
900 
901 /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
902  * START/COMPLETE is writeable. START will clear when the BIST has completed
903  * checking all 17 RAMS.
904  * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
905  */
906 #define REG_RX_BIST 0x4060 /* (ro) RX BIST */
907 #define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */
908 #define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */
909 #define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */
910 #define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */
911 #define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */
912 #define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */
913 #define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */
914 #define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */
915 #define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */
916 #define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */
917 #define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */
918 #define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */
919 #define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */
920 #define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */
921 #define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */
922 #define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */
923 #define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
924 #define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */
925 #define RX_BIST_SUMMARY 0x00000002 /* when BIST complete,
926  summary pass bit
927  contains AND of BIST
928  results of all 16
929  RAMS */
930 #define RX_BIST_START 0x00000001 /* write 1 to start
931  BIST. self clears
932  on completion. */
933 
934 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
935  * from to retrieve packet control info.
936  * DEFAULT: 0
937  */
938 #define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
939  write ptr */
940 #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
941  ptr */
942 
943 /* receive interrupt blanking. loaded each time interrupt alias register is
944  * read.
945  * DEFAULT: 0x0
946  */
947 #define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
948  alias read */
949 #define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if #
950  completion writebacks
951  > # since last ISR
952  read. 0 = no
953  blanking. up to 2
954  packets per
955  completion wb. */
956 #define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if #
957  clocks > # since last
958  ISR read. each count
959  is 512 core clocks
960  (125MHz). 0 = no
961  blanking. */
962 
963 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
964  * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
965  * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
966  * to normal operation after diagnostics, write to address location 0x0.
967  * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
968  * be the last write access of a write sequence.
969  * DEFAULT: undefined
970  */
971 #define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
972 #define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
973 #define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */
974 #define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */
975 #define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */
976 
977 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
978  * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
979  * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
980  * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
981  * should be last write access of the write sequence.
982  * DEFAULT: undefined
983  */
984 #define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
985  Batching FIFO addr */
986 #define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
987  low */
988 #define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
989  mid */
990 #define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
991  hi and flow id */
992 #define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */
993 #define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */
994 
995 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
996  * DEFAULT: undefined
997  */
998 #define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */
999 #define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */
1000 #define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */
1001 #define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high
1002  T0 */
1003 #define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high
1004  T1 */
1005 
1006 /* 64-bit pointer to receive data buffer in host memory used for headers and
1007  * small packets. MSB in high register. loaded by DMA state machine and
1008  * increments as DMA writes receive data. only 50 LSB are incremented. top
1009  * 13 bits taken from RX descriptor.
1010  * DEFAULT: undefined
1011  */
1012 #define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr
1013  low */
1014 #define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
1015  high */
1016 #define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
1017  low */
1018 #define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
1019  high */
1020 
1021 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1022  * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1023  * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1024  * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1025  * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1026  * layout:
1027  * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1028  * DEFAULT: undefined
1029  */
1030 #define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table
1031  address */
1032 #define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */
1033 
1034 #define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
1035  data low */
1036 #define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
1037  data mid */
1038 #define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
1039  data high */
1040 
1041 /* cassini+ only */
1042 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1043  * 0. same semantics as primary desc/complete rings.
1044  */
1045 #define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring
1046  2 base low */
1047 #define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring
1048  2 base high */
1049 #define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring
1050  2 base low. 4 total */
1051 #define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring
1052  2 base high. 4 total */
1053 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1054 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1055 #define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
1056 #define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
1057  reg */
1058 #define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
1059  head reg. 4 total. */
1060 #define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
1061  tail reg. 4 total. */
1062 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1063 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1064 #define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2
1065  thresholds */
1066 #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1067 #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1068 
1071 /* RX parser configuration register.
1072  * DEFAULT: 0x1651004
1073  */
1074 #define REG_HP_CFG 0x4140 /* header parser
1075  configuration reg */
1076 #define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */
1077 #define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors
1078  0 = 64. 0x3f = 63 */
1079 #define HP_CFG_NUM_CPU_SHIFT 2
1080 #define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment
1081  TCP seq # by one when
1082  stored in FDBM */
1083 #define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data
1084  needed to be considered
1085  for reassembly */
1086 #define HP_CFG_TCP_THRESH_SHIFT 9
1087 
1088 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1089  * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1090  * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1091  * of sequence.
1092  * DEFAULT: undefined
1093  */
1094 #define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM
1095  address */
1096 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1097 #define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM
1098  data low */
1099 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1100 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1101 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1102 #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1103 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1104 #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1105 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1106 #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1107 #define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM
1108  data mid */
1109 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1110 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1111 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1112 #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1113 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1114 #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1115 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1116 #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1117 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1118 #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1119 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1120 #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1121 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1122 #define HP_INSTR_RAM_MID_OP_SHIFT 30
1123 #define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM
1124  data high */
1125 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1126 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1127 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1128 #define HP_INSTR_RAM_HI_MASK_SHIFT 16
1129 
1130 /* PIO access into RX Header parser data RAM and flow database.
1131  * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1132  * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1133  * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1134  * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1135  * flow database.
1136  * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1137  * should be the last write access of the write sequence.
1138  * DEFAULT: undefined
1139  */
1140 #define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB
1141  RAM address */
1142 #define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte
1143  locations in header
1144  parser data ram to
1145  read/write */
1146 #define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1147  in the flow database */
1148 #define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */
1149 
1150 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1151  * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1152  * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1153  * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1154  * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1155  * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1156  * FLOW_DB(10) = bit 0 has value for flow valid
1157  * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1158  */
1159 #define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */
1160 #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1161 
1162 /* diagnostics for RX Header Parser block.
1163  * ASUN: the header parser state machine register is used for diagnostics
1164  * purposes. however, the spec doesn't have any details on it.
1165  */
1166 #define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */
1167 #define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */
1168 #define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */
1169 #define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
1170 #define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU
1171  number */
1172 #define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */
1173 
1174 #define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */
1175 #define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */
1176 #define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */
1177 #define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */
1178 #define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */
1179 
1180 #define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */
1181 #define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
1182 #define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start
1183  start offset */
1184 #define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */
1185 #define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */
1186 #define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o
1187  reassembly */
1188 #define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split
1189  enable */
1190 #define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload
1191  check */
1192 #define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
1193  equal to zero */
1194 #define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload
1195  chk */
1196 #define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
1197  threshold */
1198 #define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
1199 #define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */
1200 #define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */
1201 #define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */
1202 #define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */
1203 #define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */
1204 
1205 /* BIST for header parser(HP) and flow database memories (FDBM). set _START
1206  * to start BIST. controller clears _START on completion. _START can also
1207  * be cleared to force termination of BIST. a bit set indicates that that
1208  * memory passed its BIST.
1209  */
1210 #define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */
1211 #define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */
1212 #define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */
1213 #define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */
1214 #define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */
1215 #define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */
1216 #define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */
1217 #define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0
1218  bank 0 */
1219 #define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1
1220  bank 0 */
1221 #define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2
1222  bank 0 */
1223 #define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3
1224  bank 0 */
1225 #define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0
1226  bank 1 */
1227 #define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1
1228  bank 2 */
1229 #define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2
1230  bank 1 */
1231 #define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3
1232  bank 1 */
1233 #define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence
1234  RAM */
1235 #define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */
1236 #define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */
1237 
1238 
1240 /* reset bits are set using a PIO write and self-cleared after the command
1241  * execution has completed.
1242  */
1243 #define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset
1244  command (default: 0x0) */
1245 #define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset
1246  command (default: 0x0) */
1247 /* execute a pause flow control frame transmission
1248  DEFAULT: 0x0XXXX */
1249 #define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */
1250 #define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time
1251  to be sent on network
1252  in units of slot
1253  times */
1254 #define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl
1255  frame on network */
1256 
1257 /* bit set indicates that event occurred. auto-cleared when status register
1258  * is read and have corresponding mask bits in mask register. events will
1259  * trigger an interrupt if the corresponding mask bit is 0.
1260  * status register default: 0x00000000
1261  * mask register default = 0xFFFFFFFF on reset
1262  */
1263 #define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
1264 #define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
1265  transmision */
1266 #define MAC_TX_UNDERRUN 0x0002 /* terminated frame
1267  transmission due to
1268  data starvation in the
1269  xmit data path */
1270 #define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed
1271  length passed to TX MAC
1272  by the DMA engine */
1273 #define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal
1274  collision counter */
1275 #define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive
1276  collision counter */
1277 #define MAC_TX_COLL_LATE 0x0020 /* rollover of the late
1278  collision counter */
1279 #define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first
1280  collision counter */
1281 #define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer
1282  timer */
1283 #define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak
1284  attempts counter */
1285 
1286 #define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
1287 #define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of
1288  a frame */
1289 #define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to
1290  RX FIFO overflow */
1291 #define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
1292  counter */
1293 #define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment
1294  error counter */
1295 #define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
1296  counter */
1297 #define MAC_RX_LEN_ERR 0x0020 /* rollover of length
1298  error counter */
1299 #define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
1300  violation error */
1301 
1302 /* DEFAULT: 0xXXXX0000 on reset */
1303 #define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */
1304 #define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful
1305  reception of a
1306  pause control
1307  frame */
1308 #define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a
1309  transition from
1310  "not paused" to
1311  "paused" */
1312 #define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a
1313  transition from
1314  "paused" to "not
1315  paused" */
1316 #define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time
1317  operand that was
1318  received in the last
1319  pause flow control
1320  frame */
1321 
1322 /* layout identical to TX MAC[8:0] */
1323 #define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */
1324 /* layout identical to RX MAC[6:0] */
1325 #define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
1326 /* layout identical to CTRL MAC[2:0] */
1327 #define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
1328 
1329 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1330  * imposed before writes to other bits in the TX_MAC_CFG register or any of
1331  * the MAC parameters is performed. delay dependent upon time required to
1332  * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1333  * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1334  * alternatively, just poll TX_CFG_EN until it reads back as 0.
1335  * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1336  * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1337  * be 0x200 (slot time of 512 bytes)
1338  */
1339 #define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */
1340 #define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will
1341  force TXMAC state
1342  machine to remain in
1343  idle state or to
1344  transition to idle state
1345  on completion of an
1346  ongoing packet. */
1347 #define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral
1348  process. set to 1 when
1349  full duplex and 0 when
1350  half duplex */
1351 #define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff
1352  algorithm. set to 1 when
1353  full duplex and 0 when
1354  half duplex */
1355 #define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the
1356  Rx-to-TX IPG. after
1357  receiving a frame, TX
1358  MAC will reset its
1359  deferral process to
1360  carrier sense for the
1361  amount of time = IPG0 +
1362  IPG1 and commit to
1363  transmission for time
1364  specified in IPG2. when
1365  0 or when xmitting frames
1366  back-to-pack (Tx-to-Tx
1367  IPG), TX MAC ignores
1368  IPG0 and will only use
1369  IPG1 for deferral time.
1370  IPG2 still used. */
1371 #define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily
1372  give up on frame
1373  xmission. if backoff
1374  algorithm reaches the
1375  ATTEMPT_LIMIT, it will
1376  clear attempts counter
1377  and continue trying to
1378  send the frame as
1379  specified by
1380  GIVE_UP_LIM. when 0,
1381  TX MAC will execute
1382  standard CSMA/CD prot. */
1383 #define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will
1384  continue to try to xmit
1385  until successful. when
1386  0, TX MAC will continue
1387  to try xmitting until
1388  successful or backoff
1389  algorithm reaches
1390  ATTEMPT_LIMIT*16 */
1391 #define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable
1392  backoff algorithm. TX
1393  MAC will not back off
1394  after a xmission attempt
1395  that resulted in a
1396  collision. */
1397 #define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that
1398  deferral process is reset
1399  in response to carrier
1400  sense during the entire
1401  duration of IPG. TX MAC
1402  will only commit to frame
1403  xmission after frame
1404  xmission has actually
1405  begun. */
1406 #define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate
1407  CRC for all xmitted
1408  packets. when clear, CRC
1409  generation is dependent
1410  upon NO_CRC bit in the
1411  xmit control word from
1412  TX DMA */
1413 #define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the
1414  carrier extension
1415  feature. this allows for
1416  longer collision domains
1417  by extending the carrier
1418  and collision window
1419  from the end of FCS until
1420  the end of the slot time
1421  if necessary. Required
1422  for half-duplex at 1Gbps,
1423  clear otherwise. */
1424 
1425 /* when CRC is not stripped, reassembly packets will not contain the CRC.
1426  * these will be stripped by HRP because it reassembles layer 4 data, and the
1427  * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1428  * when passed to the host. to ensure proper operation, need to wait 3.2ms
1429  * after clearing RX_CFG_EN before writing to any other RX MAC registers
1430  * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1431  * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1432  * restrictions as CFG_EN.
1433  */
1434 #define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
1435 #define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
1436 #define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0.
1437  feature not supported */
1438 #define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
1439  last 4 bytes of a
1440  received frame. */
1441 #define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */
1442 #define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid
1443  multicast frames (group
1444  bit in DA field set) */
1445 #define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter
1446  multicast addresses */
1447 #define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
1448  address filtering regs
1449  to filter both unicast
1450  and multicast
1451  addresses */
1452 #define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to
1453  RX DMA by setting BAD
1454  bit but not Abort bit
1455  in the status. CRC,
1456  framing, and length errs
1457  will not increment
1458  error counters. frames
1459  which don't match dest
1460  addr will be passed up
1461  w/ BAD bit set. */
1462 #define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of
1463  packet bursts generated
1464  by carrier extension
1465  with packet bursting
1466  senders. only applies
1467  to half-duplex 1Gbps */
1468 
1469 /* DEFAULT: 0x0 */
1470 #define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */
1471 #define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for
1472  sending pause flow ctrl
1473  frames */
1474 #define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received
1475  pause flow ctrl frames */
1476 #define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl
1477  packets to RX DMA */
1478 
1479 /* to ensure proper operation, a global initialization sequence should be
1480  * performed when a loopback config is entered or exited. if programmed after
1481  * a hw or global sw reset, RX/TX MAC software reset and initialization
1482  * should be done to ensure stable clocking.
1483  * DEFAULT: 0x0
1484  */
1485 #define REG_MAC_XIF_CFG 0x603C /* XIF config reg */
1486 #define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers
1487  on MII xmit bus */
1488 #define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data
1489  path to GMII recv data
1490  path. phy mode register
1491  clock selection must be
1492  set to GMII mode and
1493  GMII_MODE should be set
1494  to 1. in loopback mode,
1495  REFCLK will drive the
1496  entire mac core. 0 for
1497  normal operation. */
1498 #define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data
1499  path during packet
1500  xmission. clear to 0
1501  in any full duplex mode,
1502  in any loopback mode,
1503  or in half-duplex SERDES
1504  or SLINK modes. set when
1505  in half-duplex when
1506  using external phy. */
1507 #define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII
1508  clocks and datapath */
1509 #define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable
1510  external tristate buffer
1511  on the MII receive
1512  bus. */
1513 #define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */
1514 #define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */
1515 
1516 #define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
1517  recommended: 0x00 */
1518 #define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
1519  recommended: 0x08 */
1520 #define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
1521  recommended: 0x04 */
1522 #define REG_MAC_SLOT_TIME 0x604C /* slot time reg
1523  recommended: 0x40 */
1524 #define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg
1525  recommended: 0x40 */
1526 
1527 /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1528  * recommended value: 0x2000.05EE
1529  */
1530 #define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */
1531 #define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */
1532 #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1533 #define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */
1534 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1535 #define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of
1536  preamble bytes that the
1537  TX MAC will xmit at the
1538  beginning of each frame
1539  value should be 2 or
1540  greater. recommended
1541  value: 0x07 */
1542 #define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration
1543  of jam in units of media
1544  byte time. recommended
1545  value: 0x04 */
1546 #define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. #
1547  of attempts TX MAC will
1548  make to xmit a frame
1549  before it resets its
1550  attempts counter. after
1551  the limit has been
1552  reached, TX MAC may or
1553  may not drop the frame
1554  dependent upon value
1555  in TX_MAC_CFG.
1556  recommended
1557  value: 0x10 */
1558 #define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg.
1559  type field of a MAC
1560  ctrl frame. recommended
1561  value: 0x8808 */
1562 
1563 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1564  * register contains comparison
1565  * 0 16 MSB of primary MAC addr [47:32] of DA field
1566  * 1 16 middle bits "" [31:16] of DA field
1567  * 2 16 LSB "" [15:0] of DA field
1568  * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1569  * 4*x 16 middle bits "" [31:16]
1570  * 5*x 16 LSB "" [15:0]
1571  * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1572  * 43 16 middle bits "" [31:16]
1573  * 44 16 LSB "" [15:0]
1574  * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1575  * if there is a match, MAC will set the bit for alternative address
1576  * filter pass [15]
1577 
1578  * here is the map of registers given MAC address notation: a:b:c:d:e:f
1579  * ab cd ef
1580  * primary addr reg 2 reg 1 reg 0
1581  * alt addr 1 reg 5 reg 4 reg 3
1582  * alt addr x reg 5*x reg 4*x reg 3*x
1583  * ctrl addr reg 44 reg 43 reg 42
1584  */
1585 #define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */
1586 #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1587 #define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg
1588  [47:32] */
1589 #define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg
1590  [31:16] */
1591 #define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg
1592  [15:0] */
1593 #define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1
1594  mask reg. 8-bit reg
1595  contains nibble mask for
1596  reg 2 and 1. */
1597 #define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
1598  reg */
1599 
1600 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1601  * 16-bit registers contain bits of the hash table.
1602  * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1603  * e.g., 15 -> [15:0], 0 -> [255:240]
1604  */
1605 #define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */
1606 #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1607 
1608 /* statistics registers. these registers generate an interrupt on
1609  * overflow. recommended initialization: 0x0000. most are 16-bits except
1610  * for PEAK_ATTEMPTS register which is 8 bits.
1611  */
1612 #define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision
1613  counter. */
1614 #define REG_MAC_COLL_FIRST 0x61A4 /* first attempt
1615  successful collision
1616  counter */
1617 #define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision
1618  counter */
1619 #define REG_MAC_COLL_LATE 0x61AC /* late collision counter */
1620 #define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base
1621  is the media byte
1622  clock/256 */
1623 #define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */
1624 #define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */
1625 #define REG_MAC_LEN_ERR 0x61BC /* length error counter */
1626 #define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */
1627 #define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */
1628 #define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation
1629  error counter */
1630 
1631 /* misc registers */
1632 #define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg.
1633  10-bit register used as a
1634  seed for the random number
1635  generator for the CSMA/CD
1636  backoff algorithm. only
1637  programmed after power-on
1638  reset and should be a
1639  random value which has a
1640  high likelihood of being
1641  unique for each MAC
1642  attached to a network
1643  segment (e.g., 10 LSB of
1644  MAC address) */
1645 
1646 /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1647  * map
1648  */
1649 
1650 /* 27-bit register has the current state for key state machines in the MAC */
1651 #define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */
1652 #define MAC_SM_RLM_MASK 0x07800000
1653 #define MAC_SM_RLM_SHIFT 23
1654 #define MAC_SM_RX_FC_MASK 0x00700000
1655 #define MAC_SM_RX_FC_SHIFT 20
1656 #define MAC_SM_TLM_MASK 0x000F0000
1657 #define MAC_SM_TLM_SHIFT 16
1658 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1659 #define MAC_SM_ENCAP_SM_SHIFT 12
1660 #define MAC_SM_TX_REQ_MASK 0x00000C00
1661 #define MAC_SM_TX_REQ_SHIFT 10
1662 #define MAC_SM_TX_FC_MASK 0x000003C0
1663 #define MAC_SM_TX_FC_SHIFT 6
1664 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1665 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1666 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1667 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1668 
1672 #define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1673  1 -> 0 will generate a
1674  rising edge. 0 -> 1 will
1675  generate a falling edge. */
1676 #define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1677  register generates data */
1678 #define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1679  enable. enable when
1680  xmitting data from MIF to
1681  transceiver. */
1682 
1683 /* 32-bit register serves as an instruction register when the MIF is
1684  * programmed in frame mode. load this register w/ a valid instruction
1685  * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1686  * execution completion. during a read operation, this register will also
1687  * contain the 16-bit data returned by the tranceiver. unless specified
1688  * otherwise, fields are considered "don't care" when polling for
1689  * completion.
1690  */
1691 #define REG_MIF_FRAME 0x620C /* MIF frame/output reg */
1692 #define MIF_FRAME_START_MASK 0xC0000000 /* start of frame.
1693  load w/ 01 when
1694  issuing an instr */
1695 #define MIF_FRAME_ST 0x40000000 /* STart of frame */
1696 #define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a
1697  write. 10 for a
1698  read */
1699 #define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
1700 #define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */
1701 #define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when
1702  issuing an instr,
1703  this field should be
1704  loaded w/ the XCVR
1705  addr */
1706 #define MIF_FRAME_PHY_ADDR_SHIFT 23
1707 #define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address.
1708  when issuing an instr,
1709  addr of register
1710  to be read/written */
1711 #define MIF_FRAME_REG_ADDR_SHIFT 18
1712 #define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB.
1713  when issuing an instr,
1714  set this bit to 1 */
1715 #define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB.
1716  when issuing an instr,
1717  set this bit to 0.
1718  when polling for
1719  completion, 1 means
1720  that instr execution
1721  has been completed */
1722 #define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload
1723  load with 16-bit data
1724  to be written in
1725  transceiver reg for a
1726  write. doesn't matter
1727  in a read. when
1728  polling for
1729  completion, field is
1730  "don't care" for write
1731  and 16-bit data
1732  returned by the
1733  transceiver for a
1734  read (if valid bit
1735  is set) */
1736 #define REG_MIF_CFG 0x6210 /* MIF config reg */
1737 #define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
1738  0 -> select MDIO_0 */
1739 #define MIF_CFG_POLL_EN 0x0002 /* enable polling
1740  mechanism. if set,
1741  BB_MODE should be 0 */
1742 #define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
1743  0 -> frame mode */
1744 #define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be
1745  used by polling mode.
1746  only meaningful if POLL_EN
1747  is set to 1 */
1748 #define MIF_CFG_POLL_REG_SHIFT 3
1749 #define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
1750  when MDIO_0 is idle,
1751  1 -> tranceiver is
1752  connected to MDIO_0.
1753  when MIF is communicating
1754  w/ MDIO_0 in bit-bang
1755  mode, this bit indicates
1756  the incoming bit stream
1757  during a read op */
1758 #define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose.
1759  when MDIO_1 is idle,
1760  1 -> transceiver is
1761  connected to MDIO_1.
1762  when MIF is communicating
1763  w/ MDIO_1 in bit-bang
1764  mode, this bit indicates
1765  the incoming bit stream
1766  during a read op */
1767 #define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to
1768  be polled */
1769 #define MIF_CFG_POLL_PHY_SHIFT 10
1770 
1771 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1772  * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1773  * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1774  * set. DEFAULT: 0xFFFF
1775  */
1776 #define REG_MIF_MASK 0x6214 /* MIF mask reg */
1777 
1778 /* 32-bit register used when in poll mode. auto-cleared after being read */
1779 #define REG_MIF_STATUS 0x6218 /* MIF status reg */
1780 #define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains
1781  the "latest image"
1782  update of the XCVR
1783  reg being read */
1784 #define MIF_STATUS_POLL_DATA_SHIFT 16
1785 #define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates
1786  which bits in the
1787  POLL_DATA field have
1788  changed since the
1789  MIF_STATUS reg was
1790  last read */
1791 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1792 
1793 /* 7-bit register has current state for all state machines in the MIF */
1794 #define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */
1795 #define MIF_SM_CONTROL_MASK 0x07 /* control state machine
1796  state */
1797 #define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine
1798  state */
1799 
1805 /* the auto-negotiation enable bit should be programmed the same at
1806  * the link partner as in the local device to enable auto-negotiation to
1807  * complete. when that bit is reprogrammed, auto-neg/manual config is
1808  * restarted automatically.
1809  * DEFAULT: 0x1040
1810  */
1811 #define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */
1812 #define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on
1813  writes */
1814 #define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS
1815  to MAC interface is
1816  activated regardless
1817  of activity */
1818 #define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS
1819  behaviour same for
1820  half and full dplx */
1821 #define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing.
1822  restart auto-
1823  negotiation */
1824 #define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
1825  on writes */
1826 #define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored
1827  on writes */
1828 #define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes
1829  through automatic
1830  link config before it
1831  can be used. when 0,
1832  link can be used
1833  w/out any link config
1834  phase */
1835 #define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
1836  writes */
1837 #define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1838  when done */
1839 
1840 /* DEFAULT: 0x0108 */
1841 #define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */
1842 #define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */
1843 #define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */
1844 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1845  0 -> link down. 0 is
1846  latched so that 0 is
1847  kept until read. read
1848  2x to determine if the
1849  link has gone up again */
1850 #define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform
1851  auto-neg) */
1852 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
1853  from received link code
1854  word. only valid after
1855  auto-neg completed */
1856 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1857  completed
1858  0 -> auto-negotiation not
1859  completed */
1860 #define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an
1861  indication that this is
1862  a 1000 Base-X PHY. writes
1863  to it are ignored */
1864 
1865 /* used during auto-negotiation.
1866  * DEFAULT: 0x00E0
1867  */
1868 #define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement
1869  reg */
1870 #define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex
1871  1000 Base-X */
1872 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
1873  1000 Base-X */
1874 #define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE
1875  symmetric capability */
1876 #define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE
1877  asymmetric capability */
1878 #define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13
1879  to optionally indicate to
1880  link partner that chip is
1881  going off-line. bit12 will
1882  get set when signal
1883  detect == FAIL and will
1884  remain set until
1885  successful negotiation */
1886 #define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */
1887 #define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */
1888 
1889 /* contents updated as a result of autonegotiation. layout and definitions
1890  * identical to PCS_MII_ADVERT
1891  */
1892 #define REG_PCS_MII_LPA 0x900C /* PCS MII link partner
1893  ability reg */
1894 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1895 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1896 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1897 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1898 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1899 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1900 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1901 
1902 /* DEFAULT: 0x0 */
1903 #define REG_PCS_CFG 0x9010 /* PCS config reg */
1904 #define PCS_CFG_EN 0x01 /* enable PCS. must be
1905  0 when modifying
1906  PCS_MII_ADVERT */
1907 #define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to
1908  OK. bit is
1909  non-resettable */
1910 #define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation
1911  of optical signal to make
1912  signal detect okay when
1913  signal is low */
1914 #define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter
1915  measurements. a single
1916  code group is xmitted
1917  regularly.
1918  0x0 = normal operation
1919  0x1 = high freq test
1920  pattern, D21.5
1921  0x2 = low freq test
1922  pattern, K28.7
1923  0x3 = reserved */
1924 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1925  negotiation timer to
1926  a few cycles for test
1927  purposes */
1928 
1929 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1930 #define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine
1931  and diagnostic reg */
1932 #define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate
1933  xmission of idle.
1934  otherwise, xmission of
1935  a packet */
1936 #define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception
1937  of idle. otherwise,
1938  reception of packet */
1939 #define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of
1940  sync */
1941 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
1942  indicates reception of
1943  Config codes. cycling
1944  through 0-1 indicates
1945  reception of idles */
1946 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1947 #define SM_LINK_STATE_UP 0x00016000 /* link state is up */
1948 
1949 #define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to
1950  recept of Config
1951  codes */
1952 #define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to
1953  loss of sync */
1954 #define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes
1955  from OK to FAIL. bit29
1956  will also be set if
1957  this is set */
1958 #define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to
1959  receipt of breaklink
1960  C codes from partner.
1961  C codes w/ 0 content
1962  received triggering
1963  start/restart of
1964  autonegotiation.
1965  should be sent for
1966  no longer than 20ms */
1967 #define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being
1968  initialized. see serdes
1969  state reg */
1970 #define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or
1971  not received */
1972 #define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not
1973  achieved */
1974 #define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes
1975  w/ ack bit set */
1976 #define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues
1977  to send C codes
1978  instead of idle
1979  symbols or pkt data */
1980 
1981 /* this register indicates interrupt changes in specific PCS MII status bits.
1982  * PCS_INT may be masked at the ISR level. only a single bit is implemented
1983  * for link status change.
1984  */
1985 #define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */
1986 #define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed
1987  since last read */
1988 
1989 /* control which network interface is used. no more than one bit should
1990  * be set.
1991  * DEFAULT: none
1992  */
1993 #define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */
1994 #define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and
1995  MII/GMII is selected.
1996  selection between MII and
1997  GMII is controlled by
1998  XIF_CFG */
1999 #define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the
2000  10-bit interface */
2001 
2002 /* input to serdes chip or serialink block */
2003 #define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */
2004 #define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on
2005  serdes interface */
2006 #define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier
2007  detection. should be
2008  0x0 for normal
2009  operation */
2010 #define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2011  to REFCLK when set.
2012  when clear, receiver
2013  clock locks to incoming
2014  serial data */
2015 
2016 /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2017  * should be 0x0 for normal operations.
2018  * 0b000 normal operation, PROM address[3:0] selected
2019  * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2020  * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2021  * 0b011 txmac req, tx ack, tx tag, tx retry req
2022  * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2023  * 0b101 R period RX, R period TX, R period HP, R period BIM
2024  * DEFAULT: 0x0
2025  */
2026 #define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */
2027 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2028 
2029 /* used for diagnostics. this register indicates progress of the SERDES
2030  * boot up.
2031  * 0b00 undergoing reset
2032  * 0b01 waiting 500us while lockrefn is asserted
2033  * 0b10 waiting for comma detect
2034  * 0b11 receive data is synchronized
2035  * DEFAULT: 0x0
2036  */
2037 #define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */
2038 #define PCS_SERDES_STATE_MASK 0x03
2039 
2040 /* used for diagnostics. indicates number of packets transmitted or received.
2041  * counters rollover w/out generating an interrupt.
2042  * DEFAULT: 0x0
2043  */
2044 #define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */
2045 #define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */
2046 #define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS
2047  whether they
2048  encountered an error
2049  or not */
2050 
2054 #define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time
2055  access */
2056 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2057 
2058 #define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus
2059  device */
2060 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2061 
2062 /* entropy device */
2063 #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2064 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2065 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2066 #define ENTROPY_STATUS_DRDY 0x01
2067 #define ENTROPY_STATUS_BUSY 0x02
2068 #define ENTROPY_STATUS_CIPHER 0x04
2069 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2070 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2071 #define ENTROPY_MODE_KEY_MASK 0x07
2072 #define ENTROPY_MODE_ENCRYPT 0x40
2073 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2074 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2075 #define ENTROPY_RESET_DES_IO 0x01
2076 #define ENTROPY_RESET_STC_MODE 0x02
2077 #define ENTROPY_RESET_KEY_CACHE 0x04
2078 #define ENTROPY_RESET_IV 0x08
2079 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2080 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2081 #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2082 
2083 /* phys of interest w/ their special mii registers */
2084 #define PHY_LUCENT_B0 0x00437421
2085 #define LUCENT_MII_REG 0x1F
2086 
2087 #define PHY_NS_DP83065 0x20005c78
2088 #define DP83065_MII_MEM 0x16
2089 #define DP83065_MII_REGD 0x1D
2090 #define DP83065_MII_REGE 0x1E
2091 
2092 #define PHY_BROADCOM_5411 0x00206071
2093 #define PHY_BROADCOM_B0 0x00206050
2094 #define BROADCOM_MII_REG4 0x14
2095 #define BROADCOM_MII_REG5 0x15
2096 #define BROADCOM_MII_REG7 0x17
2097 #define BROADCOM_MII_REG8 0x18
2098 
2099 #define CAS_MII_ANNPTR 0x07
2100 #define CAS_MII_ANNPRR 0x08
2101 #define CAS_MII_1000_CTRL 0x09
2102 #define CAS_MII_1000_STATUS 0x0A
2103 #define CAS_MII_1000_EXTEND 0x0F
2104 
2105 #define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2106 /*
2107  * if autoneg is disabled, here's the table:
2108  * BMCR_SPEED100 = 100Mbps
2109  * BMCR_SPEED1000 = 1000Mbps
2110  * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2111  */
2112 #define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */
2113 
2114 #define CAS_ADVERTISE_1000HALF 0x0100
2115 #define CAS_ADVERTISE_1000FULL 0x0200
2116 #define CAS_ADVERTISE_PAUSE 0x0400
2117 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2118 
2119 /* regular lpa register */
2120 #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2121 #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2122 
2123 /* 1000_STATUS register */
2124 #define CAS_LPA_1000HALF 0x0400
2125 #define CAS_LPA_1000FULL 0x0800
2126 
2127 #define CAS_EXTEND_1000XFULL 0x8000
2128 #define CAS_EXTEND_1000XHALF 0x4000
2129 #define CAS_EXTEND_1000TFULL 0x2000
2130 #define CAS_EXTEND_1000THALF 0x1000
2131 
2132 /* cassini header parser firmware */
2133 typedef struct cas_hp_inst {
2134  const char *note;
2135 
2136  u16 mask, val;
2137 
2138  u8 op;
2139  u8 soff, snext; /* if match succeeds, new offset and match */
2140  u8 foff, fnext; /* if match fails, new offset and match */
2141  /* output info */
2142  u8 outop; /* output opcode */
2143 
2144  u16 outarg; /* output argument */
2145  u8 outenab; /* output enable: 0 = not, 1 = if match
2146  2 = if !match, 3 = always */
2147  u8 outshift; /* barrel shift right, 4 bits */
2148  u16 outmask;
2149 } cas_hp_inst_t;
2150 
2151 /* comparison */
2152 #define OP_EQ 0 /* packet == value */
2153 #define OP_LT 1 /* packet < value */
2154 #define OP_GT 2 /* packet > value */
2155 #define OP_NP 3 /* new packet */
2156 
2157 /* output opcodes */
2158 #define CL_REG 0
2159 #define LD_FID 1
2160 #define LD_SEQ 2
2161 #define LD_CTL 3
2162 #define LD_SAP 4
2163 #define LD_R1 5
2164 #define LD_L3 6
2165 #define LD_SUM 7
2166 #define LD_HDR 8
2167 #define IM_FID 9
2168 #define IM_SEQ 10
2169 #define IM_SAP 11
2170 #define IM_R1 12
2171 #define IM_CTL 13
2172 #define LD_LEN 14
2173 #define ST_FLG 15
2174 
2175 /* match setp #s for IP4TCP4 */
2176 #define S1_PCKT 0
2177 #define S1_VLAN 1
2178 #define S1_CFI 2
2179 #define S1_8023 3
2180 #define S1_LLC 4
2181 #define S1_LLCc 5
2182 #define S1_IPV4 6
2183 #define S1_IPV4c 7
2184 #define S1_IPV4F 8
2185 #define S1_TCP44 9
2186 #define S1_IPV6 10
2187 #define S1_IPV6L 11
2188 #define S1_IPV6c 12
2189 #define S1_TCP64 13
2190 #define S1_TCPSQ 14
2191 #define S1_TCPFG 15
2192 #define S1_TCPHL 16
2193 #define S1_TCPHc 17
2194 #define S1_CLNP 18
2195 #define S1_CLNP2 19
2196 #define S1_DROP 20
2197 #define S2_HTTP 21
2198 #define S1_ESP4 22
2199 #define S1_AH4 23
2200 #define S1_ESP6 24
2201 #define S1_AH6 25
2202 
2203 #define CAS_PROG_IP46TCP4_PREAMBLE \
2204 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
2205  CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2206 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
2207  IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2208 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
2209  CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
2211  CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
2213  CL_REG, 0x000, 0, 0x0, 0x0000}, \
2214 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2215  CL_REG, 0x000, 0, 0x0, 0x0000}, \
2216 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
2217  LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2218 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
2219  LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2220 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
2221  LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2222 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
2223  LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
2224 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
2225  LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2226 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
2227  IM_R1, 0x128, 1, 0x0, 0xffff}, \
2228 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
2229  LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
2230 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2231  LD_LEN, 0x03f, 1, 0x0, 0xffff}
2232 
2233 #ifdef USE_HP_IP46TCP4
2234 static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2235  CAS_PROG_IP46TCP4_PREAMBLE,
2236  { "TCP seq", /* DADDR should point to dest port */
2237  0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2238  0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2239  { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2240  S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2241  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2242  S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2243  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2244  S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2245  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2246  IM_CTL, 0x001, 3, 0x0, 0x0001},
2247  { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2248  IM_CTL, 0x000, 0, 0x0, 0x0000},
2249  { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2250  IM_CTL, 0x080, 3, 0x0, 0xffff},
2251  { NULL },
2252 };
2253 #ifdef HP_IP46TCP4_DEFAULT
2254 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2255 #endif
2256 #endif
2257 
2258 /*
2259  * Alternate table load which excludes HTTP server traffic from reassembly.
2260  * It is substantially similar to the basic table, with one extra state
2261  * and a few extra compares. */
2262 #ifdef USE_HP_IP46TCP4NOHTTP
2263 static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2264  CAS_PROG_IP46TCP4_PREAMBLE,
2265  { "TCP seq", /* DADDR should point to dest port */
2266  0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2267  0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */
2268  { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2269  S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */
2270  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2271  LD_R1, 0x205, 3, 0xB, 0xf000},
2272  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2273  LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2274  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2275  IM_CTL, 0x001, 3, 0x0, 0x0001},
2276  { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2277  CL_REG, 0x002, 3, 0x0, 0x0000},
2278  { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2279  IM_CTL, 0x080, 3, 0x0, 0xffff},
2280  { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2281  IM_CTL, 0x044, 3, 0x0, 0xffff},
2282  { NULL },
2283 };
2284 #ifdef HP_IP46TCP4NOHTTP_DEFAULT
2285 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2286 #endif
2287 #endif
2288 
2289 /* match step #s for IP4FRAG */
2290 #define S3_IPV6c 11
2291 #define S3_TCP64 12
2292 #define S3_TCPSQ 13
2293 #define S3_TCPFG 14
2294 #define S3_TCPHL 15
2295 #define S3_TCPHc 16
2296 #define S3_FRAG 17
2297 #define S3_FOFF 18
2298 #define S3_CLNP 19
2299 
2300 #ifdef USE_HP_IP4FRAG
2301 static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2302  { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
2303  CL_REG, 0x3ff, 1, 0x0, 0x0000},
2304  { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2305  IM_CTL, 0x00a, 3, 0x0, 0xffff},
2306  { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
2307  CL_REG, 0x000, 0, 0x0, 0x0000},
2308  { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2309  CL_REG, 0x000, 0, 0x0, 0x0000},
2310  { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
2311  CL_REG, 0x000, 0, 0x0, 0x0000},
2312  { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2313  CL_REG, 0x000, 0, 0x0, 0x0000},
2314  { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2315  LD_SAP, 0x100, 3, 0x0, 0xffff},
2316  { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
2317  LD_SUM, 0x00a, 1, 0x0, 0x0000},
2318  { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
2319  LD_LEN, 0x03e, 3, 0x0, 0xffff},
2320  { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
2321  LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2322  { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
2323  LD_SUM, 0x015, 1, 0x0, 0x0000},
2324  { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
2325  LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2326  { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2327  LD_LEN, 0x03f, 1, 0x0, 0xffff},
2328  { "TCP seq", /* DADDR should point to dest port */
2329  0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2330  0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2331  { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2332  S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2333  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2334  LD_R1, 0x205, 3, 0xB, 0xf000},
2335  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2336  LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2337  { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2338  LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */
2339  { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2340  LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2341  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2342  IM_CTL, 0x001, 3, 0x0, 0x0001},
2343  { NULL },
2344 };
2345 #ifdef HP_IP4FRAG_DEFAULT
2346 #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2347 #endif
2348 #endif
2349 
2350 /*
2351  * Alternate table which does batching without reassembly
2352  */
2353 #ifdef USE_HP_IP46TCP4BATCH
2354 static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2355  CAS_PROG_IP46TCP4_PREAMBLE,
2356  { "TCP seq", /* DADDR should point to dest port */
2357  0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2358  0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2359  { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2360  S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */
2361  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2362  S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2363  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2364  S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */
2365  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2366  IM_CTL, 0x001, 3, 0x0, 0x0001},
2367  { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2368  S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
2369  { NULL },
2370 };
2371 #ifdef HP_IP46TCP4BATCH_DEFAULT
2372 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2373 #endif
2374 #endif
2375 
2376 /* Workaround for Cassini rev2 descriptor corruption problem.
2377  * Does batching without reassembly, and sets the SAP to a known
2378  * data pattern for all packets.
2379  */
2380 #ifdef USE_HP_WORKAROUND
2381 static cas_hp_inst_t cas_prog_workaroundtab[] = {
2382  { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2383  S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2384  { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2385  IM_CTL, 0x04a, 3, 0x0, 0xffff},
2386  { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2387  CL_REG, 0x000, 0, 0x0, 0x0000},
2388  { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2389  CL_REG, 0x000, 0, 0x0, 0x0000},
2390  { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2391  CL_REG, 0x000, 0, 0x0, 0x0000},
2392  { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2393  CL_REG, 0x000, 0, 0x0, 0x0000},
2394  { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2395  IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2396  { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2397  LD_SUM, 0x00a, 1, 0x0, 0x0000},
2398  { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2399  LD_LEN, 0x03e, 1, 0x0, 0xffff},
2400  { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2401  LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2402  { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2403  LD_SUM, 0x015, 1, 0x0, 0x0000},
2404  { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2405  IM_R1, 0x128, 1, 0x0, 0xffff},
2406  { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2407  LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2408  { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2409  LD_LEN, 0x03f, 1, 0x0, 0xffff},
2410  { "TCP seq", /* DADDR should point to dest port */
2411  0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2412  0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2413  { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2414  S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2415  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2416  LD_R1, 0x205, 3, 0xB, 0xf000},
2417  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2418  S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2419  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2420  IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
2421  { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2422  IM_CTL, 0x001, 3, 0x0, 0x0001},
2423  { NULL },
2424 };
2425 #ifdef HP_WORKAROUND_DEFAULT
2426 #define CAS_HP_FIRMWARE cas_prog_workaroundtab
2427 #endif
2428 #endif
2429 
2430 #ifdef USE_HP_ENCRYPT
2431 static cas_hp_inst_t cas_prog_encryptiontab[] = {
2432  { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2433  S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2434  { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2435  IM_CTL, 0x00a, 3, 0x0, 0xffff},
2436 #if 0
2437 //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2438 //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2439  00,
2440 #endif
2441  { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */
2442  0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2443  CL_REG, 0x000, 0, 0x0, 0x0000},
2444  { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2445  CL_REG, 0x000, 0, 0x0, 0x0000},
2446  { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2447  CL_REG, 0x000, 0, 0x0, 0x0000},
2448  { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2449  CL_REG, 0x000, 0, 0x0, 0x0000},
2450  { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2451  LD_SAP, 0x100, 3, 0x0, 0xffff},
2452  { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2453  LD_SUM, 0x00a, 1, 0x0, 0x0000},
2454  { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2455  LD_LEN, 0x03e, 1, 0x0, 0xffff},
2456  { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2457  LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2458  { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2459  LD_SUM, 0x015, 1, 0x0, 0x0000},
2460  { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2461  IM_R1, 0x128, 1, 0x0, 0xffff},
2462  { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2463  LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2464  { "TCP64?",
2465 #if 0
2466 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2467 #endif
2468  0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
2469  0x03f, 1, 0x0, 0xffff},
2470  { "TCP seq", /* 14:DADDR should point to dest port */
2471  0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2472  0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2473  { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2474  S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */
2475  { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2476  LD_R1, 0x205, 3, 0xB, 0xf000} ,
2477  { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2478  S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2479  { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2480  IM_CTL, 0x001, 3, 0x0, 0x0001},
2481  { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2482  CL_REG, 0x002, 3, 0x0, 0x0000},
2483  { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2484  IM_CTL, 0x080, 3, 0x0, 0xffff},
2485  { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2486  IM_CTL, 0x044, 3, 0x0, 0xffff},
2487  { "IPV4 ESP encrypted?", /* S1_ESP4 */
2488  0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2489  0x021, 1, 0x0, 0xffff},
2490  { "IPV4 AH encrypted?", /* S1_AH4 */
2491  0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2492  0x021, 1, 0x0, 0xffff},
2493  { "IPV6 ESP encrypted?", /* S1_ESP6 */
2494 #if 0
2495 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2496 #endif
2497  0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2498  0x021, 1, 0x0, 0xffff},
2499  { "IPV6 AH encrypted?", /* S1_AH6 */
2500 #if 0
2501 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2502 #endif
2503  0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2504  0x021, 1, 0x0, 0xffff},
2505  { NULL },
2506 };
2507 #ifdef HP_ENCRYPT_DEFAULT
2508 #define CAS_HP_FIRMWARE cas_prog_encryptiontab
2509 #endif
2510 #endif
2511 
2512 static cas_hp_inst_t cas_prog_null[] = { {NULL} };
2513 #ifdef HP_NULL_DEFAULT
2514 #define CAS_HP_FIRMWARE cas_prog_null
2515 #endif
2516 
2517 /* phy types */
2518 #define CAS_PHY_UNKNOWN 0x00
2519 #define CAS_PHY_SERDES 0x01
2520 #define CAS_PHY_MII_MDIO0 0x02
2521 #define CAS_PHY_MII_MDIO1 0x04
2522 #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2523 
2524 /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2525  * is the actual size. the default index for the various rings is
2526  * 8. NOTE: there a bunch of alignment constraints for the rings. to
2527  * deal with that, i just allocate rings to create the desired
2528  * alignment. here are the constraints:
2529  * RX DESC and COMP rings must be 8KB aligned
2530  * TX DESC must be 2KB aligned.
2531  * if you change the numbers, be cognizant of how the alignment will change
2532  * in INIT_BLOCK as well.
2533  */
2534 
2535 #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2536 #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2537 #define TX_DESC_RING_INDEX 4 /* 512 = 8k */
2538 #define RX_DESC_RING_INDEX 4 /* 512 = 8k */
2539 #define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */
2540 
2541 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2542 #error TX_DESC_RING_INDEX must be between 0 and 8
2543 #endif
2544 
2545 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2546 #error RX_DESC_RING_INDEX must be between 0 and 8
2547 #endif
2548 
2549 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2550 #error RX_COMP_RING_INDEX must be between 0 and 8
2551 #endif
2552 
2553 #define N_TX_RINGS MAX_TX_RINGS /* for QoS */
2554 #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2555 #define N_RX_DESC_RINGS MAX_RX_DESC_RINGS /* 1 for ipsec */
2556 #define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */
2557 
2558 /* number of flows that can go through re-assembly */
2559 #define N_RX_FLOWS 64
2560 
2561 #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2562 #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2563 #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2564 #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2565 #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2566 #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2567 #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2568 #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2569 #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2570 
2571 /* convert values */
2572 #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2573 #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2574 #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2575  TX_CFG_DESC_RINGN_SHIFT(y)) & \
2576  TX_CFG_DESC_RINGN_MASK(y))
2577 
2578 /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2579 #define CAS_MIN_PAGE_SHIFT 11 /* 2048 */
2580 #define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */
2581 #define CAS_MAX_PAGE_SHIFT 14 /* 16384 */
2582 
2583 #define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in
2584  bytes. 0 - 9256 */
2585 #define TX_DESC_BUFLEN_SHIFT 0
2586 #define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. #
2587  of bytes to be
2588  skipped before
2589  csum calc begins.
2590  value must be
2591  even */
2592 #define TX_DESC_CSUM_START_SHIFT 15
2593 #define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff.
2594  byte offset w/in
2595  the pkt for the
2596  1st csum byte.
2597  must be > 8 */
2598 #define TX_DESC_CSUM_STUFF_SHIFT 21
2599 #define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */
2600 #define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */
2601 #define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */
2602 #define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */
2603 #define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only.
2604  CRC will not be
2605  inserted into
2606  outgoing frame. */
2607 struct cas_tx_desc {
2608  __le64 control;
2609  __le64 buffer;
2610 };
2611 
2612 /* descriptor ring for free buffers contains page-sized buffers. the index
2613  * value is not used by the hw in any way. it's just stored and returned in
2614  * the completion ring.
2615  */
2616 struct cas_rx_desc {
2617  __le64 index;
2618  __le64 buffer;
2619 };
2620 
2621 /* received packets are put on the completion ring. */
2622 /* word 1 */
2623 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2624 #define RX_COMP1_DATA_SIZE_SHIFT 13
2625 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2626 #define RX_COMP1_DATA_OFF_SHIFT 27
2627 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2628 #define RX_COMP1_DATA_INDEX_SHIFT 41
2629 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2630 #define RX_COMP1_SKIP_SHIFT 55
2631 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2632 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2633 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2634 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2635 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2636 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2637 #define RX_COMP1_TYPE_SHIFT 62
2638 
2639 /* word 2 */
2640 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2641 #define RX_COMP2_NEXT_INDEX_SHIFT 21
2642 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2643 #define RX_COMP2_HDR_SIZE_SHIFT 35
2644 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2645 #define RX_COMP2_HDR_OFF_SHIFT 44
2646 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2647 #define RX_COMP2_HDR_INDEX_SHIFT 50
2648 
2649 /* word 3 */
2650 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2651 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2652 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2653 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2654 #define RX_COMP3_CSUM_START_SHIFT 12
2655 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2656 #define RX_COMP3_FLOWID_SHIFT 19
2657 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2658 #define RX_COMP3_OPCODE_SHIFT 25
2659 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2660 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2661 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2662 #define RX_COMP3_LOAD_BAL_SHIFT 35
2663 #define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */
2664 #define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */
2665 #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2666 #define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */
2667 #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2668 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2669 #define RX_COMP3_SAP_SHIFT 48
2670 
2671 /* word 4 */
2672 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2673 #define RX_COMP4_TCP_CSUM_SHIFT 0
2674 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2675 #define RX_COMP4_PKT_LEN_SHIFT 16
2676 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2677 #define RX_COMP4_PERFECT_MATCH_SHIFT 30
2678 #define RX_COMP4_ZERO 0x0000080000000000ULL
2679 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2680 #define RX_COMP4_HASH_VAL_SHIFT 44
2681 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2682 #define RX_COMP4_BAD 0x4000000000000000ULL
2683 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2684 
2685 /* we encode the following: ring/index/release. only 14 bits
2686  * are usable.
2687  * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2688  * MAX_RX_DESC_RINGS. */
2689 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2690 #define RX_INDEX_NUM_SHIFT 0
2691 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2692 #define RX_INDEX_RING_SHIFT 12
2693 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2694 
2695 struct cas_rx_comp {
2696  __le64 word1;
2697  __le64 word2;
2698  __le64 word3;
2699  __le64 word4;
2700 };
2701 
2702 enum link_state {
2703  link_down = 0, /* No link, will retry */
2704  link_aneg, /* Autoneg in progress */
2705  link_force_try, /* Try Forced link speed */
2706  link_force_ret, /* Forced mode worked, retrying autoneg */
2707  link_force_ok, /* Stay in forced mode */
2708  link_up /* Link is up */
2709 };
2710 
2711 typedef struct cas_page {
2712  struct list_head list;
2713  struct page *buffer;
2714  dma_addr_t dma_addr;
2715  int used;
2716 } cas_page_t;
2717 
2718 
2719 /* some alignment constraints:
2720  * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2721  * TX COMPWB must be 8-byte aligned.
2722  * to accomplish this, here's what we do:
2723  *
2724  * INIT_BLOCK_RX_COMP = 64k (already aligned)
2725  * INIT_BLOCK_RX_DESC = 8k
2726  * INIT_BLOCK_TX = 8k
2727  * INIT_BLOCK_RX1_DESC = 8k
2728  * TX COMPWB
2729  */
2730 #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2731 #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2732 #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2733 
2734 struct cas_init_block {
2735  struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
2736  struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
2737  struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
2738  __le64 tx_compwb;
2739 };
2740 
2741 /* tiny buffers to deal with target abort issue. we allocate a bit
2742  * over so that we don't have target abort issues with these buffers
2743  * as well.
2744  */
2745 #define TX_TINY_BUF_LEN 0x100
2746 #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2747 
2748 struct cas_tiny_count {
2749  int nbufs;
2750  int used;
2751 };
2752 
2753 struct cas {
2754  spinlock_t lock; /* for most bits */
2755  spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */
2756  spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */
2757  spinlock_t rx_inuse_lock; /* rx inuse list */
2758  spinlock_t rx_spare_lock; /* rx spare list */
2759 
2760  void __iomem *regs;
2761  int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
2762  int rx_old[N_RX_DESC_RINGS];
2763  int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
2764  int rx_last[N_RX_DESC_RINGS];
2765 
2766  struct napi_struct napi;
2767 
2768  /* Set when chip is actually in operational state
2769  * (ie. not power managed) */
2770  int hw_running;
2771  int opened;
2772  struct mutex pm_mutex; /* open/close/suspend/resume */
2773 
2774  struct cas_init_block *init_block;
2775  struct cas_tx_desc *init_txds[MAX_TX_RINGS];
2776  struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
2777  struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
2778 
2779  /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2780  * are there for flow re-assembly. */
2781  struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
2782  struct sk_buff_head rx_flows[N_RX_FLOWS];
2783  cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
2784  struct list_head rx_spare_list, rx_inuse_list;
2785  int rx_spares_needed;
2786 
2787  /* for small packets when copying would be quicker than
2788  mapping */
2789  struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
2790  u8 *tx_tiny_bufs[N_TX_RINGS];
2791 
2792  u32 msg_enable;
2793 
2794  /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2795  struct net_device_stats net_stats[N_TX_RINGS + 1];
2796 
2797  u32 pci_cfg[64 >> 2];
2798  u8 pci_revision;
2799 
2800  int phy_type;
2801  int phy_addr;
2802  u32 phy_id;
2803 #define CAS_FLAG_1000MB_CAP 0x00000001
2804 #define CAS_FLAG_REG_PLUS 0x00000002
2805 #define CAS_FLAG_TARGET_ABORT 0x00000004
2806 #define CAS_FLAG_SATURN 0x00000008
2807 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2808 #define CAS_FLAG_RXD_POST_SHIFT 4
2809 #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2810  CAS_FLAG_RXD_POST_MASK)
2811 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2812 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2813  u32 cas_flags;
2814  int packet_min; /* minimum packet size */
2815  int tx_fifo_size;
2816  int rx_fifo_size;
2817  int rx_pause_off;
2818  int rx_pause_on;
2819  int crc_size; /* 4 if half-duplex */
2820 
2821  int pci_irq_INTC;
2822  int min_frame_size; /* for tx fifo workaround */
2823 
2824  /* page size allocation */
2825  int page_size;
2826  int page_order;
2827  int mtu_stride;
2828 
2829  u32 mac_rx_cfg;
2830 
2831  /* Autoneg & PHY control */
2832  int link_cntl;
2833  int link_fcntl;
2834  enum link_state lstate;
2835  struct timer_list link_timer;
2836  int timer_ticks;
2837  struct work_struct reset_task;
2838 #if 0
2839  atomic_t reset_task_pending;
2840 #else
2841  atomic_t reset_task_pending;
2842  atomic_t reset_task_pending_mtu;
2843  atomic_t reset_task_pending_spare;
2844  atomic_t reset_task_pending_all;
2845 #endif
2846 
2847  /* Link-down problem workaround */
2848 #define LINK_TRANSITION_UNKNOWN 0
2849 #define LINK_TRANSITION_ON_FAILURE 1
2850 #define LINK_TRANSITION_STILL_FAILED 2
2851 #define LINK_TRANSITION_LINK_UP 3
2852 #define LINK_TRANSITION_LINK_CONFIG 4
2853 #define LINK_TRANSITION_LINK_DOWN 5
2854 #define LINK_TRANSITION_REQUESTED_RESET 6
2855  int link_transition;
2856  int link_transition_jiffies_valid;
2857  unsigned long link_transition_jiffies;
2858 
2859  /* Tuning */
2860  u8 orig_cacheline_size; /* value when loaded */
2861 #define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */
2862 
2863  /* Diagnostic counters and state. */
2864  int casreg_len; /* reg-space size for dumping */
2865  u64 pause_entered;
2866  u16 pause_last_time_recvd;
2867 
2868  dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2869  struct pci_dev *pdev;
2870  struct net_device *dev;
2871 #if defined(CONFIG_OF)
2872  struct device_node *of_node;
2873 #endif
2874 
2875  /* Firmware Info */
2876  u16 fw_load_addr;
2877  u32 fw_size;
2878  u8 *fw_data;
2879 };
2880 
2881 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2882 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2883 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2884 
2885 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2886  (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2887 
2888 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2889  (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2890  (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2891 
2892 #define CAS_ALIGN(addr, align) \
2893  (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2894 
2895 #define RX_FIFO_SIZE 16384
2896 #define EXPANSION_ROM_SIZE 65536
2897 
2898 #define CAS_MC_EXACT_MATCH_SIZE 15
2899 #define CAS_MC_HASH_SIZE 256
2900 #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2901  CAS_MC_HASH_SIZE)
2902 
2903 #define TX_TARGET_ABORT_LEN 0x20
2904 #define RX_SWIVEL_OFF_VAL 0x2
2905 #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2906 #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2907 #define RX_BLANK_INTR_PKT_VAL 0x05
2908 #define RX_BLANK_INTR_TIME_VAL 0x0F
2909 #define HP_TCP_THRESH_VAL 1530 /* reduce to enable reassembly */
2910 
2911 #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2912 #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)
2913 
2914 #endif /* _CASSINI_H */
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