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cassini.h File Reference

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Data Structures

struct  cas_hp_inst
 
struct  cas_tx_desc
 
struct  cas_rx_desc
 
struct  cas_rx_comp
 
struct  cas_page
 
struct  cas_init_block
 
struct  cas_tiny_count
 
struct  cas
 

Macros

#define CAS_ID_REV2   0x02
 
#define CAS_ID_REVPLUS   0x10
 
#define CAS_ID_REVPLUS02u   0x11
 
#define CAS_ID_REVSATURNB2   0x30
 
#define REG_CAWR   0x0004 /* core arbitration weight */
 
#define CAWR_RX_DMA_WEIGHT_SHIFT   0
 
#define CAWR_RX_DMA_WEIGHT_MASK   0x03 /* [0:1] */
 
#define CAWR_TX_DMA_WEIGHT_SHIFT   2
 
#define CAWR_TX_DMA_WEIGHT_MASK   0x0C /* [3:2] */
 
#define CAWR_RR_DIS   0x10 /* [4] */
 
#define REG_INF_BURST   0x0008 /* infinite burst enable reg */
 
#define INF_BURST_EN   0x1 /* enable */
 
#define REG_INTR_STATUS   0x000C /* interrupt status register */
 
#define INTR_TX_INTME
 
#define INTR_TX_ALL
 
#define INTR_TX_DONE
 
#define INTR_TX_TAG_ERROR
 
#define INTR_RX_DONE
 
#define INTR_RX_BUF_UNAVAIL
 
#define INTR_RX_TAG_ERROR
 
#define INTR_RX_COMP_FULL
 
#define INTR_RX_BUF_AE
 
#define INTR_RX_COMP_AF
 
#define INTR_RX_LEN_MISMATCH
 
#define INTR_SUMMARY
 
#define INTR_PCS_STATUS   0x00002000 /* PCS interrupt status register */
 
#define INTR_TX_MAC_STATUS
 
#define INTR_RX_MAC_STATUS
 
#define INTR_MAC_CTRL_STATUS
 
#define INTR_MIF_STATUS
 
#define INTR_PCI_ERROR_STATUS
 
#define INTR_TX_COMP_3_MASK
 
#define INTR_TX_COMP_3_SHIFT   19
 
#define INTR_ERROR_MASK
 
#define REG_INTR_MASK   0x0010 /* Interrupt mask */
 
#define REG_ALIAS_CLEAR
 
#define REG_INTR_STATUS_ALIAS
 
#define REG_PCI_ERR_STATUS   0x1000 /* PCI error status */
 
#define PCI_ERR_BADACK
 
#define PCI_ERR_DTRTO
 
#define PCI_ERR_OTHER   0x04 /* other PCI errors */
 
#define PCI_ERR_BIM_DMA_WRITE
 
#define PCI_ERR_BIM_DMA_READ
 
#define PCI_ERR_BIM_DMA_TIMEOUT
 
#define REG_PCI_ERR_STATUS_MASK   0x1004 /* PCI Error status mask */
 
#define REG_BIM_CFG   0x1008 /* BIM Configuration */
 
#define BIM_CFG_RESERVED0   0x001 /* reserved */
 
#define BIM_CFG_RESERVED1   0x002 /* reserved */
 
#define BIM_CFG_64BIT_DISABLE   0x004 /* disable 64-bit mode */
 
#define BIM_CFG_66MHZ   0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
 
#define BIM_CFG_32BIT   0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
 
#define BIM_CFG_DPAR_INTR_ENABLE   0x020 /* detected parity err enable */
 
#define BIM_CFG_RMA_INTR_ENABLE   0x040 /* master abort intr enable */
 
#define BIM_CFG_RTA_INTR_ENABLE   0x080 /* target abort intr enable */
 
#define BIM_CFG_RESERVED2   0x100 /* reserved */
 
#define BIM_CFG_BIM_DISABLE
 
#define BIM_CFG_BIM_STATUS
 
#define BIM_CFG_PERROR_BLOCK
 
#define REG_BIM_DIAG   0x100C /* BIM Diagnostic */
 
#define BIM_DIAG_MSTR_SM_MASK
 
#define BIM_DIAG_BRST_SM_MASK
 
#define REG_SW_RESET   0x1010 /* Software reset */
 
#define SW_RESET_TX
 
#define SW_RESET_RX
 
#define SW_RESET_RSTOUT
 
#define SW_RESET_BLOCK_PCS_SLINK
 
#define SW_RESET_BREQ_SM_MASK   0x00007F00 /* breq state machine [6:0] */
 
#define SW_RESET_PCIARB_SM_MASK
 
#define SW_RESET_RDPCI_SM_MASK
 
#define SW_RESET_RDARB_SM_MASK
 
#define SW_RESET_WRPCI_SM_MASK
 
#define SW_RESET_WRARB_SM_MASK
 
#define REG_MINUS_BIM_DATAPATH_TEST
 
#define REG_BIM_LOCAL_DEV_EN
 
#define BIM_LOCAL_DEV_PAD
 
#define BIM_LOCAL_DEV_PROM   0x02 /* PROM chip select */
 
#define BIM_LOCAL_DEV_EXT
 
#define BIM_LOCAL_DEV_SOFT_0   0x08 /* sw programmable ctrl bit 0 */
 
#define BIM_LOCAL_DEV_SOFT_1   0x10 /* sw programmable ctrl bit 1 */
 
#define BIM_LOCAL_DEV_HW_RESET   0x20 /* internal hw reset. Cassini+ only. */
 
#define REG_BIM_BUFFER_ADDR
 
#define BIM_BUFFER_ADDR_MASK   0x3F /* index (0 - 23) of buffer */
 
#define BIM_BUFFER_WR_SELECT
 
#define REG_BIM_BUFFER_DATA_LOW   0x1028 /* BIM buffer data low */
 
#define REG_BIM_BUFFER_DATA_HI   0x102C /* BIM buffer data high */
 
#define REG_BIM_RAM_BIST
 
#define BIM_RAM_BIST_RD_START   0x01 /* start BIST for BIM read buffer */
 
#define BIM_RAM_BIST_WR_START
 
#define BIM_RAM_BIST_RD_PASS
 
#define BIM_RAM_BIST_WR_PASS
 
#define BIM_RAM_BIST_RD_LOW_PASS   0x10 /* read low bank passes BIST */
 
#define BIM_RAM_BIST_RD_HI_PASS   0x20 /* read high bank passes BIST */
 
#define BIM_RAM_BIST_WR_LOW_PASS
 
#define BIM_RAM_BIST_WR_HI_PASS
 
#define REG_BIM_DIAG_MUX
 
#define REG_PLUS_PROBE_MUX_SELECT   0x1034 /* Cassini+: PROBE MUX SELECT */
 
#define PROBE_MUX_EN
 
#define PROBE_MUX_SUB_MUX_MASK
 
#define PROBE_MUX_SEL_HI_MASK
 
#define PROBE_MUX_SEL_LOW_MASK
 
#define REG_PLUS_INTR_MASK_1
 
#define REG_PLUS_INTRN_MASK(x)   (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
 
#define INTR_RX_DONE_ALT   0x01
 
#define INTR_RX_COMP_FULL_ALT   0x02
 
#define INTR_RX_COMP_AF_ALT   0x04
 
#define INTR_RX_BUF_UNAVAIL_1   0x08
 
#define INTR_RX_BUF_AE_1   0x10 /* almost empty */
 
#define INTRN_MASK_RX_EN   0x80
 
#define INTRN_MASK_CLEAR_ALL
 
#define REG_PLUS_INTR_STATUS_1
 
#define REG_PLUS_INTRN_STATUS(x)   (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
 
#define INTR_STATUS_ALT_INTX_EN
 
#define REG_PLUS_ALIAS_CLEAR_1
 
#define REG_PLUS_ALIASN_CLEAR(x)   (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
 
#define REG_PLUS_INTR_STATUS_ALIAS_1
 
#define REG_PLUS_INTRN_STATUS_ALIAS(x)   (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
 
#define REG_SATURN_PCFG
 
#define SATURN_PCFG_TLA   0x00000001 /* 1 = phy actled */
 
#define SATURN_PCFG_FLA   0x00000002 /* 1 = phy link10led */
 
#define SATURN_PCFG_CLA   0x00000004 /* 1 = phy link100led */
 
#define SATURN_PCFG_LLA   0x00000008 /* 1 = phy link1000led */
 
#define SATURN_PCFG_RLA   0x00000010 /* 1 = phy duplexled */
 
#define SATURN_PCFG_PDS
 
#define SATURN_PCFG_MTP   0x00000080 /* test point select */
 
#define SATURN_PCFG_GMO
 
#define SATURN_PCFG_FSI
 
#define SATURN_PCFG_LAD
 
#define MAX_TX_RINGS_SHIFT   2
 
#define MAX_TX_RINGS   (1 << MAX_TX_RINGS_SHIFT)
 
#define MAX_TX_RINGS_MASK   (MAX_TX_RINGS - 1)
 
#define REG_TX_CFG   0x2004 /* TX config */
 
#define TX_CFG_DMA_EN
 
#define TX_CFG_FIFO_PIO_SEL
 
#define TX_CFG_DESC_RING0_MASK
 
#define TX_CFG_DESC_RING0_SHIFT   2
 
#define TX_CFG_DESC_RINGN_MASK(a)   (TX_CFG_DESC_RING0_MASK << (a)*4)
 
#define TX_CFG_DESC_RINGN_SHIFT(a)   (TX_CFG_DESC_RING0_SHIFT + (a)*4)
 
#define TX_CFG_PACED_MODE
 
#define TX_CFG_DMA_RDPIPE_DIS   0x01000000 /* always set to 1 */
 
#define TX_CFG_COMPWB_Q1
 
#define TX_CFG_COMPWB_Q2
 
#define TX_CFG_COMPWB_Q3
 
#define TX_CFG_COMPWB_Q4
 
#define TX_CFG_INTR_COMPWB_DIS
 
#define TX_CFG_CTX_SEL_MASK
 
#define TX_CFG_CTX_SEL_SHIFT   30
 
#define REG_TX_FIFO_WRITE_PTR   0x2014 /* TX FIFO write pointer */
 
#define REG_TX_FIFO_SHADOW_WRITE_PTR
 
#define REG_TX_FIFO_READ_PTR   0x201C /* TX FIFO read pointer */
 
#define REG_TX_FIFO_SHADOW_READ_PTR
 
#define REG_TX_FIFO_PKT_CNT   0x2024 /* TX FIFO packet counter */
 
#define REG_TX_SM_1   0x2028 /* TX state machine reg #1 */
 
#define TX_SM_1_CHAIN_MASK   0x000003FF /* chaining state machine */
 
#define TX_SM_1_CSUM_MASK   0x00000C00 /* checksum state machine */
 
#define TX_SM_1_FIFO_LOAD_MASK
 
#define TX_SM_1_FIFO_UNLOAD_MASK   0x003C0000 /* FIFO unload state machine */
 
#define TX_SM_1_CACHE_MASK
 
#define TX_SM_1_CBQ_ARB_MASK   0xF8000000 /* CBQ arbiter state machine */
 
#define REG_TX_SM_2   0x202C /* TX state machine reg #2 */
 
#define TX_SM_2_COMP_WB_MASK   0x07 /* completion writeback sm */
 
#define TX_SM_2_SUB_LOAD_MASK   0x38 /* sub load state machine */
 
#define TX_SM_2_KICK_MASK   0xC0 /* kick state machine */
 
#define REG_TX_DATA_PTR_LOW   0x2030 /* TX data pointer low */
 
#define REG_TX_DATA_PTR_HI   0x2034 /* TX data pointer high */
 
#define REG_TX_KICK0   0x2038 /* TX kick reg #1 */
 
#define REG_TX_KICKN(x)   (REG_TX_KICK0 + (x)*4)
 
#define REG_TX_COMP0   0x2048 /* TX completion reg #1 */
 
#define REG_TX_COMPN(x)   (REG_TX_COMP0 + (x)*4)
 
#define TX_COMPWB_SIZE   8
 
#define REG_TX_COMPWB_DB_LOW
 
#define REG_TX_COMPWB_DB_HI
 
#define TX_COMPWB_MSB_MASK   0x00000000000000FFULL
 
#define TX_COMPWB_MSB_SHIFT   0
 
#define TX_COMPWB_LSB_MASK   0x000000000000FF00ULL
 
#define TX_COMPWB_LSB_SHIFT   8
 
#define TX_COMPWB_NEXT(x)   ((x) >> 16)
 
#define REG_TX_DB0_LOW   0x2060 /* TX descriptor base low #1 */
 
#define REG_TX_DB0_HI   0x2064 /* TX descriptor base hi #1 */
 
#define REG_TX_DBN_LOW(x)   (REG_TX_DB0_LOW + (x)*8)
 
#define REG_TX_DBN_HI(x)   (REG_TX_DB0_HI + (x)*8)
 
#define REG_TX_MAXBURST_0   0x2080 /* TX MaxBurst #1 */
 
#define REG_TX_MAXBURST_1   0x2084 /* TX MaxBurst #2 */
 
#define REG_TX_MAXBURST_2   0x2088 /* TX MaxBurst #3 */
 
#define REG_TX_MAXBURST_3   0x208C /* TX MaxBurst #4 */
 
#define REG_TX_FIFO_ADDR   0x2104 /* TX FIFO address */
 
#define REG_TX_FIFO_TAG   0x2108 /* TX FIFO tag */
 
#define REG_TX_FIFO_DATA_LOW   0x210C /* TX FIFO data low */
 
#define REG_TX_FIFO_DATA_HI_T1   0x2110 /* TX FIFO data high t1 */
 
#define REG_TX_FIFO_DATA_HI_T0   0x2114 /* TX FIFO data high t0 */
 
#define REG_TX_FIFO_SIZE   0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
 
#define REG_TX_RAMBIST   0x211C /* TX RAMBIST control/status */
 
#define TX_RAMBIST_STATE
 
#define TX_RAMBIST_RAM33A_PASS   0x0020 /* RAM33A passed */
 
#define TX_RAMBIST_RAM32A_PASS   0x0010 /* RAM32A passed */
 
#define TX_RAMBIST_RAM33B_PASS   0x0008 /* RAM33B passed */
 
#define TX_RAMBIST_RAM32B_PASS   0x0004 /* RAM32B passed */
 
#define TX_RAMBIST_SUMMARY   0x0002 /* all RAM passed */
 
#define TX_RAMBIST_START
 
#define MAX_RX_DESC_RINGS   2
 
#define MAX_RX_COMP_RINGS   4
 
#define REG_RX_CFG   0x4000 /* RX config */
 
#define RX_CFG_DMA_EN
 
#define RX_CFG_DESC_RING_MASK
 
#define RX_CFG_DESC_RING_SHIFT   1
 
#define RX_CFG_COMP_RING_MASK
 
#define RX_CFG_COMP_RING_SHIFT   5
 
#define RX_CFG_BATCH_DIS
 
#define RX_CFG_SWIVEL_MASK
 
#define RX_CFG_SWIVEL_SHIFT   10
 
#define RX_CFG_DESC_RING1_MASK
 
#define RX_CFG_DESC_RING1_SHIFT   16
 
#define REG_RX_PAGE_SIZE   0x4004 /* RX page size */
 
#define RX_PAGE_SIZE_MASK
 
#define RX_PAGE_SIZE_SHIFT   0
 
#define RX_PAGE_SIZE_MTU_COUNT_MASK
 
#define RX_PAGE_SIZE_MTU_COUNT_SHIFT   11
 
#define RX_PAGE_SIZE_MTU_STRIDE_MASK
 
#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT   27
 
#define RX_PAGE_SIZE_MTU_OFF_MASK
 
#define RX_PAGE_SIZE_MTU_OFF_SHIFT   30
 
#define REG_RX_FIFO_WRITE_PTR   0x4008 /* RX FIFO write pointer */
 
#define REG_RX_FIFO_READ_PTR   0x400C /* RX FIFO read pointer */
 
#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR
 
#define REG_RX_IPP_FIFO_SHADOW_READ_PTR
 
#define REG_RX_IPP_FIFO_READ_PTR
 
#define REG_RX_DEBUG   0x401C /* RX debug */
 
#define RX_DEBUG_LOAD_STATE_MASK
 
#define RX_DEBUG_LM_STATE_MASK
 
#define RX_DEBUG_FC_STATE_MASK
 
#define RX_DEBUG_DATA_STATE_MASK
 
#define RX_DEBUG_DESC_STATE_MASK
 
#define RX_DEBUG_INTR_READ_PTR_MASK
 
#define RX_DEBUG_INTR_WRITE_PTR_MASK
 
#define REG_RX_PAUSE_THRESH   0x4020 /* RX pause thresholds */
 
#define RX_PAUSE_THRESH_QUANTUM   64
 
#define RX_PAUSE_THRESH_OFF_MASK
 
#define RX_PAUSE_THRESH_OFF_SHIFT   0
 
#define RX_PAUSE_THRESH_ON_MASK
 
#define RX_PAUSE_THRESH_ON_SHIFT   12
 
#define REG_RX_KICK   0x4024 /* RX kick reg */
 
#define REG_RX_DB_LOW
 
#define REG_RX_DB_HI
 
#define REG_RX_CB_LOW
 
#define REG_RX_CB_HI
 
#define REG_RX_COMP   0x4038 /* (ro) RX completion */
 
#define REG_RX_COMP_HEAD   0x403C /* RX completion head */
 
#define REG_RX_COMP_TAIL   0x4040 /* RX completion tail */
 
#define REG_RX_BLANK
 
#define RX_BLANK_INTR_PKT_MASK
 
#define RX_BLANK_INTR_PKT_SHIFT   0
 
#define RX_BLANK_INTR_TIME_MASK
 
#define RX_BLANK_INTR_TIME_SHIFT   12
 
#define REG_RX_AE_THRESH
 
#define RX_AE_THRESH_FREE_MASK
 
#define RX_AE_THRESH_FREE_SHIFT   0
 
#define RX_AE_THRESH_COMP_MASK
 
#define RX_AE_THRESH_COMP_SHIFT   13
 
#define REG_RX_RED   0x404C /* RX random early detect enable */
 
#define RX_RED_4K_6K_FIFO_MASK   0x000000FF /* 4KB < FIFO thresh < 6KB */
 
#define RX_RED_6K_8K_FIFO_MASK   0x0000FF00 /* 6KB < FIFO thresh < 8KB */
 
#define RX_RED_8K_10K_FIFO_MASK   0x00FF0000 /* 8KB < FIFO thresh < 10KB */
 
#define RX_RED_10K_12K_FIFO_MASK   0xFF000000 /* 10KB < FIFO thresh < 12KB */
 
#define REG_RX_FIFO_FULLNESS   0x4050 /* (ro) RX FIFO fullness */
 
#define RX_FIFO_FULLNESS_RX_FIFO_MASK   0x3FF80000 /* level w/ 8B granularity */
 
#define RX_FIFO_FULLNESS_IPP_FIFO_MASK   0x0007FF00 /* level w/ 8B granularity */
 
#define RX_FIFO_FULLNESS_RX_PKT_MASK   0x000000FF /* # packets in RX FIFO */
 
#define REG_RX_IPP_PACKET_COUNT   0x4054 /* RX IPP packet counter */
 
#define REG_RX_WORK_DMA_PTR_LOW   0x4058 /* RX working DMA ptr low */
 
#define REG_RX_WORK_DMA_PTR_HI
 
#define REG_RX_BIST   0x4060 /* (ro) RX BIST */
 
#define RX_BIST_32A_PASS   0x80000000 /* RX FIFO 32A passed */
 
#define RX_BIST_33A_PASS   0x40000000 /* RX FIFO 33A passed */
 
#define RX_BIST_32B_PASS   0x20000000 /* RX FIFO 32B passed */
 
#define RX_BIST_33B_PASS   0x10000000 /* RX FIFO 33B passed */
 
#define RX_BIST_32C_PASS   0x08000000 /* RX FIFO 32C passed */
 
#define RX_BIST_33C_PASS   0x04000000 /* RX FIFO 33C passed */
 
#define RX_BIST_IPP_32A_PASS   0x02000000 /* RX IPP FIFO 33B passed */
 
#define RX_BIST_IPP_33A_PASS   0x01000000 /* RX IPP FIFO 33A passed */
 
#define RX_BIST_IPP_32B_PASS   0x00800000 /* RX IPP FIFO 32B passed */
 
#define RX_BIST_IPP_33B_PASS   0x00400000 /* RX IPP FIFO 33B passed */
 
#define RX_BIST_IPP_32C_PASS   0x00200000 /* RX IPP FIFO 32C passed */
 
#define RX_BIST_IPP_33C_PASS   0x00100000 /* RX IPP FIFO 33C passed */
 
#define RX_BIST_CTRL_32_PASS   0x00800000 /* RX CTRL FIFO 32 passed */
 
#define RX_BIST_CTRL_33_PASS   0x00400000 /* RX CTRL FIFO 33 passed */
 
#define RX_BIST_REAS_26A_PASS   0x00200000 /* RX Reas 26A passed */
 
#define RX_BIST_REAS_26B_PASS   0x00100000 /* RX Reas 26B passed */
 
#define RX_BIST_REAS_27_PASS   0x00080000 /* RX Reas 27 passed */
 
#define RX_BIST_STATE_MASK   0x00078000 /* BIST state machine */
 
#define RX_BIST_SUMMARY
 
#define RX_BIST_START
 
#define REG_RX_CTRL_FIFO_WRITE_PTR
 
#define REG_RX_CTRL_FIFO_READ_PTR
 
#define REG_RX_BLANK_ALIAS_READ
 
#define RX_BAR_INTR_PACKET_MASK
 
#define RX_BAR_INTR_TIME_MASK
 
#define REG_RX_FIFO_ADDR   0x4080 /* RX FIFO address */
 
#define REG_RX_FIFO_TAG   0x4084 /* RX FIFO tag */
 
#define REG_RX_FIFO_DATA_LOW   0x4088 /* RX FIFO data low */
 
#define REG_RX_FIFO_DATA_HI_T0   0x408C /* RX FIFO data high T0 */
 
#define REG_RX_FIFO_DATA_HI_T1   0x4090 /* RX FIFO data high T1 */
 
#define REG_RX_CTRL_FIFO_ADDR
 
#define REG_RX_CTRL_FIFO_DATA_LOW
 
#define REG_RX_CTRL_FIFO_DATA_MID
 
#define REG_RX_CTRL_FIFO_DATA_HI
 
#define RX_CTRL_FIFO_DATA_HI_CTRL   0x0001 /* upper bit of ctrl word */
 
#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK   0x007E /* flow id */
 
#define REG_RX_IPP_FIFO_ADDR   0x4104 /* RX IPP FIFO address */
 
#define REG_RX_IPP_FIFO_TAG   0x4108 /* RX IPP FIFO tag */
 
#define REG_RX_IPP_FIFO_DATA_LOW   0x410C /* RX IPP FIFO data low */
 
#define REG_RX_IPP_FIFO_DATA_HI_T0
 
#define REG_RX_IPP_FIFO_DATA_HI_T1
 
#define REG_RX_HEADER_PAGE_PTR_LOW
 
#define REG_RX_HEADER_PAGE_PTR_HI
 
#define REG_RX_MTU_PAGE_PTR_LOW
 
#define REG_RX_MTU_PAGE_PTR_HI
 
#define REG_RX_TABLE_ADDR
 
#define RX_TABLE_ADDR_MASK   0x0000003F /* address mask */
 
#define REG_RX_TABLE_DATA_LOW
 
#define REG_RX_TABLE_DATA_MID
 
#define REG_RX_TABLE_DATA_HI
 
#define REG_PLUS_RX_DB1_LOW
 
#define REG_PLUS_RX_DB1_HI
 
#define REG_PLUS_RX_CB1_LOW
 
#define REG_PLUS_RX_CB1_HI
 
#define REG_PLUS_RX_CBN_LOW(x)   (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
 
#define REG_PLUS_RX_CBN_HI(x)   (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
 
#define REG_PLUS_RX_KICK1   0x4220 /* RX Kick 2 register */
 
#define REG_PLUS_RX_COMP1
 
#define REG_PLUS_RX_COMP1_HEAD
 
#define REG_PLUS_RX_COMP1_TAIL
 
#define REG_PLUS_RX_COMPN_HEAD(x)   (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
 
#define REG_PLUS_RX_COMPN_TAIL(x)   (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
 
#define REG_PLUS_RX_AE1_THRESH
 
#define RX_AE1_THRESH_FREE_MASK   RX_AE_THRESH_FREE_MASK
 
#define RX_AE1_THRESH_FREE_SHIFT   RX_AE_THRESH_FREE_SHIFT
 
#define REG_HP_CFG
 
#define HP_CFG_PARSE_EN   0x00000001 /* enab header parsing */
 
#define HP_CFG_NUM_CPU_MASK
 
#define HP_CFG_NUM_CPU_SHIFT   2
 
#define HP_CFG_SYN_INC_MASK
 
#define HP_CFG_TCP_THRESH_MASK
 
#define HP_CFG_TCP_THRESH_SHIFT   9
 
#define REG_HP_INSTR_RAM_ADDR
 
#define HP_INSTR_RAM_ADDR_MASK   0x01F /* 5-bit mask */
 
#define REG_HP_INSTR_RAM_DATA_LOW
 
#define HP_INSTR_RAM_LOW_OUTMASK_MASK   0x0000FFFF
 
#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT   0
 
#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK   0x000F0000
 
#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT   16
 
#define HP_INSTR_RAM_LOW_OUTEN_MASK   0x00300000
 
#define HP_INSTR_RAM_LOW_OUTEN_SHIFT   20
 
#define HP_INSTR_RAM_LOW_OUTARG_MASK   0xFFC00000
 
#define HP_INSTR_RAM_LOW_OUTARG_SHIFT   22
 
#define REG_HP_INSTR_RAM_DATA_MID
 
#define HP_INSTR_RAM_MID_OUTARG_MASK   0x00000003
 
#define HP_INSTR_RAM_MID_OUTARG_SHIFT   0
 
#define HP_INSTR_RAM_MID_OUTOP_MASK   0x0000003C
 
#define HP_INSTR_RAM_MID_OUTOP_SHIFT   2
 
#define HP_INSTR_RAM_MID_FNEXT_MASK   0x000007C0
 
#define HP_INSTR_RAM_MID_FNEXT_SHIFT   6
 
#define HP_INSTR_RAM_MID_FOFF_MASK   0x0003F800
 
#define HP_INSTR_RAM_MID_FOFF_SHIFT   11
 
#define HP_INSTR_RAM_MID_SNEXT_MASK   0x007C0000
 
#define HP_INSTR_RAM_MID_SNEXT_SHIFT   18
 
#define HP_INSTR_RAM_MID_SOFF_MASK   0x3F800000
 
#define HP_INSTR_RAM_MID_SOFF_SHIFT   23
 
#define HP_INSTR_RAM_MID_OP_MASK   0xC0000000
 
#define HP_INSTR_RAM_MID_OP_SHIFT   30
 
#define REG_HP_INSTR_RAM_DATA_HI
 
#define HP_INSTR_RAM_HI_VAL_MASK   0x0000FFFF
 
#define HP_INSTR_RAM_HI_VAL_SHIFT   0
 
#define HP_INSTR_RAM_HI_MASK_MASK   0xFFFF0000
 
#define HP_INSTR_RAM_HI_MASK_SHIFT   16
 
#define REG_HP_DATA_RAM_FDB_ADDR
 
#define HP_DATA_RAM_FDB_DATA_MASK
 
#define HP_DATA_RAM_FDB_FDB_MASK
 
#define REG_HP_DATA_RAM_DATA   0x4158 /* HP data RAM data */
 
#define REG_HP_FLOW_DB0   0x415C /* HP flow database 1 reg */
 
#define REG_HP_FLOW_DBN(x)   (REG_HP_FLOW_DB0 + (x)*4)
 
#define REG_HP_STATE_MACHINE   0x418C /* (ro) HP state machine */
 
#define REG_HP_STATUS0   0x4190 /* (ro) HP status 1 */
 
#define HP_STATUS0_SAP_MASK   0xFFFF0000 /* SAP */
 
#define HP_STATUS0_L3_OFF_MASK   0x0000FE00 /* L3 offset */
 
#define HP_STATUS0_LB_CPUNUM_MASK
 
#define HP_STATUS0_HRP_OPCODE_MASK   0x00000007 /* HRP opcode */
 
#define REG_HP_STATUS1   0x4194 /* (ro) HP status 2 */
 
#define HP_STATUS1_ACCUR2_MASK   0xE0000000 /* accu R2[6:4] */
 
#define HP_STATUS1_FLOWID_MASK   0x1F800000 /* flow id */
 
#define HP_STATUS1_TCP_OFF_MASK   0x007F0000 /* tcp payload offset */
 
#define HP_STATUS1_TCP_SIZE_MASK   0x0000FFFF /* tcp payload size */
 
#define REG_HP_STATUS2   0x4198 /* (ro) HP status 3 */
 
#define HP_STATUS2_ACCUR2_MASK   0xF0000000 /* accu R2[3:0] */
 
#define HP_STATUS2_CSUM_OFF_MASK
 
#define HP_STATUS2_ACCUR1_MASK   0x000FE000 /* accu R1 */
 
#define HP_STATUS2_FORCE_DROP   0x00001000 /* force drop */
 
#define HP_STATUS2_BWO_REASSM
 
#define HP_STATUS2_JH_SPLIT_EN
 
#define HP_STATUS2_FORCE_TCP_NOCHECK
 
#define HP_STATUS2_DATA_MASK_ZERO
 
#define HP_STATUS2_FORCE_TCP_CHECK
 
#define HP_STATUS2_MASK_TCP_THRESH
 
#define HP_STATUS2_NO_ASSIST   0x00000020 /* no assist */
 
#define HP_STATUS2_CTRL_PACKET_FLAG   0x00000010 /* control packet flag */
 
#define HP_STATUS2_TCP_FLAG_CHECK   0x00000008 /* tcp flag check */
 
#define HP_STATUS2_SYN_FLAG   0x00000004 /* syn flag */
 
#define HP_STATUS2_TCP_CHECK   0x00000002 /* tcp payload chk */
 
#define HP_STATUS2_TCP_NOCHECK   0x00000001 /* tcp no payload chk */
 
#define REG_HP_RAM_BIST   0x419C /* HP RAM BIST reg */
 
#define HP_RAM_BIST_HP_DATA_PASS   0x80000000 /* HP data ram */
 
#define HP_RAM_BIST_HP_INSTR0_PASS   0x40000000 /* HP instr ram 0 */
 
#define HP_RAM_BIST_HP_INSTR1_PASS   0x20000000 /* HP instr ram 1 */
 
#define HP_RAM_BIST_HP_INSTR2_PASS   0x10000000 /* HP instr ram 2 */
 
#define HP_RAM_BIST_FDBM_AGE0_PASS   0x08000000 /* FDBM aging RAM0 */
 
#define HP_RAM_BIST_FDBM_AGE1_PASS   0x04000000 /* FDBM aging RAM1 */
 
#define HP_RAM_BIST_FDBM_FLOWID00_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID10_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID20_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID30_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID01_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID11_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID21_PASS
 
#define HP_RAM_BIST_FDBM_FLOWID31_PASS
 
#define HP_RAM_BIST_FDBM_TCPSEQ_PASS
 
#define HP_RAM_BIST_SUMMARY   0x00000002 /* all BIST tests */
 
#define HP_RAM_BIST_START   0x00000001 /* start/stop BIST */
 
#define REG_MAC_TX_RESET
 
#define REG_MAC_RX_RESET
 
#define REG_MAC_SEND_PAUSE   0x6008 /* send pause command reg */
 
#define MAC_SEND_PAUSE_TIME_MASK
 
#define MAC_SEND_PAUSE_SEND
 
#define REG_MAC_TX_STATUS   0x6010 /* TX MAC status reg */
 
#define MAC_TX_FRAME_XMIT
 
#define MAC_TX_UNDERRUN
 
#define MAC_TX_MAX_PACKET_ERR
 
#define MAC_TX_COLL_NORMAL
 
#define MAC_TX_COLL_EXCESS
 
#define MAC_TX_COLL_LATE
 
#define MAC_TX_COLL_FIRST
 
#define MAC_TX_DEFER_TIMER
 
#define MAC_TX_PEAK_ATTEMPTS
 
#define REG_MAC_RX_STATUS   0x6014 /* RX MAC status reg */
 
#define MAC_RX_FRAME_RECV
 
#define MAC_RX_OVERFLOW
 
#define MAC_RX_FRAME_COUNT
 
#define MAC_RX_ALIGN_ERR
 
#define MAC_RX_CRC_ERR
 
#define MAC_RX_LEN_ERR
 
#define MAC_RX_VIOL_ERR
 
#define REG_MAC_CTRL_STATUS   0x6018 /* MAC control status reg */
 
#define MAC_CTRL_PAUSE_RECEIVED
 
#define MAC_CTRL_PAUSE_STATE
 
#define MAC_CTRL_NOPAUSE_STATE
 
#define MAC_CTRL_PAUSE_TIME_MASK
 
#define REG_MAC_TX_MASK   0x6020 /* TX MAC mask reg */
 
#define REG_MAC_RX_MASK   0x6024 /* RX MAC mask reg */
 
#define REG_MAC_CTRL_MASK   0x6028 /* MAC control mask reg */
 
#define REG_MAC_TX_CFG   0x6030 /* TX MAC config reg */
 
#define MAC_TX_CFG_EN
 
#define MAC_TX_CFG_IGNORE_CARRIER
 
#define MAC_TX_CFG_IGNORE_COLL
 
#define MAC_TX_CFG_IPG_EN
 
#define MAC_TX_CFG_NEVER_GIVE_UP_EN
 
#define MAC_TX_CFG_NEVER_GIVE_UP_LIM
 
#define MAC_TX_CFG_NO_BACKOFF
 
#define MAC_TX_CFG_SLOW_DOWN
 
#define MAC_TX_CFG_NO_FCS
 
#define MAC_TX_CFG_CARRIER_EXTEND
 
#define REG_MAC_RX_CFG   0x6034 /* RX MAC config reg */
 
#define MAC_RX_CFG_EN   0x0001 /* enable RX MAC */
 
#define MAC_RX_CFG_STRIP_PAD
 
#define MAC_RX_CFG_STRIP_FCS
 
#define MAC_RX_CFG_PROMISC_EN   0x0008 /* promiscuous mode */
 
#define MAC_RX_CFG_PROMISC_GROUP_EN
 
#define MAC_RX_CFG_HASH_FILTER_EN
 
#define MAC_RX_CFG_ADDR_FILTER_EN
 
#define MAC_RX_CFG_DISABLE_DISCARD
 
#define MAC_RX_CFG_CARRIER_EXTEND
 
#define REG_MAC_CTRL_CFG   0x6038 /* MAC control config reg */
 
#define MAC_CTRL_CFG_SEND_PAUSE_EN
 
#define MAC_CTRL_CFG_RECV_PAUSE_EN
 
#define MAC_CTRL_CFG_PASS_CTRL
 
#define REG_MAC_XIF_CFG   0x603C /* XIF config reg */
 
#define MAC_XIF_TX_MII_OUTPUT_EN
 
#define MAC_XIF_MII_INT_LOOPBACK
 
#define MAC_XIF_DISABLE_ECHO
 
#define MAC_XIF_GMII_MODE
 
#define MAC_XIF_MII_BUFFER_OUTPUT_EN
 
#define MAC_XIF_LINK_LED   0x0020 /* LINKLED# active (low) */
 
#define MAC_XIF_FDPLX_LED   0x0040 /* FDPLXLED# active (low) */
 
#define REG_MAC_IPG0
 
#define REG_MAC_IPG1
 
#define REG_MAC_IPG2
 
#define REG_MAC_SLOT_TIME
 
#define REG_MAC_FRAMESIZE_MIN
 
#define REG_MAC_FRAMESIZE_MAX   0x6054 /* max frame size reg */
 
#define MAC_FRAMESIZE_MAX_BURST_MASK   0x3FFF0000 /* max burst size */
 
#define MAC_FRAMESIZE_MAX_BURST_SHIFT   16
 
#define MAC_FRAMESIZE_MAX_FRAME_MASK   0x00007FFF /* max frame size */
 
#define MAC_FRAMESIZE_MAX_FRAME_SHIFT   0
 
#define REG_MAC_PA_SIZE
 
#define REG_MAC_JAM_SIZE
 
#define REG_MAC_ATTEMPT_LIMIT
 
#define REG_MAC_CTRL_TYPE
 
#define REG_MAC_ADDR0   0x6080 /* MAC address 0 reg */
 
#define REG_MAC_ADDRN(x)   (REG_MAC_ADDR0 + (x)*4)
 
#define REG_MAC_ADDR_FILTER0
 
#define REG_MAC_ADDR_FILTER1
 
#define REG_MAC_ADDR_FILTER2
 
#define REG_MAC_ADDR_FILTER2_1_MASK
 
#define REG_MAC_ADDR_FILTER0_MASK
 
#define REG_MAC_HASH_TABLE0   0x6160 /* hash table 0 reg */
 
#define REG_MAC_HASH_TABLEN(x)   (REG_MAC_HASH_TABLE0 + (x)*4)
 
#define REG_MAC_COLL_NORMAL
 
#define REG_MAC_COLL_FIRST
 
#define REG_MAC_COLL_EXCESS
 
#define REG_MAC_COLL_LATE   0x61AC /* late collision counter */
 
#define REG_MAC_TIMER_DEFER
 
#define REG_MAC_ATTEMPTS_PEAK   0x61B4 /* peak attempts reg */
 
#define REG_MAC_RECV_FRAME   0x61B8 /* receive frame counter */
 
#define REG_MAC_LEN_ERR   0x61BC /* length error counter */
 
#define REG_MAC_ALIGN_ERR   0x61C0 /* alignment error counter */
 
#define REG_MAC_FCS_ERR   0x61C4 /* FCS error counter */
 
#define REG_MAC_RX_CODE_ERR
 
#define REG_MAC_RANDOM_SEED
 
#define REG_MAC_STATE_MACHINE   0x61D0 /* (ro) state machine reg */
 
#define MAC_SM_RLM_MASK   0x07800000
 
#define MAC_SM_RLM_SHIFT   23
 
#define MAC_SM_RX_FC_MASK   0x00700000
 
#define MAC_SM_RX_FC_SHIFT   20
 
#define MAC_SM_TLM_MASK   0x000F0000
 
#define MAC_SM_TLM_SHIFT   16
 
#define MAC_SM_ENCAP_SM_MASK   0x0000F000
 
#define MAC_SM_ENCAP_SM_SHIFT   12
 
#define MAC_SM_TX_REQ_MASK   0x00000C00
 
#define MAC_SM_TX_REQ_SHIFT   10
 
#define MAC_SM_TX_FC_MASK   0x000003C0
 
#define MAC_SM_TX_FC_SHIFT   6
 
#define MAC_SM_FIFO_WRITE_SEL_MASK   0x00000038
 
#define MAC_SM_FIFO_WRITE_SEL_SHIFT   3
 
#define MAC_SM_TX_FIFO_EMPTY_MASK   0x00000007
 
#define MAC_SM_TX_FIFO_EMPTY_SHIFT   0
 
#define REG_MIF_BIT_BANG_CLOCK
 
#define REG_MIF_BIT_BANG_DATA
 
#define REG_MIF_BIT_BANG_OUTPUT_EN
 
#define REG_MIF_FRAME   0x620C /* MIF frame/output reg */
 
#define MIF_FRAME_START_MASK
 
#define MIF_FRAME_ST   0x40000000 /* STart of frame */
 
#define MIF_FRAME_OPCODE_MASK
 
#define MIF_FRAME_OP_READ   0x20000000 /* read OPcode */
 
#define MIF_FRAME_OP_WRITE   0x10000000 /* write OPcode */
 
#define MIF_FRAME_PHY_ADDR_MASK
 
#define MIF_FRAME_PHY_ADDR_SHIFT   23
 
#define MIF_FRAME_REG_ADDR_MASK
 
#define MIF_FRAME_REG_ADDR_SHIFT   18
 
#define MIF_FRAME_TURN_AROUND_MSB
 
#define MIF_FRAME_TURN_AROUND_LSB
 
#define MIF_FRAME_DATA_MASK
 
#define REG_MIF_CFG   0x6210 /* MIF config reg */
 
#define MIF_CFG_PHY_SELECT
 
#define MIF_CFG_POLL_EN
 
#define MIF_CFG_BB_MODE
 
#define MIF_CFG_POLL_REG_MASK
 
#define MIF_CFG_POLL_REG_SHIFT   3
 
#define MIF_CFG_MDIO_0
 
#define MIF_CFG_MDIO_1
 
#define MIF_CFG_POLL_PHY_MASK
 
#define MIF_CFG_POLL_PHY_SHIFT   10
 
#define REG_MIF_MASK   0x6214 /* MIF mask reg */
 
#define REG_MIF_STATUS   0x6218 /* MIF status reg */
 
#define MIF_STATUS_POLL_DATA_MASK
 
#define MIF_STATUS_POLL_DATA_SHIFT   16
 
#define MIF_STATUS_POLL_STATUS_MASK
 
#define MIF_STATUS_POLL_STATUS_SHIFT   0
 
#define REG_MIF_STATE_MACHINE   0x621C /* MIF state machine reg */
 
#define MIF_SM_CONTROL_MASK
 
#define MIF_SM_EXECUTION_MASK
 
#define REG_PCS_MII_CTRL   0x9000 /* PCS MII control reg */
 
#define PCS_MII_CTRL_1000_SEL
 
#define PCS_MII_CTRL_COLLISION_TEST
 
#define PCS_MII_CTRL_DUPLEX
 
#define PCS_MII_RESTART_AUTONEG
 
#define PCS_MII_ISOLATE
 
#define PCS_MII_POWER_DOWN
 
#define PCS_MII_AUTONEG_EN
 
#define PCS_MII_10_100_SEL
 
#define PCS_MII_RESET
 
#define REG_PCS_MII_STATUS   0x9004 /* PCS MII status reg */
 
#define PCS_MII_STATUS_EXTEND_CAP   0x0001 /* reads 0 */
 
#define PCS_MII_STATUS_JABBER_DETECT   0x0002 /* reads 0 */
 
#define PCS_MII_STATUS_LINK_STATUS
 
#define PCS_MII_STATUS_AUTONEG_ABLE
 
#define PCS_MII_STATUS_REMOTE_FAULT
 
#define PCS_MII_STATUS_AUTONEG_COMP
 
#define PCS_MII_STATUS_EXTEND_STATUS
 
#define REG_PCS_MII_ADVERT
 
#define PCS_MII_ADVERT_FD
 
#define PCS_MII_ADVERT_HD
 
#define PCS_MII_ADVERT_SYM_PAUSE
 
#define PCS_MII_ADVERT_ASYM_PAUSE
 
#define PCS_MII_ADVERT_RF_MASK
 
#define PCS_MII_ADVERT_ACK   0x4000 /* (ro) */
 
#define PCS_MII_ADVERT_NEXT_PAGE   0x8000 /* (ro) forced 0x0 */
 
#define REG_PCS_MII_LPA
 
#define PCS_MII_LPA_FD   PCS_MII_ADVERT_FD
 
#define PCS_MII_LPA_HD   PCS_MII_ADVERT_HD
 
#define PCS_MII_LPA_SYM_PAUSE   PCS_MII_ADVERT_SYM_PAUSE
 
#define PCS_MII_LPA_ASYM_PAUSE   PCS_MII_ADVERT_ASYM_PAUSE
 
#define PCS_MII_LPA_RF_MASK   PCS_MII_ADVERT_RF_MASK
 
#define PCS_MII_LPA_ACK   PCS_MII_ADVERT_ACK
 
#define PCS_MII_LPA_NEXT_PAGE   PCS_MII_ADVERT_NEXT_PAGE
 
#define REG_PCS_CFG   0x9010 /* PCS config reg */
 
#define PCS_CFG_EN
 
#define PCS_CFG_SD_OVERRIDE
 
#define PCS_CFG_SD_ACTIVE_LOW
 
#define PCS_CFG_JITTER_STUDY_MASK
 
#define PCS_CFG_10MS_TIMER_OVERRIDE
 
#define REG_PCS_STATE_MACHINE
 
#define PCS_SM_TX_STATE_MASK
 
#define PCS_SM_RX_STATE_MASK
 
#define PCS_SM_WORD_SYNC_STATE_MASK
 
#define PCS_SM_SEQ_DETECT_STATE_MASK
 
#define PCS_SM_LINK_STATE_MASK   0x0001E000
 
#define SM_LINK_STATE_UP   0x00016000 /* link state is up */
 
#define PCS_SM_LOSS_LINK_C
 
#define PCS_SM_LOSS_LINK_SYNC
 
#define PCS_SM_LOSS_SIGNAL_DETECT
 
#define PCS_SM_NO_LINK_BREAKLINK
 
#define PCS_SM_NO_LINK_SERDES
 
#define PCS_SM_NO_LINK_C
 
#define PCS_SM_NO_LINK_SYNC
 
#define PCS_SM_NO_LINK_WAIT_C
 
#define PCS_SM_NO_LINK_NO_IDLE
 
#define REG_PCS_INTR_STATUS   0x9018 /* PCS interrupt status */
 
#define PCS_INTR_STATUS_LINK_CHANGE
 
#define REG_PCS_DATAPATH_MODE   0x9050 /* datapath mode reg */
 
#define PCS_DATAPATH_MODE_MII
 
#define PCS_DATAPATH_MODE_SERDES
 
#define REG_PCS_SERDES_CTRL   0x9054 /* serdes control reg */
 
#define PCS_SERDES_CTRL_LOOPBACK
 
#define PCS_SERDES_CTRL_SYNCD_EN
 
#define PCS_SERDES_CTRL_LOCKREF
 
#define REG_PCS_SHARED_OUTPUT_SEL   0x9058 /* shared output select */
 
#define PCS_SOS_PROM_ADDR_MASK   0x0007
 
#define REG_PCS_SERDES_STATE   0x905C /* (ro) serdes state */
 
#define PCS_SERDES_STATE_MASK   0x03
 
#define REG_PCS_PACKET_COUNT   0x9060 /* (ro) PCS packet counter */
 
#define PCS_PACKET_COUNT_TX   0x000007FF /* pkts xmitted by PCS */
 
#define PCS_PACKET_COUNT_RX
 
#define REG_EXPANSION_ROM_RUN_START
 
#define REG_EXPANSION_ROM_RUN_END   0x17FFFF
 
#define REG_SECOND_LOCALBUS_START
 
#define REG_SECOND_LOCALBUS_END   0x1FFFFF
 
#define REG_ENTROPY_START   REG_SECOND_LOCALBUS_START
 
#define REG_ENTROPY_DATA   (REG_ENTROPY_START + 0x00)
 
#define REG_ENTROPY_STATUS   (REG_ENTROPY_START + 0x04)
 
#define ENTROPY_STATUS_DRDY   0x01
 
#define ENTROPY_STATUS_BUSY   0x02
 
#define ENTROPY_STATUS_CIPHER   0x04
 
#define ENTROPY_STATUS_BYPASS_MASK   0x18
 
#define REG_ENTROPY_MODE   (REG_ENTROPY_START + 0x05)
 
#define ENTROPY_MODE_KEY_MASK   0x07
 
#define ENTROPY_MODE_ENCRYPT   0x40
 
#define REG_ENTROPY_RAND_REG   (REG_ENTROPY_START + 0x06)
 
#define REG_ENTROPY_RESET   (REG_ENTROPY_START + 0x07)
 
#define ENTROPY_RESET_DES_IO   0x01
 
#define ENTROPY_RESET_STC_MODE   0x02
 
#define ENTROPY_RESET_KEY_CACHE   0x04
 
#define ENTROPY_RESET_IV   0x08
 
#define REG_ENTROPY_IV   (REG_ENTROPY_START + 0x08)
 
#define REG_ENTROPY_KEY0   (REG_ENTROPY_START + 0x10)
 
#define REG_ENTROPY_KEYN(x)   (REG_ENTROPY_KEY0 + 4*(x))
 
#define PHY_LUCENT_B0   0x00437421
 
#define LUCENT_MII_REG   0x1F
 
#define PHY_NS_DP83065   0x20005c78
 
#define DP83065_MII_MEM   0x16
 
#define DP83065_MII_REGD   0x1D
 
#define DP83065_MII_REGE   0x1E
 
#define PHY_BROADCOM_5411   0x00206071
 
#define PHY_BROADCOM_B0   0x00206050
 
#define BROADCOM_MII_REG4   0x14
 
#define BROADCOM_MII_REG5   0x15
 
#define BROADCOM_MII_REG7   0x17
 
#define BROADCOM_MII_REG8   0x18
 
#define CAS_MII_ANNPTR   0x07
 
#define CAS_MII_ANNPRR   0x08
 
#define CAS_MII_1000_CTRL   0x09
 
#define CAS_MII_1000_STATUS   0x0A
 
#define CAS_MII_1000_EXTEND   0x0F
 
#define CAS_BMSR_1000_EXTEND   0x0100 /* supports 1000Base-T extended status */
 
#define CAS_BMCR_SPEED1000   0x0040 /* Select 1000Mbps */
 
#define CAS_ADVERTISE_1000HALF   0x0100
 
#define CAS_ADVERTISE_1000FULL   0x0200
 
#define CAS_ADVERTISE_PAUSE   0x0400
 
#define CAS_ADVERTISE_ASYM_PAUSE   0x0800
 
#define CAS_LPA_PAUSE   CAS_ADVERTISE_PAUSE
 
#define CAS_LPA_ASYM_PAUSE   CAS_ADVERTISE_ASYM_PAUSE
 
#define CAS_LPA_1000HALF   0x0400
 
#define CAS_LPA_1000FULL   0x0800
 
#define CAS_EXTEND_1000XFULL   0x8000
 
#define CAS_EXTEND_1000XHALF   0x4000
 
#define CAS_EXTEND_1000TFULL   0x2000
 
#define CAS_EXTEND_1000THALF   0x1000
 
#define OP_EQ   0 /* packet == value */
 
#define OP_LT   1 /* packet < value */
 
#define OP_GT   2 /* packet > value */
 
#define OP_NP   3 /* new packet */
 
#define CL_REG   0
 
#define LD_FID   1
 
#define LD_SEQ   2
 
#define LD_CTL   3
 
#define LD_SAP   4
 
#define LD_R1   5
 
#define LD_L3   6
 
#define LD_SUM   7
 
#define LD_HDR   8
 
#define IM_FID   9
 
#define IM_SEQ   10
 
#define IM_SAP   11
 
#define IM_R1   12
 
#define IM_CTL   13
 
#define LD_LEN   14
 
#define ST_FLG   15
 
#define S1_PCKT   0
 
#define S1_VLAN   1
 
#define S1_CFI   2
 
#define S1_8023   3
 
#define S1_LLC   4
 
#define S1_LLCc   5
 
#define S1_IPV4   6
 
#define S1_IPV4c   7
 
#define S1_IPV4F   8
 
#define S1_TCP44   9
 
#define S1_IPV6   10
 
#define S1_IPV6L   11
 
#define S1_IPV6c   12
 
#define S1_TCP64   13
 
#define S1_TCPSQ   14
 
#define S1_TCPFG   15
 
#define S1_TCPHL   16
 
#define S1_TCPHc   17
 
#define S1_CLNP   18
 
#define S1_CLNP2   19
 
#define S1_DROP   20
 
#define S2_HTTP   21
 
#define S1_ESP4   22
 
#define S1_AH4   23
 
#define S1_ESP6   24
 
#define S1_AH6   25
 
#define CAS_PROG_IP46TCP4_PREAMBLE
 
#define S3_IPV6c   11
 
#define S3_TCP64   12
 
#define S3_TCPSQ   13
 
#define S3_TCPFG   14
 
#define S3_TCPHL   15
 
#define S3_TCPHc   16
 
#define S3_FRAG   17
 
#define S3_FOFF   18
 
#define S3_CLNP   19
 
#define CAS_PHY_UNKNOWN   0x00
 
#define CAS_PHY_SERDES   0x01
 
#define CAS_PHY_MII_MDIO0   0x02
 
#define CAS_PHY_MII_MDIO1   0x04
 
#define CAS_PHY_MII(x)   ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
 
#define DESC_RING_I_TO_S(x)   (32*(1 << (x)))
 
#define COMP_RING_I_TO_S(x)   (128*(1 << (x)))
 
#define TX_DESC_RING_INDEX   4 /* 512 = 8k */
 
#define RX_DESC_RING_INDEX   4 /* 512 = 8k */
 
#define RX_COMP_RING_INDEX   4 /* 2048 = 64k: should be 4x rx ring size */
 
#define N_TX_RINGS   MAX_TX_RINGS /* for QoS */
 
#define N_TX_RINGS_MASK   MAX_TX_RINGS_MASK
 
#define N_RX_DESC_RINGS   MAX_RX_DESC_RINGS /* 1 for ipsec */
 
#define N_RX_COMP_RINGS   0x1 /* for mult. PCI interrupts */
 
#define N_RX_FLOWS   64
 
#define TX_DESC_RING_SIZE   DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
 
#define RX_DESC_RING_SIZE   DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
 
#define RX_COMP_RING_SIZE   COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
 
#define TX_DESC_RINGN_INDEX(x)   TX_DESC_RING_INDEX
 
#define RX_DESC_RINGN_INDEX(x)   RX_DESC_RING_INDEX
 
#define RX_COMP_RINGN_INDEX(x)   RX_COMP_RING_INDEX
 
#define TX_DESC_RINGN_SIZE(x)   TX_DESC_RING_SIZE
 
#define RX_DESC_RINGN_SIZE(x)   RX_DESC_RING_SIZE
 
#define RX_COMP_RINGN_SIZE(x)   RX_COMP_RING_SIZE
 
#define CAS_BASE(x, y)   (((y) << (x ## _SHIFT)) & (x ## _MASK))
 
#define CAS_VAL(x, y)   (((y) & (x ## _MASK)) >> (x ## _SHIFT))
 
#define CAS_TX_RINGN_BASE(y)
 
#define CAS_MIN_PAGE_SHIFT   11 /* 2048 */
 
#define CAS_JUMBO_PAGE_SHIFT   13 /* 8192 */
 
#define CAS_MAX_PAGE_SHIFT   14 /* 16384 */
 
#define TX_DESC_BUFLEN_MASK
 
#define TX_DESC_BUFLEN_SHIFT   0
 
#define TX_DESC_CSUM_START_MASK
 
#define TX_DESC_CSUM_START_SHIFT   15
 
#define TX_DESC_CSUM_STUFF_MASK
 
#define TX_DESC_CSUM_STUFF_SHIFT   21
 
#define TX_DESC_CSUM_EN   0x0000000020000000ULL /* enable checksum */
 
#define TX_DESC_EOF   0x0000000040000000ULL /* end of frame */
 
#define TX_DESC_SOF   0x0000000080000000ULL /* start of frame */
 
#define TX_DESC_INTME   0x0000000100000000ULL /* interrupt me */
 
#define TX_DESC_NO_CRC
 
#define RX_COMP1_DATA_SIZE_MASK   0x0000000007FFE000ULL
 
#define RX_COMP1_DATA_SIZE_SHIFT   13
 
#define RX_COMP1_DATA_OFF_MASK   0x000001FFF8000000ULL
 
#define RX_COMP1_DATA_OFF_SHIFT   27
 
#define RX_COMP1_DATA_INDEX_MASK   0x007FFE0000000000ULL
 
#define RX_COMP1_DATA_INDEX_SHIFT   41
 
#define RX_COMP1_SKIP_MASK   0x0180000000000000ULL
 
#define RX_COMP1_SKIP_SHIFT   55
 
#define RX_COMP1_RELEASE_NEXT   0x0200000000000000ULL
 
#define RX_COMP1_SPLIT_PKT   0x0400000000000000ULL
 
#define RX_COMP1_RELEASE_FLOW   0x0800000000000000ULL
 
#define RX_COMP1_RELEASE_DATA   0x1000000000000000ULL
 
#define RX_COMP1_RELEASE_HDR   0x2000000000000000ULL
 
#define RX_COMP1_TYPE_MASK   0xC000000000000000ULL
 
#define RX_COMP1_TYPE_SHIFT   62
 
#define RX_COMP2_NEXT_INDEX_MASK   0x00000007FFE00000ULL
 
#define RX_COMP2_NEXT_INDEX_SHIFT   21
 
#define RX_COMP2_HDR_SIZE_MASK   0x00000FF800000000ULL
 
#define RX_COMP2_HDR_SIZE_SHIFT   35
 
#define RX_COMP2_HDR_OFF_MASK   0x0003F00000000000ULL
 
#define RX_COMP2_HDR_OFF_SHIFT   44
 
#define RX_COMP2_HDR_INDEX_MASK   0xFFFC000000000000ULL
 
#define RX_COMP2_HDR_INDEX_SHIFT   50
 
#define RX_COMP3_SMALL_PKT   0x0000000000000001ULL
 
#define RX_COMP3_JUMBO_PKT   0x0000000000000002ULL
 
#define RX_COMP3_JUMBO_HDR_SPLIT_EN   0x0000000000000004ULL
 
#define RX_COMP3_CSUM_START_MASK   0x000000000007F000ULL
 
#define RX_COMP3_CSUM_START_SHIFT   12
 
#define RX_COMP3_FLOWID_MASK   0x0000000001F80000ULL
 
#define RX_COMP3_FLOWID_SHIFT   19
 
#define RX_COMP3_OPCODE_MASK   0x000000000E000000ULL
 
#define RX_COMP3_OPCODE_SHIFT   25
 
#define RX_COMP3_FORCE_FLAG   0x0000000010000000ULL
 
#define RX_COMP3_NO_ASSIST   0x0000000020000000ULL
 
#define RX_COMP3_LOAD_BAL_MASK   0x000001F800000000ULL
 
#define RX_COMP3_LOAD_BAL_SHIFT   35
 
#define RX_PLUS_COMP3_ENC_PKT   0x0000020000000000ULL /* cas+ */
 
#define RX_COMP3_L3_HEAD_OFF_MASK   0x0000FE0000000000ULL /* cas */
 
#define RX_COMP3_L3_HEAD_OFF_SHIFT   41
 
#define RX_PLUS_COMP_L3_HEAD_OFF_MASK   0x0000FC0000000000ULL /* cas+ */
 
#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT   42
 
#define RX_COMP3_SAP_MASK   0xFFFF000000000000ULL
 
#define RX_COMP3_SAP_SHIFT   48
 
#define RX_COMP4_TCP_CSUM_MASK   0x000000000000FFFFULL
 
#define RX_COMP4_TCP_CSUM_SHIFT   0
 
#define RX_COMP4_PKT_LEN_MASK   0x000000003FFF0000ULL
 
#define RX_COMP4_PKT_LEN_SHIFT   16
 
#define RX_COMP4_PERFECT_MATCH_MASK   0x00000003C0000000ULL
 
#define RX_COMP4_PERFECT_MATCH_SHIFT   30
 
#define RX_COMP4_ZERO   0x0000080000000000ULL
 
#define RX_COMP4_HASH_VAL_MASK   0x0FFFF00000000000ULL
 
#define RX_COMP4_HASH_VAL_SHIFT   44
 
#define RX_COMP4_HASH_PASS   0x1000000000000000ULL
 
#define RX_COMP4_BAD   0x4000000000000000ULL
 
#define RX_COMP4_LEN_MISMATCH   0x8000000000000000ULL
 
#define RX_INDEX_NUM_MASK   0x0000000000000FFFULL
 
#define RX_INDEX_NUM_SHIFT   0
 
#define RX_INDEX_RING_MASK   0x0000000000001000ULL
 
#define RX_INDEX_RING_SHIFT   12
 
#define RX_INDEX_RELEASE   0x0000000000002000ULL
 
#define INIT_BLOCK_TX   (TX_DESC_RING_SIZE)
 
#define INIT_BLOCK_RX_DESC   (RX_DESC_RING_SIZE)
 
#define INIT_BLOCK_RX_COMP   (RX_COMP_RING_SIZE)
 
#define TX_TINY_BUF_LEN   0x100
 
#define TX_TINY_BUF_BLOCK   ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
 
#define CAS_FLAG_1000MB_CAP   0x00000001
 
#define CAS_FLAG_REG_PLUS   0x00000002
 
#define CAS_FLAG_TARGET_ABORT   0x00000004
 
#define CAS_FLAG_SATURN   0x00000008
 
#define CAS_FLAG_RXD_POST_MASK   0x000000F0
 
#define CAS_FLAG_RXD_POST_SHIFT   4
 
#define CAS_FLAG_RXD_POST(x)
 
#define CAS_FLAG_ENTROPY_DEV   0x00000100
 
#define CAS_FLAG_NO_HW_CSUM   0x00000200
 
#define LINK_TRANSITION_UNKNOWN   0
 
#define LINK_TRANSITION_ON_FAILURE   1
 
#define LINK_TRANSITION_STILL_FAILED   2
 
#define LINK_TRANSITION_LINK_UP   3
 
#define LINK_TRANSITION_LINK_CONFIG   4
 
#define LINK_TRANSITION_LINK_DOWN   5
 
#define LINK_TRANSITION_REQUESTED_RESET   6
 
#define CAS_PREF_CACHELINE_SIZE   0x20 /* Minimum desired */
 
#define TX_DESC_NEXT(r, x)   (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
 
#define RX_DESC_ENTRY(r, x)   ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
 
#define RX_COMP_ENTRY(r, x)   ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
 
#define TX_BUFF_COUNT(r, x, y)
 
#define TX_BUFFS_AVAIL(cp, i)
 
#define CAS_ALIGN(addr, align)   (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
 
#define RX_FIFO_SIZE   16384
 
#define EXPANSION_ROM_SIZE   65536
 
#define CAS_MC_EXACT_MATCH_SIZE   15
 
#define CAS_MC_HASH_SIZE   256
 
#define CAS_MC_HASH_MAX
 
#define TX_TARGET_ABORT_LEN   0x20
 
#define RX_SWIVEL_OFF_VAL   0x2
 
#define RX_AE_FREEN_VAL(x)   (RX_DESC_RINGN_SIZE(x) >> 1)
 
#define RX_AE_COMP_VAL   (RX_COMP_RING_SIZE >> 1)
 
#define RX_BLANK_INTR_PKT_VAL   0x05
 
#define RX_BLANK_INTR_TIME_VAL   0x0F
 
#define HP_TCP_THRESH_VAL   1530 /* reduce to enable reassembly */
 
#define RX_SPARE_COUNT   (RX_DESC_RING_SIZE >> 1)
 
#define RX_SPARE_RECOVER_VAL   (RX_SPARE_COUNT >> 2)
 

Typedefs

typedef struct cas_hp_inst cas_hp_inst_t
 
typedef struct cas_page cas_page_t
 

Enumerations

enum  link_state {
  link_down = 0, link_aneg, link_force_try, link_force_ret,
  link_force_ok, link_up, link_down = 0, link_aneg,
  link_force_try, link_force_ret, link_force_ok, link_up
}
 

Macro Definition Documentation

#define BIM_BUFFER_ADDR_MASK   0x3F /* index (0 - 23) of buffer */

Definition at line 202 of file cassini.h.

#define BIM_BUFFER_WR_SELECT
Value:
0x40 /* write buffer access = 1
read buffer access = 0 */

Definition at line 203 of file cassini.h.

#define BIM_CFG_32BIT   0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */

Definition at line 148 of file cassini.h.

#define BIM_CFG_64BIT_DISABLE   0x004 /* disable 64-bit mode */

Definition at line 146 of file cassini.h.

#define BIM_CFG_66MHZ   0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */

Definition at line 147 of file cassini.h.

#define BIM_CFG_BIM_DISABLE
Value:
0x200 /* stop BIM DMA. use before global
reset. reserved in Cassini. */

Definition at line 153 of file cassini.h.

#define BIM_CFG_BIM_STATUS
Value:
0x400 /* (ro) 1 = BIM DMA suspended.
reserved in Cassini. */

Definition at line 154 of file cassini.h.

#define BIM_CFG_DPAR_INTR_ENABLE   0x020 /* detected parity err enable */

Definition at line 149 of file cassini.h.

#define BIM_CFG_PERROR_BLOCK
Value:
0x800 /* block PERR# to pci bus. def: 0.
reserved in Cassini. */

Definition at line 155 of file cassini.h.

#define BIM_CFG_RESERVED0   0x001 /* reserved */

Definition at line 144 of file cassini.h.

#define BIM_CFG_RESERVED1   0x002 /* reserved */

Definition at line 145 of file cassini.h.

#define BIM_CFG_RESERVED2   0x100 /* reserved */

Definition at line 152 of file cassini.h.

#define BIM_CFG_RMA_INTR_ENABLE   0x040 /* master abort intr enable */

Definition at line 150 of file cassini.h.

#define BIM_CFG_RTA_INTR_ENABLE   0x080 /* target abort intr enable */

Definition at line 151 of file cassini.h.

#define BIM_DIAG_BRST_SM_MASK
Value:
0x7F /* PCI burst controller state
machine bits [6:0] */

Definition at line 160 of file cassini.h.

#define BIM_DIAG_MSTR_SM_MASK
Value:
0x3FFFFF00 /* PCI master controller state
machine bits [21:0] */

Definition at line 159 of file cassini.h.

#define BIM_LOCAL_DEV_EXT
Value:
0x04 /* secondary local bus device chip
select output enable */

Definition at line 191 of file cassini.h.

#define BIM_LOCAL_DEV_HW_RESET   0x20 /* internal hw reset. Cassini+ only. */

Definition at line 194 of file cassini.h.

#define BIM_LOCAL_DEV_PAD
Value:
0x01 /* address bus, RW signal, and
OE signal output enable on the
local bus interface. these
are shared between both local
bus devices. tristate when 0. */

Definition at line 189 of file cassini.h.

#define BIM_LOCAL_DEV_PROM   0x02 /* PROM chip select */

Definition at line 190 of file cassini.h.

#define BIM_LOCAL_DEV_SOFT_0   0x08 /* sw programmable ctrl bit 0 */

Definition at line 192 of file cassini.h.

#define BIM_LOCAL_DEV_SOFT_1   0x10 /* sw programmable ctrl bit 1 */

Definition at line 193 of file cassini.h.

#define BIM_RAM_BIST_RD_HI_PASS   0x20 /* read high bank passes BIST */

Definition at line 217 of file cassini.h.

#define BIM_RAM_BIST_RD_LOW_PASS   0x10 /* read low bank passes BIST */

Definition at line 216 of file cassini.h.

#define BIM_RAM_BIST_RD_PASS
Value:
0x04 /* summary BIST pass status for read
buffer. */

Definition at line 214 of file cassini.h.

#define BIM_RAM_BIST_RD_START   0x01 /* start BIST for BIM read buffer */

Definition at line 212 of file cassini.h.

#define BIM_RAM_BIST_WR_HI_PASS
Value:
0x80 /* write high bank passes BIST.
Cassini only. reserved in
Cassini+. */

Definition at line 219 of file cassini.h.

#define BIM_RAM_BIST_WR_LOW_PASS
Value:
0x40 /* write low bank passes BIST.
Cassini only. reserved in
Cassini+. */

Definition at line 218 of file cassini.h.

#define BIM_RAM_BIST_WR_PASS
Value:
0x08 /* summary BIST pass status for write
buffer. Cassini only. reserved
in Cassini+. */

Definition at line 215 of file cassini.h.

#define BIM_RAM_BIST_WR_START
Value:
0x02 /* start BIST for BIM write buffer.
Cassini only. reserved in
Cassini+. */

Definition at line 213 of file cassini.h.

#define BROADCOM_MII_REG4   0x14

Definition at line 1309 of file cassini.h.

#define BROADCOM_MII_REG5   0x15

Definition at line 1310 of file cassini.h.

#define BROADCOM_MII_REG7   0x17

Definition at line 1311 of file cassini.h.

#define BROADCOM_MII_REG8   0x18

Definition at line 1312 of file cassini.h.

#define CAS_ADVERTISE_1000FULL   0x0200

Definition at line 1330 of file cassini.h.

#define CAS_ADVERTISE_1000HALF   0x0100

Definition at line 1329 of file cassini.h.

#define CAS_ADVERTISE_ASYM_PAUSE   0x0800

Definition at line 1332 of file cassini.h.

#define CAS_ADVERTISE_PAUSE   0x0400

Definition at line 1331 of file cassini.h.

#define CAS_ALIGN (   addr,
  align 
)    (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))

Definition at line 2094 of file cassini.h.

#define CAS_BASE (   x,
  y 
)    (((y) << (x ## _SHIFT)) & (x ## _MASK))

Definition at line 1787 of file cassini.h.

#define CAS_BMCR_SPEED1000   0x0040 /* Select 1000Mbps */

Definition at line 1327 of file cassini.h.

#define CAS_BMSR_1000_EXTEND   0x0100 /* supports 1000Base-T extended status */

Definition at line 1320 of file cassini.h.

#define CAS_EXTEND_1000TFULL   0x2000

Definition at line 1344 of file cassini.h.

#define CAS_EXTEND_1000THALF   0x1000

Definition at line 1345 of file cassini.h.

#define CAS_EXTEND_1000XFULL   0x8000

Definition at line 1342 of file cassini.h.

#define CAS_EXTEND_1000XHALF   0x4000

Definition at line 1343 of file cassini.h.

#define CAS_FLAG_1000MB_CAP   0x00000001

Definition at line 2005 of file cassini.h.

#define CAS_FLAG_ENTROPY_DEV   0x00000100

Definition at line 2013 of file cassini.h.

#define CAS_FLAG_NO_HW_CSUM   0x00000200

Definition at line 2014 of file cassini.h.

#define CAS_FLAG_REG_PLUS   0x00000002

Definition at line 2006 of file cassini.h.

#define CAS_FLAG_RXD_POST (   x)
Value:
((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
CAS_FLAG_RXD_POST_MASK)

Definition at line 2011 of file cassini.h.

#define CAS_FLAG_RXD_POST_MASK   0x000000F0

Definition at line 2009 of file cassini.h.

#define CAS_FLAG_RXD_POST_SHIFT   4

Definition at line 2010 of file cassini.h.

#define CAS_FLAG_SATURN   0x00000008

Definition at line 2008 of file cassini.h.

#define CAS_FLAG_TARGET_ABORT   0x00000004

Definition at line 2007 of file cassini.h.

#define CAS_ID_REV2   0x02

Definition at line 48 of file cassini.h.

#define CAS_ID_REVPLUS   0x10

Definition at line 49 of file cassini.h.

#define CAS_ID_REVPLUS02u   0x11

Definition at line 50 of file cassini.h.

#define CAS_ID_REVSATURNB2   0x30

Definition at line 51 of file cassini.h.

#define CAS_JUMBO_PAGE_SHIFT   13 /* 8192 */

Definition at line 1795 of file cassini.h.

#define CAS_LPA_1000FULL   0x0800

Definition at line 1340 of file cassini.h.

#define CAS_LPA_1000HALF   0x0400

Definition at line 1339 of file cassini.h.

#define CAS_LPA_ASYM_PAUSE   CAS_ADVERTISE_ASYM_PAUSE

Definition at line 1336 of file cassini.h.

#define CAS_LPA_PAUSE   CAS_ADVERTISE_PAUSE

Definition at line 1335 of file cassini.h.

#define CAS_MAX_PAGE_SHIFT   14 /* 16384 */

Definition at line 1796 of file cassini.h.

#define CAS_MC_EXACT_MATCH_SIZE   15

Definition at line 2100 of file cassini.h.

#define CAS_MC_HASH_MAX
Value:
(CAS_MC_EXACT_MATCH_SIZE + \
CAS_MC_HASH_SIZE)

Definition at line 2102 of file cassini.h.

#define CAS_MC_HASH_SIZE   256

Definition at line 2101 of file cassini.h.

#define CAS_MII_1000_CTRL   0x09

Definition at line 1316 of file cassini.h.

#define CAS_MII_1000_EXTEND   0x0F

Definition at line 1318 of file cassini.h.

#define CAS_MII_1000_STATUS   0x0A

Definition at line 1317 of file cassini.h.

#define CAS_MII_ANNPRR   0x08

Definition at line 1315 of file cassini.h.

#define CAS_MII_ANNPTR   0x07

Definition at line 1314 of file cassini.h.

#define CAS_MIN_PAGE_SHIFT   11 /* 2048 */

Definition at line 1794 of file cassini.h.

#define CAS_PHY_MII (   x)    ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))

Definition at line 1737 of file cassini.h.

#define CAS_PHY_MII_MDIO0   0x02

Definition at line 1735 of file cassini.h.

#define CAS_PHY_MII_MDIO1   0x04

Definition at line 1736 of file cassini.h.

#define CAS_PHY_SERDES   0x01

Definition at line 1734 of file cassini.h.

#define CAS_PHY_UNKNOWN   0x00

Definition at line 1733 of file cassini.h.

#define CAS_PREF_CACHELINE_SIZE   0x20 /* Minimum desired */

Definition at line 2063 of file cassini.h.

#define CAS_PROG_IP46TCP4_PREAMBLE
Value:
{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
CL_REG, 0x000, 0, 0x0, 0x0000}, \
{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
CL_REG, 0x000, 0, 0x0, 0x0000}, \
{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
CL_REG, 0x000, 0, 0x0, 0x0000}, \
{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
CL_REG, 0x000, 0, 0x0, 0x0000}, \
{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
LD_SAP, 0x100, 3, 0x0, 0xffff}, \
{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
LD_SUM, 0x015, 1, 0x0, 0x0000}, \
{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
IM_R1, 0x128, 1, 0x0, 0xffff}, \
{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
LD_LEN, 0x03f, 1, 0x0, 0xffff}

Definition at line 1418 of file cassini.h.

#define CAS_TX_RINGN_BASE (   y)
Value:
((TX_DESC_RINGN_INDEX(y) << \
TX_CFG_DESC_RINGN_SHIFT(y)) & \
TX_CFG_DESC_RINGN_MASK(y))

Definition at line 1789 of file cassini.h.

#define CAS_VAL (   x,
  y 
)    (((y) & (x ## _MASK)) >> (x ## _SHIFT))

Definition at line 1788 of file cassini.h.

#define CAWR_RR_DIS   0x10 /* [4] */

Definition at line 66 of file cassini.h.

#define CAWR_RX_DMA_WEIGHT_MASK   0x03 /* [0:1] */

Definition at line 63 of file cassini.h.

#define CAWR_RX_DMA_WEIGHT_SHIFT   0

Definition at line 62 of file cassini.h.

#define CAWR_TX_DMA_WEIGHT_MASK   0x0C /* [3:2] */

Definition at line 65 of file cassini.h.

#define CAWR_TX_DMA_WEIGHT_SHIFT   2

Definition at line 64 of file cassini.h.

#define CL_REG   0

Definition at line 1373 of file cassini.h.

#define COMP_RING_I_TO_S (   x)    (128*(1 << (x)))

Definition at line 1751 of file cassini.h.

#define DESC_RING_I_TO_S (   x)    (32*(1 << (x)))

Definition at line 1750 of file cassini.h.

#define DP83065_MII_MEM   0x16

Definition at line 1303 of file cassini.h.

#define DP83065_MII_REGD   0x1D

Definition at line 1304 of file cassini.h.

#define DP83065_MII_REGE   0x1E

Definition at line 1305 of file cassini.h.

#define ENTROPY_MODE_ENCRYPT   0x40

Definition at line 1287 of file cassini.h.

#define ENTROPY_MODE_KEY_MASK   0x07

Definition at line 1286 of file cassini.h.

#define ENTROPY_RESET_DES_IO   0x01

Definition at line 1290 of file cassini.h.

#define ENTROPY_RESET_IV   0x08

Definition at line 1293 of file cassini.h.

#define ENTROPY_RESET_KEY_CACHE   0x04

Definition at line 1292 of file cassini.h.

#define ENTROPY_RESET_STC_MODE   0x02

Definition at line 1291 of file cassini.h.

#define ENTROPY_STATUS_BUSY   0x02

Definition at line 1282 of file cassini.h.

#define ENTROPY_STATUS_BYPASS_MASK   0x18

Definition at line 1284 of file cassini.h.

#define ENTROPY_STATUS_CIPHER   0x04

Definition at line 1283 of file cassini.h.

#define ENTROPY_STATUS_DRDY   0x01

Definition at line 1281 of file cassini.h.

#define EXPANSION_ROM_SIZE   65536

Definition at line 2098 of file cassini.h.

#define HP_CFG_NUM_CPU_MASK
Value:
0x000000FC /* # processors
0 = 64. 0x3f = 63 */

Definition at line 729 of file cassini.h.

#define HP_CFG_NUM_CPU_SHIFT   2

Definition at line 730 of file cassini.h.

#define HP_CFG_PARSE_EN   0x00000001 /* enab header parsing */

Definition at line 728 of file cassini.h.

#define HP_CFG_SYN_INC_MASK
Value:
0x00000100 /* SYN bit won't increment
TCP seq # by one when
stored in FDBM */

Definition at line 731 of file cassini.h.

#define HP_CFG_TCP_THRESH_MASK
Value:
0x000FFE00 /* # bytes of TCP data
needed to be considered
for reassembly */

Definition at line 732 of file cassini.h.

#define HP_CFG_TCP_THRESH_SHIFT   9

Definition at line 733 of file cassini.h.

#define HP_DATA_RAM_FDB_DATA_MASK
Value:
0x001F /* select 1 of 86 byte
locations in header
parser data ram to
read/write */

Definition at line 784 of file cassini.h.

#define HP_DATA_RAM_FDB_FDB_MASK
Value:
0x3F00 /* 1 of 64 353-bit locations
in the flow database */

Definition at line 785 of file cassini.h.

#define HP_INSTR_RAM_ADDR_MASK   0x01F /* 5-bit mask */

Definition at line 742 of file cassini.h.

#define HP_INSTR_RAM_HI_MASK_MASK   0xFFFF0000

Definition at line 770 of file cassini.h.

#define HP_INSTR_RAM_HI_MASK_SHIFT   16

Definition at line 771 of file cassini.h.

#define HP_INSTR_RAM_HI_VAL_MASK   0x0000FFFF

Definition at line 768 of file cassini.h.

#define HP_INSTR_RAM_HI_VAL_SHIFT   0

Definition at line 769 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTARG_MASK   0xFFC00000

Definition at line 750 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTARG_SHIFT   22

Definition at line 751 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTEN_MASK   0x00300000

Definition at line 748 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTEN_SHIFT   20

Definition at line 749 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTMASK_MASK   0x0000FFFF

Definition at line 744 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT   0

Definition at line 745 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK   0x000F0000

Definition at line 746 of file cassini.h.

#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT   16

Definition at line 747 of file cassini.h.

#define HP_INSTR_RAM_MID_FNEXT_MASK   0x000007C0

Definition at line 757 of file cassini.h.

#define HP_INSTR_RAM_MID_FNEXT_SHIFT   6

Definition at line 758 of file cassini.h.

#define HP_INSTR_RAM_MID_FOFF_MASK   0x0003F800

Definition at line 759 of file cassini.h.

#define HP_INSTR_RAM_MID_FOFF_SHIFT   11

Definition at line 760 of file cassini.h.

#define HP_INSTR_RAM_MID_OP_MASK   0xC0000000

Definition at line 765 of file cassini.h.

#define HP_INSTR_RAM_MID_OP_SHIFT   30

Definition at line 766 of file cassini.h.

#define HP_INSTR_RAM_MID_OUTARG_MASK   0x00000003

Definition at line 753 of file cassini.h.

#define HP_INSTR_RAM_MID_OUTARG_SHIFT   0

Definition at line 754 of file cassini.h.

#define HP_INSTR_RAM_MID_OUTOP_MASK   0x0000003C

Definition at line 755 of file cassini.h.

#define HP_INSTR_RAM_MID_OUTOP_SHIFT   2

Definition at line 756 of file cassini.h.

#define HP_INSTR_RAM_MID_SNEXT_MASK   0x007C0000

Definition at line 761 of file cassini.h.

#define HP_INSTR_RAM_MID_SNEXT_SHIFT   18

Definition at line 762 of file cassini.h.

#define HP_INSTR_RAM_MID_SOFF_MASK   0x3F800000

Definition at line 763 of file cassini.h.

#define HP_INSTR_RAM_MID_SOFF_SHIFT   23

Definition at line 764 of file cassini.h.

#define HP_RAM_BIST_FDBM_AGE0_PASS   0x08000000 /* FDBM aging RAM0 */

Definition at line 845 of file cassini.h.

#define HP_RAM_BIST_FDBM_AGE1_PASS   0x04000000 /* FDBM aging RAM1 */

Definition at line 846 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID00_PASS
Value:
0x02000000 /* FDBM flowid RAM0
bank 0 */

Definition at line 847 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID01_PASS
Value:
0x00200000 /* FDBM flowid RAM0
bank 1 */

Definition at line 851 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID10_PASS
Value:
0x01000000 /* FDBM flowid RAM1
bank 0 */

Definition at line 848 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID11_PASS
Value:
0x00100000 /* FDBM flowid RAM1
bank 2 */

Definition at line 852 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID20_PASS
Value:
0x00800000 /* FDBM flowid RAM2
bank 0 */

Definition at line 849 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID21_PASS
Value:
0x00080000 /* FDBM flowid RAM2
bank 1 */

Definition at line 853 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID30_PASS
Value:
0x00400000 /* FDBM flowid RAM3
bank 0 */

Definition at line 850 of file cassini.h.

#define HP_RAM_BIST_FDBM_FLOWID31_PASS
Value:
0x00040000 /* FDBM flowid RAM3
bank 1 */

Definition at line 854 of file cassini.h.

#define HP_RAM_BIST_FDBM_TCPSEQ_PASS
Value:
0x00020000 /* FDBM tcp sequence
RAM */

Definition at line 855 of file cassini.h.

#define HP_RAM_BIST_HP_DATA_PASS   0x80000000 /* HP data ram */

Definition at line 841 of file cassini.h.

#define HP_RAM_BIST_HP_INSTR0_PASS   0x40000000 /* HP instr ram 0 */

Definition at line 842 of file cassini.h.

#define HP_RAM_BIST_HP_INSTR1_PASS   0x20000000 /* HP instr ram 1 */

Definition at line 843 of file cassini.h.

#define HP_RAM_BIST_HP_INSTR2_PASS   0x10000000 /* HP instr ram 2 */

Definition at line 844 of file cassini.h.

#define HP_RAM_BIST_START   0x00000001 /* start/stop BIST */

Definition at line 857 of file cassini.h.

#define HP_RAM_BIST_SUMMARY   0x00000002 /* all BIST tests */

Definition at line 856 of file cassini.h.

#define HP_STATUS0_HRP_OPCODE_MASK   0x00000007 /* HRP opcode */

Definition at line 809 of file cassini.h.

#define HP_STATUS0_L3_OFF_MASK   0x0000FE00 /* L3 offset */

Definition at line 807 of file cassini.h.

#define HP_STATUS0_LB_CPUNUM_MASK
Value:
0x000001F8 /* load balancing CPU
number */

Definition at line 808 of file cassini.h.

#define HP_STATUS0_SAP_MASK   0xFFFF0000 /* SAP */

Definition at line 806 of file cassini.h.

#define HP_STATUS1_ACCUR2_MASK   0xE0000000 /* accu R2[6:4] */

Definition at line 812 of file cassini.h.

#define HP_STATUS1_FLOWID_MASK   0x1F800000 /* flow id */

Definition at line 813 of file cassini.h.

#define HP_STATUS1_TCP_OFF_MASK   0x007F0000 /* tcp payload offset */

Definition at line 814 of file cassini.h.

#define HP_STATUS1_TCP_SIZE_MASK   0x0000FFFF /* tcp payload size */

Definition at line 815 of file cassini.h.

#define HP_STATUS2_ACCUR1_MASK   0x000FE000 /* accu R1 */

Definition at line 820 of file cassini.h.

#define HP_STATUS2_ACCUR2_MASK   0xF0000000 /* accu R2[3:0] */

Definition at line 818 of file cassini.h.

#define HP_STATUS2_BWO_REASSM
Value:
0x00000800 /* batching w/o
reassembly */

Definition at line 822 of file cassini.h.

#define HP_STATUS2_CSUM_OFF_MASK
Value:
0x07F00000 /* checksum start
start offset */

Definition at line 819 of file cassini.h.

#define HP_STATUS2_CTRL_PACKET_FLAG   0x00000010 /* control packet flag */

Definition at line 829 of file cassini.h.

#define HP_STATUS2_DATA_MASK_ZERO
Value:
0x00000100 /* mask of data length
equal to zero */

Definition at line 825 of file cassini.h.

#define HP_STATUS2_FORCE_DROP   0x00001000 /* force drop */

Definition at line 821 of file cassini.h.

#define HP_STATUS2_FORCE_TCP_CHECK
Value:
0x00000080 /* force tcp payload
chk */

Definition at line 826 of file cassini.h.

#define HP_STATUS2_FORCE_TCP_NOCHECK
Value:
0x00000200 /* force tcp no payload
check */

Definition at line 824 of file cassini.h.

#define HP_STATUS2_JH_SPLIT_EN
Value:
0x00000400 /* jumbo header split
enable */

Definition at line 823 of file cassini.h.

#define HP_STATUS2_MASK_TCP_THRESH
Value:
0x00000040 /* mask of payload
threshold */

Definition at line 827 of file cassini.h.

#define HP_STATUS2_NO_ASSIST   0x00000020 /* no assist */

Definition at line 828 of file cassini.h.

#define HP_STATUS2_SYN_FLAG   0x00000004 /* syn flag */

Definition at line 831 of file cassini.h.

#define HP_STATUS2_TCP_CHECK   0x00000002 /* tcp payload chk */

Definition at line 832 of file cassini.h.

#define HP_STATUS2_TCP_FLAG_CHECK   0x00000008 /* tcp flag check */

Definition at line 830 of file cassini.h.

#define HP_STATUS2_TCP_NOCHECK   0x00000001 /* tcp no payload chk */

Definition at line 833 of file cassini.h.

#define HP_TCP_THRESH_VAL   1530 /* reduce to enable reassembly */

Definition at line 2111 of file cassini.h.

#define IM_CTL   13

Definition at line 1386 of file cassini.h.

#define IM_FID   9

Definition at line 1382 of file cassini.h.

#define IM_R1   12

Definition at line 1385 of file cassini.h.

#define IM_SAP   11

Definition at line 1384 of file cassini.h.

#define IM_SEQ   10

Definition at line 1383 of file cassini.h.

#define INF_BURST_EN   0x1 /* enable */

Definition at line 74 of file cassini.h.

#define INIT_BLOCK_RX_COMP   (RX_COMP_RING_SIZE)

Definition at line 1934 of file cassini.h.

#define INIT_BLOCK_RX_DESC   (RX_DESC_RING_SIZE)

Definition at line 1933 of file cassini.h.

#define INIT_BLOCK_TX   (TX_DESC_RING_SIZE)

Definition at line 1932 of file cassini.h.

#define INTR_ERROR_MASK
Value:
(INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
INTR_MAC_CTRL_STATUS)

Definition at line 102 of file cassini.h.

#define INTR_MAC_CTRL_STATUS
Value:
0x00010000 /* MAC control status register has
at least 1 unmasked interrupt
set */

Definition at line 97 of file cassini.h.

#define INTR_MIF_STATUS
Value:
0x00020000 /* MIF status register has at least
1 unmasked interrupt set */

Definition at line 98 of file cassini.h.

#define INTR_PCI_ERROR_STATUS
Value:
0x00040000 /* PCI error status register in the
BIF has at least 1 unmasked
interrupt set */

Definition at line 99 of file cassini.h.

#define INTR_PCS_STATUS   0x00002000 /* PCS interrupt status register */

Definition at line 94 of file cassini.h.

#define INTR_RX_BUF_AE
Value:
0x00000100 /* less than the
programmable threshold #
of free descr avail for
hw use */

Definition at line 90 of file cassini.h.

#define INTR_RX_BUF_AE_1   0x10 /* almost empty */

Definition at line 264 of file cassini.h.

#define INTR_RX_BUF_UNAVAIL
Value:
0x00000020 /* no more receive buffers.
RX Kick == RX complete */

Definition at line 87 of file cassini.h.

#define INTR_RX_BUF_UNAVAIL_1   0x08

Definition at line 263 of file cassini.h.

#define INTR_RX_COMP_AF
Value:
0x00000200 /* less than the
programmable threshold #
of descr spaces for hw
use in completion descr
ring */

Definition at line 91 of file cassini.h.

#define INTR_RX_COMP_AF_ALT   0x04

Definition at line 262 of file cassini.h.

#define INTR_RX_COMP_FULL
Value:
0x00000080 /* no more room in completion
ring to post descriptors.
RX complete head incr to
almost reach RX complete
tail */

Definition at line 89 of file cassini.h.

#define INTR_RX_COMP_FULL_ALT   0x02

Definition at line 261 of file cassini.h.

#define INTR_RX_DONE
Value:
0x00000010 /* at least 1 frame xferred
from RX FIFO to host mem.
RX completion reg updated.
may be delayed by recv
intr blanking. */

Definition at line 86 of file cassini.h.

#define INTR_RX_DONE_ALT   0x01

Definition at line 260 of file cassini.h.

#define INTR_RX_LEN_MISMATCH
Value:
0x00000400 /* len field from MAC !=
len of non-reassembly pkt
from fifo during DMA or
header parser provides TCP
header and payload size >
MAC packet size.
FATAL ERROR */

Definition at line 92 of file cassini.h.

#define INTR_RX_MAC_STATUS
Value:
0x00008000 /* RX MAC status register has at
least 1 unmasked interrupt set */

Definition at line 96 of file cassini.h.

#define INTR_RX_TAG_ERROR
Value:
0x00000040 /* RX FIFO tag framing
corrupted. FATAL ERROR */

Definition at line 88 of file cassini.h.

#define INTR_STATUS_ALT_INTX_EN
Value:
0x80 /* generate INTX when one of the
flags are set. enables desc ring. */

Definition at line 273 of file cassini.h.

#define INTR_SUMMARY
Value:
0x00001000 /* summary interrupt bit. this
bit will be set if an interrupt
generated on the pci bus. useful
when driver is polling for
interrupts */

Definition at line 93 of file cassini.h.

#define INTR_TX_ALL
Value:
0x00000002 /* all xmit frames xferred into
TX FIFO. i.e.,
TX Kick == TX complete. if
PACED_MODE set, then TX FIFO
also empty */

Definition at line 83 of file cassini.h.

#define INTR_TX_COMP_3_MASK
Value:
0xFFF80000 /* mask for TX completion
3 reg data */

Definition at line 100 of file cassini.h.

#define INTR_TX_COMP_3_SHIFT   19

Definition at line 101 of file cassini.h.

#define INTR_TX_DONE
Value:
0x00000004 /* any frame xferred into tx
FIFO */

Definition at line 84 of file cassini.h.

#define INTR_TX_INTME
Value:
0x00000001 /* frame w/ INT ME desc bit set
xferred from host queue to
TX FIFO */

Definition at line 82 of file cassini.h.

#define INTR_TX_MAC_STATUS
Value:
0x00004000 /* TX MAC status register has at
least 1 unmasked interrupt set */

Definition at line 95 of file cassini.h.

#define INTR_TX_TAG_ERROR
Value:
0x00000008 /* TX FIFO tag framing
corrupted. FATAL ERROR */

Definition at line 85 of file cassini.h.

#define INTRN_MASK_CLEAR_ALL
Value:
(INTR_RX_DONE_ALT | \
INTR_RX_COMP_FULL_ALT | \
INTR_RX_COMP_AF_ALT | \
INTR_RX_BUF_UNAVAIL_1 | \
INTR_RX_BUF_AE_1)

Definition at line 266 of file cassini.h.

#define INTRN_MASK_RX_EN   0x80

Definition at line 265 of file cassini.h.

#define LD_CTL   3

Definition at line 1376 of file cassini.h.

#define LD_FID   1

Definition at line 1374 of file cassini.h.

#define LD_HDR   8

Definition at line 1381 of file cassini.h.

#define LD_L3   6

Definition at line 1379 of file cassini.h.

#define LD_LEN   14

Definition at line 1387 of file cassini.h.

#define LD_R1   5

Definition at line 1378 of file cassini.h.

#define LD_SAP   4

Definition at line 1377 of file cassini.h.

#define LD_SEQ   2

Definition at line 1375 of file cassini.h.

#define LD_SUM   7

Definition at line 1380 of file cassini.h.

#define LINK_TRANSITION_LINK_CONFIG   4

Definition at line 2054 of file cassini.h.

#define LINK_TRANSITION_LINK_DOWN   5

Definition at line 2055 of file cassini.h.

#define LINK_TRANSITION_LINK_UP   3

Definition at line 2053 of file cassini.h.

#define LINK_TRANSITION_ON_FAILURE   1

Definition at line 2051 of file cassini.h.

#define LINK_TRANSITION_REQUESTED_RESET   6

Definition at line 2056 of file cassini.h.

#define LINK_TRANSITION_STILL_FAILED   2

Definition at line 2052 of file cassini.h.

#define LINK_TRANSITION_UNKNOWN   0

Definition at line 2050 of file cassini.h.

#define LUCENT_MII_REG   0x1F

Definition at line 1300 of file cassini.h.

#define MAC_CTRL_CFG_PASS_CTRL
Value:
0x0004 /* pass valid MAC ctrl
packets to RX DMA */

Definition at line 958 of file cassini.h.

#define MAC_CTRL_CFG_RECV_PAUSE_EN
Value:
0x0002 /* respond to received
pause flow ctrl frames */

Definition at line 957 of file cassini.h.

#define MAC_CTRL_CFG_SEND_PAUSE_EN
Value:
0x0001 /* respond to requests for
sending pause flow ctrl
frames */

Definition at line 956 of file cassini.h.

#define MAC_CTRL_NOPAUSE_STATE
Value:
0x00000004 /* MAC has made a
transition from
"paused" to "not
paused" */

Definition at line 902 of file cassini.h.

#define MAC_CTRL_PAUSE_RECEIVED
Value:
0x00000001 /* successful
reception of a
pause control
frame */

Definition at line 900 of file cassini.h.

#define MAC_CTRL_PAUSE_STATE
Value:
0x00000002 /* MAC has made a
transition from
"not paused" to
"paused" */

Definition at line 901 of file cassini.h.

#define MAC_CTRL_PAUSE_TIME_MASK
Value:
0xFFFF0000 /* value of pause time
operand that was
received in the last
pause flow control
frame */

Definition at line 903 of file cassini.h.

#define MAC_FRAMESIZE_MAX_BURST_MASK   0x3FFF0000 /* max burst size */

Definition at line 985 of file cassini.h.

#define MAC_FRAMESIZE_MAX_BURST_SHIFT   16

Definition at line 986 of file cassini.h.

#define MAC_FRAMESIZE_MAX_FRAME_MASK   0x00007FFF /* max frame size */

Definition at line 987 of file cassini.h.

#define MAC_FRAMESIZE_MAX_FRAME_SHIFT   0

Definition at line 988 of file cassini.h.

#define MAC_RX_ALIGN_ERR
Value:
0x0008 /* rollover of alignment
error counter */

Definition at line 893 of file cassini.h.

#define MAC_RX_CFG_ADDR_FILTER_EN
Value:
0x0040 /* cause RX MAC to use
address filtering regs
to filter both unicast
and multicast
addresses */

Definition at line 950 of file cassini.h.

#define MAC_RX_CFG_CARRIER_EXTEND
Value:
0x0100 /* enable reception of
packet bursts generated
by carrier extension
with packet bursting
senders. only applies
to half-duplex 1Gbps */

Definition at line 952 of file cassini.h.

#define MAC_RX_CFG_DISABLE_DISCARD
Value:
0x0080 /* pass errored frames to
RX DMA by setting BAD
bit but not Abort bit
in the status. CRC,
framing, and length errs
will not increment
error counters. frames
which don't match dest
addr will be passed up
w/ BAD bit set. */

Definition at line 951 of file cassini.h.

#define MAC_RX_CFG_EN   0x0001 /* enable RX MAC */

Definition at line 944 of file cassini.h.

#define MAC_RX_CFG_HASH_FILTER_EN
Value:
0x0020 /* use hash table to filter
multicast addresses */

Definition at line 949 of file cassini.h.

#define MAC_RX_CFG_PROMISC_EN   0x0008 /* promiscuous mode */

Definition at line 947 of file cassini.h.

#define MAC_RX_CFG_PROMISC_GROUP_EN
Value:
0x0010 /* accept all valid
multicast frames (group
bit in DA field set) */

Definition at line 948 of file cassini.h.

#define MAC_RX_CFG_STRIP_FCS
Value:
0x0004 /* RX MAC will strip the
last 4 bytes of a
received frame. */

Definition at line 946 of file cassini.h.

#define MAC_RX_CFG_STRIP_PAD
Value:
0x0002 /* always program to 0.
feature not supported */

Definition at line 945 of file cassini.h.

#define MAC_RX_CRC_ERR
Value:
0x0010 /* rollover of crc error
counter */

Definition at line 894 of file cassini.h.

#define MAC_RX_FRAME_COUNT
Value:
0x0004 /* rollover of receive frame
counter */

Definition at line 892 of file cassini.h.

#define MAC_RX_FRAME_RECV
Value:
0x0001 /* successful receipt of
a frame */

Definition at line 890 of file cassini.h.

#define MAC_RX_LEN_ERR
Value:
0x0020 /* rollover of length
error counter */

Definition at line 895 of file cassini.h.

#define MAC_RX_OVERFLOW
Value:
0x0002 /* dropped frame due to
RX FIFO overflow */

Definition at line 891 of file cassini.h.

#define MAC_RX_VIOL_ERR
Value:
0x0040 /* rollover of code
violation error */

Definition at line 896 of file cassini.h.

#define MAC_SEND_PAUSE_SEND
Value:
0x00010000 /* send pause flow ctrl
frame on network */

Definition at line 870 of file cassini.h.

#define MAC_SEND_PAUSE_TIME_MASK
Value:
0x0000FFFF /* value of pause time
to be sent on network
in units of slot
times */

Definition at line 869 of file cassini.h.

#define MAC_SM_ENCAP_SM_MASK   0x0000F000

Definition at line 1063 of file cassini.h.

#define MAC_SM_ENCAP_SM_SHIFT   12

Definition at line 1064 of file cassini.h.

#define MAC_SM_FIFO_WRITE_SEL_MASK   0x00000038

Definition at line 1069 of file cassini.h.

#define MAC_SM_FIFO_WRITE_SEL_SHIFT   3

Definition at line 1070 of file cassini.h.

#define MAC_SM_RLM_MASK   0x07800000

Definition at line 1057 of file cassini.h.

#define MAC_SM_RLM_SHIFT   23

Definition at line 1058 of file cassini.h.

#define MAC_SM_RX_FC_MASK   0x00700000

Definition at line 1059 of file cassini.h.

#define MAC_SM_RX_FC_SHIFT   20

Definition at line 1060 of file cassini.h.

#define MAC_SM_TLM_MASK   0x000F0000

Definition at line 1061 of file cassini.h.

#define MAC_SM_TLM_SHIFT   16

Definition at line 1062 of file cassini.h.

#define MAC_SM_TX_FC_MASK   0x000003C0

Definition at line 1067 of file cassini.h.

#define MAC_SM_TX_FC_SHIFT   6

Definition at line 1068 of file cassini.h.

#define MAC_SM_TX_FIFO_EMPTY_MASK   0x00000007

Definition at line 1071 of file cassini.h.

#define MAC_SM_TX_FIFO_EMPTY_SHIFT   0

Definition at line 1072 of file cassini.h.

#define MAC_SM_TX_REQ_MASK   0x00000C00

Definition at line 1065 of file cassini.h.

#define MAC_SM_TX_REQ_SHIFT   10

Definition at line 1066 of file cassini.h.

#define MAC_TX_CFG_CARRIER_EXTEND
Value:
0x0200 /* enables xmit part of the
carrier extension
feature. this allows for
longer collision domains
by extending the carrier
and collision window
from the end of FCS until
the end of the slot time
if necessary. Required
for half-duplex at 1Gbps,
clear otherwise. */

Definition at line 932 of file cassini.h.

#define MAC_TX_CFG_EN
Value:
0x0001 /* enable TX MAC. 0 will
force TXMAC state
machine to remain in
idle state or to
transition to idle state
on completion of an
ongoing packet. */

Definition at line 923 of file cassini.h.

#define MAC_TX_CFG_IGNORE_CARRIER
Value:
0x0002 /* disable CSMA/CD deferral
process. set to 1 when
full duplex and 0 when
half duplex */

Definition at line 924 of file cassini.h.

#define MAC_TX_CFG_IGNORE_COLL
Value:
0x0004 /* disable CSMA/CD backoff
algorithm. set to 1 when
full duplex and 0 when
half duplex */

Definition at line 925 of file cassini.h.

#define MAC_TX_CFG_IPG_EN
Value:
0x0008 /* enable extension of the
Rx-to-TX IPG. after
receiving a frame, TX
MAC will reset its
deferral process to
carrier sense for the
amount of time = IPG0 +
IPG1 and commit to
transmission for time
specified in IPG2. when
0 or when xmitting frames
back-to-pack (Tx-to-Tx
IPG), TX MAC ignores
IPG0 and will only use
IPG1 for deferral time.
IPG2 still used. */

Definition at line 926 of file cassini.h.

#define MAC_TX_CFG_NEVER_GIVE_UP_EN
Value:
0x0010 /* TX MAC will not easily
give up on frame
xmission. if backoff
algorithm reaches the
ATTEMPT_LIMIT, it will
clear attempts counter
and continue trying to
send the frame as
specified by
GIVE_UP_LIM. when 0,
TX MAC will execute
standard CSMA/CD prot. */

Definition at line 927 of file cassini.h.

#define MAC_TX_CFG_NEVER_GIVE_UP_LIM
Value:
0x0020 /* when set, TX MAC will
continue to try to xmit
until successful. when
0, TX MAC will continue
to try xmitting until
successful or backoff
algorithm reaches
ATTEMPT_LIMIT*16 */

Definition at line 928 of file cassini.h.

#define MAC_TX_CFG_NO_BACKOFF
Value:
0x0040 /* modify CSMA/CD to disable
backoff algorithm. TX
MAC will not back off
after a xmission attempt
that resulted in a
collision. */

Definition at line 929 of file cassini.h.

#define MAC_TX_CFG_NO_FCS
Value:
0x0100 /* TX MAC will not generate
CRC for all xmitted
packets. when clear, CRC
generation is dependent
upon NO_CRC bit in the
xmit control word from
TX DMA */

Definition at line 931 of file cassini.h.

#define MAC_TX_CFG_SLOW_DOWN
Value:
0x0080 /* modify CSMA/CD so that
deferral process is reset
in response to carrier
sense during the entire
duration of IPG. TX MAC
will only commit to frame
xmission after frame
xmission has actually
begun. */

Definition at line 930 of file cassini.h.

#define MAC_TX_COLL_EXCESS
Value:
0x0010 /* rollover of the excessive
collision counter */

Definition at line 883 of file cassini.h.

#define MAC_TX_COLL_FIRST
Value:
0x0040 /* rollover of the first
collision counter */

Definition at line 885 of file cassini.h.

#define MAC_TX_COLL_LATE
Value:
0x0020 /* rollover of the late
collision counter */

Definition at line 884 of file cassini.h.

#define MAC_TX_COLL_NORMAL
Value:
0x0008 /* rollover of the normal
collision counter */

Definition at line 882 of file cassini.h.

#define MAC_TX_DEFER_TIMER
Value:
0x0080 /* rollover of the defer
timer */

Definition at line 886 of file cassini.h.

#define MAC_TX_FRAME_XMIT
Value:
0x0001 /* successful frame
transmision */

Definition at line 879 of file cassini.h.

#define MAC_TX_MAX_PACKET_ERR
Value:
0x0004 /* frame exceeds max allowed
length passed to TX MAC
by the DMA engine */

Definition at line 881 of file cassini.h.

#define MAC_TX_PEAK_ATTEMPTS
Value:
0x0100 /* rollover of the peak
attempts counter */

Definition at line 887 of file cassini.h.

#define MAC_TX_UNDERRUN
Value:
0x0002 /* terminated frame
transmission due to
data starvation in the
xmit data path */

Definition at line 880 of file cassini.h.

#define MAC_XIF_DISABLE_ECHO
Value:
0x0004 /* disables receive data
path during packet
xmission. clear to 0
in any full duplex mode,
in any loopback mode,
or in half-duplex SERDES
or SLINK modes. set when
in half-duplex when
using external phy. */

Definition at line 969 of file cassini.h.

#define MAC_XIF_FDPLX_LED   0x0040 /* FDPLXLED# active (low) */

Definition at line 973 of file cassini.h.

#define MAC_XIF_GMII_MODE
Value:
0x0008 /* MAC operates with GMII
clocks and datapath */

Definition at line 970 of file cassini.h.

#define MAC_XIF_LINK_LED   0x0020 /* LINKLED# active (low) */

Definition at line 972 of file cassini.h.

#define MAC_XIF_MII_BUFFER_OUTPUT_EN
Value:
0x0010 /* MII_BUF_EN pin. enable
external tristate buffer
on the MII receive
bus. */

Definition at line 971 of file cassini.h.

#define MAC_XIF_MII_INT_LOOPBACK
Value:
0x0002 /* loopback GMII xmit data
path to GMII recv data
path. phy mode register
clock selection must be
set to GMII mode and
GMII_MODE should be set
to 1. in loopback mode,
REFCLK will drive the
entire mac core. 0 for
normal operation. */

Definition at line 968 of file cassini.h.

#define MAC_XIF_TX_MII_OUTPUT_EN
Value:
0x0001 /* enable output drivers
on MII xmit bus */

Definition at line 967 of file cassini.h.

#define MAX_RX_COMP_RINGS   4

Definition at line 437 of file cassini.h.

#define MAX_RX_DESC_RINGS   2

receive dma registers

Definition at line 436 of file cassini.h.

#define MAX_TX_RINGS   (1 << MAX_TX_RINGS_SHIFT)

Definition at line 297 of file cassini.h.

#define MAX_TX_RINGS_MASK   (MAX_TX_RINGS - 1)

Definition at line 298 of file cassini.h.

#define MAX_TX_RINGS_SHIFT   2

transmit dma registers

Definition at line 296 of file cassini.h.

#define MIF_CFG_BB_MODE
Value:
0x0004 /* 1 -> bit-bang mode
0 -> frame mode */

Definition at line 1105 of file cassini.h.

#define MIF_CFG_MDIO_0
Value:
0x0100 /* (ro) dual purpose.
when MDIO_0 is idle,
1 -> tranceiver is
connected to MDIO_0.
when MIF is communicating
w/ MDIO_0 in bit-bang
mode, this bit indicates
the incoming bit stream
during a read op */

Definition at line 1108 of file cassini.h.

#define MIF_CFG_MDIO_1
Value:
0x0200 /* (ro) dual purpose.
when MDIO_1 is idle,
1 -> transceiver is
connected to MDIO_1.
when MIF is communicating
w/ MDIO_1 in bit-bang
mode, this bit indicates
the incoming bit stream
during a read op */

Definition at line 1109 of file cassini.h.

#define MIF_CFG_PHY_SELECT
Value:
0x0001 /* 1 -> select MDIO_1
0 -> select MDIO_0 */

Definition at line 1103 of file cassini.h.

#define MIF_CFG_POLL_EN
Value:
0x0002 /* enable polling
mechanism. if set,
BB_MODE should be 0 */

Definition at line 1104 of file cassini.h.

#define MIF_CFG_POLL_PHY_MASK
Value:
0x7C00 /* tranceiver address to
be polled */

Definition at line 1110 of file cassini.h.

#define MIF_CFG_POLL_PHY_SHIFT   10

Definition at line 1111 of file cassini.h.

#define MIF_CFG_POLL_REG_MASK
Value:
0x00F8 /* register address to be
used by polling mode.
only meaningful if POLL_EN
is set to 1 */

Definition at line 1106 of file cassini.h.

#define MIF_CFG_POLL_REG_SHIFT   3

Definition at line 1107 of file cassini.h.

#define MIF_FRAME_DATA_MASK
Value:
0x0000FFFF /* instruction payload
load with 16-bit data
to be written in
transceiver reg for a
write. doesn't matter
in a read. when
polling for
completion, field is
"don't care" for write
and 16-bit data
returned by the
transceiver for a
read (if valid bit
is set) */

Definition at line 1101 of file cassini.h.

#define MIF_FRAME_OP_READ   0x20000000 /* read OPcode */

Definition at line 1093 of file cassini.h.

#define MIF_FRAME_OP_WRITE   0x10000000 /* write OPcode */

Definition at line 1094 of file cassini.h.

#define MIF_FRAME_OPCODE_MASK
Value:
0x30000000 /* opcode. 01 for a
write. 10 for a
read */

Definition at line 1092 of file cassini.h.

#define MIF_FRAME_PHY_ADDR_MASK
Value:
0x0F800000 /* phy address. when
issuing an instr,
this field should be
loaded w/ the XCVR
addr */

Definition at line 1095 of file cassini.h.

#define MIF_FRAME_PHY_ADDR_SHIFT   23

Definition at line 1096 of file cassini.h.

#define MIF_FRAME_REG_ADDR_MASK
Value:
0x007C0000 /* register address.
when issuing an instr,
addr of register
to be read/written */

Definition at line 1097 of file cassini.h.

#define MIF_FRAME_REG_ADDR_SHIFT   18

Definition at line 1098 of file cassini.h.

#define MIF_FRAME_ST   0x40000000 /* STart of frame */

Definition at line 1091 of file cassini.h.

#define MIF_FRAME_START_MASK
Value:
0xC0000000 /* start of frame.
load w/ 01 when
issuing an instr */

Definition at line 1090 of file cassini.h.

#define MIF_FRAME_TURN_AROUND_LSB
Value:
0x00010000 /* turn around, LSB.
when issuing an instr,
set this bit to 0.
when polling for
completion, 1 means
that instr execution
has been completed */

Definition at line 1100 of file cassini.h.

#define MIF_FRAME_TURN_AROUND_MSB
Value:
0x00020000 /* turn around, MSB.
when issuing an instr,
set this bit to 1 */

Definition at line 1099 of file cassini.h.

#define MIF_SM_CONTROL_MASK
Value:
0x07 /* control state machine
state */

Definition at line 1129 of file cassini.h.

#define MIF_SM_EXECUTION_MASK
Value:
0x60 /* execution state machine
state */

Definition at line 1130 of file cassini.h.

#define MIF_STATUS_POLL_DATA_MASK
Value:
0xFFFF0000 /* poll data contains
the "latest image"
update of the XCVR
reg being read */

Definition at line 1122 of file cassini.h.

#define MIF_STATUS_POLL_DATA_SHIFT   16

Definition at line 1123 of file cassini.h.

#define MIF_STATUS_POLL_STATUS_MASK
Value:
0x0000FFFF /* poll status indicates
which bits in the
POLL_DATA field have
changed since the
MIF_STATUS reg was
last read */

Definition at line 1124 of file cassini.h.

#define MIF_STATUS_POLL_STATUS_SHIFT   0

Definition at line 1125 of file cassini.h.

#define N_RX_COMP_RINGS   0x1 /* for mult. PCI interrupts */

Definition at line 1771 of file cassini.h.

#define N_RX_DESC_RINGS   MAX_RX_DESC_RINGS /* 1 for ipsec */

Definition at line 1770 of file cassini.h.

#define N_RX_FLOWS   64

Definition at line 1774 of file cassini.h.

#define N_TX_RINGS   MAX_TX_RINGS /* for QoS */

Definition at line 1768 of file cassini.h.

#define N_TX_RINGS_MASK   MAX_TX_RINGS_MASK

Definition at line 1769 of file cassini.h.

#define OP_EQ   0 /* packet == value */

Definition at line 1367 of file cassini.h.

#define OP_GT   2 /* packet > value */

Definition at line 1369 of file cassini.h.

#define OP_LT   1 /* packet < value */

Definition at line 1368 of file cassini.h.

#define OP_NP   3 /* new packet */

Definition at line 1370 of file cassini.h.

#define PCI_ERR_BADACK
Value:
0x01 /* reserved in Cassini+.
set if no ACK64# during ABS64 cycle
in Cassini. */

Definition at line 127 of file cassini.h.

#define PCI_ERR_BIM_DMA_READ
Value:
0x10 /* BIM received 0 count DMA read req.
unused in Cassini. */

Definition at line 131 of file cassini.h.

#define PCI_ERR_BIM_DMA_TIMEOUT
Value:
0x20 /* BIM received 255 retries during
DMA. unused in cassini. */

Definition at line 132 of file cassini.h.

#define PCI_ERR_BIM_DMA_WRITE
Value:
0x08 /* BIM received 0 count DMA write req.
unused in Cassini. */

Definition at line 130 of file cassini.h.

#define PCI_ERR_DTRTO
Value:
0x02 /* delayed xaction timeout. set if
no read retry after 2^15 clocks */

Definition at line 128 of file cassini.h.

#define PCI_ERR_OTHER   0x04 /* other PCI errors */

Definition at line 129 of file cassini.h.

#define PCS_CFG_10MS_TIMER_OVERRIDE
Value:
0x20 /* shortens 10-20ms auto-
negotiation timer to
a few cycles for test
purposes */

Definition at line 1194 of file cassini.h.

#define PCS_CFG_EN
Value:
0x01 /* enable PCS. must be
0 when modifying
PCS_MII_ADVERT */

Definition at line 1190 of file cassini.h.

#define PCS_CFG_JITTER_STUDY_MASK
Value:
0x18 /* used to make jitter
measurements. a single
code group is xmitted
regularly.
0x0 = normal operation
0x1 = high freq test
pattern, D21.5
0x2 = low freq test
pattern, K28.7
0x3 = reserved */

Definition at line 1193 of file cassini.h.

#define PCS_CFG_SD_ACTIVE_LOW
Value:
0x04 /* changes interpretation
of optical signal to make
signal detect okay when
signal is low */

Definition at line 1192 of file cassini.h.

#define PCS_CFG_SD_OVERRIDE
Value:
0x02 /* sets signal detect to
OK. bit is
non-resettable */

Definition at line 1191 of file cassini.h.

#define PCS_DATAPATH_MODE_MII
Value:
0x00 /* PCS is not used and
MII/GMII is selected.
selection between MII and
GMII is controlled by
XIF_CFG */

Definition at line 1227 of file cassini.h.

#define PCS_DATAPATH_MODE_SERDES
Value:
0x02 /* PCS is used via the
10-bit interface */

Definition at line 1228 of file cassini.h.

#define PCS_INTR_STATUS_LINK_CHANGE
Value:
0x04 /* link status has changed
since last read */

Definition at line 1220 of file cassini.h.

#define PCS_MII_10_100_SEL
Value:
0x2000 /* read as 0. ignored on
writes */

Definition at line 1151 of file cassini.h.

#define PCS_MII_ADVERT_ACK   0x4000 /* (ro) */

Definition at line 1173 of file cassini.h.

#define PCS_MII_ADVERT_ASYM_PAUSE
Value:
0x0100 /* advertises PAUSE
asymmetric capability */

Definition at line 1171 of file cassini.h.

#define PCS_MII_ADVERT_FD
Value:
0x0020 /* advertise full duplex
1000 Base-X */

Definition at line 1168 of file cassini.h.

#define PCS_MII_ADVERT_HD
Value:
0x0040 /* advertise half-duplex
1000 Base-X */

Definition at line 1169 of file cassini.h.

#define PCS_MII_ADVERT_NEXT_PAGE   0x8000 /* (ro) forced 0x0 */

Definition at line 1174 of file cassini.h.

#define PCS_MII_ADVERT_RF_MASK
Value:
0x3000 /* remote fault. write bit13
to optionally indicate to
link partner that chip is
going off-line. bit12 will
get set when signal
detect == FAIL and will
remain set until
successful negotiation */

Definition at line 1172 of file cassini.h.

#define PCS_MII_ADVERT_SYM_PAUSE
Value:
0x0080 /* advertise PAUSE
symmetric capability */

Definition at line 1170 of file cassini.h.

#define PCS_MII_AUTONEG_EN
Value:
0x1000 /* default 1. PCS goes
through automatic
link config before it
can be used. when 0,
link can be used
w/out any link config
phase */

Definition at line 1150 of file cassini.h.

#define PCS_MII_CTRL_1000_SEL
Value:
0x0040 /* reads 1. ignored on
writes */

Definition at line 1144 of file cassini.h.

#define PCS_MII_CTRL_COLLISION_TEST
Value:
0x0080 /* COL signal at the PCS
to MAC interface is
activated regardless
of activity */

Definition at line 1145 of file cassini.h.

#define PCS_MII_CTRL_DUPLEX
Value:
0x0100 /* forced 0x0. PCS
behaviour same for
half and full dplx */

Definition at line 1146 of file cassini.h.

#define PCS_MII_ISOLATE
Value:
0x0400 /* read as 0. ignored
on writes */

Definition at line 1148 of file cassini.h.

#define PCS_MII_LPA_ACK   PCS_MII_ADVERT_ACK

Definition at line 1185 of file cassini.h.

#define PCS_MII_LPA_ASYM_PAUSE   PCS_MII_ADVERT_ASYM_PAUSE

Definition at line 1183 of file cassini.h.

#define PCS_MII_LPA_FD   PCS_MII_ADVERT_FD

Definition at line 1180 of file cassini.h.

#define PCS_MII_LPA_HD   PCS_MII_ADVERT_HD

Definition at line 1181 of file cassini.h.

#define PCS_MII_LPA_NEXT_PAGE   PCS_MII_ADVERT_NEXT_PAGE

Definition at line 1186 of file cassini.h.

#define PCS_MII_LPA_RF_MASK   PCS_MII_ADVERT_RF_MASK

Definition at line 1184 of file cassini.h.

#define PCS_MII_LPA_SYM_PAUSE   PCS_MII_ADVERT_SYM_PAUSE

Definition at line 1182 of file cassini.h.

#define PCS_MII_POWER_DOWN
Value:
0x0800 /* read as 0. ignored
on writes */

Definition at line 1149 of file cassini.h.

#define PCS_MII_RESET
Value:
0x8000 /* reset PCS. self-clears
when done */

Definition at line 1152 of file cassini.h.

#define PCS_MII_RESTART_AUTONEG
Value:
0x0200 /* self clearing.
restart auto-
negotiation */

Definition at line 1147 of file cassini.h.

#define PCS_MII_STATUS_AUTONEG_ABLE
Value:
0x0008 /* reads 1 (able to perform
auto-neg) */

Definition at line 1159 of file cassini.h.

#define PCS_MII_STATUS_AUTONEG_COMP
Value:
0x0020 /* 1 -> auto-negotiation
completed
0 -> auto-negotiation not
completed */

Definition at line 1161 of file cassini.h.

#define PCS_MII_STATUS_EXTEND_CAP   0x0001 /* reads 0 */

Definition at line 1156 of file cassini.h.

#define PCS_MII_STATUS_EXTEND_STATUS
Value:
0x0100 /* reads as 1. used as an
indication that this is
a 1000 Base-X PHY. writes
to it are ignored */

Definition at line 1162 of file cassini.h.

#define PCS_MII_STATUS_JABBER_DETECT   0x0002 /* reads 0 */

Definition at line 1157 of file cassini.h.

#define PCS_MII_STATUS_LINK_STATUS
Value:
0x0004 /* 1 -> link up.
0 -> link down. 0 is
latched so that 0 is
kept until read. read
2x to determine if the
link has gone up again */

Definition at line 1158 of file cassini.h.

#define PCS_MII_STATUS_REMOTE_FAULT
Value:
0x0010 /* 1 -> remote fault detected
from received link code
word. only valid after
auto-neg completed */

Definition at line 1160 of file cassini.h.

#define PCS_PACKET_COUNT_RX
Value:
0x07FF0000 /* pkts recvd by PCS
whether they
encountered an error
or not */

Definition at line 1266 of file cassini.h.

#define PCS_PACKET_COUNT_TX   0x000007FF /* pkts xmitted by PCS */

Definition at line 1265 of file cassini.h.

#define PCS_SERDES_CTRL_LOCKREF
Value:
0x04 /* frequency-lock RBC[0:1]
to REFCLK when set.
when clear, receiver
clock locks to incoming
serial data */

Definition at line 1234 of file cassini.h.

#define PCS_SERDES_CTRL_LOOPBACK
Value:
0x01 /* enable loopback on
serdes interface */

Definition at line 1232 of file cassini.h.

#define PCS_SERDES_CTRL_SYNCD_EN
Value:
0x02 /* enable sync carrier
detection. should be
0x0 for normal
operation */

Definition at line 1233 of file cassini.h.

#define PCS_SERDES_STATE_MASK   0x03

Definition at line 1258 of file cassini.h.

#define PCS_SM_LINK_STATE_MASK   0x0001E000

Definition at line 1202 of file cassini.h.

#define PCS_SM_LOSS_LINK_C
Value:
0x00100000 /* loss of link due to
recept of Config
codes */

Definition at line 1205 of file cassini.h.

#define PCS_SM_LOSS_LINK_SYNC
Value:
0x00200000 /* loss of link due to
loss of sync */

Definition at line 1206 of file cassini.h.

#define PCS_SM_LOSS_SIGNAL_DETECT
Value:
0x00400000 /* signal detect goes
from OK to FAIL. bit29
will also be set if
this is set */

Definition at line 1207 of file cassini.h.

#define PCS_SM_NO_LINK_BREAKLINK
Value:
0x01000000 /* link not up due to
receipt of breaklink
C codes from partner.
C codes w/ 0 content
received triggering
start/restart of
autonegotiation.
should be sent for
no longer than 20ms */

Definition at line 1208 of file cassini.h.

#define PCS_SM_NO_LINK_C
Value:
0x04000000 /* C codes not stable or
not received */

Definition at line 1210 of file cassini.h.

#define PCS_SM_NO_LINK_NO_IDLE
Value:
0x20000000 /* link partner continues
to send C codes
instead of idle
symbols or pkt data */

Definition at line 1213 of file cassini.h.

#define PCS_SM_NO_LINK_SERDES
Value:
0x02000000 /* serdes being
initialized. see serdes
state reg */

Definition at line 1209 of file cassini.h.

#define PCS_SM_NO_LINK_SYNC
Value:
0x08000000 /* word sync not
achieved */

Definition at line 1211 of file cassini.h.

#define PCS_SM_NO_LINK_WAIT_C
Value:
0x10000000 /* waiting for C codes
w/ ack bit set */

Definition at line 1212 of file cassini.h.

#define PCS_SM_RX_STATE_MASK
Value:
0x000000F0 /* 0 indicates reception
of idle. otherwise,
reception of packet */

Definition at line 1199 of file cassini.h.

#define PCS_SM_SEQ_DETECT_STATE_MASK
Value:
0x00001800 /* cycling through 0-3
indicates reception of
Config codes. cycling
through 0-1 indicates
reception of idles */

Definition at line 1201 of file cassini.h.

#define PCS_SM_TX_STATE_MASK
Value:
0x0000000F /* 0 and 1 indicate
xmission of idle.
otherwise, xmission of
a packet */

Definition at line 1198 of file cassini.h.

#define PCS_SM_WORD_SYNC_STATE_MASK
Value:
0x00000700 /* 0 indicates loss of
sync */

Definition at line 1200 of file cassini.h.

#define PCS_SOS_PROM_ADDR_MASK   0x0007

Definition at line 1247 of file cassini.h.

#define PHY_BROADCOM_5411   0x00206071

Definition at line 1307 of file cassini.h.

#define PHY_BROADCOM_B0   0x00206050

Definition at line 1308 of file cassini.h.

#define PHY_LUCENT_B0   0x00437421

Definition at line 1299 of file cassini.h.

#define PHY_NS_DP83065   0x20005c78

Definition at line 1302 of file cassini.h.

#define PROBE_MUX_EN
Value:
0x80000000 /* allow probe signals to be
driven on local bus P_A[15:0]
for debugging */

Definition at line 246 of file cassini.h.

#define PROBE_MUX_SEL_HI_MASK
Value:
0x000000F0 /* select which module to appear
on P_A[15:8]. see above for
values. */

Definition at line 248 of file cassini.h.

#define PROBE_MUX_SEL_LOW_MASK
Value:
0x0000000F /* select which module to appear
on P_A[7:0]. see above for
values. */

Definition at line 249 of file cassini.h.

#define PROBE_MUX_SUB_MUX_MASK
Value:
0x0000FF00 /* select sub module probe signals:
0x03 = mac[1:0]
0x0C = rx[1:0]
0x30 = tx[1:0]
0xC0 = hp[1:0] */

Definition at line 247 of file cassini.h.

#define REG_ALIAS_CLEAR
Value:
0x0014 /* alias clear mask
(used w/ status alias) */

Definition at line 118 of file cassini.h.

#define REG_BIM_BUFFER_ADDR
Value:
0x1024 /* BIM buffer address. for
purposes. */

Definition at line 201 of file cassini.h.

#define REG_BIM_BUFFER_DATA_HI   0x102C /* BIM buffer data high */

Definition at line 206 of file cassini.h.

#define REG_BIM_BUFFER_DATA_LOW   0x1028 /* BIM buffer data low */

Definition at line 205 of file cassini.h.

#define REG_BIM_CFG   0x1008 /* BIM Configuration */

Definition at line 143 of file cassini.h.

#define REG_BIM_DIAG   0x100C /* BIM Diagnostic */

Definition at line 158 of file cassini.h.

#define REG_BIM_DIAG_MUX
Value:
0x1030 /* BIM diagnostic probe mux
select register */

Definition at line 224 of file cassini.h.

#define REG_BIM_LOCAL_DEV_EN
Value:
0x1020 /* BIM local device
output EN. default: 0x7 */

Definition at line 188 of file cassini.h.

#define REG_BIM_RAM_BIST
Value:
0x102C /* BIM RAM (read buffer) BIST
control/status */

Definition at line 211 of file cassini.h.

#define REG_CAWR   0x0004 /* core arbitration weight */

global resources

Definition at line 61 of file cassini.h.

#define REG_ENTROPY_DATA   (REG_ENTROPY_START + 0x00)

Definition at line 1279 of file cassini.h.

#define REG_ENTROPY_IV   (REG_ENTROPY_START + 0x08)

Definition at line 1294 of file cassini.h.

#define REG_ENTROPY_KEY0   (REG_ENTROPY_START + 0x10)

Definition at line 1295 of file cassini.h.

#define REG_ENTROPY_KEYN (   x)    (REG_ENTROPY_KEY0 + 4*(x))

Definition at line 1296 of file cassini.h.

#define REG_ENTROPY_MODE   (REG_ENTROPY_START + 0x05)

Definition at line 1285 of file cassini.h.

#define REG_ENTROPY_RAND_REG   (REG_ENTROPY_START + 0x06)

Definition at line 1288 of file cassini.h.

#define REG_ENTROPY_RESET   (REG_ENTROPY_START + 0x07)

Definition at line 1289 of file cassini.h.

#define REG_ENTROPY_START   REG_SECOND_LOCALBUS_START

Definition at line 1278 of file cassini.h.

#define REG_ENTROPY_STATUS   (REG_ENTROPY_START + 0x04)

Definition at line 1280 of file cassini.h.

#define REG_EXPANSION_ROM_RUN_END   0x17FFFF

Definition at line 1272 of file cassini.h.

#define REG_EXPANSION_ROM_RUN_START
Value:
0x100000 /* expansion rom run time
access */

LocalBus Devices. the following provides run-time access to the Cassini's PROM

Definition at line 1271 of file cassini.h.

#define REG_HP_CFG
Value:
0x4140 /* header parser
configuration reg */

header parser registers

Definition at line 727 of file cassini.h.

#define REG_HP_DATA_RAM_DATA   0x4158 /* HP data RAM data */

Definition at line 786 of file cassini.h.

#define REG_HP_DATA_RAM_FDB_ADDR
Value:
0x4154 /* HP data and FDB
RAM address */

Definition at line 783 of file cassini.h.

#define REG_HP_FLOW_DB0   0x415C /* HP flow database 1 reg */

Definition at line 797 of file cassini.h.

#define REG_HP_FLOW_DBN (   x)    (REG_HP_FLOW_DB0 + (x)*4)

Definition at line 798 of file cassini.h.

#define REG_HP_INSTR_RAM_ADDR
Value:
0x4144 /* HP instruction RAM
address */

Definition at line 741 of file cassini.h.

#define REG_HP_INSTR_RAM_DATA_HI
Value:
0x4150 /* HP instruction RAM
data high */

Definition at line 767 of file cassini.h.

#define REG_HP_INSTR_RAM_DATA_LOW
Value:
0x4148 /* HP instruction RAM
data low */

Definition at line 743 of file cassini.h.

#define REG_HP_INSTR_RAM_DATA_MID
Value:
0x414C /* HP instruction RAM
data mid */

Definition at line 752 of file cassini.h.

#define REG_HP_RAM_BIST   0x419C /* HP RAM BIST reg */

Definition at line 840 of file cassini.h.

#define REG_HP_STATE_MACHINE   0x418C /* (ro) HP state machine */

Definition at line 804 of file cassini.h.

#define REG_HP_STATUS0   0x4190 /* (ro) HP status 1 */

Definition at line 805 of file cassini.h.

#define REG_HP_STATUS1   0x4194 /* (ro) HP status 2 */

Definition at line 811 of file cassini.h.

#define REG_HP_STATUS2   0x4198 /* (ro) HP status 3 */

Definition at line 817 of file cassini.h.

#define REG_INF_BURST   0x0008 /* infinite burst enable reg */

Definition at line 73 of file cassini.h.

#define REG_INTR_MASK   0x0010 /* Interrupt mask */

Definition at line 112 of file cassini.h.

#define REG_INTR_STATUS   0x000C /* interrupt status register */

Definition at line 81 of file cassini.h.

#define REG_INTR_STATUS_ALIAS
Value:
0x001C /* interrupt status alias
(selective clear) */

Definition at line 123 of file cassini.h.

#define REG_MAC_ADDR0   0x6080 /* MAC address 0 reg */

Definition at line 1016 of file cassini.h.

#define REG_MAC_ADDR_FILTER0
Value:
0x614C /* address filter 0 reg
[47:32] */

Definition at line 1018 of file cassini.h.

#define REG_MAC_ADDR_FILTER0_MASK
Value:
0x615C /* address filter 0 mask
reg */

Definition at line 1022 of file cassini.h.

#define REG_MAC_ADDR_FILTER1
Value:
0x6150 /* address filter 1 reg
[31:16] */

Definition at line 1019 of file cassini.h.

#define REG_MAC_ADDR_FILTER2
Value:
0x6154 /* address filter 2 reg
[15:0] */

Definition at line 1020 of file cassini.h.

#define REG_MAC_ADDR_FILTER2_1_MASK
Value:
0x6158 /* address filter 2 and 1
mask reg. 8-bit reg
contains nibble mask for
reg 2 and 1. */

Definition at line 1021 of file cassini.h.

#define REG_MAC_ADDRN (   x)    (REG_MAC_ADDR0 + (x)*4)

Definition at line 1017 of file cassini.h.

#define REG_MAC_ALIGN_ERR   0x61C0 /* alignment error counter */

Definition at line 1044 of file cassini.h.

#define REG_MAC_ATTEMPT_LIMIT
Value:
0x6060 /* attempt limit reg. #
of attempts TX MAC will
make to xmit a frame
before it resets its
attempts counter. after
the limit has been
reached, TX MAC may or
may not drop the frame
dependent upon value
in TX_MAC_CFG.
recommended
value: 0x10 */

Definition at line 991 of file cassini.h.

#define REG_MAC_ATTEMPTS_PEAK   0x61B4 /* peak attempts reg */

Definition at line 1041 of file cassini.h.

#define REG_MAC_COLL_EXCESS
Value:
0x61A8 /* excessive collision
counter */

Definition at line 1038 of file cassini.h.

#define REG_MAC_COLL_FIRST
Value:
0x61A4 /* first attempt
successful collision
counter */

Definition at line 1037 of file cassini.h.

#define REG_MAC_COLL_LATE   0x61AC /* late collision counter */

Definition at line 1039 of file cassini.h.

#define REG_MAC_COLL_NORMAL
Value:
0x61A0 /* normal collision
counter. */

Definition at line 1036 of file cassini.h.

#define REG_MAC_CTRL_CFG   0x6038 /* MAC control config reg */

Definition at line 955 of file cassini.h.

#define REG_MAC_CTRL_MASK   0x6028 /* MAC control mask reg */

Definition at line 910 of file cassini.h.

#define REG_MAC_CTRL_STATUS   0x6018 /* MAC control status reg */

Definition at line 899 of file cassini.h.

#define REG_MAC_CTRL_TYPE
Value:
0x6064 /* MAC control type reg.
type field of a MAC
ctrl frame. recommended
value: 0x8808 */

Definition at line 992 of file cassini.h.

#define REG_MAC_FCS_ERR   0x61C4 /* FCS error counter */

Definition at line 1045 of file cassini.h.

#define REG_MAC_FRAMESIZE_MAX   0x6054 /* max frame size reg */

Definition at line 984 of file cassini.h.

#define REG_MAC_FRAMESIZE_MIN
Value:
0x6050 /* min frame size reg
recommended: 0x40 */

Definition at line 979 of file cassini.h.

#define REG_MAC_HASH_TABLE0   0x6160 /* hash table 0 reg */

Definition at line 1029 of file cassini.h.

#define REG_MAC_HASH_TABLEN (   x)    (REG_MAC_HASH_TABLE0 + (x)*4)

Definition at line 1030 of file cassini.h.

#define REG_MAC_IPG0
Value:
0x6040 /* inter-packet gap0 reg.
recommended: 0x00 */

Definition at line 975 of file cassini.h.

#define REG_MAC_IPG1
Value:
0x6044 /* inter-packet gap1 reg
recommended: 0x08 */

Definition at line 976 of file cassini.h.

#define REG_MAC_IPG2
Value:
0x6048 /* inter-packet gap2 reg
recommended: 0x04 */

Definition at line 977 of file cassini.h.

#define REG_MAC_JAM_SIZE
Value:
0x605C /* jam size reg. duration
of jam in units of media
byte time. recommended
value: 0x04 */

Definition at line 990 of file cassini.h.

#define REG_MAC_LEN_ERR   0x61BC /* length error counter */

Definition at line 1043 of file cassini.h.

#define REG_MAC_PA_SIZE
Value:
0x6058 /* PA size reg. number of
preamble bytes that the
TX MAC will xmit at the
beginning of each frame
value should be 2 or
greater. recommended
value: 0x07 */

Definition at line 989 of file cassini.h.

#define REG_MAC_RANDOM_SEED
Value:
0x61CC /* random number seed reg.
10-bit register used as a
seed for the random number
generator for the CSMA/CD
backoff algorithm. only
programmed after power-on
reset and should be a
random value which has a
high likelihood of being
unique for each MAC
attached to a network
segment (e.g., 10 LSB of
MAC address) */

Definition at line 1049 of file cassini.h.

#define REG_MAC_RECV_FRAME   0x61B8 /* receive frame counter */

Definition at line 1042 of file cassini.h.

#define REG_MAC_RX_CFG   0x6034 /* RX MAC config reg */

Definition at line 943 of file cassini.h.

#define REG_MAC_RX_CODE_ERR
Value:
0x61C8 /* RX code violation
error counter */

Definition at line 1046 of file cassini.h.

#define REG_MAC_RX_MASK   0x6024 /* RX MAC mask reg */

Definition at line 908 of file cassini.h.

#define REG_MAC_RX_RESET
Value:
0x6004 /* RX MAC software reset
command (default: 0x0) */

Definition at line 865 of file cassini.h.

#define REG_MAC_RX_STATUS   0x6014 /* RX MAC status reg */

Definition at line 889 of file cassini.h.

#define REG_MAC_SEND_PAUSE   0x6008 /* send pause command reg */

Definition at line 868 of file cassini.h.

#define REG_MAC_SLOT_TIME
Value:
0x604C /* slot time reg
recommended: 0x40 */

Definition at line 978 of file cassini.h.

#define REG_MAC_STATE_MACHINE   0x61D0 /* (ro) state machine reg */

Definition at line 1056 of file cassini.h.

#define REG_MAC_TIMER_DEFER
Value:
0x61B0 /* defer timer. time base
is the media byte
clock/256 */

Definition at line 1040 of file cassini.h.

#define REG_MAC_TX_CFG   0x6030 /* TX MAC config reg */

Definition at line 922 of file cassini.h.

#define REG_MAC_TX_MASK   0x6020 /* TX MAC mask reg */

Definition at line 906 of file cassini.h.

#define REG_MAC_TX_RESET
Value:
0x6000 /* TX MAC software reset
command (default: 0x0) */

MAC registers.

Definition at line 864 of file cassini.h.

#define REG_MAC_TX_STATUS   0x6010 /* TX MAC status reg */

Definition at line 878 of file cassini.h.

#define REG_MAC_XIF_CFG   0x603C /* XIF config reg */

Definition at line 966 of file cassini.h.

#define REG_MIF_BIT_BANG_CLOCK
Value:
0x6200 /* MIF bit-bang clock.
1 -> 0 will generate a
rising edge. 0 -> 1 will
generate a falling edge. */

MIF registers. the MIF can be programmed in either bit-bang or frame mode.

Definition at line 1077 of file cassini.h.

#define REG_MIF_BIT_BANG_DATA
Value:
0x6204 /* MIF bit-bang data. 1-bit
register generates data */

Definition at line 1078 of file cassini.h.

#define REG_MIF_BIT_BANG_OUTPUT_EN
Value:
0x6208 /* MIF bit-bang output
enable. enable when
xmitting data from MIF to
transceiver. */

Definition at line 1079 of file cassini.h.

#define REG_MIF_CFG   0x6210 /* MIF config reg */

Definition at line 1102 of file cassini.h.

#define REG_MIF_FRAME   0x620C /* MIF frame/output reg */

Definition at line 1089 of file cassini.h.

#define REG_MIF_MASK   0x6214 /* MIF mask reg */

Definition at line 1118 of file cassini.h.

#define REG_MIF_STATE_MACHINE   0x621C /* MIF state machine reg */

Definition at line 1128 of file cassini.h.

#define REG_MIF_STATUS   0x6218 /* MIF status reg */

Definition at line 1121 of file cassini.h.

#define REG_MINUS_BIM_DATAPATH_TEST
Value:
0x1018 /* Cassini: BIM datapath test
Cassini+: reserved */

Definition at line 181 of file cassini.h.

#define REG_PCI_ERR_STATUS   0x1000 /* PCI error status */

Definition at line 126 of file cassini.h.

#define REG_PCI_ERR_STATUS_MASK   0x1004 /* PCI Error status mask */

Definition at line 138 of file cassini.h.

#define REG_PCS_CFG   0x9010 /* PCS config reg */

Definition at line 1189 of file cassini.h.

#define REG_PCS_DATAPATH_MODE   0x9050 /* datapath mode reg */

Definition at line 1226 of file cassini.h.

#define REG_PCS_INTR_STATUS   0x9018 /* PCS interrupt status */

Definition at line 1219 of file cassini.h.

#define REG_PCS_MII_ADVERT
Value:
0x9008 /* PCS MII advertisement
reg */

Definition at line 1167 of file cassini.h.

#define REG_PCS_MII_CTRL   0x9000 /* PCS MII control reg */

PCS/Serialink. the following registers are equivalent to the standard MII management registers except that they're directly mapped in Cassini's register space.

Definition at line 1143 of file cassini.h.

#define REG_PCS_MII_LPA
Value:
0x900C /* PCS MII link partner
ability reg */

Definition at line 1179 of file cassini.h.

#define REG_PCS_MII_STATUS   0x9004 /* PCS MII status reg */

Definition at line 1155 of file cassini.h.

#define REG_PCS_PACKET_COUNT   0x9060 /* (ro) PCS packet counter */

Definition at line 1264 of file cassini.h.

#define REG_PCS_SERDES_CTRL   0x9054 /* serdes control reg */

Definition at line 1231 of file cassini.h.

#define REG_PCS_SERDES_STATE   0x905C /* (ro) serdes state */

Definition at line 1257 of file cassini.h.

#define REG_PCS_SHARED_OUTPUT_SEL   0x9058 /* shared output select */

Definition at line 1246 of file cassini.h.

#define REG_PCS_STATE_MACHINE
Value:
0x9014 /* (ro) PCS state machine
and diagnostic reg */

Definition at line 1197 of file cassini.h.

#define REG_PLUS_ALIAS_CLEAR_1
Value:
0x1040 /* Cassini+: alias clear mask
register 2 for INTB */

Definition at line 275 of file cassini.h.

#define REG_PLUS_ALIASN_CLEAR (   x)    (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)

Definition at line 276 of file cassini.h.

#define REG_PLUS_INTR_MASK_1
Value:
0x1038 /* Cassini+: interrupt mask
register 2 for INTB */

Definition at line 253 of file cassini.h.

#define REG_PLUS_INTR_STATUS_1
Value:
0x103C /* Cassini+: interrupt status
register 2 for INTB. default: 0x1F */

Definition at line 271 of file cassini.h.

#define REG_PLUS_INTR_STATUS_ALIAS_1
Value:
0x1044 /* Cassini+: interrupt status
register alias 2 for INTB */

Definition at line 278 of file cassini.h.

#define REG_PLUS_INTRN_MASK (   x)    (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)

Definition at line 254 of file cassini.h.

#define REG_PLUS_INTRN_STATUS (   x)    (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)

Definition at line 272 of file cassini.h.

#define REG_PLUS_INTRN_STATUS_ALIAS (   x)    (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)

Definition at line 279 of file cassini.h.

#define REG_PLUS_PROBE_MUX_SELECT   0x1034 /* Cassini+: PROBE MUX SELECT */

Definition at line 245 of file cassini.h.

#define REG_PLUS_RX_AE1_THRESH
Value:
0x4240 /* RX almost empty 2
thresholds */

Definition at line 718 of file cassini.h.

#define REG_PLUS_RX_CB1_HI
Value:
0x420C /* RX completion ring
2 base high. 4 total */

Definition at line 709 of file cassini.h.

#define REG_PLUS_RX_CB1_LOW
Value:
0x4208 /* RX completion ring
2 base low. 4 total */

Definition at line 708 of file cassini.h.

#define REG_PLUS_RX_CBN_HI (   x)    (REG_PLUS_RX_CB1_HI + 8*((x) - 1))

Definition at line 711 of file cassini.h.

#define REG_PLUS_RX_CBN_LOW (   x)    (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))

Definition at line 710 of file cassini.h.

#define REG_PLUS_RX_COMP1
Value:
0x4224 /* (ro) RX completion 2
reg */

Definition at line 713 of file cassini.h.

#define REG_PLUS_RX_COMP1_HEAD
Value:
0x4228 /* (ro) RX completion 2
head reg. 4 total. */

Definition at line 714 of file cassini.h.

#define REG_PLUS_RX_COMP1_TAIL
Value:
0x422C /* RX completion 2
tail reg. 4 total. */

Definition at line 715 of file cassini.h.

#define REG_PLUS_RX_COMPN_HEAD (   x)    (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))

Definition at line 716 of file cassini.h.

#define REG_PLUS_RX_COMPN_TAIL (   x)    (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))

Definition at line 717 of file cassini.h.

#define REG_PLUS_RX_DB1_HI
Value:
0x4204 /* RX descriptor ring
2 base high */

Definition at line 707 of file cassini.h.

#define REG_PLUS_RX_DB1_LOW
Value:
0x4200 /* RX descriptor ring
2 base low */

Definition at line 706 of file cassini.h.

#define REG_PLUS_RX_KICK1   0x4220 /* RX Kick 2 register */

Definition at line 712 of file cassini.h.

#define REG_RX_AE_THRESH
Value:
0x4048 /* RX almost empty
thresholds */

Definition at line 566 of file cassini.h.

#define REG_RX_BIST   0x4060 /* (ro) RX BIST */

Definition at line 601 of file cassini.h.

#define REG_RX_BLANK
Value:
0x4044 /* RX blanking register
for ISR read */

Definition at line 556 of file cassini.h.

#define REG_RX_BLANK_ALIAS_READ
Value:
0x406C /* RX blanking register for
alias read */

Definition at line 634 of file cassini.h.

#define REG_RX_CB_HI
Value:
0x4034 /* RX completion ring
base hi */

Definition at line 533 of file cassini.h.

#define REG_RX_CB_LOW
Value:
0x4030 /* RX completion ring
base low */

Definition at line 532 of file cassini.h.

#define REG_RX_CFG   0x4000 /* RX config */

Definition at line 444 of file cassini.h.

#define REG_RX_COMP   0x4038 /* (ro) RX completion */

Definition at line 538 of file cassini.h.

#define REG_RX_COMP_HEAD   0x403C /* RX completion head */

Definition at line 550 of file cassini.h.

#define REG_RX_COMP_TAIL   0x4040 /* RX completion tail */

Definition at line 551 of file cassini.h.

#define REG_RX_CTRL_FIFO_ADDR
Value:
0x4094 /* RX Control FIFO and
Batching FIFO addr */

Definition at line 659 of file cassini.h.

#define REG_RX_CTRL_FIFO_DATA_HI
Value:
0x4100 /* RX Control FIFO data
hi and flow id */

Definition at line 662 of file cassini.h.

#define REG_RX_CTRL_FIFO_DATA_LOW
Value:
0x4098 /* RX Control FIFO data
low */

Definition at line 660 of file cassini.h.

#define REG_RX_CTRL_FIFO_DATA_MID
Value:
0x409C /* RX Control FIFO data
mid */

Definition at line 661 of file cassini.h.

#define REG_RX_CTRL_FIFO_READ_PTR
Value:
0x4068 /* (ro) RX control FIFO read
ptr */

Definition at line 628 of file cassini.h.

#define REG_RX_CTRL_FIFO_WRITE_PTR
Value:
0x4064 /* (ro) RX control FIFO
write ptr */

Definition at line 627 of file cassini.h.

#define REG_RX_DB_HI
Value:
0x402C /* RX descriptor ring
base hi */

Definition at line 531 of file cassini.h.

#define REG_RX_DB_LOW
Value:
0x4028 /* RX descriptor ring
base low */

Definition at line 530 of file cassini.h.

#define REG_RX_DEBUG   0x401C /* RX debug */

Definition at line 494 of file cassini.h.

#define REG_RX_FIFO_ADDR   0x4080 /* RX FIFO address */

Definition at line 646 of file cassini.h.

#define REG_RX_FIFO_DATA_HI_T0   0x408C /* RX FIFO data high T0 */

Definition at line 649 of file cassini.h.

#define REG_RX_FIFO_DATA_HI_T1   0x4090 /* RX FIFO data high T1 */

Definition at line 650 of file cassini.h.

#define REG_RX_FIFO_DATA_LOW   0x4088 /* RX FIFO data low */

Definition at line 648 of file cassini.h.

#define REG_RX_FIFO_FULLNESS   0x4050 /* (ro) RX FIFO fullness */

Definition at line 588 of file cassini.h.

#define REG_RX_FIFO_READ_PTR   0x400C /* RX FIFO read pointer */

Definition at line 486 of file cassini.h.

#define REG_RX_FIFO_TAG   0x4084 /* RX FIFO tag */

Definition at line 647 of file cassini.h.

#define REG_RX_FIFO_WRITE_PTR   0x4008 /* RX FIFO write pointer */

Definition at line 485 of file cassini.h.

#define REG_RX_HEADER_PAGE_PTR_HI
Value:
0x411C /* (ro) RX header page ptr
high */

Definition at line 682 of file cassini.h.

#define REG_RX_HEADER_PAGE_PTR_LOW
Value:
0x4118 /* (ro) RX header page ptr
low */

Definition at line 681 of file cassini.h.

#define REG_RX_IPP_FIFO_ADDR   0x4104 /* RX IPP FIFO address */

Definition at line 669 of file cassini.h.

#define REG_RX_IPP_FIFO_DATA_HI_T0
Value:
0x4110 /* RX IPP FIFO data high
T0 */

Definition at line 672 of file cassini.h.

#define REG_RX_IPP_FIFO_DATA_HI_T1
Value:
0x4114 /* RX IPP FIFO data high
T1 */

Definition at line 673 of file cassini.h.

#define REG_RX_IPP_FIFO_DATA_LOW   0x410C /* RX IPP FIFO data low */

Definition at line 671 of file cassini.h.

#define REG_RX_IPP_FIFO_READ_PTR
Value:
0x400C /* RX IPP FIFO read
pointer. (8-bit counter) */

Definition at line 489 of file cassini.h.

#define REG_RX_IPP_FIFO_SHADOW_READ_PTR
Value:
0x4014 /* RX IPP FIFO shadow read
pointer */

Definition at line 488 of file cassini.h.

#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR
Value:
0x4010 /* RX IPP FIFO shadow write
pointer */

Definition at line 487 of file cassini.h.

#define REG_RX_IPP_FIFO_TAG   0x4108 /* RX IPP FIFO tag */

Definition at line 670 of file cassini.h.

#define REG_RX_IPP_PACKET_COUNT   0x4054 /* RX IPP packet counter */

Definition at line 592 of file cassini.h.

#define REG_RX_KICK   0x4024 /* RX kick reg */

Definition at line 525 of file cassini.h.

#define REG_RX_MTU_PAGE_PTR_HI
Value:
0x4124 /* (ro) RX MTU page pointer
high */

Definition at line 684 of file cassini.h.

#define REG_RX_MTU_PAGE_PTR_LOW
Value:
0x4120 /* (ro) RX MTU page pointer
low */

Definition at line 683 of file cassini.h.

#define REG_RX_PAGE_SIZE   0x4004 /* RX page size */

Definition at line 471 of file cassini.h.

#define REG_RX_PAUSE_THRESH   0x4020 /* RX pause thresholds */

Definition at line 512 of file cassini.h.

#define REG_RX_RED   0x404C /* RX random early detect enable */

Definition at line 578 of file cassini.h.

#define REG_RX_TABLE_ADDR
Value:
0x4128 /* RX reassembly DMA table
address */

Definition at line 695 of file cassini.h.

#define REG_RX_TABLE_DATA_HI
Value:
0x4134 /* RX reassembly DMA table
data high */

Definition at line 700 of file cassini.h.

#define REG_RX_TABLE_DATA_LOW
Value:
0x412C /* RX reassembly DMA table
data low */

Definition at line 698 of file cassini.h.

#define REG_RX_TABLE_DATA_MID
Value:
0x4130 /* RX reassembly DMA table
data mid */

Definition at line 699 of file cassini.h.

#define REG_RX_WORK_DMA_PTR_HI
Value:
0x405C /* RX working DMA ptr
high */

Definition at line 594 of file cassini.h.

#define REG_RX_WORK_DMA_PTR_LOW   0x4058 /* RX working DMA ptr low */

Definition at line 593 of file cassini.h.

#define REG_SATURN_PCFG
Value:
0x106c /* pin configuration register for
integrated macphy */

Definition at line 281 of file cassini.h.

#define REG_SECOND_LOCALBUS_END   0x1FFFFF

Definition at line 1275 of file cassini.h.

#define REG_SECOND_LOCALBUS_START
Value:
0x180000 /* secondary local bus
device */

Definition at line 1274 of file cassini.h.

#define REG_SW_RESET   0x1010 /* Software reset */

Definition at line 165 of file cassini.h.

#define REG_TX_CFG   0x2004 /* TX config */

Definition at line 304 of file cassini.h.

#define REG_TX_COMP0   0x2048 /* TX completion reg #1 */

Definition at line 360 of file cassini.h.

#define REG_TX_COMPN (   x)    (REG_TX_COMP0 + (x)*4)

Definition at line 361 of file cassini.h.

#define REG_TX_COMPWB_DB_HI
Value:
0x205C /* TX completion write back
base high */

Definition at line 381 of file cassini.h.

#define REG_TX_COMPWB_DB_LOW
Value:
0x2058 /* TX completion write back
base low */

Definition at line 380 of file cassini.h.

#define REG_TX_DATA_PTR_HI   0x2034 /* TX data pointer high */

Definition at line 350 of file cassini.h.

#define REG_TX_DATA_PTR_LOW   0x2030 /* TX data pointer low */

Definition at line 349 of file cassini.h.

#define REG_TX_DB0_HI   0x2064 /* TX descriptor base hi #1 */

Definition at line 391 of file cassini.h.

#define REG_TX_DB0_LOW   0x2060 /* TX descriptor base low #1 */

Definition at line 390 of file cassini.h.

#define REG_TX_DBN_HI (   x)    (REG_TX_DB0_HI + (x)*8)

Definition at line 393 of file cassini.h.

#define REG_TX_DBN_LOW (   x)    (REG_TX_DB0_LOW + (x)*8)

Definition at line 392 of file cassini.h.

#define REG_TX_FIFO_ADDR   0x2104 /* TX FIFO address */

Definition at line 416 of file cassini.h.

#define REG_TX_FIFO_DATA_HI_T0   0x2114 /* TX FIFO data high t0 */

Definition at line 420 of file cassini.h.

#define REG_TX_FIFO_DATA_HI_T1   0x2110 /* TX FIFO data high t1 */

Definition at line 419 of file cassini.h.

#define REG_TX_FIFO_DATA_LOW   0x210C /* TX FIFO data low */

Definition at line 418 of file cassini.h.

#define REG_TX_FIFO_PKT_CNT   0x2024 /* TX FIFO packet counter */

Definition at line 330 of file cassini.h.

#define REG_TX_FIFO_READ_PTR   0x201C /* TX FIFO read pointer */

Definition at line 326 of file cassini.h.

#define REG_TX_FIFO_SHADOW_READ_PTR
Value:
0x2020 /* TX FIFO shadow read
pointer */

Definition at line 327 of file cassini.h.

#define REG_TX_FIFO_SHADOW_WRITE_PTR
Value:
0x2018 /* TX FIFO shadow write
pointer. temp hold reg.
diagnostics only. */

Definition at line 325 of file cassini.h.

#define REG_TX_FIFO_SIZE   0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */

Definition at line 421 of file cassini.h.

#define REG_TX_FIFO_TAG   0x2108 /* TX FIFO tag */

Definition at line 417 of file cassini.h.

#define REG_TX_FIFO_WRITE_PTR   0x2014 /* TX FIFO write pointer */

Definition at line 324 of file cassini.h.

#define REG_TX_KICK0   0x2038 /* TX kick reg #1 */

Definition at line 358 of file cassini.h.

#define REG_TX_KICKN (   x)    (REG_TX_KICK0 + (x)*4)

Definition at line 359 of file cassini.h.

#define REG_TX_MAXBURST_0   0x2080 /* TX MaxBurst #1 */

Definition at line 404 of file cassini.h.

#define REG_TX_MAXBURST_1   0x2084 /* TX MaxBurst #2 */

Definition at line 405 of file cassini.h.

#define REG_TX_MAXBURST_2   0x2088 /* TX MaxBurst #3 */

Definition at line 406 of file cassini.h.

#define REG_TX_MAXBURST_3   0x208C /* TX MaxBurst #4 */

Definition at line 407 of file cassini.h.

#define REG_TX_RAMBIST   0x211C /* TX RAMBIST control/status */

Definition at line 426 of file cassini.h.

#define REG_TX_SM_1   0x2028 /* TX state machine reg #1 */

Definition at line 333 of file cassini.h.

#define REG_TX_SM_2   0x202C /* TX state machine reg #2 */

Definition at line 341 of file cassini.h.

#define RX_AE1_THRESH_FREE_MASK   RX_AE_THRESH_FREE_MASK

Definition at line 719 of file cassini.h.

#define RX_AE1_THRESH_FREE_SHIFT   RX_AE_THRESH_FREE_SHIFT

Definition at line 720 of file cassini.h.

#define RX_AE_COMP_VAL   (RX_COMP_RING_SIZE >> 1)

Definition at line 2108 of file cassini.h.

#define RX_AE_FREEN_VAL (   x)    (RX_DESC_RINGN_SIZE(x) >> 1)

Definition at line 2107 of file cassini.h.

#define RX_AE_THRESH_COMP_MASK
Value:
0x0FFFE000 /* RX_COMP_AE will be
generated if # of
completion entries
avail for hw use <=
# */

Definition at line 569 of file cassini.h.

#define RX_AE_THRESH_COMP_SHIFT   13

Definition at line 570 of file cassini.h.

#define RX_AE_THRESH_FREE_MASK
Value:
0x00001FFF /* RX_BUF_AE will be
generated if # desc
avail for hw use <=
# */

Definition at line 567 of file cassini.h.

#define RX_AE_THRESH_FREE_SHIFT   0

Definition at line 568 of file cassini.h.

#define RX_BAR_INTR_PACKET_MASK
Value:
0x000001FF /* assert RX_DONE if #
completion writebacks
> # since last ISR
read. 0 = no
blanking. up to 2
packets per
completion wb. */

Definition at line 635 of file cassini.h.

#define RX_BAR_INTR_TIME_MASK
Value:
0x3FFFF000 /* assert RX_DONE if #
clocks > # since last
ISR read. each count
is 512 core clocks
(125MHz). 0 = no
blanking. */

Definition at line 636 of file cassini.h.

#define RX_BIST_32A_PASS   0x80000000 /* RX FIFO 32A passed */

Definition at line 602 of file cassini.h.

#define RX_BIST_32B_PASS   0x20000000 /* RX FIFO 32B passed */

Definition at line 604 of file cassini.h.

#define RX_BIST_32C_PASS   0x08000000 /* RX FIFO 32C passed */

Definition at line 606 of file cassini.h.

#define RX_BIST_33A_PASS   0x40000000 /* RX FIFO 33A passed */

Definition at line 603 of file cassini.h.

#define RX_BIST_33B_PASS   0x10000000 /* RX FIFO 33B passed */

Definition at line 605 of file cassini.h.

#define RX_BIST_33C_PASS   0x04000000 /* RX FIFO 33C passed */

Definition at line 607 of file cassini.h.

#define RX_BIST_CTRL_32_PASS   0x00800000 /* RX CTRL FIFO 32 passed */

Definition at line 614 of file cassini.h.

#define RX_BIST_CTRL_33_PASS   0x00400000 /* RX CTRL FIFO 33 passed */

Definition at line 615 of file cassini.h.

#define RX_BIST_IPP_32A_PASS   0x02000000 /* RX IPP FIFO 33B passed */

Definition at line 608 of file cassini.h.

#define RX_BIST_IPP_32B_PASS   0x00800000 /* RX IPP FIFO 32B passed */

Definition at line 610 of file cassini.h.

#define RX_BIST_IPP_32C_PASS   0x00200000 /* RX IPP FIFO 32C passed */

Definition at line 612 of file cassini.h.

#define RX_BIST_IPP_33A_PASS   0x01000000 /* RX IPP FIFO 33A passed */

Definition at line 609 of file cassini.h.

#define RX_BIST_IPP_33B_PASS   0x00400000 /* RX IPP FIFO 33B passed */

Definition at line 611 of file cassini.h.

#define RX_BIST_IPP_33C_PASS   0x00100000 /* RX IPP FIFO 33C passed */

Definition at line 613 of file cassini.h.

#define RX_BIST_REAS_26A_PASS   0x00200000 /* RX Reas 26A passed */

Definition at line 616 of file cassini.h.

#define RX_BIST_REAS_26B_PASS   0x00100000 /* RX Reas 26B passed */

Definition at line 617 of file cassini.h.

#define RX_BIST_REAS_27_PASS   0x00080000 /* RX Reas 27 passed */

Definition at line 618 of file cassini.h.

#define RX_BIST_START
Value:
0x00000001 /* write 1 to start
BIST. self clears
on completion. */

Definition at line 621 of file cassini.h.

#define RX_BIST_STATE_MASK   0x00078000 /* BIST state machine */

Definition at line 619 of file cassini.h.

#define RX_BIST_SUMMARY
Value:
0x00000002 /* when BIST complete,
summary pass bit
contains AND of BIST
results of all 16
RAMS */

Definition at line 620 of file cassini.h.

#define RX_BLANK_INTR_PKT_MASK
Value:
0x000001FF /* RX_DONE intr asserted if
this many sets of completion
writebacks (up to 2 packets)
occur since the last time
the ISR was read. 0 = no
packet blanking */

Definition at line 557 of file cassini.h.

#define RX_BLANK_INTR_PKT_SHIFT   0

Definition at line 558 of file cassini.h.

#define RX_BLANK_INTR_PKT_VAL   0x05

Definition at line 2109 of file cassini.h.

#define RX_BLANK_INTR_TIME_MASK
Value:
0x3FFFF000 /* RX_DONE interrupt asserted
if that many clocks were
counted since last time the
ISR was read.
each count is 512 core
clocks (125MHz). 0 = no
time blanking */

Definition at line 559 of file cassini.h.

#define RX_BLANK_INTR_TIME_SHIFT   12

Definition at line 560 of file cassini.h.

#define RX_BLANK_INTR_TIME_VAL   0x0F

Definition at line 2110 of file cassini.h.

#define RX_CFG_BATCH_DIS
Value:
0x00000200 /* disable receive desc
batching. def: 0x0 =
enabled */

Definition at line 450 of file cassini.h.

#define RX_CFG_COMP_RING_MASK
Value:
0x000001E0 /* # desc entries in RX complete
ring. def: 0x8 = 32k */

Definition at line 448 of file cassini.h.

#define RX_CFG_COMP_RING_SHIFT   5

Definition at line 449 of file cassini.h.

#define RX_CFG_DESC_RING1_MASK
Value:
0x000F0000 /* # of desc entries in
RX free desc ring 2.
def: 0x8 = 8k */

Definition at line 455 of file cassini.h.

#define RX_CFG_DESC_RING1_SHIFT   16

Definition at line 456 of file cassini.h.

#define RX_CFG_DESC_RING_MASK
Value:
0x0000001E /* # desc entries in RX
free desc ring.
def: 0x8 = 8k */

Definition at line 446 of file cassini.h.

#define RX_CFG_DESC_RING_SHIFT   1

Definition at line 447 of file cassini.h.

#define RX_CFG_DMA_EN
Value:
0x00000001 /* enable RX DMA. 0 stops
channel as soon as current
frame xfer has completed.
driver should disable MAC
for 200ms before disabling
RX */

Definition at line 445 of file cassini.h.

#define RX_CFG_SWIVEL_MASK
Value:
0x00001C00 /* byte offset of the 1st
data byte of the packet
w/in 8 byte boundares.
this swivels the data
DMA'ed to header
buffers, jumbo buffers
when header split is not
requested and MTU sized
buffers. def: 0x2 */

Definition at line 451 of file cassini.h.

#define RX_CFG_SWIVEL_SHIFT   10

Definition at line 452 of file cassini.h.

#define RX_COMP1_DATA_INDEX_MASK   0x007FFE0000000000ULL

Definition at line 1829 of file cassini.h.

#define RX_COMP1_DATA_INDEX_SHIFT   41

Definition at line 1830 of file cassini.h.

#define RX_COMP1_DATA_OFF_MASK   0x000001FFF8000000ULL

Definition at line 1827 of file cassini.h.

#define RX_COMP1_DATA_OFF_SHIFT   27

Definition at line 1828 of file cassini.h.

#define RX_COMP1_DATA_SIZE_MASK   0x0000000007FFE000ULL

Definition at line 1825 of file cassini.h.

#define RX_COMP1_DATA_SIZE_SHIFT   13

Definition at line 1826 of file cassini.h.

#define RX_COMP1_RELEASE_DATA   0x1000000000000000ULL

Definition at line 1836 of file cassini.h.

#define RX_COMP1_RELEASE_FLOW   0x0800000000000000ULL

Definition at line 1835 of file cassini.h.

#define RX_COMP1_RELEASE_HDR   0x2000000000000000ULL

Definition at line 1837 of file cassini.h.

#define RX_COMP1_RELEASE_NEXT   0x0200000000000000ULL

Definition at line 1833 of file cassini.h.

#define RX_COMP1_SKIP_MASK   0x0180000000000000ULL

Definition at line 1831 of file cassini.h.

#define RX_COMP1_SKIP_SHIFT   55

Definition at line 1832 of file cassini.h.

#define RX_COMP1_SPLIT_PKT   0x0400000000000000ULL

Definition at line 1834 of file cassini.h.

#define RX_COMP1_TYPE_MASK   0xC000000000000000ULL

Definition at line 1838 of file cassini.h.

#define RX_COMP1_TYPE_SHIFT   62

Definition at line 1839 of file cassini.h.

#define RX_COMP2_HDR_INDEX_MASK   0xFFFC000000000000ULL

Definition at line 1848 of file cassini.h.

#define RX_COMP2_HDR_INDEX_SHIFT   50

Definition at line 1849 of file cassini.h.

#define RX_COMP2_HDR_OFF_MASK   0x0003F00000000000ULL

Definition at line 1846 of file cassini.h.

#define RX_COMP2_HDR_OFF_SHIFT   44

Definition at line 1847 of file cassini.h.

#define RX_COMP2_HDR_SIZE_MASK   0x00000FF800000000ULL

Definition at line 1844 of file cassini.h.

#define RX_COMP2_HDR_SIZE_SHIFT   35

Definition at line 1845 of file cassini.h.

#define RX_COMP2_NEXT_INDEX_MASK   0x00000007FFE00000ULL

Definition at line 1842 of file cassini.h.

#define RX_COMP2_NEXT_INDEX_SHIFT   21

Definition at line 1843 of file cassini.h.

#define RX_COMP3_CSUM_START_MASK   0x000000000007F000ULL

Definition at line 1855 of file cassini.h.

#define RX_COMP3_CSUM_START_SHIFT   12

Definition at line 1856 of file cassini.h.

#define RX_COMP3_FLOWID_MASK   0x0000000001F80000ULL

Definition at line 1857 of file cassini.h.

#define RX_COMP3_FLOWID_SHIFT   19

Definition at line 1858 of file cassini.h.

#define RX_COMP3_FORCE_FLAG   0x0000000010000000ULL

Definition at line 1861 of file cassini.h.

#define RX_COMP3_JUMBO_HDR_SPLIT_EN   0x0000000000000004ULL

Definition at line 1854 of file cassini.h.

#define RX_COMP3_JUMBO_PKT   0x0000000000000002ULL

Definition at line 1853 of file cassini.h.

#define RX_COMP3_L3_HEAD_OFF_MASK   0x0000FE0000000000ULL /* cas */

Definition at line 1866 of file cassini.h.

#define RX_COMP3_L3_HEAD_OFF_SHIFT   41

Definition at line 1867 of file cassini.h.

#define RX_COMP3_LOAD_BAL_MASK   0x000001F800000000ULL

Definition at line 1863 of file cassini.h.

#define RX_COMP3_LOAD_BAL_SHIFT   35

Definition at line 1864 of file cassini.h.

#define RX_COMP3_NO_ASSIST   0x0000000020000000ULL

Definition at line 1862 of file cassini.h.

#define RX_COMP3_OPCODE_MASK   0x000000000E000000ULL

Definition at line 1859 of file cassini.h.

#define RX_COMP3_OPCODE_SHIFT   25

Definition at line 1860 of file cassini.h.

#define RX_COMP3_SAP_MASK   0xFFFF000000000000ULL

Definition at line 1870 of file cassini.h.

#define RX_COMP3_SAP_SHIFT   48

Definition at line 1871 of file cassini.h.

#define RX_COMP3_SMALL_PKT   0x0000000000000001ULL

Definition at line 1852 of file cassini.h.

#define RX_COMP4_BAD   0x4000000000000000ULL

Definition at line 1884 of file cassini.h.

#define RX_COMP4_HASH_PASS   0x1000000000000000ULL

Definition at line 1883 of file cassini.h.

#define RX_COMP4_HASH_VAL_MASK   0x0FFFF00000000000ULL

Definition at line 1881 of file cassini.h.

#define RX_COMP4_HASH_VAL_SHIFT   44

Definition at line 1882 of file cassini.h.

#define RX_COMP4_LEN_MISMATCH   0x8000000000000000ULL

Definition at line 1885 of file cassini.h.

#define RX_COMP4_PERFECT_MATCH_MASK   0x00000003C0000000ULL

Definition at line 1878 of file cassini.h.

#define RX_COMP4_PERFECT_MATCH_SHIFT   30

Definition at line 1879 of file cassini.h.

#define RX_COMP4_PKT_LEN_MASK   0x000000003FFF0000ULL

Definition at line 1876 of file cassini.h.

#define RX_COMP4_PKT_LEN_SHIFT   16

Definition at line 1877 of file cassini.h.

#define RX_COMP4_TCP_CSUM_MASK   0x000000000000FFFFULL

Definition at line 1874 of file cassini.h.

#define RX_COMP4_TCP_CSUM_SHIFT   0

Definition at line 1875 of file cassini.h.

#define RX_COMP4_ZERO   0x0000080000000000ULL

Definition at line 1880 of file cassini.h.

#define RX_COMP_ENTRY (   r,
  x 
)    ((x) & (RX_COMP_RINGN_SIZE(r) - 1))

Definition at line 2085 of file cassini.h.

#define RX_COMP_RING_INDEX   4 /* 2048 = 64k: should be 4x rx ring size */

Definition at line 1754 of file cassini.h.

#define RX_COMP_RING_SIZE   COMP_RING_I_TO_S(RX_COMP_RING_INDEX)

Definition at line 1778 of file cassini.h.

#define RX_COMP_RINGN_INDEX (   x)    RX_COMP_RING_INDEX

Definition at line 1781 of file cassini.h.

#define RX_COMP_RINGN_SIZE (   x)    RX_COMP_RING_SIZE

Definition at line 1784 of file cassini.h.

#define RX_CTRL_FIFO_DATA_HI_CTRL   0x0001 /* upper bit of ctrl word */

Definition at line 663 of file cassini.h.

#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK   0x007E /* flow id */

Definition at line 664 of file cassini.h.

#define RX_DEBUG_DATA_STATE_MASK
Value:
0x000001E00 /* unload data state machine
states:
0x0 = idle data
0x1 = header begin
0x2 = xfer header
0x3 = xfer header ld
0x4 = mtu begin
0x5 = xfer mtu
0x6 = xfer mtu ld
0x7 = jumbo begin
0x8 = xfer jumbo
0x9 = xfer jumbo ld
0xa = reas begin
0xb = xfer reas
0xc = flush tag
0xd = xfer reas ld
0xe = error
0xf = bubble idle */

Definition at line 498 of file cassini.h.

#define RX_DEBUG_DESC_STATE_MASK
Value:
0x0001E000 /* unload desc state machine
states:
0x0 = idle desc
0x1 = wait ack
0x9 = wait ack 2
0x2 = fetch desc 1
0xa = fetch desc 2
0x3 = load ptrs
0x4 = wait dma
0x5 = wait ack batch
0x6 = post batch
0x7 = xfr done */

Definition at line 499 of file cassini.h.

#define RX_DEBUG_FC_STATE_MASK
Value:
0x000000180 /* flow control state machine
w/ MAC:
0x0 = idle
0x1 = wait xoff ack
0x2 = wait xon
0x3 = wait xon ack */

Definition at line 497 of file cassini.h.

#define RX_DEBUG_INTR_READ_PTR_MASK
Value:
0x30000000 /* interrupt read ptr of the
interrupt queue */

Definition at line 500 of file cassini.h.

#define RX_DEBUG_INTR_WRITE_PTR_MASK
Value:
0xC0000000 /* interrupt write pointer
of the interrupt queue */

Definition at line 501 of file cassini.h.

#define RX_DEBUG_LM_STATE_MASK
Value:
0x00000070 /* load state machine w/ HP and
RX FIFO:
0x0 = idle, 0x1 = hp xfr
0x2 = wait hp ready
0x3 = wait flow code
0x4 = fifo xfer
0x5 = make status
0x6 = csum ready
0x7 = error */

Definition at line 496 of file cassini.h.

#define RX_DEBUG_LOAD_STATE_MASK
Value:
0x0000000F /* load state machine w/ MAC:
0x0 = idle, 0x1 = load_bop
0x2 = load 1, 0x3 = load 2
0x4 = load 3, 0x5 = load 4
0x6 = last detect
0x7 = wait req
0x8 = wait req statuss 1st
0x9 = load st
0xa = bubble mac
0xb = error */

Definition at line 495 of file cassini.h.

#define RX_DESC_ENTRY (   r,
  x 
)    ((x) & (RX_DESC_RINGN_SIZE(r) - 1))

Definition at line 2084 of file cassini.h.

#define RX_DESC_RING_INDEX   4 /* 512 = 8k */

Definition at line 1753 of file cassini.h.

#define RX_DESC_RING_SIZE   DESC_RING_I_TO_S(RX_DESC_RING_INDEX)

Definition at line 1777 of file cassini.h.

#define RX_DESC_RINGN_INDEX (   x)    RX_DESC_RING_INDEX

Definition at line 1780 of file cassini.h.

#define RX_DESC_RINGN_SIZE (   x)    RX_DESC_RING_SIZE

Definition at line 1783 of file cassini.h.

#define RX_FIFO_FULLNESS_IPP_FIFO_MASK   0x0007FF00 /* level w/ 8B granularity */

Definition at line 590 of file cassini.h.

#define RX_FIFO_FULLNESS_RX_FIFO_MASK   0x3FF80000 /* level w/ 8B granularity */

Definition at line 589 of file cassini.h.

#define RX_FIFO_FULLNESS_RX_PKT_MASK   0x000000FF /* # packets in RX FIFO */

Definition at line 591 of file cassini.h.

#define RX_FIFO_SIZE   16384

Definition at line 2097 of file cassini.h.

#define RX_INDEX_NUM_MASK   0x0000000000000FFFULL

Definition at line 1891 of file cassini.h.

#define RX_INDEX_NUM_SHIFT   0

Definition at line 1892 of file cassini.h.

#define RX_INDEX_RELEASE   0x0000000000002000ULL

Definition at line 1895 of file cassini.h.

#define RX_INDEX_RING_MASK   0x0000000000001000ULL

Definition at line 1893 of file cassini.h.

#define RX_INDEX_RING_SHIFT   12

Definition at line 1894 of file cassini.h.

#define RX_PAGE_SIZE_MASK
Value:
0x00000003 /* size of pages pointed to
by receive descriptors.
if jumbo buffers are
supported the page size
should not be < 8k.
0b00 = 2k, 0b01 = 4k
0b10 = 8k, 0b11 = 16k
DEFAULT: 8k */

Definition at line 472 of file cassini.h.

#define RX_PAGE_SIZE_MTU_COUNT_MASK
Value:
0x00007800 /* # of MTU buffers the hw
packs into a page.
DEFAULT: 4 */

Definition at line 474 of file cassini.h.

#define RX_PAGE_SIZE_MTU_COUNT_SHIFT   11

Definition at line 475 of file cassini.h.

#define RX_PAGE_SIZE_MTU_OFF_MASK
Value:
0xC0000000 /* offset in each page that
hw writes the MTU buffer
into.
0b00 = 0,
0b01 = 64 bytes
0b10 = 96, 0b11 = 128
DEFAULT: 0x1 */

Definition at line 478 of file cassini.h.

#define RX_PAGE_SIZE_MTU_OFF_SHIFT   30

Definition at line 479 of file cassini.h.

#define RX_PAGE_SIZE_MTU_STRIDE_MASK
Value:
0x18000000 /* # of bytes that separate
each MTU buffer +
offset from each
other.
0b00 = 1k, 0b01 = 2k
0b10 = 4k, 0b11 = 8k
DEFAULT: 0x1 */

Definition at line 476 of file cassini.h.

#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT   27

Definition at line 477 of file cassini.h.

#define RX_PAGE_SIZE_SHIFT   0

Definition at line 473 of file cassini.h.

#define RX_PAUSE_THRESH_OFF_MASK
Value:
0x000001FF /* XOFF PAUSE emitted when
RX FIFO occupancy >
value*64B */

Definition at line 514 of file cassini.h.

#define RX_PAUSE_THRESH_OFF_SHIFT   0

Definition at line 515 of file cassini.h.

#define RX_PAUSE_THRESH_ON_MASK
Value:
0x001FF000 /* XON PAUSE emitted after
emitting XOFF PAUSE when RX
FIFO occupancy falls below
this value*64B. must be
< XOFF threshold. if =
RX_FIFO_SIZE< XON frames are
never emitted. */

Definition at line 516 of file cassini.h.

#define RX_PAUSE_THRESH_ON_SHIFT   12

Definition at line 517 of file cassini.h.

#define RX_PAUSE_THRESH_QUANTUM   64

Definition at line 513 of file cassini.h.

#define RX_PLUS_COMP3_ENC_PKT   0x0000020000000000ULL /* cas+ */

Definition at line 1865 of file cassini.h.

#define RX_PLUS_COMP_L3_HEAD_OFF_MASK   0x0000FC0000000000ULL /* cas+ */

Definition at line 1868 of file cassini.h.

#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT   42

Definition at line 1869 of file cassini.h.

#define RX_RED_10K_12K_FIFO_MASK   0xFF000000 /* 10KB < FIFO thresh < 12KB */

Definition at line 582 of file cassini.h.

#define RX_RED_4K_6K_FIFO_MASK   0x000000FF /* 4KB < FIFO thresh < 6KB */

Definition at line 579 of file cassini.h.

#define RX_RED_6K_8K_FIFO_MASK   0x0000FF00 /* 6KB < FIFO thresh < 8KB */

Definition at line 580 of file cassini.h.

#define RX_RED_8K_10K_FIFO_MASK   0x00FF0000 /* 8KB < FIFO thresh < 10KB */

Definition at line 581 of file cassini.h.

#define RX_SPARE_COUNT   (RX_DESC_RING_SIZE >> 1)

Definition at line 2113 of file cassini.h.

#define RX_SPARE_RECOVER_VAL   (RX_SPARE_COUNT >> 2)

Definition at line 2114 of file cassini.h.

#define RX_SWIVEL_OFF_VAL   0x2

Definition at line 2106 of file cassini.h.

#define RX_TABLE_ADDR_MASK   0x0000003F /* address mask */

Definition at line 696 of file cassini.h.

#define S1_8023   3

Definition at line 1394 of file cassini.h.

#define S1_AH4   23

Definition at line 1414 of file cassini.h.

#define S1_AH6   25

Definition at line 1416 of file cassini.h.

#define S1_CFI   2

Definition at line 1393 of file cassini.h.

#define S1_CLNP   18

Definition at line 1409 of file cassini.h.

#define S1_CLNP2   19

Definition at line 1410 of file cassini.h.

#define S1_DROP   20

Definition at line 1411 of file cassini.h.

#define S1_ESP4   22

Definition at line 1413 of file cassini.h.

#define S1_ESP6   24

Definition at line 1415 of file cassini.h.

#define S1_IPV4   6

Definition at line 1397 of file cassini.h.

#define S1_IPV4c   7

Definition at line 1398 of file cassini.h.

#define S1_IPV4F   8

Definition at line 1399 of file cassini.h.

#define S1_IPV6   10

Definition at line 1401 of file cassini.h.

#define S1_IPV6c   12

Definition at line 1403 of file cassini.h.

#define S1_IPV6L   11

Definition at line 1402 of file cassini.h.

#define S1_LLC   4

Definition at line 1395 of file cassini.h.

#define S1_LLCc   5

Definition at line 1396 of file cassini.h.

#define S1_PCKT   0

Definition at line 1391 of file cassini.h.

#define S1_TCP44   9

Definition at line 1400 of file cassini.h.

#define S1_TCP64   13

Definition at line 1404 of file cassini.h.

#define S1_TCPFG   15

Definition at line 1406 of file cassini.h.

#define S1_TCPHc   17

Definition at line 1408 of file cassini.h.

#define S1_TCPHL   16

Definition at line 1407 of file cassini.h.

#define S1_TCPSQ   14

Definition at line 1405 of file cassini.h.

#define S1_VLAN   1

Definition at line 1392 of file cassini.h.

#define S2_HTTP   21

Definition at line 1412 of file cassini.h.

#define S3_CLNP   19

Definition at line 1513 of file cassini.h.

#define S3_FOFF   18

Definition at line 1512 of file cassini.h.

#define S3_FRAG   17

Definition at line 1511 of file cassini.h.

#define S3_IPV6c   11

Definition at line 1505 of file cassini.h.

#define S3_TCP64   12

Definition at line 1506 of file cassini.h.

#define S3_TCPFG   14

Definition at line 1508 of file cassini.h.

#define S3_TCPHc   16

Definition at line 1510 of file cassini.h.

#define S3_TCPHL   15

Definition at line 1509 of file cassini.h.

#define S3_TCPSQ   13

Definition at line 1507 of file cassini.h.

#define SATURN_PCFG_CLA   0x00000004 /* 1 = phy link100led */

Definition at line 285 of file cassini.h.

#define SATURN_PCFG_FLA   0x00000002 /* 1 = phy link10led */

Definition at line 284 of file cassini.h.

#define SATURN_PCFG_FSI
Value:
0x00000200 /* 1 = freeze serdes/gmii. all
pins configed as outputs.
for power saving when using
internal phy. */

Definition at line 291 of file cassini.h.

#define SATURN_PCFG_GMO
Value:
0x00000100 /* GMII observe. 1 =
GMII on SERDES pins for
monitoring. */

Definition at line 290 of file cassini.h.

#define SATURN_PCFG_LAD
Value:
0x00000800 /* 0 = mac core led ctrl
polarity from strapping
value.
1 = mac core led ctrl
polarity active low. */

Definition at line 292 of file cassini.h.

#define SATURN_PCFG_LLA   0x00000008 /* 1 = phy link1000led */

Definition at line 286 of file cassini.h.

#define SATURN_PCFG_MTP   0x00000080 /* test point select */

Definition at line 289 of file cassini.h.

#define SATURN_PCFG_PDS
Value:
0x00000020 /* phy debug mode.
0 = normal */

Definition at line 288 of file cassini.h.

#define SATURN_PCFG_RLA   0x00000010 /* 1 = phy duplexled */

Definition at line 287 of file cassini.h.

#define SATURN_PCFG_TLA   0x00000001 /* 1 = phy actled */

Definition at line 283 of file cassini.h.

#define SM_LINK_STATE_UP   0x00016000 /* link state is up */

Definition at line 1203 of file cassini.h.

#define ST_FLG   15

Definition at line 1388 of file cassini.h.

#define SW_RESET_BLOCK_PCS_SLINK
Value:
0x00000008 /* if a global reset is done with
this bit set, PCS and SLINK
modules won't be reset.
i.e., link won't drop. */

Definition at line 169 of file cassini.h.

#define SW_RESET_BREQ_SM_MASK   0x00007F00 /* breq state machine [6:0] */

Definition at line 170 of file cassini.h.

#define SW_RESET_PCIARB_SM_MASK
Value:
0x00070000 /* pci arbitration state bits:
0b000: ARB_IDLE1
0b001: ARB_IDLE2
0b010: ARB_WB_ACK
0b011: ARB_WB_WAT
0b100: ARB_RB_ACK
0b101: ARB_RB_WAT
0b110: ARB_RB_END
0b111: ARB_WB_END */

Definition at line 171 of file cassini.h.

#define SW_RESET_RDARB_SM_MASK
Value:
0x00C00000 /* read arbitration state bits:
0b00: AD_IDL_RX
0b01: AD_ACK_RX
0b10: AD_ACK_TX
0b11: AD_IDL_TX */

Definition at line 173 of file cassini.h.

#define SW_RESET_RDPCI_SM_MASK
Value:
0x00300000 /* read pci state bits:
0b00: RD_PCI_WAT
0b01: RD_PCI_RDY
0b11: RD_PCI_ACK */

Definition at line 172 of file cassini.h.

#define SW_RESET_RSTOUT
Value:
0x00000004 /* force RSTOUT# pin active (low).
resets PHY and anything else
connected to RSTOUT#. RSTOUT#
is also activated by local PCI
reset when hot-swap is being
done. */

Definition at line 168 of file cassini.h.

#define SW_RESET_RX
Value:
0x00000002 /* reset RX DMA engine. poll until
cleared to 0. */

Definition at line 167 of file cassini.h.

#define SW_RESET_TX
Value:
0x00000001 /* reset TX DMA engine. poll until
cleared to 0. */

Definition at line 166 of file cassini.h.

#define SW_RESET_WRARB_SM_MASK
Value:
0x38000000 /* write arbitration state bits:
0b000: ARB_IDLE1
0b001: ARB_IDLE2
0b010: ARB_TX_ACK
0b011: ARB_TX_WAT
0b100: ARB_RX_ACK
0b110: ARB_RX_WAT */

Definition at line 175 of file cassini.h.

#define SW_RESET_WRPCI_SM_MASK
Value:
0x06000000 /* write pci state bits
0b00: WR_PCI_WAT
0b01: WR_PCI_RDY
0b11: WR_PCI_ACK */

Definition at line 174 of file cassini.h.

#define TX_BUFF_COUNT (   r,
  x,
  y 
)
Value:
((x) <= (y) ? ((y) - (x)) : \
(TX_DESC_RINGN_SIZE(r) - (x) + (y)))

Definition at line 2087 of file cassini.h.

#define TX_BUFFS_AVAIL (   cp,
  i 
)
Value:
((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
(cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
(cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)

Definition at line 2090 of file cassini.h.

#define TX_CFG_COMPWB_Q1
Value:
0x02000000 /* completion writeback happens at
the end of every packet kicked
through Q1. */

Definition at line 313 of file cassini.h.

#define TX_CFG_COMPWB_Q2
Value:
0x04000000 /* completion writeback happens at
the end of every packet kicked
through Q2. */

Definition at line 314 of file cassini.h.

#define TX_CFG_COMPWB_Q3
Value:
0x08000000 /* completion writeback happens at
the end of every packet kicked
through Q3 */

Definition at line 315 of file cassini.h.

#define TX_CFG_COMPWB_Q4
Value:
0x10000000 /* completion writeback happens at
the end of every packet kicked
through Q4 */

Definition at line 316 of file cassini.h.

#define TX_CFG_CTX_SEL_MASK
Value:
0xC0000000 /* selects tx test port
connection
0b00: tx mac req,
tx mac retry req,
tx ack and tx tag.
0b01: txdma rd req,
txdma rd ack,
txdma rd rdy,
txdma rd type0
0b11: txdma wr req,
txdma wr ack,
txdma wr rdy,
txdma wr xfr done. */

Definition at line 318 of file cassini.h.

#define TX_CFG_CTX_SEL_SHIFT   30

Definition at line 319 of file cassini.h.

#define TX_CFG_DESC_RING0_MASK
Value:
0x0000003C /* # desc entries in
ring 1. */

Definition at line 307 of file cassini.h.

#define TX_CFG_DESC_RING0_SHIFT   2

Definition at line 308 of file cassini.h.

#define TX_CFG_DESC_RINGN_MASK (   a)    (TX_CFG_DESC_RING0_MASK << (a)*4)

Definition at line 309 of file cassini.h.

#define TX_CFG_DESC_RINGN_SHIFT (   a)    (TX_CFG_DESC_RING0_SHIFT + (a)*4)

Definition at line 310 of file cassini.h.

#define TX_CFG_DMA_EN
Value:
0x00000001 /* enable TX DMA. if cleared, DMA
will stop after xfer of current
buffer has been completed. */

Definition at line 305 of file cassini.h.

#define TX_CFG_DMA_RDPIPE_DIS   0x01000000 /* always set to 1 */

Definition at line 312 of file cassini.h.

#define TX_CFG_FIFO_PIO_SEL
Value:
0x00000002 /* TX DMA FIFO can be
accessed w/ FIFO addr
and data registers.
TX DMA should be
disabled. */

Definition at line 306 of file cassini.h.

#define TX_CFG_INTR_COMPWB_DIS
Value:
0x20000000 /* disable pre-interrupt completion
writeback */

Definition at line 317 of file cassini.h.

#define TX_CFG_PACED_MODE
Value:
0x00100000 /* TX_ALL only set after
TX FIFO becomes empty.
if 0, TX_ALL set
if descr queue empty. */

Definition at line 311 of file cassini.h.

#define TX_COMPWB_LSB_MASK   0x000000000000FF00ULL

Definition at line 384 of file cassini.h.

#define TX_COMPWB_LSB_SHIFT   8

Definition at line 385 of file cassini.h.

#define TX_COMPWB_MSB_MASK   0x00000000000000FFULL

Definition at line 382 of file cassini.h.

#define TX_COMPWB_MSB_SHIFT   0

Definition at line 383 of file cassini.h.

#define TX_COMPWB_NEXT (   x)    ((x) >> 16)

Definition at line 386 of file cassini.h.

#define TX_COMPWB_SIZE   8

Definition at line 379 of file cassini.h.

#define TX_DESC_BUFLEN_MASK
Value:
0x0000000000003FFFULL /* buffer length in
bytes. 0 - 9256 */

Definition at line 1798 of file cassini.h.

#define TX_DESC_BUFLEN_SHIFT   0

Definition at line 1799 of file cassini.h.

#define TX_DESC_CSUM_EN   0x0000000020000000ULL /* enable checksum */

Definition at line 1804 of file cassini.h.

#define TX_DESC_CSUM_START_MASK
Value:
0x00000000001F8000ULL /* checksum start. #
of bytes to be
skipped before
csum calc begins.
value must be
even */

Definition at line 1800 of file cassini.h.

#define TX_DESC_CSUM_START_SHIFT   15

Definition at line 1801 of file cassini.h.

#define TX_DESC_CSUM_STUFF_MASK
Value:
0x000000001FE00000ULL /* checksum stuff.
byte offset w/in
the pkt for the
1st csum byte.
must be > 8 */

Definition at line 1802 of file cassini.h.

#define TX_DESC_CSUM_STUFF_SHIFT   21

Definition at line 1803 of file cassini.h.

#define TX_DESC_EOF   0x0000000040000000ULL /* end of frame */

Definition at line 1805 of file cassini.h.

#define TX_DESC_INTME   0x0000000100000000ULL /* interrupt me */

Definition at line 1807 of file cassini.h.

#define TX_DESC_NEXT (   r,
  x 
)    (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))

Definition at line 2083 of file cassini.h.

#define TX_DESC_NO_CRC
Value:
0x0000000200000000ULL /* debugging only.
CRC will not be
inserted into
outgoing frame. */

Definition at line 1808 of file cassini.h.

#define TX_DESC_RING_INDEX   4 /* 512 = 8k */

Definition at line 1752 of file cassini.h.

#define TX_DESC_RING_SIZE   DESC_RING_I_TO_S(TX_DESC_RING_INDEX)

Definition at line 1776 of file cassini.h.

#define TX_DESC_RINGN_INDEX (   x)    TX_DESC_RING_INDEX

Definition at line 1779 of file cassini.h.

#define TX_DESC_RINGN_SIZE (   x)    TX_DESC_RING_SIZE

Definition at line 1782 of file cassini.h.

#define TX_DESC_SOF   0x0000000080000000ULL /* start of frame */

Definition at line 1806 of file cassini.h.

#define TX_RAMBIST_RAM32A_PASS   0x0010 /* RAM32A passed */

Definition at line 429 of file cassini.h.

#define TX_RAMBIST_RAM32B_PASS   0x0004 /* RAM32B passed */

Definition at line 431 of file cassini.h.

#define TX_RAMBIST_RAM33A_PASS   0x0020 /* RAM33A passed */

Definition at line 428 of file cassini.h.

#define TX_RAMBIST_RAM33B_PASS   0x0008 /* RAM33B passed */

Definition at line 430 of file cassini.h.

#define TX_RAMBIST_START
Value:
0x0001 /* write 1 to start BIST. self
clears on completion. */

Definition at line 433 of file cassini.h.

#define TX_RAMBIST_STATE
Value:
0x01C0 /* progress state of RAMBIST
controller state machine */

Definition at line 427 of file cassini.h.

#define TX_RAMBIST_SUMMARY   0x0002 /* all RAM passed */

Definition at line 432 of file cassini.h.

#define TX_SM_1_CACHE_MASK
Value:
0x03C00000 /* desc. prefetch cache controller
state machine */

Definition at line 338 of file cassini.h.

#define TX_SM_1_CBQ_ARB_MASK   0xF8000000 /* CBQ arbiter state machine */

Definition at line 339 of file cassini.h.

#define TX_SM_1_CHAIN_MASK   0x000003FF /* chaining state machine */

Definition at line 334 of file cassini.h.

#define TX_SM_1_CSUM_MASK   0x00000C00 /* checksum state machine */

Definition at line 335 of file cassini.h.

#define TX_SM_1_FIFO_LOAD_MASK
Value:
0x0003F000 /* FIFO load state machine.
= 0x01 when TX disabled. */

Definition at line 336 of file cassini.h.

#define TX_SM_1_FIFO_UNLOAD_MASK   0x003C0000 /* FIFO unload state machine */

Definition at line 337 of file cassini.h.

#define TX_SM_2_COMP_WB_MASK   0x07 /* completion writeback sm */

Definition at line 342 of file cassini.h.

#define TX_SM_2_KICK_MASK   0xC0 /* kick state machine */

Definition at line 344 of file cassini.h.

#define TX_SM_2_SUB_LOAD_MASK   0x38 /* sub load state machine */

Definition at line 343 of file cassini.h.

#define TX_TARGET_ABORT_LEN   0x20

Definition at line 2105 of file cassini.h.

#define TX_TINY_BUF_BLOCK   ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)

Definition at line 1948 of file cassini.h.

#define TX_TINY_BUF_LEN   0x100

Definition at line 1947 of file cassini.h.

Typedef Documentation

typedef struct cas_hp_inst cas_hp_inst_t
typedef struct cas_page cas_page_t

Enumeration Type Documentation

enum link_state
Enumerator:
link_down 
link_aneg 
link_force_try 
link_force_ret 
link_force_ok 
link_up 
link_down 
link_aneg 
link_force_try 
link_force_ret 
link_force_ok 
link_up 

Definition at line 1904 of file cassini.h.

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