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clkgen_defs.h
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1 #ifndef __clkgen_defs_h
2 #define __clkgen_defs_h
3 
4 /*
5  * This file is autogenerated from
6  * file: clkgen.r
7  *
8  * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
9  * Any changes here will be lost.
10  *
11  * -*- buffer-read-only: t -*-
12  */
13 /* Main access macros */
14 #ifndef REG_RD
15 #define REG_RD( scope, inst, reg ) \
16  REG_READ( reg_##scope##_##reg, \
17  (inst) + REG_RD_ADDR_##scope##_##reg )
18 #endif
19 
20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \
22  REG_WRITE( reg_##scope##_##reg, \
23  (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
24 #endif
25 
26 #ifndef REG_RD_VECT
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28  REG_READ( reg_##scope##_##reg, \
29  (inst) + REG_RD_ADDR_##scope##_##reg + \
30  (index) * STRIDE_##scope##_##reg )
31 #endif
32 
33 #ifndef REG_WR_VECT
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35  REG_WRITE( reg_##scope##_##reg, \
36  (inst) + REG_WR_ADDR_##scope##_##reg + \
37  (index) * STRIDE_##scope##_##reg, (val) )
38 #endif
39 
40 #ifndef REG_RD_INT
41 #define REG_RD_INT( scope, inst, reg ) \
42  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
43 #endif
44 
45 #ifndef REG_WR_INT
46 #define REG_WR_INT( scope, inst, reg, val ) \
47  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
48 #endif
49 
50 #ifndef REG_RD_INT_VECT
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53  (index) * STRIDE_##scope##_##reg )
54 #endif
55 
56 #ifndef REG_WR_INT_VECT
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59  (index) * STRIDE_##scope##_##reg, (val) )
60 #endif
61 
62 #ifndef REG_TYPE_CONV
63 #define REG_TYPE_CONV( type, orgtype, val ) \
64  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
65 #endif
66 
67 #ifndef reg_page_size
68 #define reg_page_size 8192
69 #endif
70 
71 #ifndef REG_ADDR
72 #define REG_ADDR( scope, inst, reg ) \
73  ( (inst) + REG_RD_ADDR_##scope##_##reg )
74 #endif
75 
76 #ifndef REG_ADDR_VECT
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79  (index) * STRIDE_##scope##_##reg )
80 #endif
81 
82 /* C-code for register scope clkgen */
83 
84 /* Register r_bootsel, scope clkgen, type r */
85 typedef struct {
86  unsigned int boot_mode : 5;
87  unsigned int intern_main_clk : 1;
88  unsigned int extern_usb2_clk : 1;
89  unsigned int dummy1 : 25;
90 } reg_clkgen_r_bootsel;
91 #define REG_RD_ADDR_clkgen_r_bootsel 0
92 
93 /* Register rw_clk_ctrl, scope clkgen, type rw */
94 typedef struct {
95  unsigned int pll : 1;
96  unsigned int cpu : 1;
97  unsigned int iop_usb : 1;
98  unsigned int vin : 1;
99  unsigned int sclr : 1;
100  unsigned int h264 : 1;
101  unsigned int ddr2 : 1;
102  unsigned int vout_hist : 1;
103  unsigned int eth : 1;
104  unsigned int ccd_tg_200 : 1;
105  unsigned int dma0_1_eth : 1;
106  unsigned int ccd_tg_100 : 1;
107  unsigned int jpeg : 1;
108  unsigned int sser_ser_dma6_7 : 1;
109  unsigned int strdma0_2_video : 1;
110  unsigned int dma2_3_strcop : 1;
111  unsigned int dma4_5_iop : 1;
112  unsigned int dma9_11 : 1;
113  unsigned int memarb_bar_ddr : 1;
114  unsigned int sclr_h264 : 1;
115  unsigned int dummy1 : 12;
116 } reg_clkgen_rw_clk_ctrl;
117 #define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
118 #define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
119 
120 
121 /* Constants */
122 enum {
123  regk_clkgen_eth1000_rx = 0x0000000c,
124  regk_clkgen_eth1000_tx = 0x0000000e,
125  regk_clkgen_eth100_rx = 0x0000001d,
126  regk_clkgen_eth100_rx_half = 0x0000001c,
127  regk_clkgen_eth100_tx = 0x0000001f,
128  regk_clkgen_eth100_tx_half = 0x0000001e,
129  regk_clkgen_nand_3_2 = 0x00000000,
130  regk_clkgen_nand_3_2_0x30 = 0x00000002,
131  regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
132  regk_clkgen_nand_3_2_pll = 0x00000010,
133  regk_clkgen_nand_3_3 = 0x00000001,
134  regk_clkgen_nand_3_3_0x30 = 0x00000003,
135  regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
136  regk_clkgen_nand_3_3_pll = 0x00000011,
137  regk_clkgen_nand_4_2 = 0x00000004,
138  regk_clkgen_nand_4_2_0x30 = 0x00000006,
139  regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
140  regk_clkgen_nand_4_2_pll = 0x00000014,
141  regk_clkgen_nand_4_3 = 0x00000005,
142  regk_clkgen_nand_4_3_0x30 = 0x00000007,
143  regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
144  regk_clkgen_nand_4_3_pll = 0x00000015,
145  regk_clkgen_nand_5_2 = 0x00000008,
146  regk_clkgen_nand_5_2_0x30 = 0x0000000a,
147  regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
148  regk_clkgen_nand_5_2_pll = 0x00000018,
149  regk_clkgen_nand_5_3 = 0x00000009,
150  regk_clkgen_nand_5_3_0x30 = 0x0000000b,
151  regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
152  regk_clkgen_nand_5_3_pll = 0x00000019,
153  regk_clkgen_no = 0x00000000,
154  regk_clkgen_rw_clk_ctrl_default = 0x00000002,
155  regk_clkgen_ser = 0x0000000d,
156  regk_clkgen_ser_pll = 0x0000000f,
157  regk_clkgen_yes = 0x00000001
158 };
159 #endif /* __clkgen_defs_h */
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