Macros
#define	AM33XX_AUTO_DPLL_MODE_SHIFT 0

#define	AM33XX_AUTO_DPLL_MODE_WIDTH 3

#define	AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)

#define	AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14

#define	AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)

#define	AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11

#define	AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)

#define	AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5

#define	AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)

#define	AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6

#define	AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)

#define	AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6

#define	AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)

#define	AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9

#define	AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)

#define	AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2

#define	AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)

#define	AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4

#define	AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1

#define	AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2

#define	AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)

#define	AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9

#define	AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)

#define	AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19

#define	AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)

#define	AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20

#define	AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)

#define	AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21

#define	AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)

#define	AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22

#define	AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)

#define	AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26

#define	AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)

#define	AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18

#define	AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)

#define	AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11

#define	AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)

#define	AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24

#define	AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)

#define	AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5

#define	AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)

#define	AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6

#define	AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)

#define	AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3

#define	AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)

#define	AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3

#define	AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)

#define	AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3

#define	AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)

#define	AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8

#define	AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)

#define	AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2

#define	AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)

#define	AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2

#define	AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)

#define	AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17

#define	AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)

#define	AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5

#define	AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)

#define	AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7

#define	AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)

#define	AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3

#define	AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)

#define	AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2

#define	AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)

#define	AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)

#define	AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5

#define	AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)

#define	AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9

#define	AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)

#define	AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25

#define	AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)

#define	AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3

#define	AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)

#define	AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10

#define	AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)

#define	AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13

#define	AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)

#define	AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14

#define	AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)

#define	AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15

#define	AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)

#define	AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16

#define	AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)

#define	AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27

#define	AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)

#define	AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28

#define	AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)

#define	AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13

#define	AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)

#define	AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12

#define	AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)

#define	AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10

#define	AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)

#define	AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9

#define	AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)

#define	AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4

#define	AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1

#define	AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)

#define	AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0

#define	AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1

#define	AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)

#define	AM33XX_CLKOUT2DIV_SHIFT 3

#define	AM33XX_CLKOUT2DIV_WIDTH 3

#define	AM33XX_CLKOUT2DIV_MASK (0x7 << 3)

#define	AM33XX_CLKOUT2EN_SHIFT 7

#define	AM33XX_CLKOUT2EN_WIDTH 1

#define	AM33XX_CLKOUT2EN_MASK (1 << 7)

#define	AM33XX_CLKOUT2SOURCE_SHIFT 0

#define	AM33XX_CLKOUT2SOURCE_WIDTH 3

#define	AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)

#define	AM33XX_CLKSEL_SHIFT 0

#define	AM33XX_CLKSEL_WIDTH 1

#define	AM33XX_CLKSEL_MASK (0x01 << 0)

#define	AM33XX_CLKSEL_0_0_SHIFT 0

#define	AM33XX_CLKSEL_0_0_WIDTH 1

#define	AM33XX_CLKSEL_0_0_MASK (1 << 0)

#define	AM33XX_CLKSEL_0_1_SHIFT 0

#define	AM33XX_CLKSEL_0_1_WIDTH 2

#define	AM33XX_CLKSEL_0_1_MASK (3 << 0)

#define	AM33XX_CLKSEL_0_2_SHIFT 0

#define	AM33XX_CLKSEL_0_2_WIDTH 3

#define	AM33XX_CLKSEL_0_2_MASK (7 << 0)

#define	AM33XX_CLKSEL_GFX_FCLK_SHIFT 1

#define	AM33XX_CLKSEL_GFX_FCLK_WIDTH 1

#define	AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)

#define	AM33XX_CLKTRCTRL_SHIFT 0

#define	AM33XX_CLKTRCTRL_WIDTH 2

#define	AM33XX_CLKTRCTRL_MASK (0x3 << 0)

#define	AM33XX_DELTAMSTEP_SHIFT 0

#define	AM33XX_DELTAMSTEP_WIDTH 20

#define	AM33XX_DELTAMSTEP_MASK (0xfffff << 0)

#define	AM33XX_DPLL_BYP_CLKSEL_SHIFT 23

#define	AM33XX_DPLL_BYP_CLKSEL_WIDTH 1

#define	AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)

#define	AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8

#define	AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1

#define	AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)

#define	AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12

#define	AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1

#define	AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)

#define	AM33XX_DPLL_CLKOUT_DIV_SHIFT 0

#define	AM33XX_DPLL_CLKOUT_DIV_WIDTH 5

#define	AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

#define	AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0

#define	AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7

#define	AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1

#define	AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)

#define	AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8

#define	AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1

#define	AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)

#define	AM33XX_DPLL_DIV_SHIFT 0

#define	AM33XX_DPLL_DIV_WIDTH 7

#define	AM33XX_DPLL_DIV_MASK (0x7f << 0)

#define	AM33XX_DPLL_PER_DIV_MASK (0xff << 0)

#define	AM33XX_DPLL_DIV_0_7_SHIFT 0

#define	AM33XX_DPLL_DIV_0_7_WIDTH 8

#define	AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)

#define	AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8

#define	AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1

#define	AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)

#define	AM33XX_DPLL_EN_SHIFT 0

#define	AM33XX_DPLL_EN_WIDTH 3

#define	AM33XX_DPLL_EN_MASK (0x7 << 0)

#define	AM33XX_DPLL_LPMODE_EN_SHIFT 10

#define	AM33XX_DPLL_LPMODE_EN_WIDTH 1

#define	AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)

#define	AM33XX_DPLL_MULT_SHIFT 8

#define	AM33XX_DPLL_MULT_WIDTH 11

#define	AM33XX_DPLL_MULT_MASK (0x7ff << 8)

#define	AM33XX_DPLL_MULT_PERIPH_SHIFT 8

#define	AM33XX_DPLL_MULT_PERIPH_WIDTH 12

#define	AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)

#define	AM33XX_DPLL_REGM4XEN_SHIFT 11

#define	AM33XX_DPLL_REGM4XEN_WIDTH 1

#define	AM33XX_DPLL_REGM4XEN_MASK (1 << 11)

#define	AM33XX_DPLL_SD_DIV_SHIFT 24

#define	AM33XX_DPLL_SD_DIV_WIDTH 8

#define	AM33XX_DPLL_SD_DIV_MASK (0xff << 24)

#define	AM33XX_DPLL_SSC_ACK_SHIFT 13

#define	AM33XX_DPLL_SSC_ACK_WIDTH 1

#define	AM33XX_DPLL_SSC_ACK_MASK (1 << 13)

#define	AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14

#define	AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1

#define	AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)

#define	AM33XX_DPLL_SSC_EN_SHIFT 12

#define	AM33XX_DPLL_SSC_EN_WIDTH 1

#define	AM33XX_DPLL_SSC_EN_MASK (1 << 12)

#define	AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0

#define	AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5

#define	AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)

#define	AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5

#define	AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)

#define	AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8

#define	AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)

#define	AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12

#define	AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)

#define	AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0

#define	AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5

#define	AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)

#define	AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5

#define	AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)

#define	AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8

#define	AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)

#define	AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12

#define	AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)

#define	AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0

#define	AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5

#define	AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)

#define	AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5

#define	AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)

#define	AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8

#define	AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)

#define	AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12

#define	AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1

#define	AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)

#define	AM33XX_IDLEST_SHIFT 16

#define	AM33XX_IDLEST_WIDTH 2

#define	AM33XX_IDLEST_MASK (0x3 << 16)

#define	AM33XX_MII_CLK_SEL_SHIFT 2

#define	AM33XX_MII_CLK_SEL_WIDTH 1

#define	AM33XX_MII_CLK_SEL_MASK (1 << 2)

#define	AM33XX_MODFREQDIV_EXPONENT_SHIFT 8

#define	AM33XX_MODFREQDIV_EXPONENT_WIDTH 3

#define	AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)

#define	AM33XX_MODFREQDIV_MANTISSA_SHIFT 0

#define	AM33XX_MODFREQDIV_MANTISSA_WIDTH 7

#define	AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)

#define	AM33XX_MODULEMODE_SHIFT 0

#define	AM33XX_MODULEMODE_WIDTH 2

#define	AM33XX_MODULEMODE_MASK (0x3 << 0)

#define	AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30

#define	AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1

#define	AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)

#define	AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19

#define	AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)

#define	AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)

#define	AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18

#define	AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1

#define	AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)

#define	AM33XX_STBYST_SHIFT 18

#define	AM33XX_STBYST_WIDTH 1

#define	AM33XX_STBYST_MASK (1 << 18)

#define	AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27

#define	AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3

#define	AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)

#define	AM33XX_STM_PMD_CLKSEL_SHIFT 22

#define	AM33XX_STM_PMD_CLKSEL_WIDTH 2

#define	AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)

#define	AM33XX_ST_DPLL_CLK_SHIFT 0

#define	AM33XX_ST_DPLL_CLK_WIDTH 1

#define	AM33XX_ST_DPLL_CLK_MASK (1 << 0)

#define	AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8

#define	AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1

#define	AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)

#define	AM33XX_ST_DPLL_CLKOUT_SHIFT 9

#define	AM33XX_ST_DPLL_CLKOUT_WIDTH 1

#define	AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)

#define	AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9

#define	AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1

#define	AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)

#define	AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9

#define	AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1

#define	AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)

#define	AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9

#define	AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1

#define	AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)

#define	AM33XX_ST_MN_BYPASS_SHIFT 8

#define	AM33XX_ST_MN_BYPASS_WIDTH 1

#define	AM33XX_ST_MN_BYPASS_MASK (1 << 8)

#define	AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24

#define	AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3

#define	AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)

#define	AM33XX_TRC_PMD_CLKSEL_SHIFT 20

#define	AM33XX_TRC_PMD_CLKSEL_WIDTH 2

#define	AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)

#define	AM33XX_TIMER0_CLKSEL_WIDTH 2

#define	AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)

Macro Definition Documentation

#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)

Definition at line 29 of file cm-regbits-33xx.h.

#define AM33XX_AUTO_DPLL_MODE_SHIFT 0

Definition at line 27 of file cm-regbits-33xx.h.

#define AM33XX_AUTO_DPLL_MODE_WIDTH 3

Definition at line 28 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)

Definition at line 34 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14

Definition at line 32 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1

Definition at line 33 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)

Definition at line 39 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11

Definition at line 37 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1

Definition at line 38 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)

Definition at line 44 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4

Definition at line 42 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1

Definition at line 43 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)

Definition at line 49 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4

Definition at line 47 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1

Definition at line 48 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)

Definition at line 54 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4

Definition at line 52 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1

Definition at line 53 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)

Definition at line 59 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5

Definition at line 57 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1

Definition at line 58 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)

Definition at line 64 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6

Definition at line 62 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1

Definition at line 63 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)

Definition at line 69 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6

Definition at line 67 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1

Definition at line 68 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)

Definition at line 74 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9

Definition at line 72 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1

Definition at line 73 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)

Definition at line 79 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2

Definition at line 77 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1

Definition at line 78 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)

Definition at line 84 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4

Definition at line 82 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1

Definition at line 83 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)

Definition at line 89 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2

Definition at line 87 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1

Definition at line 88 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)

Definition at line 94 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9

Definition at line 92 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1

Definition at line 93 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)

Definition at line 99 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8

Definition at line 97 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1

Definition at line 98 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)

Definition at line 104 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8

Definition at line 102 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1

Definition at line 103 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)

Definition at line 109 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19

Definition at line 107 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1

Definition at line 108 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)

Definition at line 114 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20

Definition at line 112 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1

Definition at line 113 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)

Definition at line 119 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21

Definition at line 117 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1

Definition at line 118 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)

Definition at line 124 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22

Definition at line 122 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1

Definition at line 123 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)

Definition at line 129 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26

Definition at line 127 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1

Definition at line 128 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)

Definition at line 134 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18

Definition at line 132 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1

Definition at line 133 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)

Definition at line 139 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11

Definition at line 137 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1

Definition at line 138 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)

Definition at line 144 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24

Definition at line 142 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1

Definition at line 143 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)

Definition at line 169 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3

Definition at line 167 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1

Definition at line 168 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)

Definition at line 174 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4

Definition at line 172 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1

Definition at line 173 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)

Definition at line 164 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3

Definition at line 162 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1

Definition at line 163 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)

Definition at line 199 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8

Definition at line 197 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1

Definition at line 198 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)

Definition at line 204 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8

Definition at line 202 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1

Definition at line 203 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)

Definition at line 209 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2

Definition at line 207 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1

Definition at line 208 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)

Definition at line 214 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2

Definition at line 212 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1

Definition at line 213 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)

Definition at line 179 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8

Definition at line 177 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1

Definition at line 178 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)

Definition at line 184 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3

Definition at line 182 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1

Definition at line 183 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)

Definition at line 189 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8

Definition at line 187 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1

Definition at line 188 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)

Definition at line 194 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8

Definition at line 192 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1

Definition at line 193 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)

Definition at line 219 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17

Definition at line 217 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1

Definition at line 218 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)

Definition at line 224 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4

Definition at line 222 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1

Definition at line 223 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)

Definition at line 229 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5

Definition at line 227 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1

Definition at line 228 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)

Definition at line 234 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7

Definition at line 232 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1

Definition at line 233 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)

Definition at line 239 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3

Definition at line 237 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1

Definition at line 238 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)

Definition at line 244 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2

Definition at line 242 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1

Definition at line 243 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)

Definition at line 249 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4

Definition at line 247 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1

Definition at line 248 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)

Definition at line 254 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5

Definition at line 252 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1

Definition at line 253 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)

Definition at line 149 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5

Definition at line 147 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1

Definition at line 148 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)

Definition at line 154 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4

Definition at line 152 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1

Definition at line 153 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)

Definition at line 159 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6

Definition at line 157 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1

Definition at line 158 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)

Definition at line 259 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9

Definition at line 257 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1

Definition at line 258 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)

Definition at line 264 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25

Definition at line 262 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1

Definition at line 263 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)

Definition at line 269 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3

Definition at line 267 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1

Definition at line 268 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)

Definition at line 274 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10

Definition at line 272 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1

Definition at line 273 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)

Definition at line 279 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13

Definition at line 277 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1

Definition at line 278 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)

Definition at line 284 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14

Definition at line 282 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1

Definition at line 283 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)

Definition at line 289 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15

Definition at line 287 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1

Definition at line 288 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)

Definition at line 294 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16

Definition at line 292 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1

Definition at line 293 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)

Definition at line 299 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27

Definition at line 297 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1

Definition at line 298 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)

Definition at line 304 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28

Definition at line 302 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1

Definition at line 303 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)

Definition at line 309 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13

Definition at line 307 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1

Definition at line 308 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)

Definition at line 314 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12

Definition at line 312 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1

Definition at line 313 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)

Definition at line 319 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10

Definition at line 317 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1

Definition at line 318 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)

Definition at line 324 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9

Definition at line 322 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1

Definition at line 323 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)

Definition at line 329 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4

Definition at line 327 of file cm-regbits-33xx.h.

#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1

Definition at line 328 of file cm-regbits-33xx.h.

#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)

Definition at line 334 of file cm-regbits-33xx.h.

#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0

Definition at line 332 of file cm-regbits-33xx.h.

#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1

Definition at line 333 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)

Definition at line 339 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2DIV_SHIFT 3

Definition at line 337 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2DIV_WIDTH 3

Definition at line 338 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2EN_MASK (1 << 7)

Definition at line 344 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2EN_SHIFT 7

Definition at line 342 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2EN_WIDTH 1

Definition at line 343 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)

Definition at line 349 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2SOURCE_SHIFT 0

Definition at line 347 of file cm-regbits-33xx.h.

#define AM33XX_CLKOUT2SOURCE_WIDTH 3

Definition at line 348 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_0_MASK (1 << 0)

Definition at line 366 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_0_SHIFT 0

Definition at line 364 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_0_WIDTH 1

Definition at line 365 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_1_MASK (3 << 0)

Definition at line 370 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_1_SHIFT 0

Definition at line 368 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_1_WIDTH 2

Definition at line 369 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_2_MASK (7 << 0)

Definition at line 375 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_2_SHIFT 0

Definition at line 373 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_0_2_WIDTH 3

Definition at line 374 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)

Definition at line 380 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1

Definition at line 378 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1

Definition at line 379 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_MASK (0x01 << 0)

Definition at line 358 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_SHIFT 0

Definition at line 356 of file cm-regbits-33xx.h.

#define AM33XX_CLKSEL_WIDTH 1

Definition at line 357 of file cm-regbits-33xx.h.

#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)

Definition at line 392 of file cm-regbits-33xx.h.

#define AM33XX_CLKTRCTRL_SHIFT 0

Definition at line 390 of file cm-regbits-33xx.h.

#define AM33XX_CLKTRCTRL_WIDTH 2

Definition at line 391 of file cm-regbits-33xx.h.

#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)

Definition at line 401 of file cm-regbits-33xx.h.

#define AM33XX_DELTAMSTEP_SHIFT 0

Definition at line 399 of file cm-regbits-33xx.h.

#define AM33XX_DELTAMSTEP_WIDTH 20

Definition at line 400 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)

Definition at line 406 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23

Definition at line 404 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1

Definition at line 405 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)

Definition at line 411 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8

Definition at line 409 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1

Definition at line 410 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)

Definition at line 416 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12

Definition at line 414 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1

Definition at line 415 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)

Definition at line 426 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0

Definition at line 424 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7

Definition at line 425 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

Definition at line 421 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0

Definition at line 419 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5

Definition at line 420 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)

Definition at line 436 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7

Definition at line 434 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1

Definition at line 435 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)

Definition at line 431 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5

Definition at line 429 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1

Definition at line 430 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)

Definition at line 444 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8

Definition at line 442 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1

Definition at line 443 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)

Definition at line 459 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_0_7_SHIFT 0

Definition at line 457 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_0_7_WIDTH 8

Definition at line 458 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_MASK (0x7f << 0)

Definition at line 452 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_SHIFT 0

Definition at line 450 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DIV_WIDTH 7

Definition at line 451 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)

Definition at line 467 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8

Definition at line 465 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1

Definition at line 466 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_EN_MASK (0x7 << 0)

Definition at line 475 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_EN_SHIFT 0

Definition at line 473 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_EN_WIDTH 3

Definition at line 474 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)

Definition at line 483 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_LPMODE_EN_SHIFT 10

Definition at line 481 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_LPMODE_EN_WIDTH 1

Definition at line 482 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)

Definition at line 491 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)

Definition at line 496 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8

Definition at line 494 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12

Definition at line 495 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_SHIFT 8

Definition at line 489 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_MULT_WIDTH 11

Definition at line 490 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)

Definition at line 454 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)

Definition at line 504 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_REGM4XEN_SHIFT 11

Definition at line 502 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_REGM4XEN_WIDTH 1

Definition at line 503 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)

Definition at line 509 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SD_DIV_SHIFT 24

Definition at line 507 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SD_DIV_WIDTH 8

Definition at line 508 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)

Definition at line 517 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_ACK_SHIFT 13

Definition at line 515 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_ACK_WIDTH 1

Definition at line 516 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)

Definition at line 525 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14

Definition at line 523 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1

Definition at line 524 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)

Definition at line 533 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_EN_SHIFT 12

Definition at line 531 of file cm-regbits-33xx.h.

#define AM33XX_DPLL_SSC_EN_WIDTH 1

Definition at line 532 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)

Definition at line 538 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0

Definition at line 536 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5

Definition at line 537 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)

Definition at line 543 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5

Definition at line 541 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1

Definition at line 542 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)

Definition at line 548 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8

Definition at line 546 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1

Definition at line 547 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)

Definition at line 553 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12

Definition at line 551 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1

Definition at line 552 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)

Definition at line 558 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0

Definition at line 556 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5

Definition at line 557 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)

Definition at line 563 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5

Definition at line 561 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1

Definition at line 562 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)

Definition at line 568 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8

Definition at line 566 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1

Definition at line 567 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)

Definition at line 573 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12

Definition at line 571 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1

Definition at line 572 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)

Definition at line 578 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0

Definition at line 576 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5

Definition at line 577 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)

Definition at line 583 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5

Definition at line 581 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1

Definition at line 582 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)

Definition at line 588 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8

Definition at line 586 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1

Definition at line 587 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)

Definition at line 593 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12

Definition at line 591 of file cm-regbits-33xx.h.

#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1

Definition at line 592 of file cm-regbits-33xx.h.

#define AM33XX_IDLEST_MASK (0x3 << 16)

Definition at line 630 of file cm-regbits-33xx.h.

#define AM33XX_IDLEST_SHIFT 16

Definition at line 628 of file cm-regbits-33xx.h.

#define AM33XX_IDLEST_WIDTH 2

Definition at line 629 of file cm-regbits-33xx.h.

#define AM33XX_MII_CLK_SEL_MASK (1 << 2)

Definition at line 635 of file cm-regbits-33xx.h.

#define AM33XX_MII_CLK_SEL_SHIFT 2

Definition at line 633 of file cm-regbits-33xx.h.

#define AM33XX_MII_CLK_SEL_WIDTH 1

Definition at line 634 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)

Definition at line 644 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8

Definition at line 642 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3

Definition at line 643 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)

Definition at line 653 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0

Definition at line 651 of file cm-regbits-33xx.h.

#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7

Definition at line 652 of file cm-regbits-33xx.h.

#define AM33XX_MODULEMODE_MASK (0x3 << 0)

Definition at line 691 of file cm-regbits-33xx.h.

#define AM33XX_MODULEMODE_SHIFT 0

Definition at line 689 of file cm-regbits-33xx.h.

#define AM33XX_MODULEMODE_WIDTH 2

Definition at line 690 of file cm-regbits-33xx.h.

#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)

Definition at line 696 of file cm-regbits-33xx.h.

#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30

Definition at line 694 of file cm-regbits-33xx.h.

#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1

Definition at line 695 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)

Definition at line 701 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19

Definition at line 699 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1

Definition at line 700 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)

Definition at line 706 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18

Definition at line 704 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1

Definition at line 705 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)

Definition at line 711 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18

Definition at line 709 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1

Definition at line 710 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)

Definition at line 716 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18

Definition at line 714 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1

Definition at line 715 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)

Definition at line 721 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18

Definition at line 719 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1

Definition at line 720 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)

Definition at line 726 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18

Definition at line 724 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1

Definition at line 725 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)

Definition at line 731 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18

Definition at line 729 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1

Definition at line 730 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)

Definition at line 736 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18

Definition at line 734 of file cm-regbits-33xx.h.

#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1

Definition at line 735 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)

Definition at line 766 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLK_SHIFT 0

Definition at line 764 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLK_WIDTH 1

Definition at line 765 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)

Definition at line 771 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8

Definition at line 769 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1

Definition at line 770 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)

Definition at line 779 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9

Definition at line 777 of file cm-regbits-33xx.h.

#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1

Definition at line 778 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)

Definition at line 784 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9

Definition at line 782 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1

Definition at line 783 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)

Definition at line 789 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9

Definition at line 787 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1

Definition at line 788 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)

Definition at line 794 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9

Definition at line 792 of file cm-regbits-33xx.h.

#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1

Definition at line 793 of file cm-regbits-33xx.h.

#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)

Definition at line 802 of file cm-regbits-33xx.h.

#define AM33XX_ST_MN_BYPASS_SHIFT 8

Definition at line 800 of file cm-regbits-33xx.h.

#define AM33XX_ST_MN_BYPASS_WIDTH 1

Definition at line 801 of file cm-regbits-33xx.h.

#define AM33XX_STBYST_MASK (1 << 18)

Definition at line 748 of file cm-regbits-33xx.h.

#define AM33XX_STBYST_SHIFT 18

Definition at line 746 of file cm-regbits-33xx.h.

#define AM33XX_STBYST_WIDTH 1

Definition at line 747 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)

Definition at line 753 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27

Definition at line 751 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3

Definition at line 752 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)

Definition at line 758 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKSEL_SHIFT 22

Definition at line 756 of file cm-regbits-33xx.h.

#define AM33XX_STM_PMD_CLKSEL_WIDTH 2

Definition at line 757 of file cm-regbits-33xx.h.

#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)

Definition at line 816 of file cm-regbits-33xx.h.

#define AM33XX_TIMER0_CLKSEL_WIDTH 2

Definition at line 815 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)

Definition at line 807 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24

Definition at line 805 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3

Definition at line 806 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)

Definition at line 812 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20

Definition at line 810 of file cm-regbits-33xx.h.

#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2

Definition at line 811 of file cm-regbits-33xx.h.

Macros

Macro Definition Documentation