Macros
#define	OMAP3430ES2_EN_MMC3_MASK (1 << 30)

#define	OMAP3430ES2_EN_MMC3_SHIFT 30

#define	OMAP3430_EN_MSPRO_MASK (1 << 23)

#define	OMAP3430_EN_MSPRO_SHIFT 23

#define	OMAP3430_EN_HDQ_MASK (1 << 22)

#define	OMAP3430_EN_HDQ_SHIFT 22

#define	OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)

#define	OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5

#define	OMAP3430ES1_EN_D2D_MASK (1 << 3)

#define	OMAP3430ES1_EN_D2D_SHIFT 3

#define	OMAP3430_EN_SSI_MASK (1 << 0)

#define	OMAP3430_EN_SSI_SHIFT 0

#define	OMAP3430ES2_EN_USBTLL_SHIFT 2

#define	OMAP3430ES2_EN_USBTLL_MASK (1 << 2)

#define	OMAP3430_EN_WDT2_MASK (1 << 5)

#define	OMAP3430_EN_WDT2_SHIFT 5

#define	OMAP3430_EN_CAM_MASK (1 << 0)

#define	OMAP3430_EN_CAM_SHIFT 0

#define	OMAP3430_EN_WDT3_MASK (1 << 12)

#define	OMAP3430_EN_WDT3_SHIFT 12

#define	OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)

#define	OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)

#define	OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0

#define	OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8

#define	OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)

#define	OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4

#define	OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)

#define	OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3

#define	OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)

#define	OMAP3430_EN_IVA2_DPLL_SHIFT 0

#define	OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)

#define	OMAP3430_ST_IVA2_SHIFT 0

#define	OMAP3430_ST_IVA2_MASK (1 << 0)

#define	OMAP3430_ST_IVA2_CLK_SHIFT 0

#define	OMAP3430_ST_IVA2_CLK_MASK (1 << 0)

#define	OMAP3430_AUTO_IVA2_DPLL_SHIFT 0

#define	OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)

#define	OMAP3430_IVA2_CLK_SRC_SHIFT 19

#define	OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)

#define	OMAP3430_IVA2_DPLL_MULT_SHIFT 8

#define	OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)

#define	OMAP3430_IVA2_DPLL_DIV_SHIFT 0

#define	OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)

#define	OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0

#define	OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

#define	OMAP3430_CLKTRCTRL_IVA2_SHIFT 0

#define	OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_IVA2_SHIFT 0

#define	OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)

#define	OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8

#define	OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)

#define	OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4

#define	OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)

#define	OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3

#define	OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)

#define	OMAP3430_EN_MPU_DPLL_SHIFT 0

#define	OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)

#define	OMAP3430_ST_MPU_MASK (1 << 0)

#define	OMAP3430_ST_MPU_CLK_SHIFT 0

#define	OMAP3430_ST_MPU_CLK_MASK (1 << 0)

#define	OMAP3430_AUTO_MPU_DPLL_SHIFT 0

#define	OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)

#define	OMAP3430_MPU_CLK_SRC_SHIFT 19

#define	OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)

#define	OMAP3430_MPU_DPLL_MULT_SHIFT 8

#define	OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)

#define	OMAP3430_MPU_DPLL_DIV_SHIFT 0

#define	OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)

#define	OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0

#define	OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

#define	OMAP3430_CLKTRCTRL_MPU_SHIFT 0

#define	OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_MPU_SHIFT 0

#define	OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)

#define	OMAP3430_EN_MODEM_MASK (1 << 31)

#define	OMAP3430_EN_MODEM_SHIFT 31

#define	OMAP3430_EN_ICR_MASK (1 << 29)

#define	OMAP3430_EN_ICR_SHIFT 29

#define	OMAP3430_EN_AES2_MASK (1 << 28)

#define	OMAP3430_EN_AES2_SHIFT 28

#define	OMAP3430_EN_SHA12_MASK (1 << 27)

#define	OMAP3430_EN_SHA12_SHIFT 27

#define	OMAP3430_EN_DES2_MASK (1 << 26)

#define	OMAP3430_EN_DES2_SHIFT 26

#define	OMAP3430ES1_EN_FAC_MASK (1 << 8)

#define	OMAP3430ES1_EN_FAC_SHIFT 8

#define	OMAP3430_EN_MAILBOXES_MASK (1 << 7)

#define	OMAP3430_EN_MAILBOXES_SHIFT 7

#define	OMAP3430_EN_OMAPCTRL_MASK (1 << 6)

#define	OMAP3430_EN_OMAPCTRL_SHIFT 6

#define	OMAP3430_EN_SAD2D_MASK (1 << 3)

#define	OMAP3430_EN_SAD2D_SHIFT 3

#define	OMAP3430_EN_SDRC_MASK (1 << 1)

#define	OMAP3430_EN_SDRC_SHIFT 1

#define	AM35XX_EN_IPSS_MASK (1 << 4)

#define	AM35XX_EN_IPSS_SHIFT 4

#define	OMAP3430_EN_PKA_MASK (1 << 4)

#define	OMAP3430_EN_PKA_SHIFT 4

#define	OMAP3430_EN_AES1_MASK (1 << 3)

#define	OMAP3430_EN_AES1_SHIFT 3

#define	OMAP3430_EN_RNG_MASK (1 << 2)

#define	OMAP3430_EN_RNG_SHIFT 2

#define	OMAP3430_EN_SHA11_MASK (1 << 1)

#define	OMAP3430_EN_SHA11_SHIFT 1

#define	OMAP3430_EN_DES1_MASK (1 << 0)

#define	OMAP3430_EN_DES1_SHIFT 0

#define	OMAP3430_EN_MAD2D_SHIFT 3

#define	OMAP3430_EN_MAD2D_MASK (1 << 3)

#define	OMAP3430ES2_EN_TS_SHIFT 1

#define	OMAP3430ES2_EN_TS_MASK (1 << 1)

#define	OMAP3430ES2_EN_CPEFUSE_SHIFT 0

#define	OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)

#define	OMAP3430ES2_ST_MMC3_SHIFT 30

#define	OMAP3430ES2_ST_MMC3_MASK (1 << 30)

#define	OMAP3430_ST_ICR_SHIFT 29

#define	OMAP3430_ST_ICR_MASK (1 << 29)

#define	OMAP3430_ST_AES2_SHIFT 28

#define	OMAP3430_ST_AES2_MASK (1 << 28)

#define	OMAP3430_ST_SHA12_SHIFT 27

#define	OMAP3430_ST_SHA12_MASK (1 << 27)

#define	OMAP3430_ST_DES2_SHIFT 26

#define	OMAP3430_ST_DES2_MASK (1 << 26)

#define	OMAP3430_ST_MSPRO_SHIFT 23

#define	OMAP3430_ST_MSPRO_MASK (1 << 23)

#define	AM35XX_ST_UART4_SHIFT 23

#define	AM35XX_ST_UART4_MASK (1 << 23)

#define	OMAP3430_ST_HDQ_SHIFT 22

#define	OMAP3430_ST_HDQ_MASK (1 << 22)

#define	OMAP3430ES1_ST_FAC_SHIFT 8

#define	OMAP3430ES1_ST_FAC_MASK (1 << 8)

#define	OMAP3430ES2_ST_SSI_IDLE_SHIFT 8

#define	OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)

#define	OMAP3430_ST_MAILBOXES_SHIFT 7

#define	OMAP3430_ST_MAILBOXES_MASK (1 << 7)

#define	OMAP3430_ST_OMAPCTRL_SHIFT 6

#define	OMAP3430_ST_OMAPCTRL_MASK (1 << 6)

#define	OMAP3430_ST_SAD2D_SHIFT 3

#define	OMAP3430_ST_SAD2D_MASK (1 << 3)

#define	OMAP3430_ST_SDMA_SHIFT 2

#define	OMAP3430_ST_SDMA_MASK (1 << 2)

#define	OMAP3430_ST_SDRC_SHIFT 1

#define	OMAP3430_ST_SDRC_MASK (1 << 1)

#define	OMAP3430_ST_SSI_STDBY_SHIFT 0

#define	OMAP3430_ST_SSI_STDBY_MASK (1 << 0)

#define	AM35XX_ST_IPSS_SHIFT 5

#define	AM35XX_ST_IPSS_MASK (1 << 5)

#define	OMAP3430_ST_PKA_SHIFT 4

#define	OMAP3430_ST_PKA_MASK (1 << 4)

#define	OMAP3430_ST_AES1_SHIFT 3

#define	OMAP3430_ST_AES1_MASK (1 << 3)

#define	OMAP3430_ST_RNG_SHIFT 2

#define	OMAP3430_ST_RNG_MASK (1 << 2)

#define	OMAP3430_ST_SHA11_SHIFT 1

#define	OMAP3430_ST_SHA11_MASK (1 << 1)

#define	OMAP3430_ST_DES1_SHIFT 0

#define	OMAP3430_ST_DES1_MASK (1 << 0)

#define	OMAP3430ES2_ST_USBTLL_SHIFT 2

#define	OMAP3430ES2_ST_USBTLL_MASK (1 << 2)

#define	OMAP3430ES2_ST_CPEFUSE_SHIFT 0

#define	OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)

#define	OMAP3430_AUTO_MODEM_MASK (1 << 31)

#define	OMAP3430_AUTO_MODEM_SHIFT 31

#define	OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)

#define	OMAP3430ES2_AUTO_MMC3_SHIFT 30

#define	OMAP3430ES2_AUTO_ICR_MASK (1 << 29)

#define	OMAP3430ES2_AUTO_ICR_SHIFT 29

#define	OMAP3430_AUTO_AES2_MASK (1 << 28)

#define	OMAP3430_AUTO_AES2_SHIFT 28

#define	OMAP3430_AUTO_SHA12_MASK (1 << 27)

#define	OMAP3430_AUTO_SHA12_SHIFT 27

#define	OMAP3430_AUTO_DES2_MASK (1 << 26)

#define	OMAP3430_AUTO_DES2_SHIFT 26

#define	OMAP3430_AUTO_MMC2_MASK (1 << 25)

#define	OMAP3430_AUTO_MMC2_SHIFT 25

#define	OMAP3430_AUTO_MMC1_MASK (1 << 24)

#define	OMAP3430_AUTO_MMC1_SHIFT 24

#define	OMAP3430_AUTO_MSPRO_MASK (1 << 23)

#define	OMAP3430_AUTO_MSPRO_SHIFT 23

#define	OMAP3430_AUTO_HDQ_MASK (1 << 22)

#define	OMAP3430_AUTO_HDQ_SHIFT 22

#define	OMAP3430_AUTO_MCSPI4_MASK (1 << 21)

#define	OMAP3430_AUTO_MCSPI4_SHIFT 21

#define	OMAP3430_AUTO_MCSPI3_MASK (1 << 20)

#define	OMAP3430_AUTO_MCSPI3_SHIFT 20

#define	OMAP3430_AUTO_MCSPI2_MASK (1 << 19)

#define	OMAP3430_AUTO_MCSPI2_SHIFT 19

#define	OMAP3430_AUTO_MCSPI1_MASK (1 << 18)

#define	OMAP3430_AUTO_MCSPI1_SHIFT 18

#define	OMAP3430_AUTO_I2C3_MASK (1 << 17)

#define	OMAP3430_AUTO_I2C3_SHIFT 17

#define	OMAP3430_AUTO_I2C2_MASK (1 << 16)

#define	OMAP3430_AUTO_I2C2_SHIFT 16

#define	OMAP3430_AUTO_I2C1_MASK (1 << 15)

#define	OMAP3430_AUTO_I2C1_SHIFT 15

#define	OMAP3430_AUTO_UART2_MASK (1 << 14)

#define	OMAP3430_AUTO_UART2_SHIFT 14

#define	OMAP3430_AUTO_UART1_MASK (1 << 13)

#define	OMAP3430_AUTO_UART1_SHIFT 13

#define	OMAP3430_AUTO_GPT11_MASK (1 << 12)

#define	OMAP3430_AUTO_GPT11_SHIFT 12

#define	OMAP3430_AUTO_GPT10_MASK (1 << 11)

#define	OMAP3430_AUTO_GPT10_SHIFT 11

#define	OMAP3430_AUTO_MCBSP5_MASK (1 << 10)

#define	OMAP3430_AUTO_MCBSP5_SHIFT 10

#define	OMAP3430_AUTO_MCBSP1_MASK (1 << 9)

#define	OMAP3430_AUTO_MCBSP1_SHIFT 9

#define	OMAP3430ES1_AUTO_FAC_MASK (1 << 8)

#define	OMAP3430ES1_AUTO_FAC_SHIFT 8

#define	OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)

#define	OMAP3430_AUTO_MAILBOXES_SHIFT 7

#define	OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)

#define	OMAP3430_AUTO_OMAPCTRL_SHIFT 6

#define	OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)

#define	OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5

#define	OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)

#define	OMAP3430_AUTO_HSOTGUSB_SHIFT 4

#define	OMAP3430ES1_AUTO_D2D_MASK (1 << 3)

#define	OMAP3430ES1_AUTO_D2D_SHIFT 3

#define	OMAP3430_AUTO_SAD2D_MASK (1 << 3)

#define	OMAP3430_AUTO_SAD2D_SHIFT 3

#define	OMAP3430_AUTO_SSI_MASK (1 << 0)

#define	OMAP3430_AUTO_SSI_SHIFT 0

#define	OMAP3430_AUTO_PKA_MASK (1 << 4)

#define	OMAP3430_AUTO_PKA_SHIFT 4

#define	OMAP3430_AUTO_AES1_MASK (1 << 3)

#define	OMAP3430_AUTO_AES1_SHIFT 3

#define	OMAP3430_AUTO_RNG_MASK (1 << 2)

#define	OMAP3430_AUTO_RNG_SHIFT 2

#define	OMAP3430_AUTO_SHA11_MASK (1 << 1)

#define	OMAP3430_AUTO_SHA11_SHIFT 1

#define	OMAP3430_AUTO_DES1_MASK (1 << 0)

#define	OMAP3430_AUTO_DES1_SHIFT 0

#define	OMAP3430ES2_AUTO_USBHOST (1 << 0)

#define	OMAP3430ES2_AUTO_USBHOST_SHIFT 0

#define	OMAP3430ES2_AUTO_USBTLL (1 << 2)

#define	OMAP3430ES2_AUTO_USBTLL_SHIFT 2

#define	OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)

#define	OMAP3430_AUTO_MAD2D_SHIFT 3

#define	OMAP3430_AUTO_MAD2D_MASK (1 << 3)

#define	OMAP3430_CLKSEL_SSI_SHIFT 8

#define	OMAP3430_CLKSEL_SSI_MASK (0xf << 8)

#define	OMAP3430_CLKSEL_GPT11_MASK (1 << 7)

#define	OMAP3430_CLKSEL_GPT11_SHIFT 7

#define	OMAP3430_CLKSEL_GPT10_MASK (1 << 6)

#define	OMAP3430_CLKSEL_GPT10_SHIFT 6

#define	OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4

#define	OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)

#define	OMAP3430_CLKSEL_L4_SHIFT 2

#define	OMAP3430_CLKSEL_L4_MASK (0x3 << 2)

#define	OMAP3430_CLKSEL_L3_SHIFT 0

#define	OMAP3430_CLKSEL_L3_MASK (0x3 << 0)

#define	OMAP3630_CLKSEL_96M_SHIFT 12

#define	OMAP3630_CLKSEL_96M_MASK (0x3 << 12)

#define	OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4

#define	OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)

#define	OMAP3430_CLKTRCTRL_L4_SHIFT 2

#define	OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)

#define	OMAP3430_CLKTRCTRL_L3_SHIFT 0

#define	OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)

#define	OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2

#define	OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)

#define	OMAP3430_CLKACTIVITY_L4_SHIFT 1

#define	OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)

#define	OMAP3430_CLKACTIVITY_L3_SHIFT 0

#define	OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)

#define	OMAP3430ES1_EN_3D_MASK (1 << 2)

#define	OMAP3430ES1_EN_3D_SHIFT 2

#define	OMAP3430ES1_EN_2D_MASK (1 << 1)

#define	OMAP3430ES1_EN_2D_SHIFT 1

#define	OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0

#define	OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)

#define	OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0

#define	OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)

#define	OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1

#define	OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)

#define	OMAP3430ES2_ST_SGX_SHIFT 1

#define	OMAP3430ES2_ST_SGX_MASK (1 << 1)

#define	OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0

#define	OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)

#define	OMAP3430ES2_CLKSEL_SGX_SHIFT 0

#define	OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)

#define	OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0

#define	OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)

#define	OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0

#define	OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)

#define	OMAP3430ES2_EN_USIMOCP_SHIFT 9

#define	OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)

#define	OMAP3430_EN_WDT1_MASK (1 << 4)

#define	OMAP3430_EN_WDT1_SHIFT 4

#define	OMAP3430_EN_32KSYNC_MASK (1 << 2)

#define	OMAP3430_EN_32KSYNC_SHIFT 2

#define	OMAP3430ES2_ST_USIMOCP_SHIFT 9

#define	OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)

#define	OMAP3430_ST_WDT2_SHIFT 5

#define	OMAP3430_ST_WDT2_MASK (1 << 5)

#define	OMAP3430_ST_WDT1_SHIFT 4

#define	OMAP3430_ST_WDT1_MASK (1 << 4)

#define	OMAP3430_ST_32KSYNC_SHIFT 2

#define	OMAP3430_ST_32KSYNC_MASK (1 << 2)

#define	OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)

#define	OMAP3430ES2_AUTO_USIMOCP_SHIFT 9

#define	OMAP3430_AUTO_WDT2_MASK (1 << 5)

#define	OMAP3430_AUTO_WDT2_SHIFT 5

#define	OMAP3430_AUTO_WDT1_MASK (1 << 4)

#define	OMAP3430_AUTO_WDT1_SHIFT 4

#define	OMAP3430_AUTO_GPIO1_MASK (1 << 3)

#define	OMAP3430_AUTO_GPIO1_SHIFT 3

#define	OMAP3430_AUTO_32KSYNC_MASK (1 << 2)

#define	OMAP3430_AUTO_32KSYNC_SHIFT 2

#define	OMAP3430_AUTO_GPT12_MASK (1 << 1)

#define	OMAP3430_AUTO_GPT12_SHIFT 1

#define	OMAP3430_AUTO_GPT1_MASK (1 << 0)

#define	OMAP3430_AUTO_GPT1_SHIFT 0

#define	OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)

#define	OMAP3430_CLKSEL_RM_SHIFT 1

#define	OMAP3430_CLKSEL_RM_MASK (0x3 << 1)

#define	OMAP3430_CLKSEL_GPT1_SHIFT 0

#define	OMAP3430_CLKSEL_GPT1_MASK (1 << 0)

#define	OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31

#define	OMAP3430_PWRDN_CAM_SHIFT 30

#define	OMAP3430_PWRDN_DSS1_SHIFT 29

#define	OMAP3430_PWRDN_TV_SHIFT 28

#define	OMAP3430_PWRDN_96M_SHIFT 27

#define	OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24

#define	OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)

#define	OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20

#define	OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)

#define	OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19

#define	OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)

#define	OMAP3430_EN_PERIPH_DPLL_SHIFT 16

#define	OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)

#define	OMAP3430_PWRDN_EMU_CORE_SHIFT 12

#define	OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8

#define	OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)

#define	OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4

#define	OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)

#define	OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3

#define	OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)

#define	OMAP3430_EN_CORE_DPLL_SHIFT 0

#define	OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)

#define	OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10

#define	OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)

#define	OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4

#define	OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)

#define	OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3

#define	OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0

#define	OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)

#define	OMAP3430_ST_54M_CLK_MASK (1 << 5)

#define	OMAP3430_ST_12M_CLK_MASK (1 << 4)

#define	OMAP3430_ST_48M_CLK_MASK (1 << 3)

#define	OMAP3430_ST_96M_CLK_MASK (1 << 2)

#define	OMAP3430_ST_PERIPH_CLK_SHIFT 1

#define	OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)

#define	OMAP3430_ST_CORE_CLK_SHIFT 0

#define	OMAP3430_ST_CORE_CLK_MASK (1 << 0)

#define	OMAP3430ES2_ST_USIM_CLK_SHIFT 2

#define	OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)

#define	OMAP3430ES2_ST_120M_CLK_SHIFT 1

#define	OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)

#define	OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0

#define	OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)

#define	OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3

#define	OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)

#define	OMAP3430_AUTO_CORE_DPLL_SHIFT 0

#define	OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)

#define	OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0

#define	OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)

#define	OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27

#define	OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)

#define	OMAP3430_CORE_DPLL_MULT_SHIFT 16

#define	OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)

#define	OMAP3430_CORE_DPLL_DIV_SHIFT 8

#define	OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)

#define	OMAP3430_SOURCE_96M_SHIFT 6

#define	OMAP3430_SOURCE_96M_MASK (1 << 6)

#define	OMAP3430_SOURCE_54M_SHIFT 5

#define	OMAP3430_SOURCE_54M_MASK (1 << 5)

#define	OMAP3430_SOURCE_48M_SHIFT 3

#define	OMAP3430_SOURCE_48M_MASK (1 << 3)

#define	OMAP3430_PERIPH_DPLL_MULT_SHIFT 8

#define	OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)

#define	OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)

#define	OMAP3430_PERIPH_DPLL_DIV_SHIFT 0

#define	OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)

#define	OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21

#define	OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)

#define	OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24

#define	OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)

#define	OMAP3430_DIV_96M_SHIFT 0

#define	OMAP3430_DIV_96M_MASK (0x1f << 0)

#define	OMAP3630_DIV_96M_MASK (0x3f << 0)

#define	OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8

#define	OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)

#define	OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0

#define	OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)

#define	OMAP3430ES2_DIV_120M_SHIFT 0

#define	OMAP3430ES2_DIV_120M_MASK (0x1f << 0)

#define	OMAP3430_CLKOUT2_EN_SHIFT 7

#define	OMAP3430_CLKOUT2_EN_MASK (1 << 7)

#define	OMAP3430_CLKOUT2_DIV_SHIFT 3

#define	OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)

#define	OMAP3430_CLKOUT2SOURCE_SHIFT 0

#define	OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)

#define	OMAP3430_EN_TV_MASK (1 << 2)

#define	OMAP3430_EN_TV_SHIFT 2

#define	OMAP3430_EN_DSS2_MASK (1 << 1)

#define	OMAP3430_EN_DSS2_SHIFT 1

#define	OMAP3430_EN_DSS1_MASK (1 << 0)

#define	OMAP3430_EN_DSS1_SHIFT 0

#define	OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)

#define	OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0

#define	OMAP3430ES2_ST_DSS_IDLE_SHIFT 1

#define	OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)

#define	OMAP3430ES2_ST_DSS_STDBY_SHIFT 0

#define	OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)

#define	OMAP3430ES1_ST_DSS_SHIFT 0

#define	OMAP3430ES1_ST_DSS_MASK (1 << 0)

#define	OMAP3430_AUTO_DSS_MASK (1 << 0)

#define	OMAP3430_AUTO_DSS_SHIFT 0

#define	OMAP3430_CLKSEL_TV_SHIFT 8

#define	OMAP3430_CLKSEL_TV_MASK (0x1f << 8)

#define	OMAP3630_CLKSEL_TV_MASK (0x3f << 8)

#define	OMAP3430_CLKSEL_DSS1_SHIFT 0

#define	OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)

#define	OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)

#define	OMAP3430_CLKTRCTRL_DSS_SHIFT 0

#define	OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_DSS_SHIFT 0

#define	OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)

#define	OMAP3430_EN_CSI2_MASK (1 << 1)

#define	OMAP3430_EN_CSI2_SHIFT 1

#define	OMAP3430_ST_CAM_MASK (1 << 0)

#define	OMAP3430_AUTO_CAM_MASK (1 << 0)

#define	OMAP3430_AUTO_CAM_SHIFT 0

#define	OMAP3430_CLKSEL_CAM_SHIFT 0

#define	OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)

#define	OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)

#define	OMAP3430_CLKTRCTRL_CAM_SHIFT 0

#define	OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_CAM_SHIFT 0

#define	OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)

#define	OMAP3430_ST_WDT3_SHIFT 12

#define	OMAP3430_ST_WDT3_MASK (1 << 12)

#define	OMAP3430_ST_MCBSP4_SHIFT 2

#define	OMAP3430_ST_MCBSP4_MASK (1 << 2)

#define	OMAP3430_ST_MCBSP3_SHIFT 1

#define	OMAP3430_ST_MCBSP3_MASK (1 << 1)

#define	OMAP3430_ST_MCBSP2_SHIFT 0

#define	OMAP3430_ST_MCBSP2_MASK (1 << 0)

#define	OMAP3630_AUTO_UART4_MASK (1 << 18)

#define	OMAP3630_AUTO_UART4_SHIFT 18

#define	OMAP3430_AUTO_GPIO6_MASK (1 << 17)

#define	OMAP3430_AUTO_GPIO6_SHIFT 17

#define	OMAP3430_AUTO_GPIO5_MASK (1 << 16)

#define	OMAP3430_AUTO_GPIO5_SHIFT 16

#define	OMAP3430_AUTO_GPIO4_MASK (1 << 15)

#define	OMAP3430_AUTO_GPIO4_SHIFT 15

#define	OMAP3430_AUTO_GPIO3_MASK (1 << 14)

#define	OMAP3430_AUTO_GPIO3_SHIFT 14

#define	OMAP3430_AUTO_GPIO2_MASK (1 << 13)

#define	OMAP3430_AUTO_GPIO2_SHIFT 13

#define	OMAP3430_AUTO_WDT3_MASK (1 << 12)

#define	OMAP3430_AUTO_WDT3_SHIFT 12

#define	OMAP3430_AUTO_UART3_MASK (1 << 11)

#define	OMAP3430_AUTO_UART3_SHIFT 11

#define	OMAP3430_AUTO_GPT9_MASK (1 << 10)

#define	OMAP3430_AUTO_GPT9_SHIFT 10

#define	OMAP3430_AUTO_GPT8_MASK (1 << 9)

#define	OMAP3430_AUTO_GPT8_SHIFT 9

#define	OMAP3430_AUTO_GPT7_MASK (1 << 8)

#define	OMAP3430_AUTO_GPT7_SHIFT 8

#define	OMAP3430_AUTO_GPT6_MASK (1 << 7)

#define	OMAP3430_AUTO_GPT6_SHIFT 7

#define	OMAP3430_AUTO_GPT5_MASK (1 << 6)

#define	OMAP3430_AUTO_GPT5_SHIFT 6

#define	OMAP3430_AUTO_GPT4_MASK (1 << 5)

#define	OMAP3430_AUTO_GPT4_SHIFT 5

#define	OMAP3430_AUTO_GPT3_MASK (1 << 4)

#define	OMAP3430_AUTO_GPT3_SHIFT 4

#define	OMAP3430_AUTO_GPT2_MASK (1 << 3)

#define	OMAP3430_AUTO_GPT2_SHIFT 3

#define	OMAP3430_AUTO_MCBSP4_MASK (1 << 2)

#define	OMAP3430_AUTO_MCBSP4_SHIFT 2

#define	OMAP3430_AUTO_MCBSP3_MASK (1 << 1)

#define	OMAP3430_AUTO_MCBSP3_SHIFT 1

#define	OMAP3430_AUTO_MCBSP2_MASK (1 << 0)

#define	OMAP3430_AUTO_MCBSP2_SHIFT 0

#define	OMAP3430_CLKSEL_GPT9_MASK (1 << 7)

#define	OMAP3430_CLKSEL_GPT9_SHIFT 7

#define	OMAP3430_CLKSEL_GPT8_MASK (1 << 6)

#define	OMAP3430_CLKSEL_GPT8_SHIFT 6

#define	OMAP3430_CLKSEL_GPT7_MASK (1 << 5)

#define	OMAP3430_CLKSEL_GPT7_SHIFT 5

#define	OMAP3430_CLKSEL_GPT6_MASK (1 << 4)

#define	OMAP3430_CLKSEL_GPT6_SHIFT 4

#define	OMAP3430_CLKSEL_GPT5_MASK (1 << 3)

#define	OMAP3430_CLKSEL_GPT5_SHIFT 3

#define	OMAP3430_CLKSEL_GPT4_MASK (1 << 2)

#define	OMAP3430_CLKSEL_GPT4_SHIFT 2

#define	OMAP3430_CLKSEL_GPT3_MASK (1 << 1)

#define	OMAP3430_CLKSEL_GPT3_SHIFT 1

#define	OMAP3430_CLKSEL_GPT2_MASK (1 << 0)

#define	OMAP3430_CLKSEL_GPT2_SHIFT 0

#define	OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)

#define	OMAP3430_CLKTRCTRL_PER_SHIFT 0

#define	OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_PER_SHIFT 0

#define	OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)

#define	OMAP3430_DIV_DPLL4_SHIFT 24

#define	OMAP3430_DIV_DPLL4_MASK (0x1f << 24)

#define	OMAP3630_DIV_DPLL4_MASK (0x3f << 24)

#define	OMAP3430_DIV_DPLL3_SHIFT 16

#define	OMAP3430_DIV_DPLL3_MASK (0x1f << 16)

#define	OMAP3430_CLKSEL_TRACECLK_SHIFT 11

#define	OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)

#define	OMAP3430_CLKSEL_PCLK_SHIFT 8

#define	OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)

#define	OMAP3430_CLKSEL_PCLKX2_SHIFT 6

#define	OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)

#define	OMAP3430_CLKSEL_ATCLK_SHIFT 4

#define	OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)

#define	OMAP3430_TRACE_MUX_CTRL_SHIFT 2

#define	OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)

#define	OMAP3430_MUX_CTRL_SHIFT 0

#define	OMAP3430_MUX_CTRL_MASK (0x3 << 0)

#define	OMAP3430_CLKTRCTRL_EMU_SHIFT 0

#define	OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)

#define	OMAP3430_CLKACTIVITY_EMU_SHIFT 0

#define	OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)

#define	OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8

#define	OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)

#define	OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0

#define	OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)

#define	OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8

#define	OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)

#define	OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0

#define	OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)

#define	OMAP3430_CLKOUT2_POL_MASK (1 << 0)

#define	OMAP3430_ST_NEON_MASK (1 << 0)

#define	OMAP3430_CLKTRCTRL_NEON_SHIFT 0

#define	OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)

#define	OMAP3430ES2_EN_USBHOST2_SHIFT 1

#define	OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)

#define	OMAP3430ES2_EN_USBHOST1_SHIFT 0

#define	OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)

#define	OMAP3430ES2_EN_USBHOST_SHIFT 0

#define	OMAP3430ES2_EN_USBHOST_MASK (1 << 0)

#define	OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1

#define	OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)

#define	OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0

#define	OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)

#define	OMAP3430ES2_AUTO_USBHOST_SHIFT 0

#define	OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)

#define	OMAP3430ES2_EN_MPU_SHIFT 1

#define	OMAP3430ES2_EN_MPU_MASK (1 << 1)

#define	OMAP3430ES2_EN_IVA2_SHIFT 2

#define	OMAP3430ES2_EN_IVA2_MASK (1 << 2)

#define	OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0

#define	OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)

#define	OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0

#define	OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)

#define	OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0

#define	OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1

#define	OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2

#define	OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3

Macro Definition Documentation

#define AM35XX_EN_IPSS_MASK (1 << 4)

Definition at line 171 of file cm-regbits-34xx.h.

#define AM35XX_EN_IPSS_SHIFT 4

Definition at line 172 of file cm-regbits-34xx.h.

#define AM35XX_ST_IPSS_MASK (1 << 5)

Definition at line 232 of file cm-regbits-34xx.h.

#define AM35XX_ST_IPSS_SHIFT 5

Definition at line 231 of file cm-regbits-34xx.h.

#define AM35XX_ST_UART4_MASK (1 << 23)

Definition at line 210 of file cm-regbits-34xx.h.

#define AM35XX_ST_UART4_SHIFT 23

Definition at line 209 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)

Definition at line 444 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_32KSYNC_SHIFT 2

Definition at line 445 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_AES1_MASK (1 << 3)

Definition at line 319 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_AES1_SHIFT 3

Definition at line 320 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_AES2_MASK (1 << 28)

Definition at line 259 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_AES2_SHIFT 28

Definition at line 260 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_CAM_MASK (1 << 0)

Definition at line 620 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_CAM_SHIFT 0

Definition at line 621 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)

Definition at line 513 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0

Definition at line 512 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DES1_MASK (1 << 0)

Definition at line 325 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DES1_SHIFT 0

Definition at line 326 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DES2_MASK (1 << 26)

Definition at line 263 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DES2_SHIFT 26

Definition at line 264 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DSS_MASK (1 << 0)

Definition at line 589 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_DSS_SHIFT 0

Definition at line 590 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)

Definition at line 442 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO1_SHIFT 3

Definition at line 443 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)

Definition at line 663 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO2_SHIFT 13

Definition at line 664 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)

Definition at line 661 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO3_SHIFT 14

Definition at line 662 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)

Definition at line 659 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO4_SHIFT 15

Definition at line 660 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)

Definition at line 657 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO5_SHIFT 16

Definition at line 658 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)

Definition at line 655 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPIO6_SHIFT 17

Definition at line 656 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT10_MASK (1 << 11)

Definition at line 293 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT10_SHIFT 11

Definition at line 294 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT11_MASK (1 << 12)

Definition at line 291 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT11_SHIFT 12

Definition at line 292 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT12_MASK (1 << 1)

Definition at line 446 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT12_SHIFT 1

Definition at line 447 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT1_MASK (1 << 0)

Definition at line 448 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT1_SHIFT 0

Definition at line 449 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT2_MASK (1 << 3)

Definition at line 683 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT2_SHIFT 3

Definition at line 684 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT3_MASK (1 << 4)

Definition at line 681 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT3_SHIFT 4

Definition at line 682 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT4_MASK (1 << 5)

Definition at line 679 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT4_SHIFT 5

Definition at line 680 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT5_MASK (1 << 6)

Definition at line 677 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT5_SHIFT 6

Definition at line 678 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT6_MASK (1 << 7)

Definition at line 675 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT6_SHIFT 7

Definition at line 676 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT7_MASK (1 << 8)

Definition at line 673 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT7_SHIFT 8

Definition at line 674 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT8_MASK (1 << 9)

Definition at line 671 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT8_SHIFT 9

Definition at line 672 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT9_MASK (1 << 10)

Definition at line 669 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_GPT9_SHIFT 10

Definition at line 670 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_HDQ_MASK (1 << 22)

Definition at line 271 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_HDQ_SHIFT 22

Definition at line 272 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)

Definition at line 307 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4

Definition at line 308 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C1_MASK (1 << 15)

Definition at line 285 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C1_SHIFT 15

Definition at line 286 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C2_MASK (1 << 16)

Definition at line 283 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C2_SHIFT 16

Definition at line 284 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C3_MASK (1 << 17)

Definition at line 281 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_I2C3_SHIFT 17

Definition at line 282 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)

Definition at line 79 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0

Definition at line 78 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)

Definition at line 335 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MAD2D_SHIFT 3

Definition at line 334 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)

Definition at line 301 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MAILBOXES_SHIFT 7

Definition at line 302 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)

Definition at line 297 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP1_SHIFT 9

Definition at line 298 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)

Definition at line 689 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP2_SHIFT 0

Definition at line 690 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)

Definition at line 687 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP3_SHIFT 1

Definition at line 688 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)

Definition at line 685 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP4_SHIFT 2

Definition at line 686 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)

Definition at line 295 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCBSP5_SHIFT 10

Definition at line 296 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)

Definition at line 279 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI1_SHIFT 18

Definition at line 280 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)

Definition at line 277 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI2_SHIFT 19

Definition at line 278 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)

Definition at line 275 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI3_SHIFT 20

Definition at line 276 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)

Definition at line 273 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MCSPI4_SHIFT 21

Definition at line 274 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MMC1_MASK (1 << 24)

Definition at line 267 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MMC1_SHIFT 24

Definition at line 268 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MMC2_MASK (1 << 25)

Definition at line 265 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MMC2_SHIFT 25

Definition at line 266 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MODEM_MASK (1 << 31)

Definition at line 253 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MODEM_SHIFT 31

Definition at line 254 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)

Definition at line 124 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0

Definition at line 123 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)

Definition at line 269 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_MSPRO_SHIFT 23

Definition at line 270 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)

Definition at line 303 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6

Definition at line 304 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)

Definition at line 511 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3

Definition at line 510 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_PKA_MASK (1 << 4)

Definition at line 317 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_PKA_SHIFT 4

Definition at line 318 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_RNG_MASK (1 << 2)

Definition at line 321 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_RNG_SHIFT 2

Definition at line 322 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)

Definition at line 311 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SAD2D_SHIFT 3

Definition at line 312 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SHA11_MASK (1 << 1)

Definition at line 323 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SHA11_SHIFT 1

Definition at line 324 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SHA12_MASK (1 << 27)

Definition at line 261 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SHA12_SHIFT 27

Definition at line 262 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SSI_MASK (1 << 0)

Definition at line 313 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_SSI_SHIFT 0

Definition at line 314 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART1_MASK (1 << 13)

Definition at line 289 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART1_SHIFT 13

Definition at line 290 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART2_MASK (1 << 14)

Definition at line 287 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART2_SHIFT 14

Definition at line 288 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART3_MASK (1 << 11)

Definition at line 667 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_UART3_SHIFT 11

Definition at line 668 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT1_MASK (1 << 4)

Definition at line 440 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT1_SHIFT 4

Definition at line 441 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT2_MASK (1 << 5)

Definition at line 438 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT2_SHIFT 5

Definition at line 439 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT3_MASK (1 << 12)

Definition at line 665 of file cm-regbits-34xx.h.

#define OMAP3430_AUTO_WDT3_SHIFT 12

Definition at line 666 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)

Definition at line 636 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0

Definition at line 635 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)

Definition at line 608 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0

Definition at line 607 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)

Definition at line 746 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0

Definition at line 745 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)

Definition at line 99 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0

Definition at line 98 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)

Definition at line 367 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_L3_SHIFT 0

Definition at line 366 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)

Definition at line 365 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_L4_SHIFT 1

Definition at line 364 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)

Definition at line 144 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0

Definition at line 143 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)

Definition at line 719 of file cm-regbits-34xx.h.

#define OMAP3430_CLKACTIVITY_PER_SHIFT 0

Definition at line 718 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)

Definition at line 564 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2_DIV_SHIFT 3

Definition at line 563 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)

Definition at line 562 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2_EN_SHIFT 7

Definition at line 561 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)

Definition at line 761 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)

Definition at line 566 of file cm-regbits-34xx.h.

#define OMAP3430_CLKOUT2SOURCE_SHIFT 0

Definition at line 565 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)

Definition at line 734 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_ATCLK_SHIFT 4

Definition at line 733 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)

Definition at line 625 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_CAM_SHIFT 0

Definition at line 624 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)

Definition at line 597 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_DSS1_SHIFT 0

Definition at line 596 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)

Definition at line 342 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT10_SHIFT 6

Definition at line 343 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)

Definition at line 340 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT11_SHIFT 7

Definition at line 341 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)

Definition at line 456 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT1_SHIFT 0

Definition at line 455 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)

Definition at line 707 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT2_SHIFT 0

Definition at line 708 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)

Definition at line 705 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT3_SHIFT 1

Definition at line 706 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)

Definition at line 703 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT4_SHIFT 2

Definition at line 704 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)

Definition at line 701 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT5_SHIFT 3

Definition at line 702 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)

Definition at line 699 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT6_SHIFT 4

Definition at line 700 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)

Definition at line 697 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT7_SHIFT 5

Definition at line 698 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)

Definition at line 695 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT8_SHIFT 6

Definition at line 696 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)

Definition at line 693 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_GPT9_SHIFT 7

Definition at line 694 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)

Definition at line 349 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_L3_SHIFT 0

Definition at line 348 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)

Definition at line 347 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_L4_SHIFT 2

Definition at line 346 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)

Definition at line 730 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_PCLK_SHIFT 8

Definition at line 729 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)

Definition at line 732 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6

Definition at line 731 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)

Definition at line 454 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_RM_SHIFT 1

Definition at line 453 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)

Definition at line 339 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_SSI_SHIFT 8

Definition at line 338 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)

Definition at line 728 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11

Definition at line 727 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)

Definition at line 594 of file cm-regbits-34xx.h.

#define OMAP3430_CLKSEL_TV_SHIFT 8

Definition at line 593 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)

Definition at line 632 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0

Definition at line 631 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)

Definition at line 604 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0

Definition at line 603 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)

Definition at line 742 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0

Definition at line 741 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)

Definition at line 95 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0

Definition at line 94 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)

Definition at line 359 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_L3_SHIFT 0

Definition at line 358 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)

Definition at line 357 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_L4_SHIFT 2

Definition at line 356 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)

Definition at line 140 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0

Definition at line 139 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)

Definition at line 768 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0

Definition at line 767 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)

Definition at line 715 of file cm-regbits-34xx.h.

#define OMAP3430_CLKTRCTRL_PER_SHIFT 0

Definition at line 714 of file cm-regbits-34xx.h.

#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)

Definition at line 56 of file cm-regbits-34xx.h.

#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0

Definition at line 57 of file cm-regbits-34xx.h.

#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)

Definition at line 577 of file cm-regbits-34xx.h.

#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0

Definition at line 578 of file cm-regbits-34xx.h.

#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)

Definition at line 711 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)

Definition at line 522 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27

Definition at line 521 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)

Definition at line 526 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_DIV_SHIFT 8

Definition at line 525 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)

Definition at line 752 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0

Definition at line 751 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)

Definition at line 750 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8

Definition at line 749 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)

Definition at line 476 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4

Definition at line 475 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)

Definition at line 524 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_MULT_SHIFT 16

Definition at line 523 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)

Definition at line 474 of file cm-regbits-34xx.h.

#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8

Definition at line 473 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_96M_MASK (0x1f << 0)

Definition at line 547 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_96M_SHIFT 0

Definition at line 546 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)

Definition at line 726 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_DPLL3_SHIFT 16

Definition at line 725 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)

Definition at line 723 of file cm-regbits-34xx.h.

#define OMAP3430_DIV_DPLL4_SHIFT 24

Definition at line 722 of file cm-regbits-34xx.h.

#define OMAP3430_EN_32KSYNC_MASK (1 << 2)

Definition at line 422 of file cm-regbits-34xx.h.

#define OMAP3430_EN_32KSYNC_SHIFT 2

Definition at line 423 of file cm-regbits-34xx.h.

#define OMAP3430_EN_AES1_MASK (1 << 3)

Definition at line 177 of file cm-regbits-34xx.h.

#define OMAP3430_EN_AES1_SHIFT 3

Definition at line 178 of file cm-regbits-34xx.h.

#define OMAP3430_EN_AES2_MASK (1 << 28)

Definition at line 153 of file cm-regbits-34xx.h.

#define OMAP3430_EN_AES2_SHIFT 28

Definition at line 154 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CAM_MASK (1 << 0)

Definition at line 42 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CAM_SHIFT 0

Definition at line 43 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)

Definition at line 478 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3

Definition at line 477 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)

Definition at line 480 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CORE_DPLL_SHIFT 0

Definition at line 479 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CSI2_MASK (1 << 1)

Definition at line 611 of file cm-regbits-34xx.h.

#define OMAP3430_EN_CSI2_SHIFT 1

Definition at line 612 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DES1_MASK (1 << 0)

Definition at line 183 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DES1_SHIFT 0

Definition at line 184 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DES2_MASK (1 << 26)

Definition at line 157 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DES2_SHIFT 26

Definition at line 158 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DSS1_MASK (1 << 0)

Definition at line 573 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DSS1_SHIFT 0

Definition at line 574 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DSS2_MASK (1 << 1)

Definition at line 571 of file cm-regbits-34xx.h.

#define OMAP3430_EN_DSS2_SHIFT 1

Definition at line 572 of file cm-regbits-34xx.h.

#define OMAP3430_EN_HDQ_MASK (1 << 22)

Definition at line 24 of file cm-regbits-34xx.h.

#define OMAP3430_EN_HDQ_SHIFT 22

Definition at line 25 of file cm-regbits-34xx.h.

#define OMAP3430_EN_ICR_MASK (1 << 29)

Definition at line 151 of file cm-regbits-34xx.h.

#define OMAP3430_EN_ICR_SHIFT 29

Definition at line 152 of file cm-regbits-34xx.h.

#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)

Definition at line 65 of file cm-regbits-34xx.h.

#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3

Definition at line 64 of file cm-regbits-34xx.h.

#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)

Definition at line 67 of file cm-regbits-34xx.h.

#define OMAP3430_EN_IVA2_DPLL_SHIFT 0

Definition at line 66 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MAD2D_MASK (1 << 3)

Definition at line 188 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MAD2D_SHIFT 3

Definition at line 187 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)

Definition at line 161 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MAILBOXES_SHIFT 7

Definition at line 162 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MODEM_MASK (1 << 31)

Definition at line 147 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MODEM_SHIFT 31

Definition at line 148 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)

Definition at line 111 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3

Definition at line 110 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)

Definition at line 113 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MPU_DPLL_SHIFT 0

Definition at line 112 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MSPRO_MASK (1 << 23)

Definition at line 22 of file cm-regbits-34xx.h.

#define OMAP3430_EN_MSPRO_SHIFT 23

Definition at line 23 of file cm-regbits-34xx.h.

#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)

Definition at line 163 of file cm-regbits-34xx.h.

#define OMAP3430_EN_OMAPCTRL_SHIFT 6

Definition at line 164 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)

Definition at line 469 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19

Definition at line 468 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)

Definition at line 471 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16

Definition at line 470 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PKA_MASK (1 << 4)

Definition at line 175 of file cm-regbits-34xx.h.

#define OMAP3430_EN_PKA_SHIFT 4

Definition at line 176 of file cm-regbits-34xx.h.

#define OMAP3430_EN_RNG_MASK (1 << 2)

Definition at line 179 of file cm-regbits-34xx.h.

#define OMAP3430_EN_RNG_SHIFT 2

Definition at line 180 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SAD2D_MASK (1 << 3)

Definition at line 165 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SAD2D_SHIFT 3

Definition at line 166 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SDRC_MASK (1 << 1)

Definition at line 167 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SDRC_SHIFT 1

Definition at line 168 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SHA11_MASK (1 << 1)

Definition at line 181 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SHA11_SHIFT 1

Definition at line 182 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SHA12_MASK (1 << 27)

Definition at line 155 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SHA12_SHIFT 27

Definition at line 156 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SSI_MASK (1 << 0)

Definition at line 30 of file cm-regbits-34xx.h.

#define OMAP3430_EN_SSI_SHIFT 0

Definition at line 31 of file cm-regbits-34xx.h.

#define OMAP3430_EN_TV_MASK (1 << 2)

Definition at line 569 of file cm-regbits-34xx.h.

#define OMAP3430_EN_TV_SHIFT 2

Definition at line 570 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT1_MASK (1 << 4)

Definition at line 420 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT1_SHIFT 4

Definition at line 421 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT2_MASK (1 << 5)

Definition at line 38 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT2_SHIFT 5

Definition at line 39 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT3_MASK (1 << 12)

Definition at line 46 of file cm-regbits-34xx.h.

#define OMAP3430_EN_WDT3_SHIFT 12

Definition at line 47 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)

Definition at line 83 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_CLK_SRC_SHIFT 19

Definition at line 82 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

Definition at line 91 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0

Definition at line 90 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)

Definition at line 87 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0

Definition at line 86 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)

Definition at line 63 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4

Definition at line 62 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)

Definition at line 85 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8

Definition at line 84 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)

Definition at line 61 of file cm-regbits-34xx.h.

#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8

Definition at line 60 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)

Definition at line 128 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_CLK_SRC_SHIFT 19

Definition at line 127 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)

Definition at line 136 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0

Definition at line 135 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)

Definition at line 132 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_DIV_SHIFT 0

Definition at line 131 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)

Definition at line 109 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4

Definition at line 108 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)

Definition at line 130 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_MULT_SHIFT 8

Definition at line 129 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)

Definition at line 107 of file cm-regbits-34xx.h.

#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8

Definition at line 106 of file cm-regbits-34xx.h.

#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)

Definition at line 738 of file cm-regbits-34xx.h.

#define OMAP3430_MUX_CTRL_SHIFT 0

Definition at line 737 of file cm-regbits-34xx.h.

#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)

Definition at line 50 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)

Definition at line 539 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0

Definition at line 538 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)

Definition at line 758 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0

Definition at line 757 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)

Definition at line 756 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8

Definition at line 755 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)

Definition at line 467 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20

Definition at line 466 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)

Definition at line 536 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8

Definition at line 535 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)

Definition at line 465 of file cm-regbits-34xx.h.

#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24

Definition at line 464 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_96M_SHIFT 27

Definition at line 463 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_CAM_SHIFT 30

Definition at line 460 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_DSS1_SHIFT 29

Definition at line 461 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12

Definition at line 472 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31

Definition at line 459 of file cm-regbits-34xx.h.

#define OMAP3430_PWRDN_TV_SHIFT 28

Definition at line 462 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_48M_MASK (1 << 3)

Definition at line 532 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_48M_SHIFT 3

Definition at line 531 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_54M_MASK (1 << 5)

Definition at line 530 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_54M_SHIFT 5

Definition at line 529 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_96M_MASK (1 << 6)

Definition at line 528 of file cm-regbits-34xx.h.

#define OMAP3430_SOURCE_96M_SHIFT 6

Definition at line 527 of file cm-regbits-34xx.h.

#define OMAP3430_ST_12M_CLK_MASK (1 << 4)

Definition at line 493 of file cm-regbits-34xx.h.

#define OMAP3430_ST_32KSYNC_MASK (1 << 2)

Definition at line 433 of file cm-regbits-34xx.h.

#define OMAP3430_ST_32KSYNC_SHIFT 2

Definition at line 432 of file cm-regbits-34xx.h.

#define OMAP3430_ST_48M_CLK_MASK (1 << 3)

Definition at line 494 of file cm-regbits-34xx.h.

#define OMAP3430_ST_54M_CLK_MASK (1 << 5)

Definition at line 492 of file cm-regbits-34xx.h.

#define OMAP3430_ST_96M_CLK_MASK (1 << 2)

Definition at line 495 of file cm-regbits-34xx.h.

#define OMAP3430_ST_AES1_MASK (1 << 3)

Definition at line 238 of file cm-regbits-34xx.h.

#define OMAP3430_ST_AES1_SHIFT 3

Definition at line 237 of file cm-regbits-34xx.h.

#define OMAP3430_ST_AES2_MASK (1 << 28)

Definition at line 202 of file cm-regbits-34xx.h.

#define OMAP3430_ST_AES2_SHIFT 28

Definition at line 201 of file cm-regbits-34xx.h.

#define OMAP3430_ST_CAM_MASK (1 << 0)

Definition at line 617 of file cm-regbits-34xx.h.

#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)

Definition at line 499 of file cm-regbits-34xx.h.

#define OMAP3430_ST_CORE_CLK_SHIFT 0

Definition at line 498 of file cm-regbits-34xx.h.

#define OMAP3430_ST_DES1_MASK (1 << 0)

Definition at line 244 of file cm-regbits-34xx.h.

#define OMAP3430_ST_DES1_SHIFT 0

Definition at line 243 of file cm-regbits-34xx.h.

#define OMAP3430_ST_DES2_MASK (1 << 26)

Definition at line 206 of file cm-regbits-34xx.h.

#define OMAP3430_ST_DES2_SHIFT 26

Definition at line 205 of file cm-regbits-34xx.h.

#define OMAP3430_ST_HDQ_MASK (1 << 22)

Definition at line 212 of file cm-regbits-34xx.h.

#define OMAP3430_ST_HDQ_SHIFT 22

Definition at line 211 of file cm-regbits-34xx.h.

#define OMAP3430_ST_ICR_MASK (1 << 29)

Definition at line 200 of file cm-regbits-34xx.h.

#define OMAP3430_ST_ICR_SHIFT 29

Definition at line 199 of file cm-regbits-34xx.h.

#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)

Definition at line 75 of file cm-regbits-34xx.h.

#define OMAP3430_ST_IVA2_CLK_SHIFT 0

Definition at line 74 of file cm-regbits-34xx.h.

#define OMAP3430_ST_IVA2_MASK (1 << 0)

Definition at line 71 of file cm-regbits-34xx.h.

#define OMAP3430_ST_IVA2_SHIFT 0

Definition at line 70 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)

Definition at line 218 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MAILBOXES_SHIFT 7

Definition at line 217 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP2_MASK (1 << 0)

Definition at line 650 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP2_SHIFT 0

Definition at line 649 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP3_MASK (1 << 1)

Definition at line 648 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP3_SHIFT 1

Definition at line 647 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP4_MASK (1 << 2)

Definition at line 646 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MCBSP4_SHIFT 2

Definition at line 645 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)

Definition at line 120 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MPU_CLK_SHIFT 0

Definition at line 119 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MPU_MASK (1 << 0)

Definition at line 116 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MSPRO_MASK (1 << 23)

Definition at line 208 of file cm-regbits-34xx.h.

#define OMAP3430_ST_MSPRO_SHIFT 23

Definition at line 207 of file cm-regbits-34xx.h.

#define OMAP3430_ST_NEON_MASK (1 << 0)

Definition at line 764 of file cm-regbits-34xx.h.

#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)

Definition at line 220 of file cm-regbits-34xx.h.

#define OMAP3430_ST_OMAPCTRL_SHIFT 6

Definition at line 219 of file cm-regbits-34xx.h.

#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)

Definition at line 497 of file cm-regbits-34xx.h.

#define OMAP3430_ST_PERIPH_CLK_SHIFT 1

Definition at line 496 of file cm-regbits-34xx.h.

#define OMAP3430_ST_PKA_MASK (1 << 4)

Definition at line 236 of file cm-regbits-34xx.h.

#define OMAP3430_ST_PKA_SHIFT 4

Definition at line 235 of file cm-regbits-34xx.h.

#define OMAP3430_ST_RNG_MASK (1 << 2)

Definition at line 240 of file cm-regbits-34xx.h.

#define OMAP3430_ST_RNG_SHIFT 2

Definition at line 239 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SAD2D_MASK (1 << 3)

Definition at line 222 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SAD2D_SHIFT 3

Definition at line 221 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SDMA_MASK (1 << 2)

Definition at line 224 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SDMA_SHIFT 2

Definition at line 223 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SDRC_MASK (1 << 1)

Definition at line 226 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SDRC_SHIFT 1

Definition at line 225 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SHA11_MASK (1 << 1)

Definition at line 242 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SHA11_SHIFT 1

Definition at line 241 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SHA12_MASK (1 << 27)

Definition at line 204 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SHA12_SHIFT 27

Definition at line 203 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)

Definition at line 228 of file cm-regbits-34xx.h.

#define OMAP3430_ST_SSI_STDBY_SHIFT 0

Definition at line 227 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT1_MASK (1 << 4)

Definition at line 431 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT1_SHIFT 4

Definition at line 430 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT2_MASK (1 << 5)

Definition at line 429 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT2_SHIFT 5

Definition at line 428 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT3_MASK (1 << 12)

Definition at line 644 of file cm-regbits-34xx.h.

#define OMAP3430_ST_WDT3_SHIFT 12

Definition at line 643 of file cm-regbits-34xx.h.

#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)

Definition at line 736 of file cm-regbits-34xx.h.

#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2

Definition at line 735 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)

Definition at line 309 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_D2D_SHIFT 3

Definition at line 310 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)

Definition at line 299 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_FAC_SHIFT 8

Definition at line 300 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)

Definition at line 305 of file cm-regbits-34xx.h.

#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5

Definition at line 306 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)

Definition at line 363 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2

Definition at line 362 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)

Definition at line 389 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0

Definition at line 388 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)

Definition at line 345 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4

Definition at line 344 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)

Definition at line 355 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4

Definition at line 354 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)

Definition at line 385 of file cm-regbits-34xx.h.

#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0

Definition at line 384 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_2D_MASK (1 << 1)

Definition at line 372 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_2D_SHIFT 1

Definition at line 373 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_3D_MASK (1 << 2)

Definition at line 370 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_3D_SHIFT 2

Definition at line 371 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_D2D_MASK (1 << 3)

Definition at line 28 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_D2D_SHIFT 3

Definition at line 29 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_FAC_MASK (1 << 8)

Definition at line 159 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_FAC_SHIFT 8

Definition at line 160 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)

Definition at line 26 of file cm-regbits-34xx.h.

#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5

Definition at line 27 of file cm-regbits-34xx.h.

#define OMAP3430ES1_ST_DSS_MASK (1 << 0)

Definition at line 586 of file cm-regbits-34xx.h.

#define OMAP3430ES1_ST_DSS_SHIFT 0

Definition at line 585 of file cm-regbits-34xx.h.

#define OMAP3430ES1_ST_FAC_MASK (1 << 8)

Definition at line 214 of file cm-regbits-34xx.h.

#define OMAP3430ES1_ST_FAC_SHIFT 8

Definition at line 213 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)

Definition at line 257 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_ICR_SHIFT 29

Definition at line 258 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)

Definition at line 255 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_MMC3_SHIFT 30

Definition at line 256 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)

Definition at line 517 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0

Definition at line 516 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBHOST (1 << 0)

Definition at line 329 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)

Definition at line 788 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0

Definition at line 787 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0

Definition at line 787 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBTLL (1 << 2)

Definition at line 331 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)

Definition at line 333 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2

Definition at line 332 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)

Definition at line 436 of file cm-regbits-34xx.h.

#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9

Definition at line 437 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)

Definition at line 413 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0

Definition at line 412 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)

Definition at line 802 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0

Definition at line 801 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)

Definition at line 405 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0

Definition at line 404 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)

Definition at line 452 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)

Definition at line 409 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0

Definition at line 408 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)

Definition at line 798 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0

Definition at line 797 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)

Definition at line 393 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1

Definition at line 392 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)

Definition at line 401 of file cm-regbits-34xx.h.

#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0

Definition at line 400 of file cm-regbits-34xx.h.

#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)

Definition at line 558 of file cm-regbits-34xx.h.

#define OMAP3430ES2_DIV_120M_SHIFT 0

Definition at line 557 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)

Definition at line 194 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0

Definition at line 193 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)

Definition at line 794 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_IVA2_SHIFT 2

Definition at line 793 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)

Definition at line 20 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_MMC3_SHIFT 30

Definition at line 21 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_MPU_MASK (1 << 1)

Definition at line 792 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_MPU_SHIFT 1

Definition at line 791 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3

Definition at line 487 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10

Definition at line 483 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)

Definition at line 489 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0

Definition at line 488 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_TS_MASK (1 << 1)

Definition at line 192 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_TS_SHIFT 1

Definition at line 191 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)

Definition at line 774 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST1_SHIFT 0

Definition at line 773 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)

Definition at line 772 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST2_SHIFT 1

Definition at line 771 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)

Definition at line 778 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBHOST_SHIFT 0

Definition at line 777 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)

Definition at line 35 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USBTLL_SHIFT 2

Definition at line 34 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)

Definition at line 417 of file cm-regbits-34xx.h.

#define OMAP3430ES2_EN_USIMOCP_SHIFT 9

Definition at line 416 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)

Definition at line 554 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0

Definition at line 553 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)

Definition at line 486 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4

Definition at line 485 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)

Definition at line 552 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8

Definition at line 551 of file cm-regbits-34xx.h.

#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)

Definition at line 484 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)

Definition at line 505 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_120M_CLK_SHIFT 1

Definition at line 504 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)

Definition at line 250 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0

Definition at line 249 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)

Definition at line 582 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1

Definition at line 581 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)

Definition at line 584 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0

Definition at line 583 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)

Definition at line 198 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_MMC3_SHIFT 30

Definition at line 197 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)

Definition at line 507 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0

Definition at line 506 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_SGX_MASK (1 << 1)

Definition at line 397 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_SGX_SHIFT 1

Definition at line 396 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)

Definition at line 216 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8

Definition at line 215 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)

Definition at line 782 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1

Definition at line 781 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)

Definition at line 784 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0

Definition at line 783 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)

Definition at line 248 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USBTLL_SHIFT 2

Definition at line 247 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)

Definition at line 503 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2

Definition at line 502 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)

Definition at line 427 of file cm-regbits-34xx.h.

#define OMAP3430ES2_ST_USIMOCP_SHIFT 9

Definition at line 426 of file cm-regbits-34xx.h.

#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0

Definition at line 809 of file cm-regbits-34xx.h.

#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3

Definition at line 812 of file cm-regbits-34xx.h.

#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1

Definition at line 810 of file cm-regbits-34xx.h.

#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2

Definition at line 811 of file cm-regbits-34xx.h.

#define OMAP3630_AUTO_UART4_MASK (1 << 18)

Definition at line 653 of file cm-regbits-34xx.h.

#define OMAP3630_AUTO_UART4_SHIFT 18

Definition at line 654 of file cm-regbits-34xx.h.

#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)

Definition at line 351 of file cm-regbits-34xx.h.

#define OMAP3630_CLKSEL_96M_SHIFT 12

Definition at line 350 of file cm-regbits-34xx.h.

#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)

Definition at line 626 of file cm-regbits-34xx.h.

#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)

Definition at line 598 of file cm-regbits-34xx.h.

#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)

Definition at line 595 of file cm-regbits-34xx.h.

#define OMAP3630_DIV_96M_MASK (0x3f << 0)

Definition at line 548 of file cm-regbits-34xx.h.

#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)

Definition at line 724 of file cm-regbits-34xx.h.

#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)

Definition at line 541 of file cm-regbits-34xx.h.

#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21

Definition at line 540 of file cm-regbits-34xx.h.

#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)

Definition at line 537 of file cm-regbits-34xx.h.

#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)

Definition at line 543 of file cm-regbits-34xx.h.

#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24

Definition at line 542 of file cm-regbits-34xx.h.

Macros

Macro Definition Documentation