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Functions | |
| u32 | omap4_cm1_read_inst_reg (s16 inst, u16 idx) |
| void | omap4_cm1_write_inst_reg (u32 val, s16 inst, u16 idx) |
| u32 | omap4_cm1_rmw_inst_reg_bits (u32 mask, u32 bits, s16 inst, s16 idx) |
| #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 |
Definition at line 46 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) |
Definition at line 194 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) |
Definition at line 190 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) |
Definition at line 198 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_INST 0x0500 |
Definition at line 39 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) |
Definition at line 192 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) |
Definition at line 200 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) |
Definition at line 202 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) |
Definition at line 204 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) |
Definition at line 206 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) |
Definition at line 196 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) |
Definition at line 208 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) |
Definition at line 210 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) |
Definition at line 212 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) |
Definition at line 214 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) |
Definition at line 216 of file cm1_44xx.h.
| #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) |
Definition at line 218 of file cm1_44xx.h.
| #define OMAP4430_CM1_BASE 0x4a004000 |
Definition at line 29 of file cm1_44xx.h.
| #define OMAP4430_CM1_CKGEN_INST 0x0100 |
Definition at line 36 of file cm1_44xx.h.
| #define OMAP4430_CM1_INSTR_INST 0x0f00 |
Definition at line 41 of file cm1_44xx.h.
| #define OMAP4430_CM1_MPU_INST 0x0300 |
Definition at line 37 of file cm1_44xx.h.
| #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 |
Definition at line 44 of file cm1_44xx.h.
| #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 |
Definition at line 35 of file cm1_44xx.h.
| #define OMAP4430_CM1_RESTORE_INST 0x0e00 |
Definition at line 40 of file cm1_44xx.h.
| #define OMAP4430_CM1_TESLA_INST 0x0400 |
Definition at line 38 of file cm1_44xx.h.
| #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 |
Definition at line 45 of file cm1_44xx.h.
| #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) |
Definition at line 128 of file cm1_44xx.h.
| #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) |
Definition at line 68 of file cm1_44xx.h.
| #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) |
Definition at line 144 of file cm1_44xx.h.
| #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) |
Definition at line 110 of file cm1_44xx.h.
| #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) |
Definition at line 94 of file cm1_44xx.h.
| #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) |
Definition at line 122 of file cm1_44xx.h.
| #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) |
Definition at line 104 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) |
Definition at line 124 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) |
Definition at line 64 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) |
Definition at line 140 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) |
Definition at line 106 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) |
Definition at line 90 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) |
Definition at line 60 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) |
Definition at line 58 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) |
Definition at line 130 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) |
Definition at line 70 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) |
Definition at line 146 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) |
Definition at line 112 of file cm1_44xx.h.
| #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) |
Definition at line 96 of file cm1_44xx.h.
| #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) |
Definition at line 54 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) |
Definition at line 132 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) |
Definition at line 72 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) |
Definition at line 148 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) |
Definition at line 98 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) |
Definition at line 134 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) |
Definition at line 74 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) |
Definition at line 76 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) |
Definition at line 150 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) |
Definition at line 114 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) |
Definition at line 78 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) |
Definition at line 152 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) |
Definition at line 116 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) |
Definition at line 80 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) |
Definition at line 154 of file cm1_44xx.h.
| #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) |
Definition at line 82 of file cm1_44xx.h.
| #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) |
Definition at line 62 of file cm1_44xx.h.
| #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) |
Definition at line 164 of file cm1_44xx.h.
| #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) |
Definition at line 88 of file cm1_44xx.h.
| #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) |
Definition at line 126 of file cm1_44xx.h.
| #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) |
Definition at line 66 of file cm1_44xx.h.
| #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) |
Definition at line 142 of file cm1_44xx.h.
| #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) |
Definition at line 108 of file cm1_44xx.h.
| #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) |
Definition at line 92 of file cm1_44xx.h.
| #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) |
Definition at line 170 of file cm1_44xx.h.
| #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) |
Definition at line 174 of file cm1_44xx.h.
| #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) |
Definition at line 176 of file cm1_44xx.h.
| #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) |
Definition at line 172 of file cm1_44xx.h.
| #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) |
Definition at line 166 of file cm1_44xx.h.
| #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) |
Definition at line 160 of file cm1_44xx.h.
| #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) |
Definition at line 162 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) |
Definition at line 136 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) |
Definition at line 84 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) |
Definition at line 156 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) |
Definition at line 118 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) |
Definition at line 100 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) |
Definition at line 138 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) |
Definition at line 86 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) |
Definition at line 158 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) |
Definition at line 120 of file cm1_44xx.h.
| #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) |
Definition at line 102 of file cm1_44xx.h.
| #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) |
Definition at line 180 of file cm1_44xx.h.
| #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) |
Definition at line 184 of file cm1_44xx.h.
| #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) |
Definition at line 182 of file cm1_44xx.h.
| #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) |
Definition at line 186 of file cm1_44xx.h.
| #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) |
Definition at line 52 of file cm1_44xx.h.
| #define OMAP44XX_CM1_REGADDR | ( | inst, | |
| reg | |||
| ) | OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) |
Definition at line 31 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 |
Definition at line 193 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 |
Definition at line 189 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 |
Definition at line 197 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 |
Definition at line 191 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 |
Definition at line 199 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 |
Definition at line 201 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 |
Definition at line 203 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 |
Definition at line 205 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 |
Definition at line 195 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 |
Definition at line 207 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 |
Definition at line 209 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 |
Definition at line 211 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 |
Definition at line 213 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 |
Definition at line 215 of file cm1_44xx.h.
| #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 |
Definition at line 217 of file cm1_44xx.h.
| #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 |
Definition at line 127 of file cm1_44xx.h.
| #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 |
Definition at line 67 of file cm1_44xx.h.
| #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 |
Definition at line 143 of file cm1_44xx.h.
| #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 |
Definition at line 109 of file cm1_44xx.h.
| #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 |
Definition at line 93 of file cm1_44xx.h.
| #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc |
Definition at line 121 of file cm1_44xx.h.
| #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c |
Definition at line 103 of file cm1_44xx.h.
| #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 |
Definition at line 123 of file cm1_44xx.h.
| #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 |
Definition at line 63 of file cm1_44xx.h.
| #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 |
Definition at line 139 of file cm1_44xx.h.
| #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 |
Definition at line 105 of file cm1_44xx.h.
| #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 |
Definition at line 89 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 |
Definition at line 59 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 |
Definition at line 57 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec |
Definition at line 129 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c |
Definition at line 69 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c |
Definition at line 145 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac |
Definition at line 111 of file cm1_44xx.h.
| #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c |
Definition at line 95 of file cm1_44xx.h.
| #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 |
Definition at line 53 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 |
Definition at line 131 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 |
Definition at line 71 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 |
Definition at line 147 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 |
Definition at line 97 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 |
Definition at line 133 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 |
Definition at line 73 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 |
Definition at line 75 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 |
Definition at line 149 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 |
Definition at line 113 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c |
Definition at line 77 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c |
Definition at line 151 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc |
Definition at line 115 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 |
Definition at line 79 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 |
Definition at line 153 of file cm1_44xx.h.
| #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 |
Definition at line 81 of file cm1_44xx.h.
| #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 |
Definition at line 61 of file cm1_44xx.h.
| #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 |
Definition at line 163 of file cm1_44xx.h.
| #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 |
Definition at line 87 of file cm1_44xx.h.
| #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 |
Definition at line 125 of file cm1_44xx.h.
| #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 |
Definition at line 65 of file cm1_44xx.h.
| #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 |
Definition at line 141 of file cm1_44xx.h.
| #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 |
Definition at line 107 of file cm1_44xx.h.
| #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 |
Definition at line 91 of file cm1_44xx.h.
| #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 |
Definition at line 169 of file cm1_44xx.h.
| #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 |
Definition at line 173 of file cm1_44xx.h.
| #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 |
Definition at line 175 of file cm1_44xx.h.
| #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 |
Definition at line 171 of file cm1_44xx.h.
| #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 |
Definition at line 165 of file cm1_44xx.h.
| #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 |
Definition at line 159 of file cm1_44xx.h.
| #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 |
Definition at line 161 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 |
Definition at line 135 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 |
Definition at line 83 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 |
Definition at line 155 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 |
Definition at line 117 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 |
Definition at line 99 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c |
Definition at line 137 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c |
Definition at line 85 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c |
Definition at line 157 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc |
Definition at line 119 of file cm1_44xx.h.
| #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c |
Definition at line 101 of file cm1_44xx.h.
| #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 |
Definition at line 179 of file cm1_44xx.h.
| #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 |
Definition at line 183 of file cm1_44xx.h.
| #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 |
Definition at line 181 of file cm1_44xx.h.
| #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 |
Definition at line 185 of file cm1_44xx.h.
| #define OMAP4_REVISION_CM1_OFFSET 0x0000 |
Definition at line 51 of file cm1_44xx.h.
1.8.2