Macros
#define	TRACER_ACCESSED_BIT 0

#define	TRACER_RUNNING_BIT 1

#define	TRACER_CYCLE_ACC_BIT 2

#define	TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT)

#define	TRACER_RUNNING BIT(TRACER_RUNNING_BIT)

#define	TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)

#define	TRACER_TIMEOUT 10000

#define	etm_writel(t, v, x) (__raw_writel((v), (t)->etm_regs + (x)))

#define	etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))

#define	CSMR_LOCKACCESS 0xfb0

#define	CSMR_LOCKSTATUS 0xfb4

#define	CSMR_AUTHSTATUS 0xfb8

#define	CSMR_DEVID 0xfc8

#define	CSMR_DEVTYPE 0xfcc

#define	CSCR_CLASS 0xff4

#define	UNLOCK_MAGIC 0xc5acce55

#define	ETMR_CTRL 0

#define	ETMCTRL_POWERDOWN 1

#define	ETMCTRL_PROGRAM (1 << 10)

#define	ETMCTRL_PORTSEL (1 << 11)

#define	ETMCTRL_DO_CONTEXTID (3 << 14)

#define	ETMCTRL_PORTMASK1 (7 << 4)

#define	ETMCTRL_PORTMASK2 (1 << 21)

#define	ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 \| ETMCTRL_PORTMASK2)

#define	ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) \| (!!((x) & 8)) << 21)

#define	ETMCTRL_DO_CPRT (1 << 1)

#define	ETMCTRL_DATAMASK (3 << 2)

#define	ETMCTRL_DATA_DO_DATA (1 << 2)

#define	ETMCTRL_DATA_DO_ADDR (1 << 3)

#define	ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA \| ETMCTRL_DATA_DO_ADDR)

#define	ETMCTRL_BRANCH_OUTPUT (1 << 8)

#define	ETMCTRL_CYCLEACCURATE (1 << 12)

#define	ETMR_CONFCODE (0x04)

#define	ETMR_TRACESSCTRL (0x18)

#define	ETMR_TRIGEVT (0x08)

#define	ETMAAT_IFETCH 0

#define	ETMAAT_IEXEC 1

#define	ETMAAT_IEXECPASS 2

#define	ETMAAT_IEXECFAIL 3

#define	ETMAAT_DLOADSTORE 4

#define	ETMAAT_DLOAD 5

#define	ETMAAT_DSTORE 6

#define	ETMAAT_JAVA (0 << 3)

#define	ETMAAT_THUMB (1 << 3)

#define	ETMAAT_ARM (3 << 3)

#define	ETMAAT_NOVALCMP (0 << 5)

#define	ETMAAT_VALMATCH (1 << 5)

#define	ETMAAT_VALNOMATCH (3 << 5)

#define	ETMAAT_EXACTMATCH (1 << 7)

#define	ETMAAT_IGNCONTEXTID (0 << 8)

#define	ETMAAT_VALUE1 (1 << 8)

#define	ETMAAT_VALUE2 (2 << 8)

#define	ETMAAT_VALUE3 (3 << 8)

#define	ETMAAT_IGNSECURITY (0 << 10)

#define	ETMAAT_NSONLY (1 << 10)

#define	ETMAAT_SONLY (2 << 10)

#define	ETMR_COMP_VAL(x) (0x40 + (x) * 4)

#define	ETMR_COMP_ACC_TYPE(x) (0x80 + (x) * 4)

#define	ETMR_STATUS (0x10)

#define	ETMST_OVERFLOW BIT(0)

#define	ETMST_PROGBIT BIT(1)

#define	ETMST_STARTSTOP BIT(2)

#define	ETMST_TRIGGER BIT(3)

#define	etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)

#define	etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)

#define	etm_triggered(t) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)

#define	ETMR_TRACEENCTRL2 0x1c

#define	ETMR_TRACEENCTRL 0x24

#define	ETMTE_INCLEXCL BIT(24)

#define	ETMR_TRACEENEVT 0x20

#define	ETMCTRL_OPTS

#define	ETMMR_OSLAR 0x300

#define	ETMMR_OSLSR 0x304

#define	ETMMR_OSSRR 0x308

#define	ETMMR_PDSR 0x314

#define	ETBR_DEPTH 0x04

#define	ETBR_STATUS 0x0c

#define	ETBR_READMEM 0x10

#define	ETBR_READADDR 0x14

#define	ETBR_WRITEADDR 0x18

#define	ETBR_TRIGGERCOUNT 0x1c

#define	ETBR_CTRL 0x20

#define	ETBR_FORMATTERCTRL 0x304

#define	ETBFF_ENFTC 1

#define	ETBFF_ENFCONT BIT(1)

#define	ETBFF_FONFLIN BIT(4)

#define	ETBFF_MANUAL_FLUSH BIT(6)

#define	ETBFF_TRIGIN BIT(8)

#define	ETBFF_TRIGEVT BIT(9)

#define	ETBFF_TRIGFL BIT(10)

#define	etb_writel(t, v, x) (__raw_writel((v), (t)->etb_regs + (x)))

#define	etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))

#define	etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)

#define	etm_unlock(t) do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)

#define	etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)

#define	etb_unlock(t) do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)

Macro Definition Documentation

#define CSCR_CLASS 0xff4

Definition at line 37 of file coresight.h.

#define CSMR_AUTHSTATUS 0xfb8

Definition at line 33 of file coresight.h.

#define CSMR_DEVID 0xfc8

Definition at line 34 of file coresight.h.

#define CSMR_DEVTYPE 0xfcc

Definition at line 35 of file coresight.h.

#define CSMR_LOCKACCESS 0xfb0

Definition at line 31 of file coresight.h.

#define CSMR_LOCKSTATUS 0xfb4

Definition at line 32 of file coresight.h.

#define etb_lock ( t ) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)

Definition at line 152 of file coresight.h.

#define etb_readl	(	t,
		x
	)	(__raw_readl((t)->etb_regs + (x)))

Definition at line 146 of file coresight.h.

#define etb_unlock ( t ) do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)

Definition at line 153 of file coresight.h.

#define etb_writel	(	t,
		v,
		x
	)	(__raw_writel((v), (t)->etb_regs + (x)))

Definition at line 144 of file coresight.h.

#define ETBFF_ENFCONT BIT(1)

Definition at line 137 of file coresight.h.

#define ETBFF_ENFTC 1

Definition at line 136 of file coresight.h.

#define ETBFF_FONFLIN BIT(4)

Definition at line 138 of file coresight.h.

#define ETBFF_MANUAL_FLUSH BIT(6)

Definition at line 139 of file coresight.h.

#define ETBFF_TRIGEVT BIT(9)

Definition at line 141 of file coresight.h.

#define ETBFF_TRIGFL BIT(10)

Definition at line 142 of file coresight.h.

#define ETBFF_TRIGIN BIT(8)

Definition at line 140 of file coresight.h.

#define ETBR_CTRL 0x20

Definition at line 134 of file coresight.h.

#define ETBR_DEPTH 0x04

Definition at line 128 of file coresight.h.

#define ETBR_FORMATTERCTRL 0x304

Definition at line 135 of file coresight.h.

#define ETBR_READADDR 0x14

Definition at line 131 of file coresight.h.

#define ETBR_READMEM 0x10

Definition at line 130 of file coresight.h.

#define ETBR_STATUS 0x0c

Definition at line 129 of file coresight.h.

#define ETBR_TRIGGERCOUNT 0x1c

Definition at line 133 of file coresight.h.

#define ETBR_WRITEADDR 0x18

Definition at line 132 of file coresight.h.

#define etm_lock ( t ) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)

Definition at line 148 of file coresight.h.

#define etm_progbit ( t ) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)

Definition at line 108 of file coresight.h.

#define etm_readl	(	t,
		x
	)	(__raw_readl((t)->etm_regs + (x)))

Definition at line 28 of file coresight.h.

#define etm_started ( t ) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)

Definition at line 109 of file coresight.h.

#define etm_triggered ( t ) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER)

Definition at line 110 of file coresight.h.

#define etm_unlock ( t ) do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)

Definition at line 149 of file coresight.h.

#define etm_writel	(	t,
		v,
		x
	)	(__raw_writel((v), (t)->etm_regs + (x)))

Definition at line 26 of file coresight.h.

#define ETMAAT_ARM (3 << 3)

Definition at line 81 of file coresight.h.

#define ETMAAT_DLOAD 5

Definition at line 76 of file coresight.h.

#define ETMAAT_DLOADSTORE 4

Definition at line 75 of file coresight.h.

#define ETMAAT_DSTORE 6

Definition at line 77 of file coresight.h.

#define ETMAAT_EXACTMATCH (1 << 7)

Definition at line 87 of file coresight.h.

#define ETMAAT_IEXEC 1

Definition at line 72 of file coresight.h.

#define ETMAAT_IEXECFAIL 3

Definition at line 74 of file coresight.h.

#define ETMAAT_IEXECPASS 2

Definition at line 73 of file coresight.h.

#define ETMAAT_IFETCH 0

Definition at line 71 of file coresight.h.

#define ETMAAT_IGNCONTEXTID (0 << 8)

Definition at line 89 of file coresight.h.

#define ETMAAT_IGNSECURITY (0 << 10)

Definition at line 94 of file coresight.h.

#define ETMAAT_JAVA (0 << 3)

Definition at line 79 of file coresight.h.

#define ETMAAT_NOVALCMP (0 << 5)

Definition at line 83 of file coresight.h.

#define ETMAAT_NSONLY (1 << 10)

Definition at line 95 of file coresight.h.

#define ETMAAT_SONLY (2 << 10)

Definition at line 96 of file coresight.h.

#define ETMAAT_THUMB (1 << 3)

Definition at line 80 of file coresight.h.

#define ETMAAT_VALMATCH (1 << 5)

Definition at line 84 of file coresight.h.

#define ETMAAT_VALNOMATCH (3 << 5)

Definition at line 85 of file coresight.h.

#define ETMAAT_VALUE1 (1 << 8)

Definition at line 90 of file coresight.h.

#define ETMAAT_VALUE2 (2 << 8)

Definition at line 91 of file coresight.h.

#define ETMAAT_VALUE3 (3 << 8)

Definition at line 92 of file coresight.h.

#define ETMCTRL_BRANCH_OUTPUT (1 << 8)

Definition at line 56 of file coresight.h.

#define ETMCTRL_CYCLEACCURATE (1 << 12)

Definition at line 57 of file coresight.h.

#define ETMCTRL_DATA_DO_ADDR (1 << 3)

Definition at line 54 of file coresight.h.

#define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)

Definition at line 55 of file coresight.h.

#define ETMCTRL_DATA_DO_DATA (1 << 2)

Definition at line 53 of file coresight.h.

#define ETMCTRL_DATAMASK (3 << 2)

Definition at line 52 of file coresight.h.

#define ETMCTRL_DO_CONTEXTID (3 << 14)

Definition at line 46 of file coresight.h.

#define ETMCTRL_DO_CPRT (1 << 1)

Definition at line 51 of file coresight.h.

#define ETMCTRL_OPTS

Value:

(ETMCTRL_DO_CPRT | \
                ETMCTRL_DATA_DO_ADDR | \
                ETMCTRL_BRANCH_OUTPUT | \
                ETMCTRL_DO_CONTEXTID)

Definition at line 116 of file coresight.h.

#define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)

Definition at line 49 of file coresight.h.

#define ETMCTRL_PORTMASK1 (7 << 4)

Definition at line 47 of file coresight.h.

#define ETMCTRL_PORTMASK2 (1 << 21)

Definition at line 48 of file coresight.h.

#define ETMCTRL_PORTSEL (1 << 11)

Definition at line 45 of file coresight.h.

#define ETMCTRL_PORTSIZE ( x ) ((((x) & 7) << 4) | (!!((x) & 8)) << 21)

Definition at line 50 of file coresight.h.

#define ETMCTRL_POWERDOWN 1

Definition at line 43 of file coresight.h.

#define ETMCTRL_PROGRAM (1 << 10)

Definition at line 44 of file coresight.h.

#define ETMMR_OSLAR 0x300

Definition at line 122 of file coresight.h.

#define ETMMR_OSLSR 0x304

Definition at line 123 of file coresight.h.

#define ETMMR_OSSRR 0x308

Definition at line 124 of file coresight.h.

#define ETMMR_PDSR 0x314

Definition at line 125 of file coresight.h.

#define ETMR_COMP_ACC_TYPE ( x ) (0x80 + (x) * 4)

Definition at line 99 of file coresight.h.

#define ETMR_COMP_VAL ( x ) (0x40 + (x) * 4)

Definition at line 98 of file coresight.h.

#define ETMR_CONFCODE (0x04)

Definition at line 60 of file coresight.h.

#define ETMR_CTRL 0

Definition at line 42 of file coresight.h.

#define ETMR_STATUS (0x10)

Definition at line 102 of file coresight.h.

#define ETMR_TRACEENCTRL 0x24

Definition at line 113 of file coresight.h.

#define ETMR_TRACEENCTRL2 0x1c

Definition at line 112 of file coresight.h.

#define ETMR_TRACEENEVT 0x20

Definition at line 115 of file coresight.h.

#define ETMR_TRACESSCTRL (0x18)

Definition at line 63 of file coresight.h.

#define ETMR_TRIGEVT (0x08)

Definition at line 66 of file coresight.h.

#define ETMST_OVERFLOW BIT(0)

Definition at line 103 of file coresight.h.

#define ETMST_PROGBIT BIT(1)

Definition at line 104 of file coresight.h.

#define ETMST_STARTSTOP BIT(2)

Definition at line 105 of file coresight.h.

#define ETMST_TRIGGER BIT(3)

Definition at line 106 of file coresight.h.

#define ETMTE_INCLEXCL BIT(24)

Definition at line 114 of file coresight.h.

#define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT)

Definition at line 20 of file coresight.h.

#define TRACER_ACCESSED_BIT 0

Definition at line 17 of file coresight.h.

#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)

Definition at line 22 of file coresight.h.

#define TRACER_CYCLE_ACC_BIT 2

Definition at line 19 of file coresight.h.

#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)

Definition at line 21 of file coresight.h.

#define TRACER_RUNNING_BIT 1

Definition at line 18 of file coresight.h.

#define TRACER_TIMEOUT 10000

Definition at line 24 of file coresight.h.

#define UNLOCK_MAGIC 0xc5acce55

Definition at line 39 of file coresight.h.

Macros

Macro Definition Documentation