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cpm1.h
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1 /*
2  * MPC8xx Communication Processor Module.
3  * Copyright (c) 1997 Dan Malek ([email protected])
4  *
5  * This file contains structures and information for the communication
6  * processor channels. Some CPM control and status is available
7  * through the MPC8xx internal memory map. See immap.h for details.
8  * This file only contains what I need for the moment, not the total
9  * CPM capabilities. I (or someone else) will add definitions as they
10  * are needed. -- Dan
11  *
12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13  * bytes of the DP RAM and relocates the I2C parameter area to the
14  * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15  * or other use.
16  */
17 #ifndef __CPM1__
18 #define __CPM1__
19 
20 #include <linux/init.h>
21 #include <asm/8xx_immap.h>
22 #include <asm/ptrace.h>
23 #include <asm/cpm.h>
24 
25 /* CPM Command register.
26 */
27 #define CPM_CR_RST ((ushort)0x8000)
28 #define CPM_CR_OPCODE ((ushort)0x0f00)
29 #define CPM_CR_CHAN ((ushort)0x00f0)
30 #define CPM_CR_FLG ((ushort)0x0001)
31 
32 /* Channel numbers.
33 */
34 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
35 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
36 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
37 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
38 #define CPM_CR_CH_TIMER CPM_CR_CH_SPI
39 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
40 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
41 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
42 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
43 
44 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
45 
46 /* Export the base address of the communication processor registers
47  * and dual port ram.
48  */
49 extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
50 
51 #define cpm_dpalloc cpm_muram_alloc
52 #define cpm_dpfree cpm_muram_free
53 #define cpm_dpram_addr cpm_muram_addr
54 #define cpm_dpram_phys cpm_muram_dma
55 
56 extern void cpm_setbrg(uint brg, uint rate);
57 
58 extern void __init cpm_load_patch(cpm8xx_t *cp);
59 
60 extern void cpm_reset(void);
61 
62 /* Parameter RAM offsets.
63 */
64 #define PROFF_SCC1 ((uint)0x0000)
65 #define PROFF_IIC ((uint)0x0080)
66 #define PROFF_SCC2 ((uint)0x0100)
67 #define PROFF_SPI ((uint)0x0180)
68 #define PROFF_SCC3 ((uint)0x0200)
69 #define PROFF_SMC1 ((uint)0x0280)
70 #define PROFF_SCC4 ((uint)0x0300)
71 #define PROFF_SMC2 ((uint)0x0380)
72 
73 /* Define enough so I can at least use the serial port as a UART.
74  * The MBX uses SMC1 as the host serial port.
75  */
76 typedef struct smc_uart {
77  ushort smc_rbase; /* Rx Buffer descriptor base address */
78  ushort smc_tbase; /* Tx Buffer descriptor base address */
79  u_char smc_rfcr; /* Rx function code */
80  u_char smc_tfcr; /* Tx function code */
81  ushort smc_mrblr; /* Max receive buffer length */
82  uint smc_rstate; /* Internal */
83  uint smc_idp; /* Internal */
84  ushort smc_rbptr; /* Internal */
85  ushort smc_ibc; /* Internal */
86  uint smc_rxtmp; /* Internal */
87  uint smc_tstate; /* Internal */
88  uint smc_tdp; /* Internal */
89  ushort smc_tbptr; /* Internal */
90  ushort smc_tbc; /* Internal */
91  uint smc_txtmp; /* Internal */
92  ushort smc_maxidl; /* Maximum idle characters */
93  ushort smc_tmpidl; /* Temporary idle counter */
94  ushort smc_brklen; /* Last received break length */
95  ushort smc_brkec; /* rcv'd break condition counter */
96  ushort smc_brkcr; /* xmt break count register */
97  ushort smc_rmask; /* Temporary bit mask */
98  char res1[8]; /* Reserved */
99  ushort smc_rpbase; /* Relocation pointer */
100 } smc_uart_t;
101 
102 /* Function code bits.
103 */
104 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
105 
106 /* SMC uart mode register.
107 */
108 #define SMCMR_REN ((ushort)0x0001)
109 #define SMCMR_TEN ((ushort)0x0002)
110 #define SMCMR_DM ((ushort)0x000c)
111 #define SMCMR_SM_GCI ((ushort)0x0000)
112 #define SMCMR_SM_UART ((ushort)0x0020)
113 #define SMCMR_SM_TRANS ((ushort)0x0030)
114 #define SMCMR_SM_MASK ((ushort)0x0030)
115 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
116 #define SMCMR_REVD SMCMR_PM_EVEN
117 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
118 #define SMCMR_BS SMCMR_PEN
119 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
120 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
121 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
122 
123 /* SMC2 as Centronics parallel printer. It is half duplex, in that
124  * it can only receive or transmit. The parameter ram values for
125  * each direction are either unique or properly overlap, so we can
126  * include them in one structure.
127  */
128 typedef struct smc_centronics {
129  ushort scent_rbase;
130  ushort scent_tbase;
131  u_char scent_cfcr;
132  u_char scent_smask;
133  ushort scent_mrblr;
134  uint scent_rstate;
135  uint scent_r_ptr;
136  ushort scent_rbptr;
137  ushort scent_r_cnt;
138  uint scent_rtemp;
139  uint scent_tstate;
140  uint scent_t_ptr;
141  ushort scent_tbptr;
142  ushort scent_t_cnt;
143  uint scent_ttemp;
144  ushort scent_max_sl;
145  ushort scent_sl_cnt;
146  ushort scent_character1;
147  ushort scent_character2;
148  ushort scent_character3;
149  ushort scent_character4;
150  ushort scent_character5;
151  ushort scent_character6;
152  ushort scent_character7;
153  ushort scent_character8;
154  ushort scent_rccm;
155  ushort scent_rccr;
156 } smc_cent_t;
157 
158 /* Centronics Status Mask Register.
159 */
160 #define SMC_CENT_F ((u_char)0x08)
161 #define SMC_CENT_PE ((u_char)0x04)
162 #define SMC_CENT_S ((u_char)0x02)
163 
164 /* SMC Event and Mask register.
165 */
166 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
167 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
168 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
169 #define SMCM_BSY ((unsigned char)0x04)
170 #define SMCM_TX ((unsigned char)0x02)
171 #define SMCM_RX ((unsigned char)0x01)
172 
173 /* Baud rate generators.
174 */
175 #define CPM_BRG_RST ((uint)0x00020000)
176 #define CPM_BRG_EN ((uint)0x00010000)
177 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
178 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
179 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
180 #define CPM_BRG_ATB ((uint)0x00002000)
181 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
182 #define CPM_BRG_DIV16 ((uint)0x00000001)
183 
184 /* SI Clock Route Register
185 */
186 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
187 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
188 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
189 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
190 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
191 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
192 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
193 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
194 
195 /* SCCs.
196 */
197 #define SCC_GSMRH_IRP ((uint)0x00040000)
198 #define SCC_GSMRH_GDE ((uint)0x00010000)
199 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
200 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
201 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
202 #define SCC_GSMRH_REVD ((uint)0x00002000)
203 #define SCC_GSMRH_TRX ((uint)0x00001000)
204 #define SCC_GSMRH_TTX ((uint)0x00000800)
205 #define SCC_GSMRH_CDP ((uint)0x00000400)
206 #define SCC_GSMRH_CTSP ((uint)0x00000200)
207 #define SCC_GSMRH_CDS ((uint)0x00000100)
208 #define SCC_GSMRH_CTSS ((uint)0x00000080)
209 #define SCC_GSMRH_TFL ((uint)0x00000040)
210 #define SCC_GSMRH_RFW ((uint)0x00000020)
211 #define SCC_GSMRH_TXSY ((uint)0x00000010)
212 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
213 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
214 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
215 #define SCC_GSMRH_RTSM ((uint)0x00000002)
216 #define SCC_GSMRH_RSYN ((uint)0x00000001)
217 
218 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
219 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
220 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
221 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
222 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
223 #define SCC_GSMRL_TCI ((uint)0x10000000)
224 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
225 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
226 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
227 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
228 #define SCC_GSMRL_RINV ((uint)0x02000000)
229 #define SCC_GSMRL_TINV ((uint)0x01000000)
230 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
231 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
232 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
233 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
234 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
235 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
236 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
237 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
238 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
239 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
240 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
241 #define SCC_GSMRL_TEND ((uint)0x00040000)
242 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
243 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
244 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
245 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
246 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
247 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
248 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
249 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
250 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
251 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
252 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
253 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
254 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
255 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
256 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
257 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
258 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
259 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
260 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
261 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
262 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
263 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
264 #define SCC_GSMRL_ENR ((uint)0x00000020)
265 #define SCC_GSMRL_ENT ((uint)0x00000010)
266 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
267 #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
268 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
269 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
270 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
271 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
272 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
273 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
274 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
275 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
276 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
277 
278 #define SCC_TODR_TOD ((ushort)0x8000)
279 
280 /* SCC Event and Mask register.
281 */
282 #define SCCM_TXE ((unsigned char)0x10)
283 #define SCCM_BSY ((unsigned char)0x04)
284 #define SCCM_TX ((unsigned char)0x02)
285 #define SCCM_RX ((unsigned char)0x01)
286 
287 typedef struct scc_param {
288  ushort scc_rbase; /* Rx Buffer descriptor base address */
289  ushort scc_tbase; /* Tx Buffer descriptor base address */
290  u_char scc_rfcr; /* Rx function code */
291  u_char scc_tfcr; /* Tx function code */
292  ushort scc_mrblr; /* Max receive buffer length */
293  uint scc_rstate; /* Internal */
294  uint scc_idp; /* Internal */
295  ushort scc_rbptr; /* Internal */
296  ushort scc_ibc; /* Internal */
297  uint scc_rxtmp; /* Internal */
298  uint scc_tstate; /* Internal */
299  uint scc_tdp; /* Internal */
300  ushort scc_tbptr; /* Internal */
301  ushort scc_tbc; /* Internal */
302  uint scc_txtmp; /* Internal */
303  uint scc_rcrc; /* Internal */
304  uint scc_tcrc; /* Internal */
305 } sccp_t;
306 
307 /* Function code bits.
308 */
309 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
310 
311 /* CPM Ethernet through SCCx.
312  */
313 typedef struct scc_enet {
314  sccp_t sen_genscc;
315  uint sen_cpres; /* Preset CRC */
316  uint sen_cmask; /* Constant mask for CRC */
317  uint sen_crcec; /* CRC Error counter */
318  uint sen_alec; /* alignment error counter */
319  uint sen_disfc; /* discard frame counter */
320  ushort sen_pads; /* Tx short frame pad character */
321  ushort sen_retlim; /* Retry limit threshold */
322  ushort sen_retcnt; /* Retry limit counter */
323  ushort sen_maxflr; /* maximum frame length register */
324  ushort sen_minflr; /* minimum frame length register */
325  ushort sen_maxd1; /* maximum DMA1 length */
326  ushort sen_maxd2; /* maximum DMA2 length */
327  ushort sen_maxd; /* Rx max DMA */
328  ushort sen_dmacnt; /* Rx DMA counter */
329  ushort sen_maxb; /* Max BD byte count */
330  ushort sen_gaddr1; /* Group address filter */
331  ushort sen_gaddr2;
332  ushort sen_gaddr3;
333  ushort sen_gaddr4;
334  uint sen_tbuf0data0; /* Save area 0 - current frame */
335  uint sen_tbuf0data1; /* Save area 1 - current frame */
336  uint sen_tbuf0rba; /* Internal */
337  uint sen_tbuf0crc; /* Internal */
338  ushort sen_tbuf0bcnt; /* Internal */
339  ushort sen_paddrh; /* physical address (MSB) */
340  ushort sen_paddrm;
341  ushort sen_paddrl; /* physical address (LSB) */
342  ushort sen_pper; /* persistence */
343  ushort sen_rfbdptr; /* Rx first BD pointer */
344  ushort sen_tfbdptr; /* Tx first BD pointer */
345  ushort sen_tlbdptr; /* Tx last BD pointer */
346  uint sen_tbuf1data0; /* Save area 0 - current frame */
347  uint sen_tbuf1data1; /* Save area 1 - current frame */
348  uint sen_tbuf1rba; /* Internal */
349  uint sen_tbuf1crc; /* Internal */
350  ushort sen_tbuf1bcnt; /* Internal */
351  ushort sen_txlen; /* Tx Frame length counter */
352  ushort sen_iaddr1; /* Individual address filter */
353  ushort sen_iaddr2;
354  ushort sen_iaddr3;
355  ushort sen_iaddr4;
356  ushort sen_boffcnt; /* Backoff counter */
357 
358  /* NOTE: Some versions of the manual have the following items
359  * incorrectly documented. Below is the proper order.
360  */
361  ushort sen_taddrh; /* temp address (MSB) */
362  ushort sen_taddrm;
363  ushort sen_taddrl; /* temp address (LSB) */
364 } scc_enet_t;
365 
366 /* SCC Event register as used by Ethernet.
367 */
368 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
369 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
370 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
371 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
372 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
373 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
374 
375 /* SCC Mode Register (PMSR) as used by Ethernet.
376 */
377 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
378 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
379 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
380 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
381 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
382 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
383 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
384 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
385 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
386 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
387 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
388 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
389 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
390 
391 /* SCC as UART
392 */
393 typedef struct scc_uart {
394  sccp_t scc_genscc;
395  char res1[8]; /* Reserved */
396  ushort scc_maxidl; /* Maximum idle chars */
397  ushort scc_idlc; /* temp idle counter */
398  ushort scc_brkcr; /* Break count register */
399  ushort scc_parec; /* receive parity error counter */
400  ushort scc_frmec; /* receive framing error counter */
401  ushort scc_nosec; /* receive noise counter */
402  ushort scc_brkec; /* receive break condition counter */
403  ushort scc_brkln; /* last received break length */
404  ushort scc_uaddr1; /* UART address character 1 */
405  ushort scc_uaddr2; /* UART address character 2 */
406  ushort scc_rtemp; /* Temp storage */
407  ushort scc_toseq; /* Transmit out of sequence char */
408  ushort scc_char1; /* control character 1 */
409  ushort scc_char2; /* control character 2 */
410  ushort scc_char3; /* control character 3 */
411  ushort scc_char4; /* control character 4 */
412  ushort scc_char5; /* control character 5 */
413  ushort scc_char6; /* control character 6 */
414  ushort scc_char7; /* control character 7 */
415  ushort scc_char8; /* control character 8 */
416  ushort scc_rccm; /* receive control character mask */
417  ushort scc_rccr; /* receive control character register */
418  ushort scc_rlbc; /* receive last break character */
419 } scc_uart_t;
420 
421 /* SCC Event and Mask registers when it is used as a UART.
422 */
423 #define UART_SCCM_GLR ((ushort)0x1000)
424 #define UART_SCCM_GLT ((ushort)0x0800)
425 #define UART_SCCM_AB ((ushort)0x0200)
426 #define UART_SCCM_IDL ((ushort)0x0100)
427 #define UART_SCCM_GRA ((ushort)0x0080)
428 #define UART_SCCM_BRKE ((ushort)0x0040)
429 #define UART_SCCM_BRKS ((ushort)0x0020)
430 #define UART_SCCM_CCR ((ushort)0x0008)
431 #define UART_SCCM_BSY ((ushort)0x0004)
432 #define UART_SCCM_TX ((ushort)0x0002)
433 #define UART_SCCM_RX ((ushort)0x0001)
434 
435 /* The SCC PMSR when used as a UART.
436 */
437 #define SCU_PSMR_FLC ((ushort)0x8000)
438 #define SCU_PSMR_SL ((ushort)0x4000)
439 #define SCU_PSMR_CL ((ushort)0x3000)
440 #define SCU_PSMR_UM ((ushort)0x0c00)
441 #define SCU_PSMR_FRZ ((ushort)0x0200)
442 #define SCU_PSMR_RZS ((ushort)0x0100)
443 #define SCU_PSMR_SYN ((ushort)0x0080)
444 #define SCU_PSMR_DRT ((ushort)0x0040)
445 #define SCU_PSMR_PEN ((ushort)0x0010)
446 #define SCU_PSMR_RPM ((ushort)0x000c)
447 #define SCU_PSMR_REVP ((ushort)0x0008)
448 #define SCU_PSMR_TPM ((ushort)0x0003)
449 #define SCU_PSMR_TEVP ((ushort)0x0002)
450 
451 /* CPM Transparent mode SCC.
452  */
453 typedef struct scc_trans {
454  sccp_t st_genscc;
455  uint st_cpres; /* Preset CRC */
456  uint st_cmask; /* Constant mask for CRC */
457 } scc_trans_t;
458 
459 /* IIC parameter RAM.
460 */
461 typedef struct iic {
462  ushort iic_rbase; /* Rx Buffer descriptor base address */
463  ushort iic_tbase; /* Tx Buffer descriptor base address */
464  u_char iic_rfcr; /* Rx function code */
465  u_char iic_tfcr; /* Tx function code */
466  ushort iic_mrblr; /* Max receive buffer length */
467  uint iic_rstate; /* Internal */
468  uint iic_rdp; /* Internal */
469  ushort iic_rbptr; /* Internal */
470  ushort iic_rbc; /* Internal */
471  uint iic_rxtmp; /* Internal */
472  uint iic_tstate; /* Internal */
473  uint iic_tdp; /* Internal */
474  ushort iic_tbptr; /* Internal */
475  ushort iic_tbc; /* Internal */
476  uint iic_txtmp; /* Internal */
477  char res1[4]; /* Reserved */
478  ushort iic_rpbase; /* Relocation pointer */
479  char res2[2]; /* Reserved */
480 } iic_t;
481 
482 /*
483  * RISC Controller Configuration Register definitons
484  */
485 #define RCCR_TIME 0x8000 /* RISC Timer Enable */
486 #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
487 #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
488 
489 /* RISC Timer Parameter RAM offset */
490 #define PROFF_RTMR ((uint)0x01B0)
491 
492 typedef struct risc_timer_pram {
493  unsigned short tm_base; /* RISC Timer Table Base Address */
494  unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
495  unsigned short r_tmr; /* RISC Timer Mode Register */
496  unsigned short r_tmv; /* RISC Timer Valid Register */
497  unsigned long tm_cmd; /* RISC Timer Command Register */
498  unsigned long tm_cnt; /* RISC Timer Internal Count */
499 } rt_pram_t;
500 
501 /* Bits in RISC Timer Command Register */
502 #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
503 #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
504 #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
505 #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
506 #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
507 
508 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
509  * channels or devices. All of these are presented to the PPC core
510  * as a single interrupt. The CPM interrupt handler dispatches its
511  * own handlers, in a similar fashion to the PPC core handler. We
512  * use the table as defined in the manuals (i.e. no special high
513  * priority and SCC1 == SCCa, etc...).
514  */
515 #define CPMVEC_NR 32
516 #define CPMVEC_PIO_PC15 ((ushort)0x1f)
517 #define CPMVEC_SCC1 ((ushort)0x1e)
518 #define CPMVEC_SCC2 ((ushort)0x1d)
519 #define CPMVEC_SCC3 ((ushort)0x1c)
520 #define CPMVEC_SCC4 ((ushort)0x1b)
521 #define CPMVEC_PIO_PC14 ((ushort)0x1a)
522 #define CPMVEC_TIMER1 ((ushort)0x19)
523 #define CPMVEC_PIO_PC13 ((ushort)0x18)
524 #define CPMVEC_PIO_PC12 ((ushort)0x17)
525 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
526 #define CPMVEC_IDMA1 ((ushort)0x15)
527 #define CPMVEC_IDMA2 ((ushort)0x14)
528 #define CPMVEC_TIMER2 ((ushort)0x12)
529 #define CPMVEC_RISCTIMER ((ushort)0x11)
530 #define CPMVEC_I2C ((ushort)0x10)
531 #define CPMVEC_PIO_PC11 ((ushort)0x0f)
532 #define CPMVEC_PIO_PC10 ((ushort)0x0e)
533 #define CPMVEC_TIMER3 ((ushort)0x0c)
534 #define CPMVEC_PIO_PC9 ((ushort)0x0b)
535 #define CPMVEC_PIO_PC8 ((ushort)0x0a)
536 #define CPMVEC_PIO_PC7 ((ushort)0x09)
537 #define CPMVEC_TIMER4 ((ushort)0x07)
538 #define CPMVEC_PIO_PC6 ((ushort)0x06)
539 #define CPMVEC_SPI ((ushort)0x05)
540 #define CPMVEC_SMC1 ((ushort)0x04)
541 #define CPMVEC_SMC2 ((ushort)0x03)
542 #define CPMVEC_PIO_PC5 ((ushort)0x02)
543 #define CPMVEC_PIO_PC4 ((ushort)0x01)
544 #define CPMVEC_ERROR ((ushort)0x00)
545 
546 /* CPM interrupt configuration vector.
547 */
548 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
549 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
550 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
551 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
552 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
553 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
554 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
555 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
556 
557 #define CPM_PIN_INPUT 0
558 #define CPM_PIN_OUTPUT 1
559 #define CPM_PIN_PRIMARY 0
560 #define CPM_PIN_SECONDARY 2
561 #define CPM_PIN_GPIO 4
562 #define CPM_PIN_OPENDRAIN 8
563 
564 enum cpm_port {
565  CPM_PORTA,
566  CPM_PORTB,
567  CPM_PORTC,
568  CPM_PORTD,
569  CPM_PORTE,
570 };
571 
572 void cpm1_set_pin(enum cpm_port port, int pin, int flags);
573 
574 enum cpm_clk_dir {
575  CPM_CLK_RX,
576  CPM_CLK_TX,
577  CPM_CLK_RTX
578 };
579 
580 enum cpm_clk_target {
581  CPM_CLK_SCC1,
582  CPM_CLK_SCC2,
583  CPM_CLK_SCC3,
584  CPM_CLK_SCC4,
585  CPM_CLK_SMC1,
586  CPM_CLK_SMC2,
587 };
588 
589 enum cpm_clk {
590  CPM_BRG1, /* Baud Rate Generator 1 */
591  CPM_BRG2, /* Baud Rate Generator 2 */
592  CPM_BRG3, /* Baud Rate Generator 3 */
593  CPM_BRG4, /* Baud Rate Generator 4 */
594  CPM_CLK1, /* Clock 1 */
595  CPM_CLK2, /* Clock 2 */
596  CPM_CLK3, /* Clock 3 */
597  CPM_CLK4, /* Clock 4 */
598  CPM_CLK5, /* Clock 5 */
599  CPM_CLK6, /* Clock 6 */
600  CPM_CLK7, /* Clock 7 */
601  CPM_CLK8, /* Clock 8 */
602 };
603 
604 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
605 
606 #endif /* __CPM1__ */
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