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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | smc_uart |
| struct | smc_centronics |
| struct | scc_param |
| struct | scc_enet |
| struct | scc_uart |
| struct | scc_trans |
| struct | iic |
| struct | risc_timer_pram |
Macros | |
| #define | CPM_CR_RST ((ushort)0x8000) |
| #define | CPM_CR_OPCODE ((ushort)0x0f00) |
| #define | CPM_CR_CHAN ((ushort)0x00f0) |
| #define | CPM_CR_FLG ((ushort)0x0001) |
| #define | CPM_CR_CH_SCC1 ((ushort)0x0000) |
| #define | CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ |
| #define | CPM_CR_CH_SCC2 ((ushort)0x0004) |
| #define | CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ |
| #define | CPM_CR_CH_TIMER CPM_CR_CH_SPI |
| #define | CPM_CR_CH_SCC3 ((ushort)0x0008) |
| #define | CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ |
| #define | CPM_CR_CH_SCC4 ((ushort)0x000c) |
| #define | CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ |
| #define | mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) |
| #define | cpm_dpalloc cpm_muram_alloc |
| #define | cpm_dpfree cpm_muram_free |
| #define | cpm_dpram_addr cpm_muram_addr |
| #define | cpm_dpram_phys cpm_muram_dma |
| #define | PROFF_SCC1 ((uint)0x0000) |
| #define | PROFF_IIC ((uint)0x0080) |
| #define | PROFF_SCC2 ((uint)0x0100) |
| #define | PROFF_SPI ((uint)0x0180) |
| #define | PROFF_SCC3 ((uint)0x0200) |
| #define | PROFF_SMC1 ((uint)0x0280) |
| #define | PROFF_SCC4 ((uint)0x0300) |
| #define | PROFF_SMC2 ((uint)0x0380) |
| #define | SMC_EB ((u_char)0x10) /* Set big endian byte order */ |
| #define | SMCMR_REN ((ushort)0x0001) |
| #define | SMCMR_TEN ((ushort)0x0002) |
| #define | SMCMR_DM ((ushort)0x000c) |
| #define | SMCMR_SM_GCI ((ushort)0x0000) |
| #define | SMCMR_SM_UART ((ushort)0x0020) |
| #define | SMCMR_SM_TRANS ((ushort)0x0030) |
| #define | SMCMR_SM_MASK ((ushort)0x0030) |
| #define | SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ |
| #define | SMCMR_REVD SMCMR_PM_EVEN |
| #define | SMCMR_PEN ((ushort)0x0200) /* Parity enable */ |
| #define | SMCMR_BS SMCMR_PEN |
| #define | SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ |
| #define | SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ |
| #define | smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) |
| #define | SMC_CENT_F ((u_char)0x08) |
| #define | SMC_CENT_PE ((u_char)0x04) |
| #define | SMC_CENT_S ((u_char)0x02) |
| #define | SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ |
| #define | SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ |
| #define | SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ |
| #define | SMCM_BSY ((unsigned char)0x04) |
| #define | SMCM_TX ((unsigned char)0x02) |
| #define | SMCM_RX ((unsigned char)0x01) |
| #define | CPM_BRG_RST ((uint)0x00020000) |
| #define | CPM_BRG_EN ((uint)0x00010000) |
| #define | CPM_BRG_EXTC_INT ((uint)0x00000000) |
| #define | CPM_BRG_EXTC_CLK2 ((uint)0x00004000) |
| #define | CPM_BRG_EXTC_CLK6 ((uint)0x00008000) |
| #define | CPM_BRG_ATB ((uint)0x00002000) |
| #define | CPM_BRG_CD_MASK ((uint)0x00001ffe) |
| #define | CPM_BRG_DIV16 ((uint)0x00000001) |
| #define | SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) |
| #define | SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) |
| #define | SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) |
| #define | SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) |
| #define | SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) |
| #define | SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) |
| #define | SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) |
| #define | SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) |
| #define | SCC_GSMRH_IRP ((uint)0x00040000) |
| #define | SCC_GSMRH_GDE ((uint)0x00010000) |
| #define | SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) |
| #define | SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) |
| #define | SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) |
| #define | SCC_GSMRH_REVD ((uint)0x00002000) |
| #define | SCC_GSMRH_TRX ((uint)0x00001000) |
| #define | SCC_GSMRH_TTX ((uint)0x00000800) |
| #define | SCC_GSMRH_CDP ((uint)0x00000400) |
| #define | SCC_GSMRH_CTSP ((uint)0x00000200) |
| #define | SCC_GSMRH_CDS ((uint)0x00000100) |
| #define | SCC_GSMRH_CTSS ((uint)0x00000080) |
| #define | SCC_GSMRH_TFL ((uint)0x00000040) |
| #define | SCC_GSMRH_RFW ((uint)0x00000020) |
| #define | SCC_GSMRH_TXSY ((uint)0x00000010) |
| #define | SCC_GSMRH_SYNL16 ((uint)0x0000000c) |
| #define | SCC_GSMRH_SYNL8 ((uint)0x00000008) |
| #define | SCC_GSMRH_SYNL4 ((uint)0x00000004) |
| #define | SCC_GSMRH_RTSM ((uint)0x00000002) |
| #define | SCC_GSMRH_RSYN ((uint)0x00000001) |
| #define | SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ |
| #define | SCC_GSMRL_EDGE_NONE ((uint)0x60000000) |
| #define | SCC_GSMRL_EDGE_NEG ((uint)0x40000000) |
| #define | SCC_GSMRL_EDGE_POS ((uint)0x20000000) |
| #define | SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) |
| #define | SCC_GSMRL_TCI ((uint)0x10000000) |
| #define | SCC_GSMRL_TSNC_3 ((uint)0x0c000000) |
| #define | SCC_GSMRL_TSNC_4 ((uint)0x08000000) |
| #define | SCC_GSMRL_TSNC_14 ((uint)0x04000000) |
| #define | SCC_GSMRL_TSNC_INF ((uint)0x00000000) |
| #define | SCC_GSMRL_RINV ((uint)0x02000000) |
| #define | SCC_GSMRL_TINV ((uint)0x01000000) |
| #define | SCC_GSMRL_TPL_128 ((uint)0x00c00000) |
| #define | SCC_GSMRL_TPL_64 ((uint)0x00a00000) |
| #define | SCC_GSMRL_TPL_48 ((uint)0x00800000) |
| #define | SCC_GSMRL_TPL_32 ((uint)0x00600000) |
| #define | SCC_GSMRL_TPL_16 ((uint)0x00400000) |
| #define | SCC_GSMRL_TPL_8 ((uint)0x00200000) |
| #define | SCC_GSMRL_TPL_NONE ((uint)0x00000000) |
| #define | SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) |
| #define | SCC_GSMRL_TPP_01 ((uint)0x00100000) |
| #define | SCC_GSMRL_TPP_10 ((uint)0x00080000) |
| #define | SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) |
| #define | SCC_GSMRL_TEND ((uint)0x00040000) |
| #define | SCC_GSMRL_TDCR_32 ((uint)0x00030000) |
| #define | SCC_GSMRL_TDCR_16 ((uint)0x00020000) |
| #define | SCC_GSMRL_TDCR_8 ((uint)0x00010000) |
| #define | SCC_GSMRL_TDCR_1 ((uint)0x00000000) |
| #define | SCC_GSMRL_RDCR_32 ((uint)0x0000c000) |
| #define | SCC_GSMRL_RDCR_16 ((uint)0x00008000) |
| #define | SCC_GSMRL_RDCR_8 ((uint)0x00004000) |
| #define | SCC_GSMRL_RDCR_1 ((uint)0x00000000) |
| #define | SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) |
| #define | SCC_GSMRL_RENC_MANCH ((uint)0x00002000) |
| #define | SCC_GSMRL_RENC_FM0 ((uint)0x00001000) |
| #define | SCC_GSMRL_RENC_NRZI ((uint)0x00000800) |
| #define | SCC_GSMRL_RENC_NRZ ((uint)0x00000000) |
| #define | SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) |
| #define | SCC_GSMRL_TENC_MANCH ((uint)0x00000400) |
| #define | SCC_GSMRL_TENC_FM0 ((uint)0x00000200) |
| #define | SCC_GSMRL_TENC_NRZI ((uint)0x00000100) |
| #define | SCC_GSMRL_TENC_NRZ ((uint)0x00000000) |
| #define | SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ |
| #define | SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) |
| #define | SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) |
| #define | SCC_GSMRL_DIAG_NORM ((uint)0x00000000) |
| #define | SCC_GSMRL_ENR ((uint)0x00000020) |
| #define | SCC_GSMRL_ENT ((uint)0x00000010) |
| #define | SCC_GSMRL_MODE_ENET ((uint)0x0000000c) |
| #define | SCC_GSMRL_MODE_QMC ((uint)0x0000000a) |
| #define | SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) |
| #define | SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) |
| #define | SCC_GSMRL_MODE_V14 ((uint)0x00000007) |
| #define | SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) |
| #define | SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) |
| #define | SCC_GSMRL_MODE_UART ((uint)0x00000004) |
| #define | SCC_GSMRL_MODE_SS7 ((uint)0x00000003) |
| #define | SCC_GSMRL_MODE_ATALK ((uint)0x00000002) |
| #define | SCC_GSMRL_MODE_HDLC ((uint)0x00000000) |
| #define | SCC_TODR_TOD ((ushort)0x8000) |
| #define | SCCM_TXE ((unsigned char)0x10) |
| #define | SCCM_BSY ((unsigned char)0x04) |
| #define | SCCM_TX ((unsigned char)0x02) |
| #define | SCCM_RX ((unsigned char)0x01) |
| #define | SCC_EB ((u_char)0x10) /* Set big endian byte order */ |
| #define | SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ |
| #define | SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ |
| #define | SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ |
| #define | SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ |
| #define | SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ |
| #define | SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ |
| #define | SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ |
| #define | SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ |
| #define | SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ |
| #define | SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ |
| #define | SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ |
| #define | SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ |
| #define | SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ |
| #define | SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ |
| #define | SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ |
| #define | SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ |
| #define | SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ |
| #define | SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ |
| #define | SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ |
| #define | UART_SCCM_GLR ((ushort)0x1000) |
| #define | UART_SCCM_GLT ((ushort)0x0800) |
| #define | UART_SCCM_AB ((ushort)0x0200) |
| #define | UART_SCCM_IDL ((ushort)0x0100) |
| #define | UART_SCCM_GRA ((ushort)0x0080) |
| #define | UART_SCCM_BRKE ((ushort)0x0040) |
| #define | UART_SCCM_BRKS ((ushort)0x0020) |
| #define | UART_SCCM_CCR ((ushort)0x0008) |
| #define | UART_SCCM_BSY ((ushort)0x0004) |
| #define | UART_SCCM_TX ((ushort)0x0002) |
| #define | UART_SCCM_RX ((ushort)0x0001) |
| #define | SCU_PSMR_FLC ((ushort)0x8000) |
| #define | SCU_PSMR_SL ((ushort)0x4000) |
| #define | SCU_PSMR_CL ((ushort)0x3000) |
| #define | SCU_PSMR_UM ((ushort)0x0c00) |
| #define | SCU_PSMR_FRZ ((ushort)0x0200) |
| #define | SCU_PSMR_RZS ((ushort)0x0100) |
| #define | SCU_PSMR_SYN ((ushort)0x0080) |
| #define | SCU_PSMR_DRT ((ushort)0x0040) |
| #define | SCU_PSMR_PEN ((ushort)0x0010) |
| #define | SCU_PSMR_RPM ((ushort)0x000c) |
| #define | SCU_PSMR_REVP ((ushort)0x0008) |
| #define | SCU_PSMR_TPM ((ushort)0x0003) |
| #define | SCU_PSMR_TEVP ((ushort)0x0002) |
| #define | RCCR_TIME 0x8000 /* RISC Timer Enable */ |
| #define | RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ |
| #define | RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ |
| #define | PROFF_RTMR ((uint)0x01B0) |
| #define | TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ |
| #define | TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ |
| #define | TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ |
| #define | TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ |
| #define | TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ |
| #define | CPMVEC_NR 32 |
| #define | CPMVEC_PIO_PC15 ((ushort)0x1f) |
| #define | CPMVEC_SCC1 ((ushort)0x1e) |
| #define | CPMVEC_SCC2 ((ushort)0x1d) |
| #define | CPMVEC_SCC3 ((ushort)0x1c) |
| #define | CPMVEC_SCC4 ((ushort)0x1b) |
| #define | CPMVEC_PIO_PC14 ((ushort)0x1a) |
| #define | CPMVEC_TIMER1 ((ushort)0x19) |
| #define | CPMVEC_PIO_PC13 ((ushort)0x18) |
| #define | CPMVEC_PIO_PC12 ((ushort)0x17) |
| #define | CPMVEC_SDMA_CB_ERR ((ushort)0x16) |
| #define | CPMVEC_IDMA1 ((ushort)0x15) |
| #define | CPMVEC_IDMA2 ((ushort)0x14) |
| #define | CPMVEC_TIMER2 ((ushort)0x12) |
| #define | CPMVEC_RISCTIMER ((ushort)0x11) |
| #define | CPMVEC_I2C ((ushort)0x10) |
| #define | CPMVEC_PIO_PC11 ((ushort)0x0f) |
| #define | CPMVEC_PIO_PC10 ((ushort)0x0e) |
| #define | CPMVEC_TIMER3 ((ushort)0x0c) |
| #define | CPMVEC_PIO_PC9 ((ushort)0x0b) |
| #define | CPMVEC_PIO_PC8 ((ushort)0x0a) |
| #define | CPMVEC_PIO_PC7 ((ushort)0x09) |
| #define | CPMVEC_TIMER4 ((ushort)0x07) |
| #define | CPMVEC_PIO_PC6 ((ushort)0x06) |
| #define | CPMVEC_SPI ((ushort)0x05) |
| #define | CPMVEC_SMC1 ((ushort)0x04) |
| #define | CPMVEC_SMC2 ((ushort)0x03) |
| #define | CPMVEC_PIO_PC5 ((ushort)0x02) |
| #define | CPMVEC_PIO_PC4 ((ushort)0x01) |
| #define | CPMVEC_ERROR ((ushort)0x00) |
| #define | CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ |
| #define | CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ |
| #define | CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ |
| #define | CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ |
| #define | CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ |
| #define | CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ |
| #define | CICR_IEN ((uint)0x00000080) /* Int. enable */ |
| #define | CICR_SPS ((uint)0x00000001) /* SCC Spread */ |
| #define | CPM_PIN_INPUT 0 |
| #define | CPM_PIN_OUTPUT 1 |
| #define | CPM_PIN_PRIMARY 0 |
| #define | CPM_PIN_SECONDARY 2 |
| #define | CPM_PIN_GPIO 4 |
| #define | CPM_PIN_OPENDRAIN 8 |
Typedefs | |
| typedef struct smc_uart | smc_uart_t |
| typedef struct smc_centronics | smc_cent_t |
| typedef struct scc_param | sccp_t |
| typedef struct scc_enet | scc_enet_t |
| typedef struct scc_uart | scc_uart_t |
| typedef struct scc_trans | scc_trans_t |
| typedef struct iic | iic_t |
| typedef struct risc_timer_pram | rt_pram_t |
Enumerations | |
| enum | cpm_port { CPM_PORTA, CPM_PORTB, CPM_PORTC, CPM_PORTD, CPM_PORTE } |
| enum | cpm_clk_dir { CPM_CLK_RX, CPM_CLK_TX, CPM_CLK_RTX } |
| enum | cpm_clk_target { CPM_CLK_SCC1, CPM_CLK_SCC2, CPM_CLK_SCC3, CPM_CLK_SCC4, CPM_CLK_SMC1, CPM_CLK_SMC2 } |
| enum | cpm_clk { CPM_BRG1, CPM_BRG2, CPM_BRG3, CPM_BRG4, CPM_CLK1, CPM_CLK2, CPM_CLK3, CPM_CLK4, CPM_CLK5, CPM_CLK6, CPM_CLK7, CPM_CLK8 } |
Functions | |
| void | cpm_setbrg (uint brg, uint rate) |
| void __init | cpm_load_patch (cpm8xx_t *cp) |
| void | cpm_reset (void) |
| void | cpm1_set_pin (enum cpm_port port, int pin, int flags) |
| int | cpm1_clk_setup (enum cpm_clk_target target, int clock, int mode) |
Variables | |
| cpm8xx_t __iomem * | cpmp |
| #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ |
| #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ |
| #define CPM_CR_CH_TIMER CPM_CR_CH_SPI |
| #define cpm_dpalloc cpm_muram_alloc |
| #define cpm_dpfree cpm_muram_free |
| #define cpm_dpram_addr cpm_muram_addr |
| #define cpm_dpram_phys cpm_muram_dma |
| #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ |
| #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ |
| #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ |
| #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ |
| #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ |
| #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ |
| #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ |
| #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ |
| #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ |
| #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ |
| #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ |
| #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ |
| #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ |
| #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ |
| #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ |
| #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ |
| #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ |
| #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ |
| #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ |
| #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ |
| #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ |
| #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ |
| #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ |
| #define SMCMR_REVD SMCMR_PM_EVEN |
| #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ |
| #define smcr_mk_clen | ( | C | ) | (((C) << 11) & SMCR_CLEN_MASK) |
| #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ |
| #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ |
| #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ |
| typedef struct risc_timer_pram rt_pram_t |
| typedef struct scc_enet scc_enet_t |
| typedef struct scc_trans scc_trans_t |
| typedef struct scc_uart scc_uart_t |
| typedef struct smc_centronics smc_cent_t |
| typedef struct smc_uart smc_uart_t |
| enum cpm_clk |
| enum cpm_clk_dir |
| enum cpm_clk_target |
| enum cpm_port |
| int cpm1_clk_setup | ( | enum cpm_clk_target | target, |
| int | clock, | ||
| int | mode | ||
| ) |
Definition at line 625 of file micropatch.c.
1.8.2