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cpu-info.h
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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 Waldorf GMBH
7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8  * Copyright (C) 1996 Paul M. Antoine
9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10  * Copyright (C) 2004 Maciej W. Rozycki
11  */
12 #ifndef __ASM_CPU_INFO_H
13 #define __ASM_CPU_INFO_H
14 
15 #include <linux/types.h>
16 
17 #include <asm/cache.h>
18 
19 /*
20  * Descriptor for a cache
21  */
22 struct cache_desc {
23  unsigned int waysize; /* Bytes per way */
24  unsigned short sets; /* Number of lines per set */
25  unsigned char ways; /* Number of ways */
26  unsigned char linesz; /* Size of line in bytes */
27  unsigned char waybit; /* Bits to select in a cache set */
28  unsigned char flags; /* Flags describing cache properties */
29 };
30 
31 /*
32  * Flag definitions
33  */
34 #define MIPS_CACHE_NOT_PRESENT 0x00000001
35 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
36 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
37 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
38 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
39 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
40 
41 struct cpuinfo_mips {
42  unsigned int udelay_val;
43  unsigned int asid_cache;
44 
45  /*
46  * Capability and feature descriptor structure for MIPS CPU
47  */
48  unsigned long options;
49  unsigned long ases;
50  unsigned int processor_id;
51  unsigned int fpu_id;
52  unsigned int cputype;
53  int isa_level;
54  int tlbsize;
55  struct cache_desc icache; /* Primary I-cache */
56  struct cache_desc dcache; /* Primary D or combined I/D cache */
57  struct cache_desc scache; /* Secondary cache */
58  struct cache_desc tcache; /* Tertiary/split secondary cache */
59  int srsets; /* Shadow register sets */
60  int core; /* physical core number */
61 #ifdef CONFIG_64BIT
62  int vmbits; /* Virtual memory size in bits */
63 #endif
64 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
65  /*
66  * In the MIPS MT "SMTC" model, each TC is considered
67  * to be a "CPU" for the purposes of scheduling, but
68  * exception resources, ASID spaces, etc, are common
69  * to all TCs within the same VPE.
70  */
71  int vpe_id; /* Virtual Processor number */
72 #endif
73 #ifdef CONFIG_MIPS_MT_SMTC
74  int tc_id; /* Thread Context number */
75 #endif
76  void *data; /* Additional data */
77  unsigned int watch_reg_count; /* Number that exist */
78  unsigned int watch_reg_use_cnt; /* Usable by ptrace */
79 #define NUM_WATCH_REGS 4
81  unsigned int kscratch_mask; /* Usable KScratch mask. */
83 
84 extern struct cpuinfo_mips cpu_data[];
85 #define current_cpu_data cpu_data[smp_processor_id()]
86 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
87 
88 extern void cpu_probe(void);
89 extern void cpu_report(void);
90 
91 extern const char *__cpu_name[];
92 #define cpu_name_string() __cpu_name[smp_processor_id()]
93 
94 #endif /* __ASM_CPU_INFO_H */