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12 #ifndef _ASM_S390_CPU_MF_H
13 #define _ASM_S390_CPU_MF_H
17 #define CPU_MF_INT_SF_IAE (1 << 31)
18 #define CPU_MF_INT_SF_ISE (1 << 30)
19 #define CPU_MF_INT_SF_PRA (1 << 29)
20 #define CPU_MF_INT_SF_SACA (1 << 23)
21 #define CPU_MF_INT_SF_LSDA (1 << 22)
22 #define CPU_MF_INT_CF_CACA (1 << 7)
23 #define CPU_MF_INT_CF_LCDA (1 << 6)
24 #define CPU_MF_INT_RI_HALTED (1 << 5)
25 #define CPU_MF_INT_RI_BUF_FULL (1 << 4)
28 #define CPU_MF_INT_CF_MASK (CPU_MF_INT_CF_CACA|CPU_MF_INT_CF_LCDA)
29 #define CPU_MF_INT_SF_MASK (CPU_MF_INT_SF_IAE|CPU_MF_INT_SF_ISE| \
30 CPU_MF_INT_SF_PRA|CPU_MF_INT_SF_SACA| \
32 #define CPU_MF_INT_RI_MASK (CPU_MF_INT_RI_HALTED|CPU_MF_INT_RI_BUF_FULL)
35 static inline int cpum_cf_avail(
void)
40 static inline int cpum_sf_avail(
void)
64 "0: .insn s,0xb28e0000,%1\n"
68 :
"+d" (
rc),
"=Q" (*info));
73 static inline int lcctl(
u64 ctl)
78 " .insn s,0xb2840000,%1\n"
81 :
"=d" (
cc) :
"m" (ctl) :
"cc");
86 static inline int ecctr(
u64 ctr,
u64 *
val)
88 register u64 content
asm(
"4") = 0;
92 " .insn rre,0xb2e40000,%0,%2\n"
95 :
"=d" (content),
"=d" (cc) :
"d" (ctr) :
"cc");