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csr.h
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63 #ifndef __il_csr_h__
64 #define __il_csr_h__
65 /*
66  * CSR (control and status registers)
67  *
68  * CSR registers are mapped directly into PCI bus space, and are accessible
69  * whenever platform supplies power to device, even when device is in
70  * low power states due to driver-invoked device resets
71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
72  *
73  * Use _il_wr() and _il_rd() family to access these registers;
74  * these provide simple PCI bus access, without waking up the MAC.
75  * Do not use il_wr() family for these registers;
76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
78  * the CSR registers.
79  *
80  * NOTE: Device does need to be awake in order to read this memory
81  * via CSR_EEPROM register
82  */
83 #define CSR_BASE (0x000)
84 
85 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
87 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
88 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
89 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
90 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
91 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
92 #define CSR_GP_CNTRL (CSR_BASE+0x024)
93 
94 /* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */
95 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
96 
97 /*
98  * Hardware revision info
99  * Bit fields:
100  * 31-8: Reserved
101  * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102  * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
103  * 1-0: "Dash" (-) value, as in A-1, etc.
104  *
105  * NOTE: Revision step affects calculation of CCK txpower for 4965.
106  * NOTE: See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
107  */
108 #define CSR_HW_REV (CSR_BASE+0x028)
109 
110 /*
111  * EEPROM memory reads
112  *
113  * NOTE: Device must be awake, initialized via apm_ops.init(),
114  * in order to read.
115  */
116 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
117 #define CSR_EEPROM_GP (CSR_BASE+0x030)
118 
119 #define CSR_GIO_REG (CSR_BASE+0x03C)
120 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
121 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
122 
123 /*
124  * UCODE-DRIVER GP (general purpose) mailbox registers.
125  * SET/CLR registers set/clear bit(s) if "1" is written.
126  */
127 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
128 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
129 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
130 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
131 
132 #define CSR_LED_REG (CSR_BASE+0x094)
133 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
134 
135 /* GIO Chicken Bits (PCI Express bus link power management) */
136 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
137 
138 /* Analog phase-lock-loop configuration */
139 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
140 
141 /*
142  * CSR Hardware Revision Workaround Register. Indicates hardware rev;
143  * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
144  * See also CSR_HW_REV register.
145  * Bit fields:
146  * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
147  * 1-0: "Dash" (-) value, as in C-1, etc.
148  */
149 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
150 
151 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
152 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
153 
154 /* Bits for CSR_HW_IF_CONFIG_REG */
155 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
156 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
157 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
158 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
159 
160 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
161 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
162 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
163 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
164 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
165 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
166 
167 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
168 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
169 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
170 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
171 #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
172 
173 #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int */
174 #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec */
175 
176 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
177  * acknowledged (reset) by host writing "1" to flagged bits. */
178 #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
179 #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
180 #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
181 #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
182 #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
183 #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
184 #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
185 #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
186 #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
187 #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
188 #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
189 
190 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
191  CSR_INT_BIT_HW_ERR | \
192  CSR_INT_BIT_FH_TX | \
193  CSR_INT_BIT_SW_ERR | \
194  CSR_INT_BIT_RF_KILL | \
195  CSR_INT_BIT_SW_RX | \
196  CSR_INT_BIT_WAKEUP | \
197  CSR_INT_BIT_ALIVE)
198 
199 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
200 #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
201 #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
202 #define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
203 #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
204 #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
205 #define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
206 #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
207 #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
208 
209 #define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
210  CSR39_FH_INT_BIT_RX_CHNL2 | \
211  CSR_FH_INT_BIT_RX_CHNL1 | \
212  CSR_FH_INT_BIT_RX_CHNL0)
213 
214 #define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \
215  CSR_FH_INT_BIT_TX_CHNL1 | \
216  CSR_FH_INT_BIT_TX_CHNL0)
217 
218 #define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
219  CSR_FH_INT_BIT_RX_CHNL1 | \
220  CSR_FH_INT_BIT_RX_CHNL0)
221 
222 #define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
223  CSR_FH_INT_BIT_TX_CHNL0)
224 
225 /* GPIO */
226 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
227 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
228 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
229 
230 /* RESET */
231 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
232 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
233 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
234 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
235 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
236 #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
237 
238 /*
239  * GP (general purpose) CONTROL REGISTER
240  * Bit fields:
241  * 27: HW_RF_KILL_SW
242  * Indicates state of (platform's) hardware RF-Kill switch
243  * 26-24: POWER_SAVE_TYPE
244  * Indicates current power-saving mode:
245  * 000 -- No power saving
246  * 001 -- MAC power-down
247  * 010 -- PHY (radio) power-down
248  * 011 -- Error
249  * 9-6: SYS_CONFIG
250  * Indicates current system configuration, reflecting pins on chip
251  * as forced high/low by device circuit board.
252  * 4: GOING_TO_SLEEP
253  * Indicates MAC is entering a power-saving sleep power-down.
254  * Not a good time to access device-internal resources.
255  * 3: MAC_ACCESS_REQ
256  * Host sets this to request and maintain MAC wakeup, to allow host
257  * access to device-internal resources. Host must wait for
258  * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
259  * device registers.
260  * 2: INIT_DONE
261  * Host sets this to put device into fully operational D0 power mode.
262  * Host resets this after SW_RESET to put device into low power mode.
263  * 0: MAC_CLOCK_READY
264  * Indicates MAC (ucode processor, etc.) is powered up and can run.
265  * Internal resources are accessible.
266  * NOTE: This does not indicate that the processor is actually running.
267  * NOTE: This does not indicate that 4965 or 3945 has completed
268  * init or post-power-down restore of internal SRAM memory.
269  * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
270  * SRAM is restored and uCode is in normal operation mode.
271  * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
272  * do not need to save/restore it.
273  * NOTE: After device reset, this bit remains "0" until host sets
274  * INIT_DONE
275  */
276 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
277 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
278 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
279 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
280 
281 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
282 
283 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
284 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
285 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
286 
287 /* EEPROM REG */
288 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
289 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
290 #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
291 #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
292 
293 /* EEPROM GP */
294 #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
295 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
296 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
297 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
298 
299 /* GP REG */
300 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
301 #define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
302 #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
303 #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
304 #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
305 
306 /* CSR GIO */
307 #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
308 
309 /*
310  * UCODE-DRIVER GP (general purpose) mailbox register 1
311  * Host driver and uCode write and/or read this register to communicate with
312  * each other.
313  * Bit fields:
314  * 4: UCODE_DISABLE
315  * Host sets this to request permanent halt of uCode, same as
316  * sending CARD_STATE command with "halt" bit set.
317  * 3: CT_KILL_EXIT
318  * Host sets this to request exit from CT_KILL state, i.e. host thinks
319  * device temperature is low enough to continue normal operation.
320  * 2: CMD_BLOCKED
321  * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
322  * to release uCode to clear all Tx and command queues, enter
323  * unassociated mode, and power down.
324  * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
325  * 1: SW_BIT_RFKILL
326  * Host sets this when issuing CARD_STATE command to request
327  * device sleep.
328  * 0: MAC_SLEEP
329  * uCode sets this when preparing a power-saving power-down.
330  * uCode resets this when power-up is complete and SRAM is sane.
331  * NOTE: 3945/4965 saves internal SRAM data to host when powering down,
332  * and must restore this data after powering back up.
333  * MAC_SLEEP is the best indication that restore is complete.
334  * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
335  * do not need to save/restore it.
336  */
337 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
338 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
339 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
340 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
341 
342 /* GIO Chicken Bits (PCI Express bus link power management) */
343 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
344 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
345 
346 /* LED */
347 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
348 #define CSR_LED_REG_TRUN_ON (0x78)
349 #define CSR_LED_REG_TRUN_OFF (0x38)
350 
351 /* ANA_PLL */
352 #define CSR39_ANA_PLL_CFG_VAL (0x01000000)
353 
354 /* HPET MEM debug */
355 #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
356 
357 /* DRAM INT TBL */
358 #define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
359 #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
360 
361 /*
362  * HBUS (Host-side Bus)
363  *
364  * HBUS registers are mapped directly into PCI bus space, but are used
365  * to indirectly access device's internal memory or registers that
366  * may be powered-down.
367  *
368  * Use il_wr()/il_rd() family
369  * for these registers;
370  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
371  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
372  * internal resources.
373  *
374  * Do not use _il_wr()/_il_rd() family to access these registers;
375  * these provide only simple PCI bus access, without waking up the MAC.
376  */
377 #define HBUS_BASE (0x400)
378 
379 /*
380  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
381  * structures, error log, event log, verifying uCode load).
382  * First write to address register, then read from or write to data register
383  * to complete the job. Once the address register is set up, accesses to
384  * data registers auto-increment the address by one dword.
385  * Bit usage for address registers (read or write):
386  * 0-31: memory address within device
387  */
388 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
389 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
390 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
391 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
392 
393 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
394 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
395 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
396 
397 /*
398  * Registers for accessing device's internal peripheral registers
399  * (e.g. SCD, BSM, etc.). First write to address register,
400  * then read from or write to data register to complete the job.
401  * Bit usage for address registers (read or write):
402  * 0-15: register address (offset) within device
403  * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
404  */
405 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
406 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
407 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
408 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
409 
410 /*
411  * Per-Tx-queue write pointer (idx, really!)
412  * Indicates idx to next TFD that driver will fill (1 past latest filled).
413  * Bit usage:
414  * 0-7: queue write idx
415  * 11-8: queue selector
416  */
417 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
418 
419 #endif /* !__il_csr_h__ */
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