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| #define | CSR_BASE (0x000) |
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| #define | CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ |
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| #define | CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
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| #define | CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
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| #define | CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ |
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| #define | CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ |
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| #define | CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ |
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| #define | CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ |
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| #define | CSR_GP_CNTRL (CSR_BASE+0x024) |
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| #define | CSR_INT_PERIODIC_REG (CSR_BASE+0x005) |
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| #define | CSR_HW_REV (CSR_BASE+0x028) |
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| #define | CSR_EEPROM_REG (CSR_BASE+0x02c) |
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| #define | CSR_EEPROM_GP (CSR_BASE+0x030) |
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| #define | CSR_GIO_REG (CSR_BASE+0x03C) |
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| #define | CSR_GP_UCODE_REG (CSR_BASE+0x048) |
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| #define | CSR_GP_DRIVER_REG (CSR_BASE+0x050) |
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| #define | CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
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| #define | CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) |
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| #define | CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) |
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| #define | CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) |
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| #define | CSR_LED_REG (CSR_BASE+0x094) |
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| #define | CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) |
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| #define | CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
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| #define | CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
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| #define | CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
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| #define | CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) |
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| #define | CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) |
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| #define | CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) |
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| #define | CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
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| #define | CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) |
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| #define | CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) |
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| #define | CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) |
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| #define | CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) |
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| #define | CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) |
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| #define | CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ |
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| #define | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ |
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| #define | CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ |
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| #define | CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int */ |
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| #define | CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec */ |
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| #define | CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ |
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| #define | CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ |
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| #define | CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
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| #define | CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
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| #define | CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ |
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| #define | CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ |
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| #define | CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
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| #define | CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ |
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| #define | CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ |
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| #define | CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
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| #define | CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ |
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| #define | CSR_INI_SET_MASK |
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| #define | CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ |
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| #define | CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ |
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| #define | CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ |
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| #define | CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
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| #define | CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ |
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| #define | CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ |
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| #define | CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
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| #define | CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ |
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| #define | CSR39_FH_INT_RX_MASK |
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| #define | CSR39_FH_INT_TX_MASK |
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| #define | CSR49_FH_INT_RX_MASK |
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| #define | CSR49_FH_INT_TX_MASK |
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| #define | CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) |
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| #define | CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) |
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| #define | CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) |
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| #define | CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) |
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| #define | CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) |
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| #define | CSR_RESET_REG_FLAG_SW_RESET (0x00000080) |
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| #define | CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) |
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| #define | CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) |
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| #define | CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
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| #define | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
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| #define | CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) |
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| #define | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) |
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| #define | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) |
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| #define | CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) |
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| #define | CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) |
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| #define | CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) |
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| #define | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) |
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| #define | CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) |
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| #define | CSR_EEPROM_REG_BIT_CMD (0x00000002) |
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| #define | CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
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| #define | CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) |
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| #define | CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
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| #define | CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
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| #define | CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) |
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| #define | CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) |
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| #define | CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
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| #define | CSR_GP_REG_NO_POWER_SAVE (0x00000000) |
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| #define | CSR_GP_REG_MAC_POWER_SAVE (0x01000000) |
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| #define | CSR_GP_REG_PHY_POWER_SAVE (0x02000000) |
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| #define | CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) |
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| #define | CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) |
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| #define | CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
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| #define | CSR_UCODE_SW_BIT_RFKILL (0x00000002) |
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| #define | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) |
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| #define | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) |
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| #define | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
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| #define | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
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| #define | CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) |
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| #define | CSR_LED_REG_TRUN_ON (0x78) |
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| #define | CSR_LED_REG_TRUN_OFF (0x38) |
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| #define | CSR39_ANA_PLL_CFG_VAL (0x01000000) |
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| #define | CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) |
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| #define | CSR_DRAM_INT_TBL_ENABLE (1 << 31) |
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| #define | CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) |
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| #define | HBUS_BASE (0x400) |
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| #define | HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) |
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| #define | HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) |
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| #define | HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) |
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| #define | HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) |
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| #define | HBUS_TARG_MBX_C (HBUS_BASE+0x030) |
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| #define | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) |
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| #define | HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) |
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| #define | HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) |
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| #define | HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) |
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| #define | HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) |
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| #define | HBUS_TARG_WRPTR (HBUS_BASE+0x060) |
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1.8.2