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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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| #define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ |
| #define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ |
| #define CSR39_FH_INT_RX_MASK |
| #define CSR39_FH_INT_TX_MASK |
| #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) |
| #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) |
| #define CSR49_FH_INT_RX_MASK |
| #define CSR49_FH_INT_TX_MASK |
| #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ |
| #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
| #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
| #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
| #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ |
| #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ |
| #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ |
| #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ |
| #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ |
| #define CSR_INI_SET_MASK |
| #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
| #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ |
| #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
| #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ |
| #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
| #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
| #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ |
| #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int */ |
| #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec */ |
| #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ |
1.8.2