Linux Kernel: arch/arm/mach-omap2/ctrl_module_pad_core

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 /*
  * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
  *
  * Copyright (C) 2009-2010 Texas Instruments, Inc.
  *
  * Benoit Cousson ([email protected])
  * Santosh Shilimkar ([email protected])
  *
  * This file is automatically generated from the OMAP hardware databases.
  * We respectfully ask that any modifications to this file be coordinated
  * with the public [email protected] mailing list and the
  * authors above to ensure that the autogeneration scripts are kept
  * up-to-date with the file contents.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
 
 
 /* Base address */
 #define OMAP4_CTRL_MODULE_PAD_CORE              0x4a100000
 
 /* Registers offset */
 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION          0x0000
 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO            0x0004
 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG         0x0010
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0    0x01d8
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1    0x01dc
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2    0x01e0
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3    0x01e4
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4    0x01e8
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5    0x01ec
 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6    0x01f0
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL   0x05a0
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE     0x05a4
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC        0x05c4
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS      0x05c8
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE        0x0600
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0        0x0604
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX        0x0608
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC        0x060c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY      0x0610
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2         0x0614
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY       0x0618
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP      0x061c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE      0x0620
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1        0x0624
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1         0x0628
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI          0x062c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB          0x0630
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ          0x0634
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0      0x0638
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1      0x063c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2      0x0640
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3      0x0644
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0      0x0648
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1      0x064c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2      0x0650
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3      0x0654
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD     0x0658
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C          0x065c
 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW    0x0660
 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R     0x0664
 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0  0x0668
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1      0x0700
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2      0x0704
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3      0x0708
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4      0x070c
 
 /* Registers shifts and masks */
 
 /* IP_REVISION */
 #define OMAP4_IP_REV_SCHEME_SHIFT               30
 #define OMAP4_IP_REV_SCHEME_MASK                (0x3 << 30)
 #define OMAP4_IP_REV_FUNC_SHIFT                 16
 #define OMAP4_IP_REV_FUNC_MASK                  (0xfff << 16)
 #define OMAP4_IP_REV_RTL_SHIFT                  11
 #define OMAP4_IP_REV_RTL_MASK                   (0x1f << 11)
 #define OMAP4_IP_REV_MAJOR_SHIFT                8
 #define OMAP4_IP_REV_MAJOR_MASK                 (0x7 << 8)
 #define OMAP4_IP_REV_CUSTOM_SHIFT               6
 #define OMAP4_IP_REV_CUSTOM_MASK                (0x3 << 6)
 #define OMAP4_IP_REV_MINOR_SHIFT                0
 #define OMAP4_IP_REV_MINOR_MASK                 (0x3f << 0)
 
 /* IP_HWINFO */
 #define OMAP4_IP_HWINFO_SHIFT                   0
 #define OMAP4_IP_HWINFO_MASK                    (0xffffffff << 0)
 
 /* IP_SYSCONFIG */
 #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT           2
 #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK            (0x3 << 2)
 
 /* PADCONF_WAKEUPEVENT_0 */
 #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT       31
 #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK        (1 << 31)
 #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT       30
 #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK        (1 << 30)
 #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT      29
 #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
 #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT      28
 #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK       (1 << 28)
 #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT      27
 #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK       (1 << 27)
 #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT      26
 #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK       (1 << 26)
 #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT       25
 #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK        (1 << 25)
 #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT       24
 #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK        (1 << 24)
 #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT       23
 #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK        (1 << 23)
 #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT       22
 #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK        (1 << 22)
 #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT       21
 #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK        (1 << 21)
 #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT       20
 #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK        (1 << 20)
 #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT       19
 #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK        (1 << 19)
 #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT       18
 #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK        (1 << 18)
 #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT       17
 #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK        (1 << 17)
 #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT       16
 #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK        (1 << 16)
 #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT      15
 #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK       (1 << 15)
 #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT      14
 #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
 #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT      13
 #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK       (1 << 13)
 #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT      12
 #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK       (1 << 12)
 #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT      11
 #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK       (1 << 11)
 #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT      10
 #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK       (1 << 10)
 #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT       9
 #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK        (1 << 9)
 #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT       8
 #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK        (1 << 8)
 #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT       7
 #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK        (1 << 7)
 #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT       6
 #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK        (1 << 6)
 #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT       5
 #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK        (1 << 5)
 #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT       4
 #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK        (1 << 4)
 #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT       3
 #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK        (1 << 3)
 #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT       2
 #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK        (1 << 2)
 #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT       1
 #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK        (1 << 1)
 #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT       0
 #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK        (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_1 */
 #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT     31
 #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK      (1 << 31)
 #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT        30
 #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK     (1 << 30)
 #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT      29
 #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
 #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT      28
 #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK       (1 << 28)
 #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT      27
 #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK       (1 << 27)
 #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT      26
 #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK       (1 << 26)
 #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT      25
 #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK       (1 << 25)
 #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT      24
 #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK       (1 << 24)
 #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT      23
 #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK       (1 << 23)
 #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT      22
 #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK       (1 << 22)
 #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT      21
 #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK       (1 << 21)
 #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT      20
 #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK       (1 << 20)
 #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT      19
 #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
 #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT      18
 #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
 #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT      17
 #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
 #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT      16
 #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
 #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT       15
 #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK        (1 << 15)
 #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT       14
 #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK        (1 << 14)
 #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT       13
 #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK        (1 << 13)
 #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT       12
 #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK        (1 << 12)
 #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT     11
 #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
 #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT     10
 #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
 #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT     9
 #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
 #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT     8
 #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
 #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT     7
 #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
 #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT     6
 #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
 #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT     5
 #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
 #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT      4
 #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
 #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT      3
 #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
 #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT       2
 #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK        (1 << 2)
 #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT       1
 #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK        (1 << 1)
 #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT      0
 #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK       (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_2 */
 #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT    31
 #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK     (1 << 31)
 #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT     30
 #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK      (1 << 30)
 #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT      29
 #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
 #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT      28
 #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK       (1 << 28)
 #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT    27
 #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK     (1 << 27)
 #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT        26
 #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK     (1 << 26)
 #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT        25
 #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK     (1 << 25)
 #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT        24
 #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK     (1 << 24)
 #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT        23
 #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK     (1 << 23)
 #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT        22
 #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK     (1 << 22)
 #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT        21
 #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK     (1 << 21)
 #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT        20
 #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK     (1 << 20)
 #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT        19
 #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK     (1 << 19)
 #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT     18
 #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK      (1 << 18)
 #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT     17
 #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK      (1 << 17)
 #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT     16
 #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK      (1 << 16)
 #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT     15
 #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK      (1 << 15)
 #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT  14
 #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK   (1 << 14)
 #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT    13
 #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK     (1 << 13)
 #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
 #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK  (1 << 12)
 #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
 #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK  (1 << 11)
 #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
 #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK  (1 << 10)
 #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
 #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK  (1 << 9)
 #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
 #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK  (1 << 8)
 #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
 #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK  (1 << 7)
 #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
 #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK  (1 << 6)
 #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
 #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK  (1 << 5)
 #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT  4
 #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK   (1 << 4)
 #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT  3
 #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK   (1 << 3)
 #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT  2
 #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK   (1 << 2)
 #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT  1
 #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK   (1 << 1)
 #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT    0
 #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK     (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_3 */
 #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT     31
 #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK      (1 << 31)
 #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT     30
 #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK      (1 << 30)
 #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT     29
 #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK      (1 << 29)
 #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT     28
 #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK      (1 << 28)
 #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT        27
 #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK     (1 << 27)
 #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT        26
 #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK     (1 << 26)
 #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT     25
 #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
 #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT       24
 #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK        (1 << 24)
 #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT       23
 #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK        (1 << 23)
 #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT       22
 #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK        (1 << 22)
 #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT       21
 #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK        (1 << 21)
 #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT       20
 #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK        (1 << 20)
 #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT       19
 #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK        (1 << 19)
 #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT       18
 #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK        (1 << 18)
 #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT       17
 #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK        (1 << 17)
 #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT        16
 #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK         (1 << 16)
 #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT       15
 #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK        (1 << 15)
 #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT       14
 #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK        (1 << 14)
 #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT      13
 #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK       (1 << 13)
 #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT      12
 #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK       (1 << 12)
 #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT      11
 #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK       (1 << 11)
 #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT      10
 #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK       (1 << 10)
 #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT      9
 #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK       (1 << 9)
 #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT      8
 #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK       (1 << 8)
 #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT       7
 #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK        (1 << 7)
 #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT     6
 #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
 #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT      5
 #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK       (1 << 5)
 #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT    4
 #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK     (1 << 4)
 #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT    3
 #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK     (1 << 3)
 #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT     2
 #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK      (1 << 2)
 #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT      1
 #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
 #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT      0
 #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK       (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_4 */
 #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT     31
 #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK      (1 << 31)
 #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT     30
 #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK      (1 << 30)
 #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT  29
 #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK   (1 << 29)
 #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT    28
 #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK     (1 << 28)
 #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
 #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK  (1 << 27)
 #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
 #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK  (1 << 26)
 #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
 #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK  (1 << 25)
 #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
 #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK  (1 << 24)
 #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
 #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK  (1 << 23)
 #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
 #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK  (1 << 22)
 #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
 #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK  (1 << 21)
 #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
 #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK  (1 << 20)
 #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT  19
 #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK   (1 << 19)
 #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT  18
 #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK   (1 << 18)
 #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT  17
 #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK   (1 << 17)
 #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT  16
 #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK   (1 << 16)
 #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT       15
 #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK        (1 << 15)
 #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT       14
 #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK        (1 << 14)
 #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT     13
 #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK      (1 << 13)
 #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT        12
 #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK     (1 << 12)
 #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT        11
 #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK     (1 << 11)
 #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT     10
 #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
 #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT        9
 #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK     (1 << 9)
 #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT        8
 #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK     (1 << 8)
 #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT        7
 #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK     (1 << 7)
 #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT        6
 #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK     (1 << 6)
 #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT     5
 #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
 #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT     4
 #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK      (1 << 4)
 #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT      3
 #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
 #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT      2
 #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
 #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT       1
 #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK        (1 << 1)
 #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT     0
 #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK      (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_5 */
 #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT      31
 #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK       (1 << 31)
 #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT      30
 #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK       (1 << 30)
 #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT       29
 #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK        (1 << 29)
 #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT       28
 #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK        (1 << 28)
 #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT       27
 #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK        (1 << 27)
 #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT       26
 #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK        (1 << 26)
 #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT       25
 #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK        (1 << 25)
 #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT       24
 #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK        (1 << 24)
 #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT       23
 #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK        (1 << 23)
 #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT       22
 #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK        (1 << 22)
 #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT       21
 #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK        (1 << 21)
 #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT       20
 #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK        (1 << 20)
 #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT      19
 #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
 #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT      18
 #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
 #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT      17
 #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
 #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT      16
 #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
 #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT      15
 #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK       (1 << 15)
 #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT      14
 #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
 #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT      13
 #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK       (1 << 13)
 #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT      12
 #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK       (1 << 12)
 #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT      11
 #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK       (1 << 11)
 #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT      10
 #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK       (1 << 10)
 #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT     9
 #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
 #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT     8
 #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
 #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT     7
 #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
 #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT     6
 #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
 #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT     5
 #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
 #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT     4
 #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK      (1 << 4)
 #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT     3
 #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK      (1 << 3)
 #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT     2
 #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK      (1 << 2)
 #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT     1
 #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK      (1 << 1)
 #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT     0
 #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK      (1 << 0)
 
 /* PADCONF_WAKEUPEVENT_6 */
 #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT      7
 #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK       (1 << 7)
 #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT      6
 #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK       (1 << 6)
 #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT      5
 #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK       (1 << 5)
 #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT      4
 #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
 #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT      3
 #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
 #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT      2
 #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
 #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT      1
 #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
 #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT      0
 #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK       (1 << 0)
 
 /* CONTROL_PADCONF_GLOBAL */
 #define OMAP4_FORCE_OFFMODE_EN_SHIFT                31
 #define OMAP4_FORCE_OFFMODE_EN_MASK             (1 << 31)
 
 /* CONTROL_PADCONF_MODE */
 #define OMAP4_VDDS_DV_BANK0_SHIFT               31
 #define OMAP4_VDDS_DV_BANK0_MASK                (1 << 31)
 #define OMAP4_VDDS_DV_BANK1_SHIFT               30
 #define OMAP4_VDDS_DV_BANK1_MASK                (1 << 30)
 #define OMAP4_VDDS_DV_BANK3_SHIFT               29
 #define OMAP4_VDDS_DV_BANK3_MASK                (1 << 29)
 #define OMAP4_VDDS_DV_BANK4_SHIFT               28
 #define OMAP4_VDDS_DV_BANK4_MASK                (1 << 28)
 #define OMAP4_VDDS_DV_BANK5_SHIFT               27
 #define OMAP4_VDDS_DV_BANK5_MASK                (1 << 27)
 #define OMAP4_VDDS_DV_BANK6_SHIFT               26
 #define OMAP4_VDDS_DV_BANK6_MASK                (1 << 26)
 #define OMAP4_VDDS_DV_C2C_SHIFT                 25
 #define OMAP4_VDDS_DV_C2C_MASK                  (1 << 25)
 #define OMAP4_VDDS_DV_CAM_SHIFT                 24
 #define OMAP4_VDDS_DV_CAM_MASK                  (1 << 24)
 #define OMAP4_VDDS_DV_GPMC_SHIFT                23
 #define OMAP4_VDDS_DV_GPMC_MASK                 (1 << 23)
 #define OMAP4_VDDS_DV_SDMMC2_SHIFT              22
 #define OMAP4_VDDS_DV_SDMMC2_MASK               (1 << 22)
 
 /* CONTROL_SMART1IO_PADCONF_0 */
 #define OMAP4_ABE_DR0_SC_SHIFT                  30
 #define OMAP4_ABE_DR0_SC_MASK                   (0x3 << 30)
 #define OMAP4_CAM_DR0_SC_SHIFT                  28
 #define OMAP4_CAM_DR0_SC_MASK                   (0x3 << 28)
 #define OMAP4_FREF_DR2_SC_SHIFT                 26
 #define OMAP4_FREF_DR2_SC_MASK                  (0x3 << 26)
 #define OMAP4_FREF_DR3_SC_SHIFT                 24
 #define OMAP4_FREF_DR3_SC_MASK                  (0x3 << 24)
 #define OMAP4_GPIO_DR8_SC_SHIFT                 22
 #define OMAP4_GPIO_DR8_SC_MASK                  (0x3 << 22)
 #define OMAP4_GPIO_DR9_SC_SHIFT                 20
 #define OMAP4_GPIO_DR9_SC_MASK                  (0x3 << 20)
 #define OMAP4_GPMC_DR2_SC_SHIFT                 18
 #define OMAP4_GPMC_DR2_SC_MASK                  (0x3 << 18)
 #define OMAP4_GPMC_DR3_SC_SHIFT                 16
 #define OMAP4_GPMC_DR3_SC_MASK                  (0x3 << 16)
 #define OMAP4_GPMC_DR6_SC_SHIFT                 14
 #define OMAP4_GPMC_DR6_SC_MASK                  (0x3 << 14)
 #define OMAP4_HDMI_DR0_SC_SHIFT                 12
 #define OMAP4_HDMI_DR0_SC_MASK                  (0x3 << 12)
 #define OMAP4_MCSPI1_DR0_SC_SHIFT               10
 #define OMAP4_MCSPI1_DR0_SC_MASK                (0x3 << 10)
 #define OMAP4_UART1_DR0_SC_SHIFT                8
 #define OMAP4_UART1_DR0_SC_MASK                 (0x3 << 8)
 #define OMAP4_UART3_DR0_SC_SHIFT                6
 #define OMAP4_UART3_DR0_SC_MASK                 (0x3 << 6)
 #define OMAP4_UART3_DR1_SC_SHIFT                4
 #define OMAP4_UART3_DR1_SC_MASK                 (0x3 << 4)
 #define OMAP4_UNIPRO_DR0_SC_SHIFT               2
 #define OMAP4_UNIPRO_DR0_SC_MASK                (0x3 << 2)
 #define OMAP4_UNIPRO_DR1_SC_SHIFT               0
 #define OMAP4_UNIPRO_DR1_SC_MASK                (0x3 << 0)
 
 /* CONTROL_SMART1IO_PADCONF_1 */
 #define OMAP4_ABE_DR0_LB_SHIFT                  30
 #define OMAP4_ABE_DR0_LB_MASK                   (0x3 << 30)
 #define OMAP4_CAM_DR0_LB_SHIFT                  28
 #define OMAP4_CAM_DR0_LB_MASK                   (0x3 << 28)
 #define OMAP4_FREF_DR2_LB_SHIFT                 26
 #define OMAP4_FREF_DR2_LB_MASK                  (0x3 << 26)
 #define OMAP4_FREF_DR3_LB_SHIFT                 24
 #define OMAP4_FREF_DR3_LB_MASK                  (0x3 << 24)
 #define OMAP4_GPIO_DR8_LB_SHIFT                 22
 #define OMAP4_GPIO_DR8_LB_MASK                  (0x3 << 22)
 #define OMAP4_GPIO_DR9_LB_SHIFT                 20
 #define OMAP4_GPIO_DR9_LB_MASK                  (0x3 << 20)
 #define OMAP4_GPMC_DR2_LB_SHIFT                 18
 #define OMAP4_GPMC_DR2_LB_MASK                  (0x3 << 18)
 #define OMAP4_GPMC_DR3_LB_SHIFT                 16
 #define OMAP4_GPMC_DR3_LB_MASK                  (0x3 << 16)
 #define OMAP4_GPMC_DR6_LB_SHIFT                 14
 #define OMAP4_GPMC_DR6_LB_MASK                  (0x3 << 14)
 #define OMAP4_HDMI_DR0_LB_SHIFT                 12
 #define OMAP4_HDMI_DR0_LB_MASK                  (0x3 << 12)
 #define OMAP4_MCSPI1_DR0_LB_SHIFT               10
 #define OMAP4_MCSPI1_DR0_LB_MASK                (0x3 << 10)
 #define OMAP4_UART1_DR0_LB_SHIFT                8
 #define OMAP4_UART1_DR0_LB_MASK                 (0x3 << 8)
 #define OMAP4_UART3_DR0_LB_SHIFT                6
 #define OMAP4_UART3_DR0_LB_MASK                 (0x3 << 6)
 #define OMAP4_UART3_DR1_LB_SHIFT                4
 #define OMAP4_UART3_DR1_LB_MASK                 (0x3 << 4)
 #define OMAP4_UNIPRO_DR0_LB_SHIFT               2
 #define OMAP4_UNIPRO_DR0_LB_MASK                (0x3 << 2)
 #define OMAP4_UNIPRO_DR1_LB_SHIFT               0
 #define OMAP4_UNIPRO_DR1_LB_MASK                (0x3 << 0)
 
 /* CONTROL_SMART2IO_PADCONF_0 */
 #define OMAP4_C2C_DR0_LB_SHIFT                  31
 #define OMAP4_C2C_DR0_LB_MASK                   (1 << 31)
 #define OMAP4_DPM_DR1_LB_SHIFT                  30
 #define OMAP4_DPM_DR1_LB_MASK                   (1 << 30)
 #define OMAP4_DPM_DR2_LB_SHIFT                  29
 #define OMAP4_DPM_DR2_LB_MASK                   (1 << 29)
 #define OMAP4_DPM_DR3_LB_SHIFT                  28
 #define OMAP4_DPM_DR3_LB_MASK                   (1 << 28)
 #define OMAP4_GPIO_DR0_LB_SHIFT                 27
 #define OMAP4_GPIO_DR0_LB_MASK                  (1 << 27)
 #define OMAP4_GPIO_DR1_LB_SHIFT                 26
 #define OMAP4_GPIO_DR1_LB_MASK                  (1 << 26)
 #define OMAP4_GPIO_DR10_LB_SHIFT                25
 #define OMAP4_GPIO_DR10_LB_MASK                 (1 << 25)
 #define OMAP4_GPIO_DR2_LB_SHIFT                 24
 #define OMAP4_GPIO_DR2_LB_MASK                  (1 << 24)
 #define OMAP4_GPMC_DR0_LB_SHIFT                 23
 #define OMAP4_GPMC_DR0_LB_MASK                  (1 << 23)
 #define OMAP4_GPMC_DR1_LB_SHIFT                 22
 #define OMAP4_GPMC_DR1_LB_MASK                  (1 << 22)
 #define OMAP4_GPMC_DR4_LB_SHIFT                 21
 #define OMAP4_GPMC_DR4_LB_MASK                  (1 << 21)
 #define OMAP4_GPMC_DR5_LB_SHIFT                 20
 #define OMAP4_GPMC_DR5_LB_MASK                  (1 << 20)
 #define OMAP4_GPMC_DR7_LB_SHIFT                 19
 #define OMAP4_GPMC_DR7_LB_MASK                  (1 << 19)
 #define OMAP4_HSI2_DR0_LB_SHIFT                 18
 #define OMAP4_HSI2_DR0_LB_MASK                  (1 << 18)
 #define OMAP4_HSI2_DR1_LB_SHIFT                 17
 #define OMAP4_HSI2_DR1_LB_MASK                  (1 << 17)
 #define OMAP4_HSI2_DR2_LB_SHIFT                 16
 #define OMAP4_HSI2_DR2_LB_MASK                  (1 << 16)
 #define OMAP4_KPD_DR0_LB_SHIFT                  15
 #define OMAP4_KPD_DR0_LB_MASK                   (1 << 15)
 #define OMAP4_KPD_DR1_LB_SHIFT                  14
 #define OMAP4_KPD_DR1_LB_MASK                   (1 << 14)
 #define OMAP4_PDM_DR0_LB_SHIFT                  13
 #define OMAP4_PDM_DR0_LB_MASK                   (1 << 13)
 #define OMAP4_SDMMC2_DR0_LB_SHIFT               12
 #define OMAP4_SDMMC2_DR0_LB_MASK                (1 << 12)
 #define OMAP4_SDMMC3_DR0_LB_SHIFT               11
 #define OMAP4_SDMMC3_DR0_LB_MASK                (1 << 11)
 #define OMAP4_SDMMC4_DR0_LB_SHIFT               10
 #define OMAP4_SDMMC4_DR0_LB_MASK                (1 << 10)
 #define OMAP4_SDMMC4_DR1_LB_SHIFT               9
 #define OMAP4_SDMMC4_DR1_LB_MASK                (1 << 9)
 #define OMAP4_SPI3_DR0_LB_SHIFT                 8
 #define OMAP4_SPI3_DR0_LB_MASK                  (1 << 8)
 #define OMAP4_SPI3_DR1_LB_SHIFT                 7
 #define OMAP4_SPI3_DR1_LB_MASK                  (1 << 7)
 #define OMAP4_UART3_DR2_LB_SHIFT                6
 #define OMAP4_UART3_DR2_LB_MASK                 (1 << 6)
 #define OMAP4_UART3_DR3_LB_SHIFT                5
 #define OMAP4_UART3_DR3_LB_MASK                 (1 << 5)
 #define OMAP4_UART3_DR4_LB_SHIFT                4
 #define OMAP4_UART3_DR4_LB_MASK                 (1 << 4)
 #define OMAP4_UART3_DR5_LB_SHIFT                3
 #define OMAP4_UART3_DR5_LB_MASK                 (1 << 3)
 #define OMAP4_USBA0_DR1_LB_SHIFT                2
 #define OMAP4_USBA0_DR1_LB_MASK                 (1 << 2)
 #define OMAP4_USBA_DR2_LB_SHIFT                 1
 #define OMAP4_USBA_DR2_LB_MASK                  (1 << 1)
 
 /* CONTROL_SMART2IO_PADCONF_1 */
 #define OMAP4_USBB1_DR0_LB_SHIFT                31
 #define OMAP4_USBB1_DR0_LB_MASK                 (1 << 31)
 #define OMAP4_USBB2_DR0_LB_SHIFT                30
 #define OMAP4_USBB2_DR0_LB_MASK                 (1 << 30)
 #define OMAP4_USBA0_DR0_LB_SHIFT                29
 #define OMAP4_USBA0_DR0_LB_MASK                 (1 << 29)
 
 /* CONTROL_SMART3IO_PADCONF_0 */
 #define OMAP4_DMIC_DR0_MB_SHIFT                 30
 #define OMAP4_DMIC_DR0_MB_MASK                  (0x3 << 30)
 #define OMAP4_GPIO_DR3_MB_SHIFT                 28
 #define OMAP4_GPIO_DR3_MB_MASK                  (0x3 << 28)
 #define OMAP4_GPIO_DR4_MB_SHIFT                 26
 #define OMAP4_GPIO_DR4_MB_MASK                  (0x3 << 26)
 #define OMAP4_GPIO_DR5_MB_SHIFT                 24
 #define OMAP4_GPIO_DR5_MB_MASK                  (0x3 << 24)
 #define OMAP4_GPIO_DR6_MB_SHIFT                 22
 #define OMAP4_GPIO_DR6_MB_MASK                  (0x3 << 22)
 #define OMAP4_HSI_DR1_MB_SHIFT                  20
 #define OMAP4_HSI_DR1_MB_MASK                   (0x3 << 20)
 #define OMAP4_HSI_DR2_MB_SHIFT                  18
 #define OMAP4_HSI_DR2_MB_MASK                   (0x3 << 18)
 #define OMAP4_HSI_DR3_MB_SHIFT                  16
 #define OMAP4_HSI_DR3_MB_MASK                   (0x3 << 16)
 #define OMAP4_MCBSP2_DR0_MB_SHIFT               14
 #define OMAP4_MCBSP2_DR0_MB_MASK                (0x3 << 14)
 #define OMAP4_MCSPI4_DR0_MB_SHIFT               12
 #define OMAP4_MCSPI4_DR0_MB_MASK                (0x3 << 12)
 #define OMAP4_MCSPI4_DR1_MB_SHIFT               10
 #define OMAP4_MCSPI4_DR1_MB_MASK                (0x3 << 10)
 #define OMAP4_SDMMC3_DR0_MB_SHIFT               8
 #define OMAP4_SDMMC3_DR0_MB_MASK                (0x3 << 8)
 #define OMAP4_SPI2_DR0_MB_SHIFT                 0
 #define OMAP4_SPI2_DR0_MB_MASK                  (0x3 << 0)
 
 /* CONTROL_SMART3IO_PADCONF_1 */
 #define OMAP4_SPI2_DR1_MB_SHIFT                 30
 #define OMAP4_SPI2_DR1_MB_MASK                  (0x3 << 30)
 #define OMAP4_SPI2_DR2_MB_SHIFT                 28
 #define OMAP4_SPI2_DR2_MB_MASK                  (0x3 << 28)
 #define OMAP4_UART2_DR0_MB_SHIFT                26
 #define OMAP4_UART2_DR0_MB_MASK                 (0x3 << 26)
 #define OMAP4_UART2_DR1_MB_SHIFT                24
 #define OMAP4_UART2_DR1_MB_MASK                 (0x3 << 24)
 #define OMAP4_UART4_DR0_MB_SHIFT                22
 #define OMAP4_UART4_DR0_MB_MASK                 (0x3 << 22)
 #define OMAP4_HSI_DR0_MB_SHIFT                  20
 #define OMAP4_HSI_DR0_MB_MASK                   (0x3 << 20)
 
 /* CONTROL_SMART3IO_PADCONF_2 */
 #define OMAP4_DMIC_DR0_LB_SHIFT                 31
 #define OMAP4_DMIC_DR0_LB_MASK                  (1 << 31)
 #define OMAP4_GPIO_DR3_LB_SHIFT                 30
 #define OMAP4_GPIO_DR3_LB_MASK                  (1 << 30)
 #define OMAP4_GPIO_DR4_LB_SHIFT                 29
 #define OMAP4_GPIO_DR4_LB_MASK                  (1 << 29)
 #define OMAP4_GPIO_DR5_LB_SHIFT                 28
 #define OMAP4_GPIO_DR5_LB_MASK                  (1 << 28)
 #define OMAP4_GPIO_DR6_LB_SHIFT                 27
 #define OMAP4_GPIO_DR6_LB_MASK                  (1 << 27)
 #define OMAP4_HSI_DR1_LB_SHIFT                  26
 #define OMAP4_HSI_DR1_LB_MASK                   (1 << 26)
 #define OMAP4_HSI_DR2_LB_SHIFT                  25
 #define OMAP4_HSI_DR2_LB_MASK                   (1 << 25)
 #define OMAP4_HSI_DR3_LB_SHIFT                  24
 #define OMAP4_HSI_DR3_LB_MASK                   (1 << 24)
 #define OMAP4_MCBSP2_DR0_LB_SHIFT               23
 #define OMAP4_MCBSP2_DR0_LB_MASK                (1 << 23)
 #define OMAP4_MCSPI4_DR0_LB_SHIFT               22
 #define OMAP4_MCSPI4_DR0_LB_MASK                (1 << 22)
 #define OMAP4_MCSPI4_DR1_LB_SHIFT               21
 #define OMAP4_MCSPI4_DR1_LB_MASK                (1 << 21)
 #define OMAP4_SLIMBUS2_DR0_LB_SHIFT             18
 #define OMAP4_SLIMBUS2_DR0_LB_MASK              (1 << 18)
 #define OMAP4_SPI2_DR0_LB_SHIFT                 16
 #define OMAP4_SPI2_DR0_LB_MASK                  (1 << 16)
 #define OMAP4_SPI2_DR1_LB_SHIFT                 15
 #define OMAP4_SPI2_DR1_LB_MASK                  (1 << 15)
 #define OMAP4_SPI2_DR2_LB_SHIFT                 14
 #define OMAP4_SPI2_DR2_LB_MASK                  (1 << 14)
 #define OMAP4_UART2_DR0_LB_SHIFT                13
 #define OMAP4_UART2_DR0_LB_MASK                 (1 << 13)
 #define OMAP4_UART2_DR1_LB_SHIFT                12
 #define OMAP4_UART2_DR1_LB_MASK                 (1 << 12)
 #define OMAP4_UART4_DR0_LB_SHIFT                11
 #define OMAP4_UART4_DR0_LB_MASK                 (1 << 11)
 #define OMAP4_HSI_DR0_LB_SHIFT                  10
 #define OMAP4_HSI_DR0_LB_MASK                   (1 << 10)
 
 /* CONTROL_USBB_HSIC */
 #define OMAP4_USBB2_DR1_SR_SHIFT                30
 #define OMAP4_USBB2_DR1_SR_MASK                 (0x3 << 30)
 #define OMAP4_USBB2_DR1_I_SHIFT                 27
 #define OMAP4_USBB2_DR1_I_MASK                  (0x7 << 27)
 #define OMAP4_USBB1_DR1_SR_SHIFT                25
 #define OMAP4_USBB1_DR1_SR_MASK                 (0x3 << 25)
 #define OMAP4_USBB1_DR1_I_SHIFT                 22
 #define OMAP4_USBB1_DR1_I_MASK                  (0x7 << 22)
 #define OMAP4_USBB1_HSIC_DATA_WD_SHIFT              20
 #define OMAP4_USBB1_HSIC_DATA_WD_MASK               (0x3 << 20)
 #define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT            18
 #define OMAP4_USBB1_HSIC_STROBE_WD_MASK             (0x3 << 18)
 #define OMAP4_USBB2_HSIC_DATA_WD_SHIFT              16
 #define OMAP4_USBB2_HSIC_DATA_WD_MASK               (0x3 << 16)
 #define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT            14
 #define OMAP4_USBB2_HSIC_STROBE_WD_MASK             (0x3 << 14)
 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT       13
 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK        (1 << 13)
 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT          11
 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK           (0x3 << 11)
 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT     10
 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK      (1 << 10)
 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT        8
 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK         (0x3 << 8)
 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT       7
 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK        (1 << 7)
 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT          5
 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK           (0x3 << 5)
 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT     4
 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK      (1 << 4)
 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT        2
 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK         (0x3 << 2)
 
 /* CONTROL_SLIMBUS */
 #define OMAP4_SLIMBUS1_DR0_MB_SHIFT             30
 #define OMAP4_SLIMBUS1_DR0_MB_MASK              (0x3 << 30)
 #define OMAP4_SLIMBUS1_DR1_MB_SHIFT             28
 #define OMAP4_SLIMBUS1_DR1_MB_MASK              (0x3 << 28)
 #define OMAP4_SLIMBUS2_DR0_MB_SHIFT             26
 #define OMAP4_SLIMBUS2_DR0_MB_MASK              (0x3 << 26)
 #define OMAP4_SLIMBUS2_DR1_MB_SHIFT             24
 #define OMAP4_SLIMBUS2_DR1_MB_MASK              (0x3 << 24)
 #define OMAP4_SLIMBUS2_DR2_MB_SHIFT             22
 #define OMAP4_SLIMBUS2_DR2_MB_MASK              (0x3 << 22)
 #define OMAP4_SLIMBUS2_DR3_MB_SHIFT             20
 #define OMAP4_SLIMBUS2_DR3_MB_MASK              (0x3 << 20)
 #define OMAP4_SLIMBUS1_DR0_LB_SHIFT             19
 #define OMAP4_SLIMBUS1_DR0_LB_MASK              (1 << 19)
 #define OMAP4_SLIMBUS2_DR1_LB_SHIFT             18
 #define OMAP4_SLIMBUS2_DR1_LB_MASK              (1 << 18)
 
 /* CONTROL_PBIASLITE */
 #define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT         31
 #define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK          (1 << 31)
 #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT        30
 #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK         (1 << 30)
 #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT          29
 #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK           (1 << 29)
 #define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT           28
 #define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK            (1 << 28)
 #define OMAP4_USIM_PBIASLITE_VMODE_SHIFT            27
 #define OMAP4_USIM_PBIASLITE_VMODE_MASK             (1 << 27)
 #define OMAP4_MMC1_PWRDNZ_SHIFT                 26
 #define OMAP4_MMC1_PWRDNZ_MASK                  (1 << 26)
 #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT         25
 #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK          (1 << 25)
 #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT        24
 #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK         (1 << 24)
 #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT          23
 #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK           (1 << 23)
 #define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT           22
 #define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK            (1 << 22)
 #define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT            21
 #define OMAP4_MMC1_PBIASLITE_VMODE_MASK             (1 << 21)
 #define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT              20
 #define OMAP4_USBC1_ICUSB_PWRDNZ_MASK               (1 << 20)
 
 /* CONTROL_I2C_0 */
 #define OMAP4_I2C4_SDA_GLFENB_SHIFT             31
 #define OMAP4_I2C4_SDA_GLFENB_MASK              (1 << 31)
 #define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT              29
 #define OMAP4_I2C4_SDA_LOAD_BITS_MASK               (0x3 << 29)
 #define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT             28
 #define OMAP4_I2C4_SDA_PULLUPRESX_MASK              (1 << 28)
 #define OMAP4_I2C3_SDA_GLFENB_SHIFT             27
 #define OMAP4_I2C3_SDA_GLFENB_MASK              (1 << 27)
 #define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT              25
 #define OMAP4_I2C3_SDA_LOAD_BITS_MASK               (0x3 << 25)
 #define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT             24
 #define OMAP4_I2C3_SDA_PULLUPRESX_MASK              (1 << 24)
 #define OMAP4_I2C2_SDA_GLFENB_SHIFT             23
 #define OMAP4_I2C2_SDA_GLFENB_MASK              (1 << 23)
 #define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT              21
 #define OMAP4_I2C2_SDA_LOAD_BITS_MASK               (0x3 << 21)
 #define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT             20
 #define OMAP4_I2C2_SDA_PULLUPRESX_MASK              (1 << 20)
 #define OMAP4_I2C1_SDA_GLFENB_SHIFT             19
 #define OMAP4_I2C1_SDA_GLFENB_MASK              (1 << 19)
 #define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT              17
 #define OMAP4_I2C1_SDA_LOAD_BITS_MASK               (0x3 << 17)
 #define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT             16
 #define OMAP4_I2C1_SDA_PULLUPRESX_MASK              (1 << 16)
 #define OMAP4_I2C4_SCL_GLFENB_SHIFT             15
 #define OMAP4_I2C4_SCL_GLFENB_MASK              (1 << 15)
 #define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT              13
 #define OMAP4_I2C4_SCL_LOAD_BITS_MASK               (0x3 << 13)
 #define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT             12
 #define OMAP4_I2C4_SCL_PULLUPRESX_MASK              (1 << 12)
 #define OMAP4_I2C3_SCL_GLFENB_SHIFT             11
 #define OMAP4_I2C3_SCL_GLFENB_MASK              (1 << 11)
 #define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT              9
 #define OMAP4_I2C3_SCL_LOAD_BITS_MASK               (0x3 << 9)
 #define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT             8
 #define OMAP4_I2C3_SCL_PULLUPRESX_MASK              (1 << 8)
 #define OMAP4_I2C2_SCL_GLFENB_SHIFT             7
 #define OMAP4_I2C2_SCL_GLFENB_MASK              (1 << 7)
 #define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT              5
 #define OMAP4_I2C2_SCL_LOAD_BITS_MASK               (0x3 << 5)
 #define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT             4
 #define OMAP4_I2C2_SCL_PULLUPRESX_MASK              (1 << 4)
 #define OMAP4_I2C1_SCL_GLFENB_SHIFT             3
 #define OMAP4_I2C1_SCL_GLFENB_MASK              (1 << 3)
 #define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT              1
 #define OMAP4_I2C1_SCL_LOAD_BITS_MASK               (0x3 << 1)
 #define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT             0
 #define OMAP4_I2C1_SCL_PULLUPRESX_MASK              (1 << 0)
 
 /* CONTROL_CAMERA_RX */
 #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT           31
 #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK            (1 << 31)
 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT           29
 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK            (0x3 << 29)
 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT           24
 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK            (0x1f << 24)
 #define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT         22
 #define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK          (0x3 << 22)
 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT            21
 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK         (1 << 21)
 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT          19
 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK           (0x3 << 19)
 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT            18
 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK         (1 << 18)
 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT          16
 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK           (0x3 << 16)
 
 /* CONTROL_AVDAC */
 #define OMAP4_AVDAC_ACEN_SHIFT                  31
 #define OMAP4_AVDAC_ACEN_MASK                   (1 << 31)
 #define OMAP4_AVDAC_TVOUTBYPASS_SHIFT               30
 #define OMAP4_AVDAC_TVOUTBYPASS_MASK                (1 << 30)
 #define OMAP4_AVDAC_INPUTINV_SHIFT              29
 #define OMAP4_AVDAC_INPUTINV_MASK               (1 << 29)
 #define OMAP4_AVDAC_CTL_SHIFT                   13
 #define OMAP4_AVDAC_CTL_MASK                    (0xffff << 13)
 #define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                12
 #define OMAP4_AVDAC_CTL_WR_ACK_MASK             (1 << 12)
 
 /* CONTROL_HDMI_TX_PHY */
 #define OMAP4_HDMITXPHY_PADORDER_SHIFT              31
 #define OMAP4_HDMITXPHY_PADORDER_MASK               (1 << 31)
 #define OMAP4_HDMITXPHY_TXVALID_SHIFT               30
 #define OMAP4_HDMITXPHY_TXVALID_MASK                (1 << 30)
 #define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT           29
 #define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK            (1 << 29)
 #define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT          28
 #define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK           (1 << 28)
 
 /* CONTROL_MMC2 */
 #define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT           31
 #define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK            (1 << 31)
 
 /* CONTROL_DSIPHY */
 #define OMAP4_DSI2_LANEENABLE_SHIFT             29
 #define OMAP4_DSI2_LANEENABLE_MASK              (0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT             24
 #define OMAP4_DSI1_LANEENABLE_MASK              (0x1f << 24)
 #define OMAP4_DSI1_PIPD_SHIFT                   19
 #define OMAP4_DSI1_PIPD_MASK                    (0x1f << 19)
 #define OMAP4_DSI2_PIPD_SHIFT                   14
 #define OMAP4_DSI2_PIPD_MASK                    (0x1f << 14)
 
 /* CONTROL_MCBSPLP */
 #define OMAP4_ALBCTRLRX_FSX_SHIFT               31
 #define OMAP4_ALBCTRLRX_FSX_MASK                (1 << 31)
 #define OMAP4_ALBCTRLRX_CLKX_SHIFT              30
 #define OMAP4_ALBCTRLRX_CLKX_MASK               (1 << 30)
 #define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                29
 #define OMAP4_ABE_MCBSP1_DR_EN_MASK             (1 << 29)
 
 /* CONTROL_USB2PHYCORE */
 #define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT           31
 #define OMAP4_USB2PHY_AUTORESUME_EN_MASK            (1 << 31)
 #define OMAP4_USB2PHY_DISCHGDET_SHIFT               30
 #define OMAP4_USB2PHY_DISCHGDET_MASK                (1 << 30)
 #define OMAP4_USB2PHY_GPIOMODE_SHIFT                29
 #define OMAP4_USB2PHY_GPIOMODE_MASK             (1 << 29)
 #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT         28
 #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK          (1 << 28)
 #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT            27
 #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK         (1 << 27)
 #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT            26
 #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK         (1 << 26)
 #define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT             25
 #define OMAP4_USB2PHY_CHG_VSRC_EN_MASK              (1 << 25)
 #define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT            24
 #define OMAP4_USB2PHY_CHG_ISINK_EN_MASK             (1 << 24)
 #define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT          21
 #define OMAP4_USB2PHY_CHG_DET_STATUS_MASK           (0x7 << 21)
 #define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT         20
 #define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK          (1 << 20)
 #define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT         19
 #define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK          (1 << 19)
 #define OMAP4_USB2PHY_DATADET_SHIFT             18
 #define OMAP4_USB2PHY_DATADET_MASK              (1 << 18)
 #define OMAP4_USB2PHY_SINKONDP_SHIFT                17
 #define OMAP4_USB2PHY_SINKONDP_MASK             (1 << 17)
 #define OMAP4_USB2PHY_SRCONDM_SHIFT             16
 #define OMAP4_USB2PHY_SRCONDM_MASK              (1 << 16)
 #define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT           15
 #define OMAP4_USB2PHY_RESTARTCHGDET_MASK            (1 << 15)
 #define OMAP4_USB2PHY_CHGDETDONE_SHIFT              14
 #define OMAP4_USB2PHY_CHGDETDONE_MASK               (1 << 14)
 #define OMAP4_USB2PHY_CHGDETECTED_SHIFT             13
 #define OMAP4_USB2PHY_CHGDETECTED_MASK              (1 << 13)
 #define OMAP4_USB2PHY_MCPCPUEN_SHIFT                12
 #define OMAP4_USB2PHY_MCPCPUEN_MASK             (1 << 12)
 #define OMAP4_USB2PHY_MCPCMODEEN_SHIFT              11
 #define OMAP4_USB2PHY_MCPCMODEEN_MASK               (1 << 11)
 #define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT           10
 #define OMAP4_USB2PHY_RESETDONEMCLK_MASK            (1 << 10)
 #define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT           9
 #define OMAP4_USB2PHY_UTMIRESETDONE_MASK            (1 << 9)
 #define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT            8
 #define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK         (1 << 8)
 #define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT           7
 #define OMAP4_USB2PHY_DATAPOLARITYN_MASK            (1 << 7)
 #define OMAP4_USBDPLL_FREQLOCK_SHIFT                6
 #define OMAP4_USBDPLL_FREQLOCK_MASK             (1 << 6)
 #define OMAP4_USB2PHY_RESETDONETCLK_SHIFT           5
 #define OMAP4_USB2PHY_RESETDONETCLK_MASK            (1 << 5)
 
 /* CONTROL_I2C_1 */
 #define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT             31
 #define OMAP4_HDMI_DDC_SDA_GLFENB_MASK              (1 << 31)
 #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT          29
 #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK           (0x3 << 29)
 #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT         28
 #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK          (1 << 28)
 #define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT             27
 #define OMAP4_HDMI_DDC_SCL_GLFENB_MASK              (1 << 27)
 #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT          25
 #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK           (0x3 << 25)
 #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT         24
 #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK          (1 << 24)
 #define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT             23
 #define OMAP4_HDMI_DDC_SDA_HSMODE_MASK              (1 << 23)
 #define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT              22
 #define OMAP4_HDMI_DDC_SDA_NMODE_MASK               (1 << 22)
 #define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT             21
 #define OMAP4_HDMI_DDC_SCL_HSMODE_MASK              (1 << 21)
 #define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT              20
 #define OMAP4_HDMI_DDC_SCL_NMODE_MASK               (1 << 20)
 
 /* CONTROL_MMC1 */
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT          31
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK           (1 << 31)
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT          30
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK           (1 << 30)
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT          29
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK           (1 << 29)
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT          28
 #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK           (1 << 28)
 #define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT            27
 #define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK             (1 << 27)
 #define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT            26
 #define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK             (1 << 26)
 #define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT            25
 #define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK             (1 << 25)
 #define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT             24
 #define OMAP4_USBC1_DR0_SPEEDCTRL_MASK              (1 << 24)
 #define OMAP4_USB_FD_CDEN_SHIFT                 23
 #define OMAP4_USB_FD_CDEN_MASK                  (1 << 23)
 #define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT            22
 #define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK             (1 << 22)
 #define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT            21
 #define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK             (1 << 21)
 
 /* CONTROL_HSI */
 #define OMAP4_HSI1_CALLOOP_SEL_SHIFT                31
 #define OMAP4_HSI1_CALLOOP_SEL_MASK             (1 << 31)
 #define OMAP4_HSI1_CALMUX_SEL_SHIFT             30
 #define OMAP4_HSI1_CALMUX_SEL_MASK              (1 << 30)
 #define OMAP4_HSI2_CALLOOP_SEL_SHIFT                29
 #define OMAP4_HSI2_CALLOOP_SEL_MASK             (1 << 29)
 #define OMAP4_HSI2_CALMUX_SEL_SHIFT             28
 #define OMAP4_HSI2_CALMUX_SEL_MASK              (1 << 28)
 
 /* CONTROL_USB */
 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT       31
 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK        (1 << 31)
 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT       30
 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK        (1 << 30)
 
 /* CONTROL_HDQ */
 #define OMAP4_HDQ_SIO_PWRDNZ_SHIFT              31
 #define OMAP4_HDQ_SIO_PWRDNZ_MASK               (1 << 31)
 
 /* CONTROL_LPDDR2IO1_0 */
 #define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                30
 #define OMAP4_LPDDR2IO1_GR4_SR_MASK             (0x3 << 30)
 #define OMAP4_LPDDR2IO1_GR4_I_SHIFT             27
 #define OMAP4_LPDDR2IO1_GR4_I_MASK              (0x7 << 27)
 #define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                25
 #define OMAP4_LPDDR2IO1_GR4_WD_MASK             (0x3 << 25)
 #define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                22
 #define OMAP4_LPDDR2IO1_GR3_SR_MASK             (0x3 << 22)
 #define OMAP4_LPDDR2IO1_GR3_I_SHIFT             19
 #define OMAP4_LPDDR2IO1_GR3_I_MASK              (0x7 << 19)
 #define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                17
 #define OMAP4_LPDDR2IO1_GR3_WD_MASK             (0x3 << 17)
 #define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                14
 #define OMAP4_LPDDR2IO1_GR2_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO1_GR2_I_SHIFT             11
 #define OMAP4_LPDDR2IO1_GR2_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                9
 #define OMAP4_LPDDR2IO1_GR2_WD_MASK             (0x3 << 9)
 #define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                6
 #define OMAP4_LPDDR2IO1_GR1_SR_MASK             (0x3 << 6)
 #define OMAP4_LPDDR2IO1_GR1_I_SHIFT             3
 #define OMAP4_LPDDR2IO1_GR1_I_MASK              (0x7 << 3)
 #define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                1
 #define OMAP4_LPDDR2IO1_GR1_WD_MASK             (0x3 << 1)
 
 /* CONTROL_LPDDR2IO1_1 */
 #define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                30
 #define OMAP4_LPDDR2IO1_GR8_SR_MASK             (0x3 << 30)
 #define OMAP4_LPDDR2IO1_GR8_I_SHIFT             27
 #define OMAP4_LPDDR2IO1_GR8_I_MASK              (0x7 << 27)
 #define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                25
 #define OMAP4_LPDDR2IO1_GR8_WD_MASK             (0x3 << 25)
 #define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                22
 #define OMAP4_LPDDR2IO1_GR7_SR_MASK             (0x3 << 22)
 #define OMAP4_LPDDR2IO1_GR7_I_SHIFT             19
 #define OMAP4_LPDDR2IO1_GR7_I_MASK              (0x7 << 19)
 #define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                17
 #define OMAP4_LPDDR2IO1_GR7_WD_MASK             (0x3 << 17)
 #define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                14
 #define OMAP4_LPDDR2IO1_GR6_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO1_GR6_I_SHIFT             11
 #define OMAP4_LPDDR2IO1_GR6_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                9
 #define OMAP4_LPDDR2IO1_GR6_WD_MASK             (0x3 << 9)
 #define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                6
 #define OMAP4_LPDDR2IO1_GR5_SR_MASK             (0x3 << 6)
 #define OMAP4_LPDDR2IO1_GR5_I_SHIFT             3
 #define OMAP4_LPDDR2IO1_GR5_I_MASK              (0x7 << 3)
 #define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                1
 #define OMAP4_LPDDR2IO1_GR5_WD_MASK             (0x3 << 1)
 
 /* CONTROL_LPDDR2IO1_2 */
 #define OMAP4_LPDDR2IO1_GR11_SR_SHIFT               30
 #define OMAP4_LPDDR2IO1_GR11_SR_MASK                (0x3 << 30)
 #define OMAP4_LPDDR2IO1_GR11_I_SHIFT                27
 #define OMAP4_LPDDR2IO1_GR11_I_MASK             (0x7 << 27)
 #define OMAP4_LPDDR2IO1_GR11_WD_SHIFT               25
 #define OMAP4_LPDDR2IO1_GR11_WD_MASK                (0x3 << 25)
 #define OMAP4_LPDDR2IO1_GR10_SR_SHIFT               22
 #define OMAP4_LPDDR2IO1_GR10_SR_MASK                (0x3 << 22)
 #define OMAP4_LPDDR2IO1_GR10_I_SHIFT                19
 #define OMAP4_LPDDR2IO1_GR10_I_MASK             (0x7 << 19)
 #define OMAP4_LPDDR2IO1_GR10_WD_SHIFT               17
 #define OMAP4_LPDDR2IO1_GR10_WD_MASK                (0x3 << 17)
 #define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                14
 #define OMAP4_LPDDR2IO1_GR9_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO1_GR9_I_SHIFT             11
 #define OMAP4_LPDDR2IO1_GR9_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                9
 #define OMAP4_LPDDR2IO1_GR9_WD_MASK             (0x3 << 9)
 
 /* CONTROL_LPDDR2IO1_3 */
 #define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT           31
 #define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK            (1 << 31)
 #define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT           30
 #define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK            (1 << 30)
 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT           29
 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK            (1 << 29)
 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT           28
 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK            (1 << 28)
 #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT            27
 #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK         (1 << 27)
 #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT            26
 #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK         (1 << 26)
 #define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT            25
 #define OMAP4_LPDDR21_VREF_CA_TAP0_MASK             (1 << 25)
 #define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT            24
 #define OMAP4_LPDDR21_VREF_CA_TAP1_MASK             (1 << 24)
 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT          23
 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK           (1 << 23)
 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT          22
 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK           (1 << 22)
 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT           21
 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK            (1 << 21)
 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT           20
 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK            (1 << 20)
 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT          19
 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK           (1 << 19)
 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT          18
 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK           (1 << 18)
 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT           17
 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK            (1 << 17)
 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT           16
 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK            (1 << 16)
 #define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT           15
 #define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK            (1 << 15)
 #define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT           14
 #define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK            (1 << 14)
 #define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT            13
 #define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK             (1 << 13)
 #define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT            12
 #define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK             (1 << 12)
 
 /* CONTROL_LPDDR2IO2_0 */
 #define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                30
 #define OMAP4_LPDDR2IO2_GR4_SR_MASK             (0x3 << 30)
 #define OMAP4_LPDDR2IO2_GR4_I_SHIFT             27
 #define OMAP4_LPDDR2IO2_GR4_I_MASK              (0x7 << 27)
 #define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                25
 #define OMAP4_LPDDR2IO2_GR4_WD_MASK             (0x3 << 25)
 #define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                22
 #define OMAP4_LPDDR2IO2_GR3_SR_MASK             (0x3 << 22)
 #define OMAP4_LPDDR2IO2_GR3_I_SHIFT             19
 #define OMAP4_LPDDR2IO2_GR3_I_MASK              (0x7 << 19)
 #define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                17
 #define OMAP4_LPDDR2IO2_GR3_WD_MASK             (0x3 << 17)
 #define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                14
 #define OMAP4_LPDDR2IO2_GR2_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO2_GR2_I_SHIFT             11
 #define OMAP4_LPDDR2IO2_GR2_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                9
 #define OMAP4_LPDDR2IO2_GR2_WD_MASK             (0x3 << 9)
 #define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                6
 #define OMAP4_LPDDR2IO2_GR1_SR_MASK             (0x3 << 6)
 #define OMAP4_LPDDR2IO2_GR1_I_SHIFT             3
 #define OMAP4_LPDDR2IO2_GR1_I_MASK              (0x7 << 3)
 #define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                1
 #define OMAP4_LPDDR2IO2_GR1_WD_MASK             (0x3 << 1)
 
 /* CONTROL_LPDDR2IO2_1 */
 #define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                30
 #define OMAP4_LPDDR2IO2_GR8_SR_MASK             (0x3 << 30)
 #define OMAP4_LPDDR2IO2_GR8_I_SHIFT             27
 #define OMAP4_LPDDR2IO2_GR8_I_MASK              (0x7 << 27)
 #define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                25
 #define OMAP4_LPDDR2IO2_GR8_WD_MASK             (0x3 << 25)
 #define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                22
 #define OMAP4_LPDDR2IO2_GR7_SR_MASK             (0x3 << 22)
 #define OMAP4_LPDDR2IO2_GR7_I_SHIFT             19
 #define OMAP4_LPDDR2IO2_GR7_I_MASK              (0x7 << 19)
 #define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                17
 #define OMAP4_LPDDR2IO2_GR7_WD_MASK             (0x3 << 17)
 #define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                14
 #define OMAP4_LPDDR2IO2_GR6_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO2_GR6_I_SHIFT             11
 #define OMAP4_LPDDR2IO2_GR6_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                9
 #define OMAP4_LPDDR2IO2_GR6_WD_MASK             (0x3 << 9)
 #define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                6
 #define OMAP4_LPDDR2IO2_GR5_SR_MASK             (0x3 << 6)
 #define OMAP4_LPDDR2IO2_GR5_I_SHIFT             3
 #define OMAP4_LPDDR2IO2_GR5_I_MASK              (0x7 << 3)
 #define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                1
 #define OMAP4_LPDDR2IO2_GR5_WD_MASK             (0x3 << 1)
 
 /* CONTROL_LPDDR2IO2_2 */
 #define OMAP4_LPDDR2IO2_GR11_SR_SHIFT               30
 #define OMAP4_LPDDR2IO2_GR11_SR_MASK                (0x3 << 30)
 #define OMAP4_LPDDR2IO2_GR11_I_SHIFT                27
 #define OMAP4_LPDDR2IO2_GR11_I_MASK             (0x7 << 27)
 #define OMAP4_LPDDR2IO2_GR11_WD_SHIFT               25
 #define OMAP4_LPDDR2IO2_GR11_WD_MASK                (0x3 << 25)
 #define OMAP4_LPDDR2IO2_GR10_SR_SHIFT               22
 #define OMAP4_LPDDR2IO2_GR10_SR_MASK                (0x3 << 22)
 #define OMAP4_LPDDR2IO2_GR10_I_SHIFT                19
 #define OMAP4_LPDDR2IO2_GR10_I_MASK             (0x7 << 19)
 #define OMAP4_LPDDR2IO2_GR10_WD_SHIFT               17
 #define OMAP4_LPDDR2IO2_GR10_WD_MASK                (0x3 << 17)
 #define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                14
 #define OMAP4_LPDDR2IO2_GR9_SR_MASK             (0x3 << 14)
 #define OMAP4_LPDDR2IO2_GR9_I_SHIFT             11
 #define OMAP4_LPDDR2IO2_GR9_I_MASK              (0x7 << 11)
 #define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                9
 #define OMAP4_LPDDR2IO2_GR9_WD_MASK             (0x3 << 9)
 
 /* CONTROL_LPDDR2IO2_3 */
 #define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT           31
 #define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK            (1 << 31)
 #define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT           30
 #define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK            (1 << 30)
 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT           29
 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK            (1 << 29)
 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT           28
 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK            (1 << 28)
 #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT            27
 #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK         (1 << 27)
 #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT            26
 #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK         (1 << 26)
 #define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT            25
 #define OMAP4_LPDDR22_VREF_CA_TAP0_MASK             (1 << 25)
 #define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT            24
 #define OMAP4_LPDDR22_VREF_CA_TAP1_MASK             (1 << 24)
 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT          23
 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK           (1 << 23)
 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT          22
 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK           (1 << 22)
 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT           21
 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK            (1 << 21)
 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT           20
 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK            (1 << 20)
 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT          19
 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK           (1 << 19)
 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT          18
 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK           (1 << 18)
 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT           17
 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK            (1 << 17)
 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT           16
 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK            (1 << 16)
 #define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT           15
 #define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK            (1 << 15)
 #define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT           14
 #define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK            (1 << 14)
 #define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT            13
 #define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK             (1 << 13)
 #define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT            12
 #define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK             (1 << 12)
 
 /* CONTROL_BUS_HOLD */
 #define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                31
 #define OMAP4_ABE_DMIC_DIN3_EN_MASK             (1 << 31)
 #define OMAP4_MCSPI1_CS3_EN_SHIFT               30
 #define OMAP4_MCSPI1_CS3_EN_MASK                (1 << 30)
 
 /* CONTROL_C2C */
 #define OMAP4_MIRROR_MODE_EN_SHIFT              31
 #define OMAP4_MIRROR_MODE_EN_MASK               (1 << 31)
 #define OMAP4_C2C_SPARE_SHIFT                   24
 #define OMAP4_C2C_SPARE_MASK                    (0x7f << 24)
 
 /* CORE_CONTROL_SPARE_RW */
 #define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT           0
 #define OMAP4_CORE_CONTROL_SPARE_RW_MASK            (0xffffffff << 0)
 
 /* CORE_CONTROL_SPARE_R */
 #define OMAP4_CORE_CONTROL_SPARE_R_SHIFT            0
 #define OMAP4_CORE_CONTROL_SPARE_R_MASK             (0xffffffff << 0)
 
 /* CORE_CONTROL_SPARE_R_C0 */
 #define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT         31
 #define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK          (1 << 31)
 #define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT         30
 #define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK          (1 << 30)
 #define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT         29
 #define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK          (1 << 29)
 #define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT         28
 #define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK          (1 << 28)
 #define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT         27
 #define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK          (1 << 27)
 #define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT         26
 #define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK          (1 << 26)
 #define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT         25
 #define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK          (1 << 25)
 #define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT         24
 #define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK          (1 << 24)
 
 /* CONTROL_EFUSE_1 */
 #define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                24
 #define OMAP4_AVDAC_TRIM_BYTE3_MASK             (0x7f << 24)
 #define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                16
 #define OMAP4_AVDAC_TRIM_BYTE2_MASK             (0xff << 16)
 #define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                8
 #define OMAP4_AVDAC_TRIM_BYTE1_MASK             (0xff << 8)
 #define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                0
 #define OMAP4_AVDAC_TRIM_BYTE0_MASK             (0xff << 0)
 
 /* CONTROL_EFUSE_2 */
 #define OMAP4_EFUSE_SMART2TEST_P0_SHIFT             31
 #define OMAP4_EFUSE_SMART2TEST_P0_MASK              (1 << 31)
 #define OMAP4_EFUSE_SMART2TEST_P1_SHIFT             30
 #define OMAP4_EFUSE_SMART2TEST_P1_MASK              (1 << 30)
 #define OMAP4_EFUSE_SMART2TEST_P2_SHIFT             29
 #define OMAP4_EFUSE_SMART2TEST_P2_MASK              (1 << 29)
 #define OMAP4_EFUSE_SMART2TEST_P3_SHIFT             28
 #define OMAP4_EFUSE_SMART2TEST_P3_MASK              (1 << 28)
 #define OMAP4_EFUSE_SMART2TEST_N0_SHIFT             27
 #define OMAP4_EFUSE_SMART2TEST_N0_MASK              (1 << 27)
 #define OMAP4_EFUSE_SMART2TEST_N1_SHIFT             26
 #define OMAP4_EFUSE_SMART2TEST_N1_MASK              (1 << 26)
 #define OMAP4_EFUSE_SMART2TEST_N2_SHIFT             25
 #define OMAP4_EFUSE_SMART2TEST_N2_MASK              (1 << 25)
 #define OMAP4_EFUSE_SMART2TEST_N3_SHIFT             24
 #define OMAP4_EFUSE_SMART2TEST_N3_MASK              (1 << 24)
 #define OMAP4_LPDDR2_PTV_N1_SHIFT               23
 #define OMAP4_LPDDR2_PTV_N1_MASK                (1 << 23)
 #define OMAP4_LPDDR2_PTV_N2_SHIFT               22
 #define OMAP4_LPDDR2_PTV_N2_MASK                (1 << 22)
 #define OMAP4_LPDDR2_PTV_N3_SHIFT               21
 #define OMAP4_LPDDR2_PTV_N3_MASK                (1 << 21)
 #define OMAP4_LPDDR2_PTV_N4_SHIFT               20
 #define OMAP4_LPDDR2_PTV_N4_MASK                (1 << 20)
 #define OMAP4_LPDDR2_PTV_N5_SHIFT               19
 #define OMAP4_LPDDR2_PTV_N5_MASK                (1 << 19)
 #define OMAP4_LPDDR2_PTV_P1_SHIFT               18
 #define OMAP4_LPDDR2_PTV_P1_MASK                (1 << 18)
 #define OMAP4_LPDDR2_PTV_P2_SHIFT               17
 #define OMAP4_LPDDR2_PTV_P2_MASK                (1 << 17)
 #define OMAP4_LPDDR2_PTV_P3_SHIFT               16
 #define OMAP4_LPDDR2_PTV_P3_MASK                (1 << 16)
 #define OMAP4_LPDDR2_PTV_P4_SHIFT               15
 #define OMAP4_LPDDR2_PTV_P4_MASK                (1 << 15)
 #define OMAP4_LPDDR2_PTV_P5_SHIFT               14
 #define OMAP4_LPDDR2_PTV_P5_MASK                (1 << 14)
 
 /* CONTROL_EFUSE_3 */
 #define OMAP4_STD_FUSE_SPARE_1_SHIFT                24
 #define OMAP4_STD_FUSE_SPARE_1_MASK             (0xff << 24)
 #define OMAP4_STD_FUSE_SPARE_2_SHIFT                16
 #define OMAP4_STD_FUSE_SPARE_2_MASK             (0xff << 16)
 #define OMAP4_STD_FUSE_SPARE_3_SHIFT                8
 #define OMAP4_STD_FUSE_SPARE_3_MASK             (0xff << 8)
 #define OMAP4_STD_FUSE_SPARE_4_SHIFT                0
 #define OMAP4_STD_FUSE_SPARE_4_MASK             (0xff << 0)
 
 /* CONTROL_EFUSE_4 */
 #define OMAP4_STD_FUSE_SPARE_5_SHIFT                24
 #define OMAP4_STD_FUSE_SPARE_5_MASK             (0xff << 24)
 #define OMAP4_STD_FUSE_SPARE_6_SHIFT                16
 #define OMAP4_STD_FUSE_SPARE_6_MASK             (0xff << 16)
 #define OMAP4_STD_FUSE_SPARE_7_SHIFT                8
 #define OMAP4_STD_FUSE_SPARE_7_MASK             (0xff << 8)
 #define OMAP4_STD_FUSE_SPARE_8_SHIFT                0
 #define OMAP4_STD_FUSE_SPARE_8_MASK             (0xff << 0)
 
 #endif