26 static u8 *bridge_base;
30 u32 i,
v[30], enables, acc_bits;
32 unsigned long cpu_base;
34 void *devp, *mv64x60_devp;
35 u8 *bridge_pbase, is_coherent;
54 mv64x60_devp = find_node_by_compatible(
NULL,
"marvell,mv64360");
55 if (mv64x60_devp ==
NULL)
56 fatal(
"Error: Missing marvell,mv64360 device tree node\n\r");
59 enables |= 0x007ffe00;
64 for (bus = 0; ; bus++) {
67 name[
strlen(name)-1] = bus+
'0';
69 devp = find_node_by_alias(name);
74 fatal(
"Error: Only 2 PCI controllers are supported at" \
80 rc = getprop(devp,
"ranges", v,
sizeof(v));
82 fatal(
"Error: Can't find marvell,mv64360-pci ranges"
87 for (i = 0; i <
rc; i += 6) {
88 switch (v[i] & 0xff000000) {
100 pci_base_lo = v[i+2];
108 fatal(
"Error: Can't translate PCI address " \
109 "0x%x\n\r", (
u32)cpu_base);
112 pci_base_hi, pci_base_lo, cpu_base, size, tbl);
115 enables &= ~(3<<(9+bus*5));
122 static void c2k_fixups(
void)
127 c2k_bridge_setup(mem_size);
130 #define MV64x60_MPP_CNTL_0 0xf000
131 #define MV64x60_MPP_CNTL_2 0xf008
132 #define MV64x60_GPP_IO_CNTL 0xf100
133 #define MV64x60_GPP_LEVEL_CNTL 0xf110
134 #define MV64x60_GPP_VALUE_SET 0xf118
136 static void c2k_reset(
void)
142 if (bridge_base != 0) {
177 unsigned long r6,
unsigned long r7)