Go to the source code of this file.
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u32 | mv64x60_cfg_read (u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) |
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void | mv64x60_cfg_write (u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, u32 val) |
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void | mv64x60_config_ctlr_windows (u8 *bridge_base, u8 *bridge_pbase, u8 is_coherent) |
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void | mv64x60_config_pci_windows (u8 *bridge_base, u8 *bridge_pbase, u8 hose, u8 bus, u32 mem_size, u32 acc_bits) |
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void | mv64x60_config_cpu2pci_window (u8 *bridge_base, u8 hose, u32 pci_base_hi, u32 pci_base_lo, u32 cpu_base, u32 size, struct mv64x60_cpu2pci_win *offset_tbl) |
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u32 | mv64x60_get_mem_size (u8 *bridge_base) |
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u8 * | mv64x60_get_bridge_pbase (void) |
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u8 * | mv64x60_get_bridge_base (void) |
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u8 | mv64x60_is_coherent (void) |
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int | mv64x60_i2c_open (void) |
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int | mv64x60_i2c_read (u32 devaddr, u8 *buf, u32 offset, u32 offset_size, u32 count) |
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void | mv64x60_i2c_close (void) |
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#define MV64x60_CPU_BAR_ENABLE 0x0278 |
#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4) |
#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0) |
#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 |
#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 |
#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 |
#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300 |
#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 |
#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 |
#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 |
#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 |
#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 |
#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1) |
#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c |
#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 |
#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008 |
#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004 |
#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 |
#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 |
#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 |
#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040 |
#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 |
#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5) |
u32 mv64x60_cfg_read |
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u8 * |
bridge_base, |
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u8 |
hose, |
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u8 |
bus, |
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u8 |
devfn, |
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u8 |
offset |
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) |
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void mv64x60_cfg_write |
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u8 * |
bridge_base, |
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u8 |
hose, |
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u8 |
bus, |
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u8 |
devfn, |
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u8 |
offset, |
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u32 |
val |
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) |
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void mv64x60_config_ctlr_windows |
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u8 * |
bridge_base, |
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u8 * |
bridge_pbase, |
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u8 |
is_coherent |
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) |
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void mv64x60_config_pci_windows |
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u8 * |
bridge_base, |
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u8 * |
bridge_pbase, |
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u8 |
hose, |
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u8 |
bus, |
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u32 |
mem_size, |
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u32 |
acc_bits |
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) |
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u8* mv64x60_get_bridge_base |
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void |
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u8* mv64x60_get_bridge_pbase |
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void |
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u32 mv64x60_get_mem_size |
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u8 * |
bridge_base | ) |
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int mv64x60_i2c_read |
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u32 |
devaddr, |
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u8 * |
buf, |
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u32 |
offset, |
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u32 |
offset_size, |
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u32 |
count |
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) |
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u8 mv64x60_is_coherent |
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void |
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