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cvmx-ciu2-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
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15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_CIU2_DEFS_H__
29 #define __CVMX_CIU2_DEFS_H__
30 
31 #define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
32 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
33 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
34 #define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
35 #define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
36 #define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
37 #define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
38 #define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
39 #define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
40 #define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
41 #define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
42 #define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
43 #define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
44 #define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
45 #define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
46 #define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
47 #define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
48 #define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
49 #define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
50 #define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
51 #define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
52 #define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
53 #define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
54 #define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
55 #define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
56 #define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
57 #define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
58 #define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
59 #define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
60 #define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
61 #define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
62 #define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
63 #define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
64 #define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
65 #define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
66 #define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
67 #define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
68 #define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
69 #define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
70 #define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
71 #define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
72 #define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
73 #define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
74 #define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
75 #define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
76 #define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
77 #define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
78 #define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
79 #define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
80 #define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
81 #define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
82 #define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
83 #define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
84 #define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
85 #define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
86 #define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
87 #define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
88 #define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
89 #define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
90 #define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
91 #define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
92 #define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
93 #define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
94 #define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
95 #define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
96 #define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
97 #define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
98 #define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
99 #define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
100 #define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
101 #define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
102 #define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
103 #define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
104 #define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
105 #define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
106 #define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
107 #define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
108 #define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
109 #define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
110 #define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
111 #define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
112 #define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
113 #define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
114 #define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
115 #define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
116 #define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
117 #define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
118 #define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
119 #define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
120 #define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
121 #define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
122 #define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
123 #define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
124 #define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
125 #define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
126 #define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
127 #define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
128 #define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
129 #define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
130 #define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
131 #define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
132 #define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
133 #define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
134 #define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
135 #define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
136 #define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
137 #define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
138 #define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
139 #define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
140 #define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
141 #define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
142 #define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
143 #define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
144 #define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
145 #define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
146 #define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
147 #define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
148 #define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
149 #define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
150 #define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
151 #define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
152 #define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
153 #define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
154 #define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
155 #define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
156 #define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
157 #define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
158 #define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
159 #define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
160 #define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
161 #define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
162 #define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
163 #define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
164 #define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
165 #define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
166 #define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
167 #define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
168 #define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
169 #define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
170 #define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
171 #define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
172 #define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
173 #define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
174 #define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
175 #define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
176 #define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
177 #define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
178 #define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
179 #define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
180 #define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
181 #define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
182 #define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
183 #define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
184 #define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
185 #define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
186 #define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
187 #define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
188 #define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
189 #define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
190 #define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
191 #define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
192 #define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
193 #define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
194 #define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
195 #define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
196 #define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
197 #define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
198 #define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
199 #define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
200 #define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
201 #define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
202 #define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
203 #define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
204 #define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
205 #define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
206 #define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
207 #define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
208 #define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
209 #define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
210 #define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
211 #define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
212 #define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
213 #define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
214 #define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
215 #define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
216 #define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
217 #define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
218 #define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
219 #define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
220 #define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
221 #define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
222 #define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
223 #define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
224 
225 union cvmx_ciu2_ack_iox_int {
226  uint64_t u64;
227  struct cvmx_ciu2_ack_iox_int_s {
228 #ifdef __BIG_ENDIAN_BITFIELD
229  uint64_t reserved_1_63:63;
230  uint64_t ack:1;
231 #else
232  uint64_t ack:1;
233  uint64_t reserved_1_63:63;
234 #endif
235  } s;
236  struct cvmx_ciu2_ack_iox_int_s cn68xx;
237  struct cvmx_ciu2_ack_iox_int_s cn68xxp1;
238 };
239 
240 union cvmx_ciu2_ack_ppx_ip2 {
241  uint64_t u64;
242  struct cvmx_ciu2_ack_ppx_ip2_s {
243 #ifdef __BIG_ENDIAN_BITFIELD
244  uint64_t reserved_1_63:63;
245  uint64_t ack:1;
246 #else
247  uint64_t ack:1;
248  uint64_t reserved_1_63:63;
249 #endif
250  } s;
251  struct cvmx_ciu2_ack_ppx_ip2_s cn68xx;
252  struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1;
253 };
254 
255 union cvmx_ciu2_ack_ppx_ip3 {
256  uint64_t u64;
257  struct cvmx_ciu2_ack_ppx_ip3_s {
258 #ifdef __BIG_ENDIAN_BITFIELD
259  uint64_t reserved_1_63:63;
260  uint64_t ack:1;
261 #else
262  uint64_t ack:1;
263  uint64_t reserved_1_63:63;
264 #endif
265  } s;
266  struct cvmx_ciu2_ack_ppx_ip3_s cn68xx;
267  struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1;
268 };
269 
270 union cvmx_ciu2_ack_ppx_ip4 {
271  uint64_t u64;
272  struct cvmx_ciu2_ack_ppx_ip4_s {
273 #ifdef __BIG_ENDIAN_BITFIELD
274  uint64_t reserved_1_63:63;
275  uint64_t ack:1;
276 #else
277  uint64_t ack:1;
278  uint64_t reserved_1_63:63;
279 #endif
280  } s;
281  struct cvmx_ciu2_ack_ppx_ip4_s cn68xx;
282  struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1;
283 };
284 
285 union cvmx_ciu2_en_iox_int_gpio {
286  uint64_t u64;
287  struct cvmx_ciu2_en_iox_int_gpio_s {
288 #ifdef __BIG_ENDIAN_BITFIELD
289  uint64_t reserved_16_63:48;
290  uint64_t gpio:16;
291 #else
292  uint64_t gpio:16;
293  uint64_t reserved_16_63:48;
294 #endif
295  } s;
296  struct cvmx_ciu2_en_iox_int_gpio_s cn68xx;
297  struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1;
298 };
299 
300 union cvmx_ciu2_en_iox_int_gpio_w1c {
301  uint64_t u64;
302  struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
303 #ifdef __BIG_ENDIAN_BITFIELD
304  uint64_t reserved_16_63:48;
305  uint64_t gpio:16;
306 #else
307  uint64_t gpio:16;
308  uint64_t reserved_16_63:48;
309 #endif
310  } s;
311  struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
312  struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
313 };
314 
315 union cvmx_ciu2_en_iox_int_gpio_w1s {
316  uint64_t u64;
317  struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
318 #ifdef __BIG_ENDIAN_BITFIELD
319  uint64_t reserved_16_63:48;
320  uint64_t gpio:16;
321 #else
322  uint64_t gpio:16;
323  uint64_t reserved_16_63:48;
324 #endif
325  } s;
326  struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
327  struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
328 };
329 
330 union cvmx_ciu2_en_iox_int_io {
331  uint64_t u64;
332  struct cvmx_ciu2_en_iox_int_io_s {
333 #ifdef __BIG_ENDIAN_BITFIELD
334  uint64_t reserved_34_63:30;
335  uint64_t pem:2;
336  uint64_t reserved_18_31:14;
337  uint64_t pci_inta:2;
338  uint64_t reserved_13_15:3;
339  uint64_t msired:1;
340  uint64_t pci_msi:4;
341  uint64_t reserved_4_7:4;
342  uint64_t pci_intr:4;
343 #else
344  uint64_t pci_intr:4;
345  uint64_t reserved_4_7:4;
346  uint64_t pci_msi:4;
347  uint64_t msired:1;
348  uint64_t reserved_13_15:3;
349  uint64_t pci_inta:2;
350  uint64_t reserved_18_31:14;
351  uint64_t pem:2;
352  uint64_t reserved_34_63:30;
353 #endif
354  } s;
355  struct cvmx_ciu2_en_iox_int_io_s cn68xx;
356  struct cvmx_ciu2_en_iox_int_io_s cn68xxp1;
357 };
358 
359 union cvmx_ciu2_en_iox_int_io_w1c {
360  uint64_t u64;
361  struct cvmx_ciu2_en_iox_int_io_w1c_s {
362 #ifdef __BIG_ENDIAN_BITFIELD
363  uint64_t reserved_34_63:30;
364  uint64_t pem:2;
365  uint64_t reserved_18_31:14;
366  uint64_t pci_inta:2;
367  uint64_t reserved_13_15:3;
368  uint64_t msired:1;
369  uint64_t pci_msi:4;
370  uint64_t reserved_4_7:4;
371  uint64_t pci_intr:4;
372 #else
373  uint64_t pci_intr:4;
374  uint64_t reserved_4_7:4;
375  uint64_t pci_msi:4;
376  uint64_t msired:1;
377  uint64_t reserved_13_15:3;
378  uint64_t pci_inta:2;
379  uint64_t reserved_18_31:14;
380  uint64_t pem:2;
381  uint64_t reserved_34_63:30;
382 #endif
383  } s;
384  struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx;
385  struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1;
386 };
387 
388 union cvmx_ciu2_en_iox_int_io_w1s {
389  uint64_t u64;
390  struct cvmx_ciu2_en_iox_int_io_w1s_s {
391 #ifdef __BIG_ENDIAN_BITFIELD
392  uint64_t reserved_34_63:30;
393  uint64_t pem:2;
394  uint64_t reserved_18_31:14;
395  uint64_t pci_inta:2;
396  uint64_t reserved_13_15:3;
397  uint64_t msired:1;
398  uint64_t pci_msi:4;
399  uint64_t reserved_4_7:4;
400  uint64_t pci_intr:4;
401 #else
402  uint64_t pci_intr:4;
403  uint64_t reserved_4_7:4;
404  uint64_t pci_msi:4;
405  uint64_t msired:1;
406  uint64_t reserved_13_15:3;
407  uint64_t pci_inta:2;
408  uint64_t reserved_18_31:14;
409  uint64_t pem:2;
410  uint64_t reserved_34_63:30;
411 #endif
412  } s;
413  struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx;
414  struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1;
415 };
416 
417 union cvmx_ciu2_en_iox_int_mbox {
418  uint64_t u64;
419  struct cvmx_ciu2_en_iox_int_mbox_s {
420 #ifdef __BIG_ENDIAN_BITFIELD
421  uint64_t reserved_4_63:60;
422  uint64_t mbox:4;
423 #else
424  uint64_t mbox:4;
425  uint64_t reserved_4_63:60;
426 #endif
427  } s;
428  struct cvmx_ciu2_en_iox_int_mbox_s cn68xx;
429  struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1;
430 };
431 
432 union cvmx_ciu2_en_iox_int_mbox_w1c {
433  uint64_t u64;
434  struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
435 #ifdef __BIG_ENDIAN_BITFIELD
436  uint64_t reserved_4_63:60;
437  uint64_t mbox:4;
438 #else
439  uint64_t mbox:4;
440  uint64_t reserved_4_63:60;
441 #endif
442  } s;
443  struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
444  struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
445 };
446 
447 union cvmx_ciu2_en_iox_int_mbox_w1s {
448  uint64_t u64;
449  struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
450 #ifdef __BIG_ENDIAN_BITFIELD
451  uint64_t reserved_4_63:60;
452  uint64_t mbox:4;
453 #else
454  uint64_t mbox:4;
455  uint64_t reserved_4_63:60;
456 #endif
457  } s;
458  struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
459  struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
460 };
461 
462 union cvmx_ciu2_en_iox_int_mem {
463  uint64_t u64;
464  struct cvmx_ciu2_en_iox_int_mem_s {
465 #ifdef __BIG_ENDIAN_BITFIELD
466  uint64_t reserved_4_63:60;
467  uint64_t lmc:4;
468 #else
469  uint64_t lmc:4;
470  uint64_t reserved_4_63:60;
471 #endif
472  } s;
473  struct cvmx_ciu2_en_iox_int_mem_s cn68xx;
474  struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1;
475 };
476 
477 union cvmx_ciu2_en_iox_int_mem_w1c {
478  uint64_t u64;
479  struct cvmx_ciu2_en_iox_int_mem_w1c_s {
480 #ifdef __BIG_ENDIAN_BITFIELD
481  uint64_t reserved_4_63:60;
482  uint64_t lmc:4;
483 #else
484  uint64_t lmc:4;
485  uint64_t reserved_4_63:60;
486 #endif
487  } s;
488  struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
489  struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
490 };
491 
492 union cvmx_ciu2_en_iox_int_mem_w1s {
493  uint64_t u64;
494  struct cvmx_ciu2_en_iox_int_mem_w1s_s {
495 #ifdef __BIG_ENDIAN_BITFIELD
496  uint64_t reserved_4_63:60;
497  uint64_t lmc:4;
498 #else
499  uint64_t lmc:4;
500  uint64_t reserved_4_63:60;
501 #endif
502  } s;
503  struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
504  struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
505 };
506 
507 union cvmx_ciu2_en_iox_int_mio {
508  uint64_t u64;
509  struct cvmx_ciu2_en_iox_int_mio_s {
510 #ifdef __BIG_ENDIAN_BITFIELD
511  uint64_t rst:1;
512  uint64_t reserved_49_62:14;
513  uint64_t ptp:1;
514  uint64_t reserved_45_47:3;
515  uint64_t usb_hci:1;
516  uint64_t reserved_41_43:3;
517  uint64_t usb_uctl:1;
518  uint64_t reserved_38_39:2;
519  uint64_t uart:2;
520  uint64_t reserved_34_35:2;
521  uint64_t twsi:2;
522  uint64_t reserved_19_31:13;
523  uint64_t bootdma:1;
524  uint64_t mio:1;
525  uint64_t nand:1;
526  uint64_t reserved_12_15:4;
527  uint64_t timer:4;
528  uint64_t reserved_3_7:5;
529  uint64_t ipd_drp:1;
530  uint64_t ssoiq:1;
531  uint64_t ipdppthr:1;
532 #else
533  uint64_t ipdppthr:1;
534  uint64_t ssoiq:1;
535  uint64_t ipd_drp:1;
536  uint64_t reserved_3_7:5;
537  uint64_t timer:4;
538  uint64_t reserved_12_15:4;
539  uint64_t nand:1;
540  uint64_t mio:1;
541  uint64_t bootdma:1;
542  uint64_t reserved_19_31:13;
543  uint64_t twsi:2;
544  uint64_t reserved_34_35:2;
545  uint64_t uart:2;
546  uint64_t reserved_38_39:2;
547  uint64_t usb_uctl:1;
548  uint64_t reserved_41_43:3;
549  uint64_t usb_hci:1;
550  uint64_t reserved_45_47:3;
551  uint64_t ptp:1;
552  uint64_t reserved_49_62:14;
553  uint64_t rst:1;
554 #endif
555  } s;
556  struct cvmx_ciu2_en_iox_int_mio_s cn68xx;
557  struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1;
558 };
559 
560 union cvmx_ciu2_en_iox_int_mio_w1c {
561  uint64_t u64;
562  struct cvmx_ciu2_en_iox_int_mio_w1c_s {
563 #ifdef __BIG_ENDIAN_BITFIELD
564  uint64_t rst:1;
565  uint64_t reserved_49_62:14;
566  uint64_t ptp:1;
567  uint64_t reserved_45_47:3;
568  uint64_t usb_hci:1;
569  uint64_t reserved_41_43:3;
570  uint64_t usb_uctl:1;
571  uint64_t reserved_38_39:2;
572  uint64_t uart:2;
573  uint64_t reserved_34_35:2;
574  uint64_t twsi:2;
575  uint64_t reserved_19_31:13;
576  uint64_t bootdma:1;
577  uint64_t mio:1;
578  uint64_t nand:1;
579  uint64_t reserved_12_15:4;
580  uint64_t timer:4;
581  uint64_t reserved_3_7:5;
582  uint64_t ipd_drp:1;
583  uint64_t ssoiq:1;
584  uint64_t ipdppthr:1;
585 #else
586  uint64_t ipdppthr:1;
587  uint64_t ssoiq:1;
588  uint64_t ipd_drp:1;
589  uint64_t reserved_3_7:5;
590  uint64_t timer:4;
591  uint64_t reserved_12_15:4;
592  uint64_t nand:1;
593  uint64_t mio:1;
594  uint64_t bootdma:1;
595  uint64_t reserved_19_31:13;
596  uint64_t twsi:2;
597  uint64_t reserved_34_35:2;
598  uint64_t uart:2;
599  uint64_t reserved_38_39:2;
600  uint64_t usb_uctl:1;
601  uint64_t reserved_41_43:3;
602  uint64_t usb_hci:1;
603  uint64_t reserved_45_47:3;
604  uint64_t ptp:1;
605  uint64_t reserved_49_62:14;
606  uint64_t rst:1;
607 #endif
608  } s;
609  struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
610  struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
611 };
612 
613 union cvmx_ciu2_en_iox_int_mio_w1s {
614  uint64_t u64;
615  struct cvmx_ciu2_en_iox_int_mio_w1s_s {
616 #ifdef __BIG_ENDIAN_BITFIELD
617  uint64_t rst:1;
618  uint64_t reserved_49_62:14;
619  uint64_t ptp:1;
620  uint64_t reserved_45_47:3;
621  uint64_t usb_hci:1;
622  uint64_t reserved_41_43:3;
623  uint64_t usb_uctl:1;
624  uint64_t reserved_38_39:2;
625  uint64_t uart:2;
626  uint64_t reserved_34_35:2;
627  uint64_t twsi:2;
628  uint64_t reserved_19_31:13;
629  uint64_t bootdma:1;
630  uint64_t mio:1;
631  uint64_t nand:1;
632  uint64_t reserved_12_15:4;
633  uint64_t timer:4;
634  uint64_t reserved_3_7:5;
635  uint64_t ipd_drp:1;
636  uint64_t ssoiq:1;
637  uint64_t ipdppthr:1;
638 #else
639  uint64_t ipdppthr:1;
640  uint64_t ssoiq:1;
641  uint64_t ipd_drp:1;
642  uint64_t reserved_3_7:5;
643  uint64_t timer:4;
644  uint64_t reserved_12_15:4;
645  uint64_t nand:1;
646  uint64_t mio:1;
647  uint64_t bootdma:1;
648  uint64_t reserved_19_31:13;
649  uint64_t twsi:2;
650  uint64_t reserved_34_35:2;
651  uint64_t uart:2;
652  uint64_t reserved_38_39:2;
653  uint64_t usb_uctl:1;
654  uint64_t reserved_41_43:3;
655  uint64_t usb_hci:1;
656  uint64_t reserved_45_47:3;
657  uint64_t ptp:1;
658  uint64_t reserved_49_62:14;
659  uint64_t rst:1;
660 #endif
661  } s;
662  struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
663  struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
664 };
665 
666 union cvmx_ciu2_en_iox_int_pkt {
667  uint64_t u64;
668  struct cvmx_ciu2_en_iox_int_pkt_s {
669 #ifdef __BIG_ENDIAN_BITFIELD
670  uint64_t reserved_54_63:10;
671  uint64_t ilk_drp:2;
672  uint64_t reserved_49_51:3;
673  uint64_t ilk:1;
674  uint64_t reserved_41_47:7;
675  uint64_t mii:1;
676  uint64_t reserved_33_39:7;
677  uint64_t agl:1;
678  uint64_t reserved_13_31:19;
679  uint64_t gmx_drp:5;
680  uint64_t reserved_5_7:3;
681  uint64_t agx:5;
682 #else
683  uint64_t agx:5;
684  uint64_t reserved_5_7:3;
685  uint64_t gmx_drp:5;
686  uint64_t reserved_13_31:19;
687  uint64_t agl:1;
688  uint64_t reserved_33_39:7;
689  uint64_t mii:1;
690  uint64_t reserved_41_47:7;
691  uint64_t ilk:1;
692  uint64_t reserved_49_51:3;
693  uint64_t ilk_drp:2;
694  uint64_t reserved_54_63:10;
695 #endif
696  } s;
697  struct cvmx_ciu2_en_iox_int_pkt_s cn68xx;
698  struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
699 #ifdef __BIG_ENDIAN_BITFIELD
700  uint64_t reserved_49_63:15;
701  uint64_t ilk:1;
702  uint64_t reserved_41_47:7;
703  uint64_t mii:1;
704  uint64_t reserved_33_39:7;
705  uint64_t agl:1;
706  uint64_t reserved_13_31:19;
707  uint64_t gmx_drp:5;
708  uint64_t reserved_5_7:3;
709  uint64_t agx:5;
710 #else
711  uint64_t agx:5;
712  uint64_t reserved_5_7:3;
713  uint64_t gmx_drp:5;
714  uint64_t reserved_13_31:19;
715  uint64_t agl:1;
716  uint64_t reserved_33_39:7;
717  uint64_t mii:1;
718  uint64_t reserved_41_47:7;
719  uint64_t ilk:1;
720  uint64_t reserved_49_63:15;
721 #endif
722  } cn68xxp1;
723 };
724 
725 union cvmx_ciu2_en_iox_int_pkt_w1c {
726  uint64_t u64;
727  struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
728 #ifdef __BIG_ENDIAN_BITFIELD
729  uint64_t reserved_54_63:10;
730  uint64_t ilk_drp:2;
731  uint64_t reserved_49_51:3;
732  uint64_t ilk:1;
733  uint64_t reserved_41_47:7;
734  uint64_t mii:1;
735  uint64_t reserved_33_39:7;
736  uint64_t agl:1;
737  uint64_t reserved_13_31:19;
738  uint64_t gmx_drp:5;
739  uint64_t reserved_5_7:3;
740  uint64_t agx:5;
741 #else
742  uint64_t agx:5;
743  uint64_t reserved_5_7:3;
744  uint64_t gmx_drp:5;
745  uint64_t reserved_13_31:19;
746  uint64_t agl:1;
747  uint64_t reserved_33_39:7;
748  uint64_t mii:1;
749  uint64_t reserved_41_47:7;
750  uint64_t ilk:1;
751  uint64_t reserved_49_51:3;
752  uint64_t ilk_drp:2;
753  uint64_t reserved_54_63:10;
754 #endif
755  } s;
756  struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
757  struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
758 #ifdef __BIG_ENDIAN_BITFIELD
759  uint64_t reserved_49_63:15;
760  uint64_t ilk:1;
761  uint64_t reserved_41_47:7;
762  uint64_t mii:1;
763  uint64_t reserved_33_39:7;
764  uint64_t agl:1;
765  uint64_t reserved_13_31:19;
766  uint64_t gmx_drp:5;
767  uint64_t reserved_5_7:3;
768  uint64_t agx:5;
769 #else
770  uint64_t agx:5;
771  uint64_t reserved_5_7:3;
772  uint64_t gmx_drp:5;
773  uint64_t reserved_13_31:19;
774  uint64_t agl:1;
775  uint64_t reserved_33_39:7;
776  uint64_t mii:1;
777  uint64_t reserved_41_47:7;
778  uint64_t ilk:1;
779  uint64_t reserved_49_63:15;
780 #endif
781  } cn68xxp1;
782 };
783 
784 union cvmx_ciu2_en_iox_int_pkt_w1s {
785  uint64_t u64;
786  struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
787 #ifdef __BIG_ENDIAN_BITFIELD
788  uint64_t reserved_54_63:10;
789  uint64_t ilk_drp:2;
790  uint64_t reserved_49_51:3;
791  uint64_t ilk:1;
792  uint64_t reserved_41_47:7;
793  uint64_t mii:1;
794  uint64_t reserved_33_39:7;
795  uint64_t agl:1;
796  uint64_t reserved_13_31:19;
797  uint64_t gmx_drp:5;
798  uint64_t reserved_5_7:3;
799  uint64_t agx:5;
800 #else
801  uint64_t agx:5;
802  uint64_t reserved_5_7:3;
803  uint64_t gmx_drp:5;
804  uint64_t reserved_13_31:19;
805  uint64_t agl:1;
806  uint64_t reserved_33_39:7;
807  uint64_t mii:1;
808  uint64_t reserved_41_47:7;
809  uint64_t ilk:1;
810  uint64_t reserved_49_51:3;
811  uint64_t ilk_drp:2;
812  uint64_t reserved_54_63:10;
813 #endif
814  } s;
815  struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
816  struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
817 #ifdef __BIG_ENDIAN_BITFIELD
818  uint64_t reserved_49_63:15;
819  uint64_t ilk:1;
820  uint64_t reserved_41_47:7;
821  uint64_t mii:1;
822  uint64_t reserved_33_39:7;
823  uint64_t agl:1;
824  uint64_t reserved_13_31:19;
825  uint64_t gmx_drp:5;
826  uint64_t reserved_5_7:3;
827  uint64_t agx:5;
828 #else
829  uint64_t agx:5;
830  uint64_t reserved_5_7:3;
831  uint64_t gmx_drp:5;
832  uint64_t reserved_13_31:19;
833  uint64_t agl:1;
834  uint64_t reserved_33_39:7;
835  uint64_t mii:1;
836  uint64_t reserved_41_47:7;
837  uint64_t ilk:1;
838  uint64_t reserved_49_63:15;
839 #endif
840  } cn68xxp1;
841 };
842 
843 union cvmx_ciu2_en_iox_int_rml {
844  uint64_t u64;
845  struct cvmx_ciu2_en_iox_int_rml_s {
846 #ifdef __BIG_ENDIAN_BITFIELD
847  uint64_t reserved_56_63:8;
848  uint64_t trace:4;
849  uint64_t reserved_49_51:3;
850  uint64_t l2c:1;
851  uint64_t reserved_41_47:7;
852  uint64_t dfa:1;
853  uint64_t reserved_37_39:3;
854  uint64_t dpi_dma:1;
855  uint64_t reserved_34_35:2;
856  uint64_t dpi:1;
857  uint64_t sli:1;
858  uint64_t reserved_31_31:1;
859  uint64_t key:1;
860  uint64_t rad:1;
861  uint64_t tim:1;
862  uint64_t reserved_25_27:3;
863  uint64_t zip:1;
864  uint64_t reserved_17_23:7;
865  uint64_t sso:1;
866  uint64_t reserved_8_15:8;
867  uint64_t pko:1;
868  uint64_t pip:1;
869  uint64_t ipd:1;
870  uint64_t fpa:1;
871  uint64_t reserved_1_3:3;
872  uint64_t iob:1;
873 #else
874  uint64_t iob:1;
875  uint64_t reserved_1_3:3;
876  uint64_t fpa:1;
877  uint64_t ipd:1;
878  uint64_t pip:1;
879  uint64_t pko:1;
880  uint64_t reserved_8_15:8;
881  uint64_t sso:1;
882  uint64_t reserved_17_23:7;
883  uint64_t zip:1;
884  uint64_t reserved_25_27:3;
885  uint64_t tim:1;
886  uint64_t rad:1;
887  uint64_t key:1;
888  uint64_t reserved_31_31:1;
889  uint64_t sli:1;
890  uint64_t dpi:1;
891  uint64_t reserved_34_35:2;
892  uint64_t dpi_dma:1;
893  uint64_t reserved_37_39:3;
894  uint64_t dfa:1;
895  uint64_t reserved_41_47:7;
896  uint64_t l2c:1;
897  uint64_t reserved_49_51:3;
898  uint64_t trace:4;
899  uint64_t reserved_56_63:8;
900 #endif
901  } s;
902  struct cvmx_ciu2_en_iox_int_rml_s cn68xx;
903  struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
904 #ifdef __BIG_ENDIAN_BITFIELD
905  uint64_t reserved_56_63:8;
906  uint64_t trace:4;
907  uint64_t reserved_49_51:3;
908  uint64_t l2c:1;
909  uint64_t reserved_41_47:7;
910  uint64_t dfa:1;
911  uint64_t reserved_34_39:6;
912  uint64_t dpi:1;
913  uint64_t sli:1;
914  uint64_t reserved_31_31:1;
915  uint64_t key:1;
916  uint64_t rad:1;
917  uint64_t tim:1;
918  uint64_t reserved_25_27:3;
919  uint64_t zip:1;
920  uint64_t reserved_17_23:7;
921  uint64_t sso:1;
922  uint64_t reserved_8_15:8;
923  uint64_t pko:1;
924  uint64_t pip:1;
925  uint64_t ipd:1;
926  uint64_t fpa:1;
927  uint64_t reserved_1_3:3;
928  uint64_t iob:1;
929 #else
930  uint64_t iob:1;
931  uint64_t reserved_1_3:3;
932  uint64_t fpa:1;
933  uint64_t ipd:1;
934  uint64_t pip:1;
935  uint64_t pko:1;
936  uint64_t reserved_8_15:8;
937  uint64_t sso:1;
938  uint64_t reserved_17_23:7;
939  uint64_t zip:1;
940  uint64_t reserved_25_27:3;
941  uint64_t tim:1;
942  uint64_t rad:1;
943  uint64_t key:1;
944  uint64_t reserved_31_31:1;
945  uint64_t sli:1;
946  uint64_t dpi:1;
947  uint64_t reserved_34_39:6;
948  uint64_t dfa:1;
949  uint64_t reserved_41_47:7;
950  uint64_t l2c:1;
951  uint64_t reserved_49_51:3;
952  uint64_t trace:4;
953  uint64_t reserved_56_63:8;
954 #endif
955  } cn68xxp1;
956 };
957 
958 union cvmx_ciu2_en_iox_int_rml_w1c {
959  uint64_t u64;
960  struct cvmx_ciu2_en_iox_int_rml_w1c_s {
961 #ifdef __BIG_ENDIAN_BITFIELD
962  uint64_t reserved_56_63:8;
963  uint64_t trace:4;
964  uint64_t reserved_49_51:3;
965  uint64_t l2c:1;
966  uint64_t reserved_41_47:7;
967  uint64_t dfa:1;
968  uint64_t reserved_37_39:3;
969  uint64_t dpi_dma:1;
970  uint64_t reserved_34_35:2;
971  uint64_t dpi:1;
972  uint64_t sli:1;
973  uint64_t reserved_31_31:1;
974  uint64_t key:1;
975  uint64_t rad:1;
976  uint64_t tim:1;
977  uint64_t reserved_25_27:3;
978  uint64_t zip:1;
979  uint64_t reserved_17_23:7;
980  uint64_t sso:1;
981  uint64_t reserved_8_15:8;
982  uint64_t pko:1;
983  uint64_t pip:1;
984  uint64_t ipd:1;
985  uint64_t fpa:1;
986  uint64_t reserved_1_3:3;
987  uint64_t iob:1;
988 #else
989  uint64_t iob:1;
990  uint64_t reserved_1_3:3;
991  uint64_t fpa:1;
992  uint64_t ipd:1;
993  uint64_t pip:1;
994  uint64_t pko:1;
995  uint64_t reserved_8_15:8;
996  uint64_t sso:1;
997  uint64_t reserved_17_23:7;
998  uint64_t zip:1;
999  uint64_t reserved_25_27:3;
1000  uint64_t tim:1;
1001  uint64_t rad:1;
1002  uint64_t key:1;
1003  uint64_t reserved_31_31:1;
1004  uint64_t sli:1;
1005  uint64_t dpi:1;
1006  uint64_t reserved_34_35:2;
1007  uint64_t dpi_dma:1;
1008  uint64_t reserved_37_39:3;
1009  uint64_t dfa:1;
1010  uint64_t reserved_41_47:7;
1011  uint64_t l2c:1;
1012  uint64_t reserved_49_51:3;
1013  uint64_t trace:4;
1014  uint64_t reserved_56_63:8;
1015 #endif
1016  } s;
1017  struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
1018  struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
1019 #ifdef __BIG_ENDIAN_BITFIELD
1020  uint64_t reserved_56_63:8;
1021  uint64_t trace:4;
1022  uint64_t reserved_49_51:3;
1023  uint64_t l2c:1;
1024  uint64_t reserved_41_47:7;
1025  uint64_t dfa:1;
1026  uint64_t reserved_34_39:6;
1027  uint64_t dpi:1;
1028  uint64_t sli:1;
1029  uint64_t reserved_31_31:1;
1030  uint64_t key:1;
1031  uint64_t rad:1;
1032  uint64_t tim:1;
1033  uint64_t reserved_25_27:3;
1034  uint64_t zip:1;
1035  uint64_t reserved_17_23:7;
1036  uint64_t sso:1;
1037  uint64_t reserved_8_15:8;
1038  uint64_t pko:1;
1039  uint64_t pip:1;
1040  uint64_t ipd:1;
1041  uint64_t fpa:1;
1042  uint64_t reserved_1_3:3;
1043  uint64_t iob:1;
1044 #else
1045  uint64_t iob:1;
1046  uint64_t reserved_1_3:3;
1047  uint64_t fpa:1;
1048  uint64_t ipd:1;
1049  uint64_t pip:1;
1050  uint64_t pko:1;
1051  uint64_t reserved_8_15:8;
1052  uint64_t sso:1;
1053  uint64_t reserved_17_23:7;
1054  uint64_t zip:1;
1055  uint64_t reserved_25_27:3;
1056  uint64_t tim:1;
1057  uint64_t rad:1;
1058  uint64_t key:1;
1059  uint64_t reserved_31_31:1;
1060  uint64_t sli:1;
1061  uint64_t dpi:1;
1062  uint64_t reserved_34_39:6;
1063  uint64_t dfa:1;
1064  uint64_t reserved_41_47:7;
1065  uint64_t l2c:1;
1066  uint64_t reserved_49_51:3;
1067  uint64_t trace:4;
1068  uint64_t reserved_56_63:8;
1069 #endif
1070  } cn68xxp1;
1071 };
1072 
1073 union cvmx_ciu2_en_iox_int_rml_w1s {
1074  uint64_t u64;
1075  struct cvmx_ciu2_en_iox_int_rml_w1s_s {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077  uint64_t reserved_56_63:8;
1078  uint64_t trace:4;
1079  uint64_t reserved_49_51:3;
1080  uint64_t l2c:1;
1081  uint64_t reserved_41_47:7;
1082  uint64_t dfa:1;
1083  uint64_t reserved_37_39:3;
1084  uint64_t dpi_dma:1;
1085  uint64_t reserved_34_35:2;
1086  uint64_t dpi:1;
1087  uint64_t sli:1;
1088  uint64_t reserved_31_31:1;
1089  uint64_t key:1;
1090  uint64_t rad:1;
1091  uint64_t tim:1;
1092  uint64_t reserved_25_27:3;
1093  uint64_t zip:1;
1094  uint64_t reserved_17_23:7;
1095  uint64_t sso:1;
1096  uint64_t reserved_8_15:8;
1097  uint64_t pko:1;
1098  uint64_t pip:1;
1099  uint64_t ipd:1;
1100  uint64_t fpa:1;
1101  uint64_t reserved_1_3:3;
1102  uint64_t iob:1;
1103 #else
1104  uint64_t iob:1;
1105  uint64_t reserved_1_3:3;
1106  uint64_t fpa:1;
1107  uint64_t ipd:1;
1108  uint64_t pip:1;
1109  uint64_t pko:1;
1110  uint64_t reserved_8_15:8;
1111  uint64_t sso:1;
1112  uint64_t reserved_17_23:7;
1113  uint64_t zip:1;
1114  uint64_t reserved_25_27:3;
1115  uint64_t tim:1;
1116  uint64_t rad:1;
1117  uint64_t key:1;
1118  uint64_t reserved_31_31:1;
1119  uint64_t sli:1;
1120  uint64_t dpi:1;
1121  uint64_t reserved_34_35:2;
1122  uint64_t dpi_dma:1;
1123  uint64_t reserved_37_39:3;
1124  uint64_t dfa:1;
1125  uint64_t reserved_41_47:7;
1126  uint64_t l2c:1;
1127  uint64_t reserved_49_51:3;
1128  uint64_t trace:4;
1129  uint64_t reserved_56_63:8;
1130 #endif
1131  } s;
1132  struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
1133  struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
1134 #ifdef __BIG_ENDIAN_BITFIELD
1135  uint64_t reserved_56_63:8;
1136  uint64_t trace:4;
1137  uint64_t reserved_49_51:3;
1138  uint64_t l2c:1;
1139  uint64_t reserved_41_47:7;
1140  uint64_t dfa:1;
1141  uint64_t reserved_34_39:6;
1142  uint64_t dpi:1;
1143  uint64_t sli:1;
1144  uint64_t reserved_31_31:1;
1145  uint64_t key:1;
1146  uint64_t rad:1;
1147  uint64_t tim:1;
1148  uint64_t reserved_25_27:3;
1149  uint64_t zip:1;
1150  uint64_t reserved_17_23:7;
1151  uint64_t sso:1;
1152  uint64_t reserved_8_15:8;
1153  uint64_t pko:1;
1154  uint64_t pip:1;
1155  uint64_t ipd:1;
1156  uint64_t fpa:1;
1157  uint64_t reserved_1_3:3;
1158  uint64_t iob:1;
1159 #else
1160  uint64_t iob:1;
1161  uint64_t reserved_1_3:3;
1162  uint64_t fpa:1;
1163  uint64_t ipd:1;
1164  uint64_t pip:1;
1165  uint64_t pko:1;
1166  uint64_t reserved_8_15:8;
1167  uint64_t sso:1;
1168  uint64_t reserved_17_23:7;
1169  uint64_t zip:1;
1170  uint64_t reserved_25_27:3;
1171  uint64_t tim:1;
1172  uint64_t rad:1;
1173  uint64_t key:1;
1174  uint64_t reserved_31_31:1;
1175  uint64_t sli:1;
1176  uint64_t dpi:1;
1177  uint64_t reserved_34_39:6;
1178  uint64_t dfa:1;
1179  uint64_t reserved_41_47:7;
1180  uint64_t l2c:1;
1181  uint64_t reserved_49_51:3;
1182  uint64_t trace:4;
1183  uint64_t reserved_56_63:8;
1184 #endif
1185  } cn68xxp1;
1186 };
1187 
1188 union cvmx_ciu2_en_iox_int_wdog {
1189  uint64_t u64;
1190  struct cvmx_ciu2_en_iox_int_wdog_s {
1191 #ifdef __BIG_ENDIAN_BITFIELD
1192  uint64_t reserved_32_63:32;
1193  uint64_t wdog:32;
1194 #else
1195  uint64_t wdog:32;
1196  uint64_t reserved_32_63:32;
1197 #endif
1198  } s;
1199  struct cvmx_ciu2_en_iox_int_wdog_s cn68xx;
1200  struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1;
1201 };
1202 
1203 union cvmx_ciu2_en_iox_int_wdog_w1c {
1204  uint64_t u64;
1205  struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
1206 #ifdef __BIG_ENDIAN_BITFIELD
1207  uint64_t reserved_32_63:32;
1208  uint64_t wdog:32;
1209 #else
1210  uint64_t wdog:32;
1211  uint64_t reserved_32_63:32;
1212 #endif
1213  } s;
1214  struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
1215  struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
1216 };
1217 
1218 union cvmx_ciu2_en_iox_int_wdog_w1s {
1219  uint64_t u64;
1220  struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
1221 #ifdef __BIG_ENDIAN_BITFIELD
1222  uint64_t reserved_32_63:32;
1223  uint64_t wdog:32;
1224 #else
1225  uint64_t wdog:32;
1226  uint64_t reserved_32_63:32;
1227 #endif
1228  } s;
1229  struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
1230  struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
1231 };
1232 
1233 union cvmx_ciu2_en_iox_int_wrkq {
1234  uint64_t u64;
1235  struct cvmx_ciu2_en_iox_int_wrkq_s {
1236 #ifdef __BIG_ENDIAN_BITFIELD
1237  uint64_t workq:64;
1238 #else
1239  uint64_t workq:64;
1240 #endif
1241  } s;
1242  struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx;
1243  struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1;
1244 };
1245 
1246 union cvmx_ciu2_en_iox_int_wrkq_w1c {
1247  uint64_t u64;
1248  struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
1249 #ifdef __BIG_ENDIAN_BITFIELD
1250  uint64_t workq:64;
1251 #else
1252  uint64_t workq:64;
1253 #endif
1254  } s;
1255  struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
1256  struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
1257 };
1258 
1259 union cvmx_ciu2_en_iox_int_wrkq_w1s {
1260  uint64_t u64;
1261  struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
1262 #ifdef __BIG_ENDIAN_BITFIELD
1263  uint64_t workq:64;
1264 #else
1265  uint64_t workq:64;
1266 #endif
1267  } s;
1268  struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
1269  struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
1270 };
1271 
1272 union cvmx_ciu2_en_ppx_ip2_gpio {
1273  uint64_t u64;
1274  struct cvmx_ciu2_en_ppx_ip2_gpio_s {
1275 #ifdef __BIG_ENDIAN_BITFIELD
1276  uint64_t reserved_16_63:48;
1277  uint64_t gpio:16;
1278 #else
1279  uint64_t gpio:16;
1280  uint64_t reserved_16_63:48;
1281 #endif
1282  } s;
1283  struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx;
1284  struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1;
1285 };
1286 
1287 union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
1288  uint64_t u64;
1289  struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
1290 #ifdef __BIG_ENDIAN_BITFIELD
1291  uint64_t reserved_16_63:48;
1292  uint64_t gpio:16;
1293 #else
1294  uint64_t gpio:16;
1295  uint64_t reserved_16_63:48;
1296 #endif
1297  } s;
1298  struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
1299  struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
1300 };
1301 
1302 union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
1303  uint64_t u64;
1304  struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
1305 #ifdef __BIG_ENDIAN_BITFIELD
1306  uint64_t reserved_16_63:48;
1307  uint64_t gpio:16;
1308 #else
1309  uint64_t gpio:16;
1310  uint64_t reserved_16_63:48;
1311 #endif
1312  } s;
1313  struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
1314  struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
1315 };
1316 
1317 union cvmx_ciu2_en_ppx_ip2_io {
1318  uint64_t u64;
1319  struct cvmx_ciu2_en_ppx_ip2_io_s {
1320 #ifdef __BIG_ENDIAN_BITFIELD
1321  uint64_t reserved_34_63:30;
1322  uint64_t pem:2;
1323  uint64_t reserved_18_31:14;
1324  uint64_t pci_inta:2;
1325  uint64_t reserved_13_15:3;
1326  uint64_t msired:1;
1327  uint64_t pci_msi:4;
1328  uint64_t reserved_4_7:4;
1329  uint64_t pci_intr:4;
1330 #else
1331  uint64_t pci_intr:4;
1332  uint64_t reserved_4_7:4;
1333  uint64_t pci_msi:4;
1334  uint64_t msired:1;
1335  uint64_t reserved_13_15:3;
1336  uint64_t pci_inta:2;
1337  uint64_t reserved_18_31:14;
1338  uint64_t pem:2;
1339  uint64_t reserved_34_63:30;
1340 #endif
1341  } s;
1342  struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx;
1343  struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1;
1344 };
1345 
1346 union cvmx_ciu2_en_ppx_ip2_io_w1c {
1347  uint64_t u64;
1348  struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1350  uint64_t reserved_34_63:30;
1351  uint64_t pem:2;
1352  uint64_t reserved_18_31:14;
1353  uint64_t pci_inta:2;
1354  uint64_t reserved_13_15:3;
1355  uint64_t msired:1;
1356  uint64_t pci_msi:4;
1357  uint64_t reserved_4_7:4;
1358  uint64_t pci_intr:4;
1359 #else
1360  uint64_t pci_intr:4;
1361  uint64_t reserved_4_7:4;
1362  uint64_t pci_msi:4;
1363  uint64_t msired:1;
1364  uint64_t reserved_13_15:3;
1365  uint64_t pci_inta:2;
1366  uint64_t reserved_18_31:14;
1367  uint64_t pem:2;
1368  uint64_t reserved_34_63:30;
1369 #endif
1370  } s;
1371  struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx;
1372  struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1;
1373 };
1374 
1375 union cvmx_ciu2_en_ppx_ip2_io_w1s {
1376  uint64_t u64;
1377  struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
1378 #ifdef __BIG_ENDIAN_BITFIELD
1379  uint64_t reserved_34_63:30;
1380  uint64_t pem:2;
1381  uint64_t reserved_18_31:14;
1382  uint64_t pci_inta:2;
1383  uint64_t reserved_13_15:3;
1384  uint64_t msired:1;
1385  uint64_t pci_msi:4;
1386  uint64_t reserved_4_7:4;
1387  uint64_t pci_intr:4;
1388 #else
1389  uint64_t pci_intr:4;
1390  uint64_t reserved_4_7:4;
1391  uint64_t pci_msi:4;
1392  uint64_t msired:1;
1393  uint64_t reserved_13_15:3;
1394  uint64_t pci_inta:2;
1395  uint64_t reserved_18_31:14;
1396  uint64_t pem:2;
1397  uint64_t reserved_34_63:30;
1398 #endif
1399  } s;
1400  struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx;
1401  struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1;
1402 };
1403 
1404 union cvmx_ciu2_en_ppx_ip2_mbox {
1405  uint64_t u64;
1406  struct cvmx_ciu2_en_ppx_ip2_mbox_s {
1407 #ifdef __BIG_ENDIAN_BITFIELD
1408  uint64_t reserved_4_63:60;
1409  uint64_t mbox:4;
1410 #else
1411  uint64_t mbox:4;
1412  uint64_t reserved_4_63:60;
1413 #endif
1414  } s;
1415  struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx;
1416  struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1;
1417 };
1418 
1419 union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
1420  uint64_t u64;
1421  struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
1422 #ifdef __BIG_ENDIAN_BITFIELD
1423  uint64_t reserved_4_63:60;
1424  uint64_t mbox:4;
1425 #else
1426  uint64_t mbox:4;
1427  uint64_t reserved_4_63:60;
1428 #endif
1429  } s;
1430  struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
1431  struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
1432 };
1433 
1434 union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
1435  uint64_t u64;
1436  struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
1437 #ifdef __BIG_ENDIAN_BITFIELD
1438  uint64_t reserved_4_63:60;
1439  uint64_t mbox:4;
1440 #else
1441  uint64_t mbox:4;
1442  uint64_t reserved_4_63:60;
1443 #endif
1444  } s;
1445  struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
1446  struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
1447 };
1448 
1449 union cvmx_ciu2_en_ppx_ip2_mem {
1450  uint64_t u64;
1451  struct cvmx_ciu2_en_ppx_ip2_mem_s {
1452 #ifdef __BIG_ENDIAN_BITFIELD
1453  uint64_t reserved_4_63:60;
1454  uint64_t lmc:4;
1455 #else
1456  uint64_t lmc:4;
1457  uint64_t reserved_4_63:60;
1458 #endif
1459  } s;
1460  struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx;
1461  struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1;
1462 };
1463 
1464 union cvmx_ciu2_en_ppx_ip2_mem_w1c {
1465  uint64_t u64;
1466  struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
1467 #ifdef __BIG_ENDIAN_BITFIELD
1468  uint64_t reserved_4_63:60;
1469  uint64_t lmc:4;
1470 #else
1471  uint64_t lmc:4;
1472  uint64_t reserved_4_63:60;
1473 #endif
1474  } s;
1475  struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
1476  struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
1477 };
1478 
1479 union cvmx_ciu2_en_ppx_ip2_mem_w1s {
1480  uint64_t u64;
1481  struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
1482 #ifdef __BIG_ENDIAN_BITFIELD
1483  uint64_t reserved_4_63:60;
1484  uint64_t lmc:4;
1485 #else
1486  uint64_t lmc:4;
1487  uint64_t reserved_4_63:60;
1488 #endif
1489  } s;
1490  struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
1491  struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
1492 };
1493 
1494 union cvmx_ciu2_en_ppx_ip2_mio {
1495  uint64_t u64;
1496  struct cvmx_ciu2_en_ppx_ip2_mio_s {
1497 #ifdef __BIG_ENDIAN_BITFIELD
1498  uint64_t rst:1;
1499  uint64_t reserved_49_62:14;
1500  uint64_t ptp:1;
1501  uint64_t reserved_45_47:3;
1502  uint64_t usb_hci:1;
1503  uint64_t reserved_41_43:3;
1504  uint64_t usb_uctl:1;
1505  uint64_t reserved_38_39:2;
1506  uint64_t uart:2;
1507  uint64_t reserved_34_35:2;
1508  uint64_t twsi:2;
1509  uint64_t reserved_19_31:13;
1510  uint64_t bootdma:1;
1511  uint64_t mio:1;
1512  uint64_t nand:1;
1513  uint64_t reserved_12_15:4;
1514  uint64_t timer:4;
1515  uint64_t reserved_3_7:5;
1516  uint64_t ipd_drp:1;
1517  uint64_t ssoiq:1;
1518  uint64_t ipdppthr:1;
1519 #else
1520  uint64_t ipdppthr:1;
1521  uint64_t ssoiq:1;
1522  uint64_t ipd_drp:1;
1523  uint64_t reserved_3_7:5;
1524  uint64_t timer:4;
1525  uint64_t reserved_12_15:4;
1526  uint64_t nand:1;
1527  uint64_t mio:1;
1528  uint64_t bootdma:1;
1529  uint64_t reserved_19_31:13;
1530  uint64_t twsi:2;
1531  uint64_t reserved_34_35:2;
1532  uint64_t uart:2;
1533  uint64_t reserved_38_39:2;
1534  uint64_t usb_uctl:1;
1535  uint64_t reserved_41_43:3;
1536  uint64_t usb_hci:1;
1537  uint64_t reserved_45_47:3;
1538  uint64_t ptp:1;
1539  uint64_t reserved_49_62:14;
1540  uint64_t rst:1;
1541 #endif
1542  } s;
1543  struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx;
1544  struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1;
1545 };
1546 
1547 union cvmx_ciu2_en_ppx_ip2_mio_w1c {
1548  uint64_t u64;
1549  struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
1550 #ifdef __BIG_ENDIAN_BITFIELD
1551  uint64_t rst:1;
1552  uint64_t reserved_49_62:14;
1553  uint64_t ptp:1;
1554  uint64_t reserved_45_47:3;
1555  uint64_t usb_hci:1;
1556  uint64_t reserved_41_43:3;
1557  uint64_t usb_uctl:1;
1558  uint64_t reserved_38_39:2;
1559  uint64_t uart:2;
1560  uint64_t reserved_34_35:2;
1561  uint64_t twsi:2;
1562  uint64_t reserved_19_31:13;
1563  uint64_t bootdma:1;
1564  uint64_t mio:1;
1565  uint64_t nand:1;
1566  uint64_t reserved_12_15:4;
1567  uint64_t timer:4;
1568  uint64_t reserved_3_7:5;
1569  uint64_t ipd_drp:1;
1570  uint64_t ssoiq:1;
1571  uint64_t ipdppthr:1;
1572 #else
1573  uint64_t ipdppthr:1;
1574  uint64_t ssoiq:1;
1575  uint64_t ipd_drp:1;
1576  uint64_t reserved_3_7:5;
1577  uint64_t timer:4;
1578  uint64_t reserved_12_15:4;
1579  uint64_t nand:1;
1580  uint64_t mio:1;
1581  uint64_t bootdma:1;
1582  uint64_t reserved_19_31:13;
1583  uint64_t twsi:2;
1584  uint64_t reserved_34_35:2;
1585  uint64_t uart:2;
1586  uint64_t reserved_38_39:2;
1587  uint64_t usb_uctl:1;
1588  uint64_t reserved_41_43:3;
1589  uint64_t usb_hci:1;
1590  uint64_t reserved_45_47:3;
1591  uint64_t ptp:1;
1592  uint64_t reserved_49_62:14;
1593  uint64_t rst:1;
1594 #endif
1595  } s;
1596  struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
1597  struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
1598 };
1599 
1600 union cvmx_ciu2_en_ppx_ip2_mio_w1s {
1601  uint64_t u64;
1602  struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604  uint64_t rst:1;
1605  uint64_t reserved_49_62:14;
1606  uint64_t ptp:1;
1607  uint64_t reserved_45_47:3;
1608  uint64_t usb_hci:1;
1609  uint64_t reserved_41_43:3;
1610  uint64_t usb_uctl:1;
1611  uint64_t reserved_38_39:2;
1612  uint64_t uart:2;
1613  uint64_t reserved_34_35:2;
1614  uint64_t twsi:2;
1615  uint64_t reserved_19_31:13;
1616  uint64_t bootdma:1;
1617  uint64_t mio:1;
1618  uint64_t nand:1;
1619  uint64_t reserved_12_15:4;
1620  uint64_t timer:4;
1621  uint64_t reserved_3_7:5;
1622  uint64_t ipd_drp:1;
1623  uint64_t ssoiq:1;
1624  uint64_t ipdppthr:1;
1625 #else
1626  uint64_t ipdppthr:1;
1627  uint64_t ssoiq:1;
1628  uint64_t ipd_drp:1;
1629  uint64_t reserved_3_7:5;
1630  uint64_t timer:4;
1631  uint64_t reserved_12_15:4;
1632  uint64_t nand:1;
1633  uint64_t mio:1;
1634  uint64_t bootdma:1;
1635  uint64_t reserved_19_31:13;
1636  uint64_t twsi:2;
1637  uint64_t reserved_34_35:2;
1638  uint64_t uart:2;
1639  uint64_t reserved_38_39:2;
1640  uint64_t usb_uctl:1;
1641  uint64_t reserved_41_43:3;
1642  uint64_t usb_hci:1;
1643  uint64_t reserved_45_47:3;
1644  uint64_t ptp:1;
1645  uint64_t reserved_49_62:14;
1646  uint64_t rst:1;
1647 #endif
1648  } s;
1649  struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
1650  struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
1651 };
1652 
1653 union cvmx_ciu2_en_ppx_ip2_pkt {
1654  uint64_t u64;
1655  struct cvmx_ciu2_en_ppx_ip2_pkt_s {
1656 #ifdef __BIG_ENDIAN_BITFIELD
1657  uint64_t reserved_54_63:10;
1658  uint64_t ilk_drp:2;
1659  uint64_t reserved_49_51:3;
1660  uint64_t ilk:1;
1661  uint64_t reserved_41_47:7;
1662  uint64_t mii:1;
1663  uint64_t reserved_33_39:7;
1664  uint64_t agl:1;
1665  uint64_t reserved_13_31:19;
1666  uint64_t gmx_drp:5;
1667  uint64_t reserved_5_7:3;
1668  uint64_t agx:5;
1669 #else
1670  uint64_t agx:5;
1671  uint64_t reserved_5_7:3;
1672  uint64_t gmx_drp:5;
1673  uint64_t reserved_13_31:19;
1674  uint64_t agl:1;
1675  uint64_t reserved_33_39:7;
1676  uint64_t mii:1;
1677  uint64_t reserved_41_47:7;
1678  uint64_t ilk:1;
1679  uint64_t reserved_49_51:3;
1680  uint64_t ilk_drp:2;
1681  uint64_t reserved_54_63:10;
1682 #endif
1683  } s;
1684  struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx;
1685  struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
1686 #ifdef __BIG_ENDIAN_BITFIELD
1687  uint64_t reserved_49_63:15;
1688  uint64_t ilk:1;
1689  uint64_t reserved_41_47:7;
1690  uint64_t mii:1;
1691  uint64_t reserved_33_39:7;
1692  uint64_t agl:1;
1693  uint64_t reserved_13_31:19;
1694  uint64_t gmx_drp:5;
1695  uint64_t reserved_5_7:3;
1696  uint64_t agx:5;
1697 #else
1698  uint64_t agx:5;
1699  uint64_t reserved_5_7:3;
1700  uint64_t gmx_drp:5;
1701  uint64_t reserved_13_31:19;
1702  uint64_t agl:1;
1703  uint64_t reserved_33_39:7;
1704  uint64_t mii:1;
1705  uint64_t reserved_41_47:7;
1706  uint64_t ilk:1;
1707  uint64_t reserved_49_63:15;
1708 #endif
1709  } cn68xxp1;
1710 };
1711 
1712 union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
1713  uint64_t u64;
1714  struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
1715 #ifdef __BIG_ENDIAN_BITFIELD
1716  uint64_t reserved_54_63:10;
1717  uint64_t ilk_drp:2;
1718  uint64_t reserved_49_51:3;
1719  uint64_t ilk:1;
1720  uint64_t reserved_41_47:7;
1721  uint64_t mii:1;
1722  uint64_t reserved_33_39:7;
1723  uint64_t agl:1;
1724  uint64_t reserved_13_31:19;
1725  uint64_t gmx_drp:5;
1726  uint64_t reserved_5_7:3;
1727  uint64_t agx:5;
1728 #else
1729  uint64_t agx:5;
1730  uint64_t reserved_5_7:3;
1731  uint64_t gmx_drp:5;
1732  uint64_t reserved_13_31:19;
1733  uint64_t agl:1;
1734  uint64_t reserved_33_39:7;
1735  uint64_t mii:1;
1736  uint64_t reserved_41_47:7;
1737  uint64_t ilk:1;
1738  uint64_t reserved_49_51:3;
1739  uint64_t ilk_drp:2;
1740  uint64_t reserved_54_63:10;
1741 #endif
1742  } s;
1743  struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
1744  struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
1745 #ifdef __BIG_ENDIAN_BITFIELD
1746  uint64_t reserved_49_63:15;
1747  uint64_t ilk:1;
1748  uint64_t reserved_41_47:7;
1749  uint64_t mii:1;
1750  uint64_t reserved_33_39:7;
1751  uint64_t agl:1;
1752  uint64_t reserved_13_31:19;
1753  uint64_t gmx_drp:5;
1754  uint64_t reserved_5_7:3;
1755  uint64_t agx:5;
1756 #else
1757  uint64_t agx:5;
1758  uint64_t reserved_5_7:3;
1759  uint64_t gmx_drp:5;
1760  uint64_t reserved_13_31:19;
1761  uint64_t agl:1;
1762  uint64_t reserved_33_39:7;
1763  uint64_t mii:1;
1764  uint64_t reserved_41_47:7;
1765  uint64_t ilk:1;
1766  uint64_t reserved_49_63:15;
1767 #endif
1768  } cn68xxp1;
1769 };
1770 
1771 union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
1772  uint64_t u64;
1773  struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
1774 #ifdef __BIG_ENDIAN_BITFIELD
1775  uint64_t reserved_54_63:10;
1776  uint64_t ilk_drp:2;
1777  uint64_t reserved_49_51:3;
1778  uint64_t ilk:1;
1779  uint64_t reserved_41_47:7;
1780  uint64_t mii:1;
1781  uint64_t reserved_33_39:7;
1782  uint64_t agl:1;
1783  uint64_t reserved_13_31:19;
1784  uint64_t gmx_drp:5;
1785  uint64_t reserved_5_7:3;
1786  uint64_t agx:5;
1787 #else
1788  uint64_t agx:5;
1789  uint64_t reserved_5_7:3;
1790  uint64_t gmx_drp:5;
1791  uint64_t reserved_13_31:19;
1792  uint64_t agl:1;
1793  uint64_t reserved_33_39:7;
1794  uint64_t mii:1;
1795  uint64_t reserved_41_47:7;
1796  uint64_t ilk:1;
1797  uint64_t reserved_49_51:3;
1798  uint64_t ilk_drp:2;
1799  uint64_t reserved_54_63:10;
1800 #endif
1801  } s;
1802  struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
1803  struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
1804 #ifdef __BIG_ENDIAN_BITFIELD
1805  uint64_t reserved_49_63:15;
1806  uint64_t ilk:1;
1807  uint64_t reserved_41_47:7;
1808  uint64_t mii:1;
1809  uint64_t reserved_33_39:7;
1810  uint64_t agl:1;
1811  uint64_t reserved_13_31:19;
1812  uint64_t gmx_drp:5;
1813  uint64_t reserved_5_7:3;
1814  uint64_t agx:5;
1815 #else
1816  uint64_t agx:5;
1817  uint64_t reserved_5_7:3;
1818  uint64_t gmx_drp:5;
1819  uint64_t reserved_13_31:19;
1820  uint64_t agl:1;
1821  uint64_t reserved_33_39:7;
1822  uint64_t mii:1;
1823  uint64_t reserved_41_47:7;
1824  uint64_t ilk:1;
1825  uint64_t reserved_49_63:15;
1826 #endif
1827  } cn68xxp1;
1828 };
1829 
1830 union cvmx_ciu2_en_ppx_ip2_rml {
1831  uint64_t u64;
1832  struct cvmx_ciu2_en_ppx_ip2_rml_s {
1833 #ifdef __BIG_ENDIAN_BITFIELD
1834  uint64_t reserved_56_63:8;
1835  uint64_t trace:4;
1836  uint64_t reserved_49_51:3;
1837  uint64_t l2c:1;
1838  uint64_t reserved_41_47:7;
1839  uint64_t dfa:1;
1840  uint64_t reserved_37_39:3;
1841  uint64_t dpi_dma:1;
1842  uint64_t reserved_34_35:2;
1843  uint64_t dpi:1;
1844  uint64_t sli:1;
1845  uint64_t reserved_31_31:1;
1846  uint64_t key:1;
1847  uint64_t rad:1;
1848  uint64_t tim:1;
1849  uint64_t reserved_25_27:3;
1850  uint64_t zip:1;
1851  uint64_t reserved_17_23:7;
1852  uint64_t sso:1;
1853  uint64_t reserved_8_15:8;
1854  uint64_t pko:1;
1855  uint64_t pip:1;
1856  uint64_t ipd:1;
1857  uint64_t fpa:1;
1858  uint64_t reserved_1_3:3;
1859  uint64_t iob:1;
1860 #else
1861  uint64_t iob:1;
1862  uint64_t reserved_1_3:3;
1863  uint64_t fpa:1;
1864  uint64_t ipd:1;
1865  uint64_t pip:1;
1866  uint64_t pko:1;
1867  uint64_t reserved_8_15:8;
1868  uint64_t sso:1;
1869  uint64_t reserved_17_23:7;
1870  uint64_t zip:1;
1871  uint64_t reserved_25_27:3;
1872  uint64_t tim:1;
1873  uint64_t rad:1;
1874  uint64_t key:1;
1875  uint64_t reserved_31_31:1;
1876  uint64_t sli:1;
1877  uint64_t dpi:1;
1878  uint64_t reserved_34_35:2;
1879  uint64_t dpi_dma:1;
1880  uint64_t reserved_37_39:3;
1881  uint64_t dfa:1;
1882  uint64_t reserved_41_47:7;
1883  uint64_t l2c:1;
1884  uint64_t reserved_49_51:3;
1885  uint64_t trace:4;
1886  uint64_t reserved_56_63:8;
1887 #endif
1888  } s;
1889  struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx;
1890  struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
1891 #ifdef __BIG_ENDIAN_BITFIELD
1892  uint64_t reserved_56_63:8;
1893  uint64_t trace:4;
1894  uint64_t reserved_49_51:3;
1895  uint64_t l2c:1;
1896  uint64_t reserved_41_47:7;
1897  uint64_t dfa:1;
1898  uint64_t reserved_34_39:6;
1899  uint64_t dpi:1;
1900  uint64_t sli:1;
1901  uint64_t reserved_31_31:1;
1902  uint64_t key:1;
1903  uint64_t rad:1;
1904  uint64_t tim:1;
1905  uint64_t reserved_25_27:3;
1906  uint64_t zip:1;
1907  uint64_t reserved_17_23:7;
1908  uint64_t sso:1;
1909  uint64_t reserved_8_15:8;
1910  uint64_t pko:1;
1911  uint64_t pip:1;
1912  uint64_t ipd:1;
1913  uint64_t fpa:1;
1914  uint64_t reserved_1_3:3;
1915  uint64_t iob:1;
1916 #else
1917  uint64_t iob:1;
1918  uint64_t reserved_1_3:3;
1919  uint64_t fpa:1;
1920  uint64_t ipd:1;
1921  uint64_t pip:1;
1922  uint64_t pko:1;
1923  uint64_t reserved_8_15:8;
1924  uint64_t sso:1;
1925  uint64_t reserved_17_23:7;
1926  uint64_t zip:1;
1927  uint64_t reserved_25_27:3;
1928  uint64_t tim:1;
1929  uint64_t rad:1;
1930  uint64_t key:1;
1931  uint64_t reserved_31_31:1;
1932  uint64_t sli:1;
1933  uint64_t dpi:1;
1934  uint64_t reserved_34_39:6;
1935  uint64_t dfa:1;
1936  uint64_t reserved_41_47:7;
1937  uint64_t l2c:1;
1938  uint64_t reserved_49_51:3;
1939  uint64_t trace:4;
1940  uint64_t reserved_56_63:8;
1941 #endif
1942  } cn68xxp1;
1943 };
1944 
1945 union cvmx_ciu2_en_ppx_ip2_rml_w1c {
1946  uint64_t u64;
1947  struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
1948 #ifdef __BIG_ENDIAN_BITFIELD
1949  uint64_t reserved_56_63:8;
1950  uint64_t trace:4;
1951  uint64_t reserved_49_51:3;
1952  uint64_t l2c:1;
1953  uint64_t reserved_41_47:7;
1954  uint64_t dfa:1;
1955  uint64_t reserved_37_39:3;
1956  uint64_t dpi_dma:1;
1957  uint64_t reserved_34_35:2;
1958  uint64_t dpi:1;
1959  uint64_t sli:1;
1960  uint64_t reserved_31_31:1;
1961  uint64_t key:1;
1962  uint64_t rad:1;
1963  uint64_t tim:1;
1964  uint64_t reserved_25_27:3;
1965  uint64_t zip:1;
1966  uint64_t reserved_17_23:7;
1967  uint64_t sso:1;
1968  uint64_t reserved_8_15:8;
1969  uint64_t pko:1;
1970  uint64_t pip:1;
1971  uint64_t ipd:1;
1972  uint64_t fpa:1;
1973  uint64_t reserved_1_3:3;
1974  uint64_t iob:1;
1975 #else
1976  uint64_t iob:1;
1977  uint64_t reserved_1_3:3;
1978  uint64_t fpa:1;
1979  uint64_t ipd:1;
1980  uint64_t pip:1;
1981  uint64_t pko:1;
1982  uint64_t reserved_8_15:8;
1983  uint64_t sso:1;
1984  uint64_t reserved_17_23:7;
1985  uint64_t zip:1;
1986  uint64_t reserved_25_27:3;
1987  uint64_t tim:1;
1988  uint64_t rad:1;
1989  uint64_t key:1;
1990  uint64_t reserved_31_31:1;
1991  uint64_t sli:1;
1992  uint64_t dpi:1;
1993  uint64_t reserved_34_35:2;
1994  uint64_t dpi_dma:1;
1995  uint64_t reserved_37_39:3;
1996  uint64_t dfa:1;
1997  uint64_t reserved_41_47:7;
1998  uint64_t l2c:1;
1999  uint64_t reserved_49_51:3;
2000  uint64_t trace:4;
2001  uint64_t reserved_56_63:8;
2002 #endif
2003  } s;
2004  struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
2005  struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
2006 #ifdef __BIG_ENDIAN_BITFIELD
2007  uint64_t reserved_56_63:8;
2008  uint64_t trace:4;
2009  uint64_t reserved_49_51:3;
2010  uint64_t l2c:1;
2011  uint64_t reserved_41_47:7;
2012  uint64_t dfa:1;
2013  uint64_t reserved_34_39:6;
2014  uint64_t dpi:1;
2015  uint64_t sli:1;
2016  uint64_t reserved_31_31:1;
2017  uint64_t key:1;
2018  uint64_t rad:1;
2019  uint64_t tim:1;
2020  uint64_t reserved_25_27:3;
2021  uint64_t zip:1;
2022  uint64_t reserved_17_23:7;
2023  uint64_t sso:1;
2024  uint64_t reserved_8_15:8;
2025  uint64_t pko:1;
2026  uint64_t pip:1;
2027  uint64_t ipd:1;
2028  uint64_t fpa:1;
2029  uint64_t reserved_1_3:3;
2030  uint64_t iob:1;
2031 #else
2032  uint64_t iob:1;
2033  uint64_t reserved_1_3:3;
2034  uint64_t fpa:1;
2035  uint64_t ipd:1;
2036  uint64_t pip:1;
2037  uint64_t pko:1;
2038  uint64_t reserved_8_15:8;
2039  uint64_t sso:1;
2040  uint64_t reserved_17_23:7;
2041  uint64_t zip:1;
2042  uint64_t reserved_25_27:3;
2043  uint64_t tim:1;
2044  uint64_t rad:1;
2045  uint64_t key:1;
2046  uint64_t reserved_31_31:1;
2047  uint64_t sli:1;
2048  uint64_t dpi:1;
2049  uint64_t reserved_34_39:6;
2050  uint64_t dfa:1;
2051  uint64_t reserved_41_47:7;
2052  uint64_t l2c:1;
2053  uint64_t reserved_49_51:3;
2054  uint64_t trace:4;
2055  uint64_t reserved_56_63:8;
2056 #endif
2057  } cn68xxp1;
2058 };
2059 
2060 union cvmx_ciu2_en_ppx_ip2_rml_w1s {
2061  uint64_t u64;
2062  struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
2063 #ifdef __BIG_ENDIAN_BITFIELD
2064  uint64_t reserved_56_63:8;
2065  uint64_t trace:4;
2066  uint64_t reserved_49_51:3;
2067  uint64_t l2c:1;
2068  uint64_t reserved_41_47:7;
2069  uint64_t dfa:1;
2070  uint64_t reserved_37_39:3;
2071  uint64_t dpi_dma:1;
2072  uint64_t reserved_34_35:2;
2073  uint64_t dpi:1;
2074  uint64_t sli:1;
2075  uint64_t reserved_31_31:1;
2076  uint64_t key:1;
2077  uint64_t rad:1;
2078  uint64_t tim:1;
2079  uint64_t reserved_25_27:3;
2080  uint64_t zip:1;
2081  uint64_t reserved_17_23:7;
2082  uint64_t sso:1;
2083  uint64_t reserved_8_15:8;
2084  uint64_t pko:1;
2085  uint64_t pip:1;
2086  uint64_t ipd:1;
2087  uint64_t fpa:1;
2088  uint64_t reserved_1_3:3;
2089  uint64_t iob:1;
2090 #else
2091  uint64_t iob:1;
2092  uint64_t reserved_1_3:3;
2093  uint64_t fpa:1;
2094  uint64_t ipd:1;
2095  uint64_t pip:1;
2096  uint64_t pko:1;
2097  uint64_t reserved_8_15:8;
2098  uint64_t sso:1;
2099  uint64_t reserved_17_23:7;
2100  uint64_t zip:1;
2101  uint64_t reserved_25_27:3;
2102  uint64_t tim:1;
2103  uint64_t rad:1;
2104  uint64_t key:1;
2105  uint64_t reserved_31_31:1;
2106  uint64_t sli:1;
2107  uint64_t dpi:1;
2108  uint64_t reserved_34_35:2;
2109  uint64_t dpi_dma:1;
2110  uint64_t reserved_37_39:3;
2111  uint64_t dfa:1;
2112  uint64_t reserved_41_47:7;
2113  uint64_t l2c:1;
2114  uint64_t reserved_49_51:3;
2115  uint64_t trace:4;
2116  uint64_t reserved_56_63:8;
2117 #endif
2118  } s;
2119  struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
2120  struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122  uint64_t reserved_56_63:8;
2123  uint64_t trace:4;
2124  uint64_t reserved_49_51:3;
2125  uint64_t l2c:1;
2126  uint64_t reserved_41_47:7;
2127  uint64_t dfa:1;
2128  uint64_t reserved_34_39:6;
2129  uint64_t dpi:1;
2130  uint64_t sli:1;
2131  uint64_t reserved_31_31:1;
2132  uint64_t key:1;
2133  uint64_t rad:1;
2134  uint64_t tim:1;
2135  uint64_t reserved_25_27:3;
2136  uint64_t zip:1;
2137  uint64_t reserved_17_23:7;
2138  uint64_t sso:1;
2139  uint64_t reserved_8_15:8;
2140  uint64_t pko:1;
2141  uint64_t pip:1;
2142  uint64_t ipd:1;
2143  uint64_t fpa:1;
2144  uint64_t reserved_1_3:3;
2145  uint64_t iob:1;
2146 #else
2147  uint64_t iob:1;
2148  uint64_t reserved_1_3:3;
2149  uint64_t fpa:1;
2150  uint64_t ipd:1;
2151  uint64_t pip:1;
2152  uint64_t pko:1;
2153  uint64_t reserved_8_15:8;
2154  uint64_t sso:1;
2155  uint64_t reserved_17_23:7;
2156  uint64_t zip:1;
2157  uint64_t reserved_25_27:3;
2158  uint64_t tim:1;
2159  uint64_t rad:1;
2160  uint64_t key:1;
2161  uint64_t reserved_31_31:1;
2162  uint64_t sli:1;
2163  uint64_t dpi:1;
2164  uint64_t reserved_34_39:6;
2165  uint64_t dfa:1;
2166  uint64_t reserved_41_47:7;
2167  uint64_t l2c:1;
2168  uint64_t reserved_49_51:3;
2169  uint64_t trace:4;
2170  uint64_t reserved_56_63:8;
2171 #endif
2172  } cn68xxp1;
2173 };
2174 
2175 union cvmx_ciu2_en_ppx_ip2_wdog {
2176  uint64_t u64;
2177  struct cvmx_ciu2_en_ppx_ip2_wdog_s {
2178 #ifdef __BIG_ENDIAN_BITFIELD
2179  uint64_t reserved_32_63:32;
2180  uint64_t wdog:32;
2181 #else
2182  uint64_t wdog:32;
2183  uint64_t reserved_32_63:32;
2184 #endif
2185  } s;
2186  struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx;
2187  struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1;
2188 };
2189 
2190 union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
2191  uint64_t u64;
2192  struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
2193 #ifdef __BIG_ENDIAN_BITFIELD
2194  uint64_t reserved_32_63:32;
2195  uint64_t wdog:32;
2196 #else
2197  uint64_t wdog:32;
2198  uint64_t reserved_32_63:32;
2199 #endif
2200  } s;
2201  struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
2202  struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
2203 };
2204 
2205 union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
2206  uint64_t u64;
2207  struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
2208 #ifdef __BIG_ENDIAN_BITFIELD
2209  uint64_t reserved_32_63:32;
2210  uint64_t wdog:32;
2211 #else
2212  uint64_t wdog:32;
2213  uint64_t reserved_32_63:32;
2214 #endif
2215  } s;
2216  struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
2217  struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
2218 };
2219 
2220 union cvmx_ciu2_en_ppx_ip2_wrkq {
2221  uint64_t u64;
2222  struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
2223 #ifdef __BIG_ENDIAN_BITFIELD
2224  uint64_t workq:64;
2225 #else
2226  uint64_t workq:64;
2227 #endif
2228  } s;
2229  struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx;
2230  struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1;
2231 };
2232 
2233 union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
2234  uint64_t u64;
2235  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
2236 #ifdef __BIG_ENDIAN_BITFIELD
2237  uint64_t workq:64;
2238 #else
2239  uint64_t workq:64;
2240 #endif
2241  } s;
2242  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
2243  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
2244 };
2245 
2246 union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
2247  uint64_t u64;
2248  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
2249 #ifdef __BIG_ENDIAN_BITFIELD
2250  uint64_t workq:64;
2251 #else
2252  uint64_t workq:64;
2253 #endif
2254  } s;
2255  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
2256  struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
2257 };
2258 
2259 union cvmx_ciu2_en_ppx_ip3_gpio {
2260  uint64_t u64;
2261  struct cvmx_ciu2_en_ppx_ip3_gpio_s {
2262 #ifdef __BIG_ENDIAN_BITFIELD
2263  uint64_t reserved_16_63:48;
2264  uint64_t gpio:16;
2265 #else
2266  uint64_t gpio:16;
2267  uint64_t reserved_16_63:48;
2268 #endif
2269  } s;
2270  struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx;
2271  struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1;
2272 };
2273 
2274 union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
2275  uint64_t u64;
2276  struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
2277 #ifdef __BIG_ENDIAN_BITFIELD
2278  uint64_t reserved_16_63:48;
2279  uint64_t gpio:16;
2280 #else
2281  uint64_t gpio:16;
2282  uint64_t reserved_16_63:48;
2283 #endif
2284  } s;
2285  struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
2286  struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
2287 };
2288 
2289 union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
2290  uint64_t u64;
2291  struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
2292 #ifdef __BIG_ENDIAN_BITFIELD
2293  uint64_t reserved_16_63:48;
2294  uint64_t gpio:16;
2295 #else
2296  uint64_t gpio:16;
2297  uint64_t reserved_16_63:48;
2298 #endif
2299  } s;
2300  struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
2301  struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
2302 };
2303 
2304 union cvmx_ciu2_en_ppx_ip3_io {
2305  uint64_t u64;
2306  struct cvmx_ciu2_en_ppx_ip3_io_s {
2307 #ifdef __BIG_ENDIAN_BITFIELD
2308  uint64_t reserved_34_63:30;
2309  uint64_t pem:2;
2310  uint64_t reserved_18_31:14;
2311  uint64_t pci_inta:2;
2312  uint64_t reserved_13_15:3;
2313  uint64_t msired:1;
2314  uint64_t pci_msi:4;
2315  uint64_t reserved_4_7:4;
2316  uint64_t pci_intr:4;
2317 #else
2318  uint64_t pci_intr:4;
2319  uint64_t reserved_4_7:4;
2320  uint64_t pci_msi:4;
2321  uint64_t msired:1;
2322  uint64_t reserved_13_15:3;
2323  uint64_t pci_inta:2;
2324  uint64_t reserved_18_31:14;
2325  uint64_t pem:2;
2326  uint64_t reserved_34_63:30;
2327 #endif
2328  } s;
2329  struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx;
2330  struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1;
2331 };
2332 
2333 union cvmx_ciu2_en_ppx_ip3_io_w1c {
2334  uint64_t u64;
2335  struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
2336 #ifdef __BIG_ENDIAN_BITFIELD
2337  uint64_t reserved_34_63:30;
2338  uint64_t pem:2;
2339  uint64_t reserved_18_31:14;
2340  uint64_t pci_inta:2;
2341  uint64_t reserved_13_15:3;
2342  uint64_t msired:1;
2343  uint64_t pci_msi:4;
2344  uint64_t reserved_4_7:4;
2345  uint64_t pci_intr:4;
2346 #else
2347  uint64_t pci_intr:4;
2348  uint64_t reserved_4_7:4;
2349  uint64_t pci_msi:4;
2350  uint64_t msired:1;
2351  uint64_t reserved_13_15:3;
2352  uint64_t pci_inta:2;
2353  uint64_t reserved_18_31:14;
2354  uint64_t pem:2;
2355  uint64_t reserved_34_63:30;
2356 #endif
2357  } s;
2358  struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx;
2359  struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1;
2360 };
2361 
2362 union cvmx_ciu2_en_ppx_ip3_io_w1s {
2363  uint64_t u64;
2364  struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
2365 #ifdef __BIG_ENDIAN_BITFIELD
2366  uint64_t reserved_34_63:30;
2367  uint64_t pem:2;
2368  uint64_t reserved_18_31:14;
2369  uint64_t pci_inta:2;
2370  uint64_t reserved_13_15:3;
2371  uint64_t msired:1;
2372  uint64_t pci_msi:4;
2373  uint64_t reserved_4_7:4;
2374  uint64_t pci_intr:4;
2375 #else
2376  uint64_t pci_intr:4;
2377  uint64_t reserved_4_7:4;
2378  uint64_t pci_msi:4;
2379  uint64_t msired:1;
2380  uint64_t reserved_13_15:3;
2381  uint64_t pci_inta:2;
2382  uint64_t reserved_18_31:14;
2383  uint64_t pem:2;
2384  uint64_t reserved_34_63:30;
2385 #endif
2386  } s;
2387  struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx;
2388  struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1;
2389 };
2390 
2391 union cvmx_ciu2_en_ppx_ip3_mbox {
2392  uint64_t u64;
2393  struct cvmx_ciu2_en_ppx_ip3_mbox_s {
2394 #ifdef __BIG_ENDIAN_BITFIELD
2395  uint64_t reserved_4_63:60;
2396  uint64_t mbox:4;
2397 #else
2398  uint64_t mbox:4;
2399  uint64_t reserved_4_63:60;
2400 #endif
2401  } s;
2402  struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx;
2403  struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1;
2404 };
2405 
2406 union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
2407  uint64_t u64;
2408  struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
2409 #ifdef __BIG_ENDIAN_BITFIELD
2410  uint64_t reserved_4_63:60;
2411  uint64_t mbox:4;
2412 #else
2413  uint64_t mbox:4;
2414  uint64_t reserved_4_63:60;
2415 #endif
2416  } s;
2417  struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
2418  struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
2419 };
2420 
2421 union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
2422  uint64_t u64;
2423  struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
2424 #ifdef __BIG_ENDIAN_BITFIELD
2425  uint64_t reserved_4_63:60;
2426  uint64_t mbox:4;
2427 #else
2428  uint64_t mbox:4;
2429  uint64_t reserved_4_63:60;
2430 #endif
2431  } s;
2432  struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
2433  struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
2434 };
2435 
2436 union cvmx_ciu2_en_ppx_ip3_mem {
2437  uint64_t u64;
2438  struct cvmx_ciu2_en_ppx_ip3_mem_s {
2439 #ifdef __BIG_ENDIAN_BITFIELD
2440  uint64_t reserved_4_63:60;
2441  uint64_t lmc:4;
2442 #else
2443  uint64_t lmc:4;
2444  uint64_t reserved_4_63:60;
2445 #endif
2446  } s;
2447  struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx;
2448  struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1;
2449 };
2450 
2451 union cvmx_ciu2_en_ppx_ip3_mem_w1c {
2452  uint64_t u64;
2453  struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
2454 #ifdef __BIG_ENDIAN_BITFIELD
2455  uint64_t reserved_4_63:60;
2456  uint64_t lmc:4;
2457 #else
2458  uint64_t lmc:4;
2459  uint64_t reserved_4_63:60;
2460 #endif
2461  } s;
2462  struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
2463  struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
2464 };
2465 
2466 union cvmx_ciu2_en_ppx_ip3_mem_w1s {
2467  uint64_t u64;
2468  struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
2469 #ifdef __BIG_ENDIAN_BITFIELD
2470  uint64_t reserved_4_63:60;
2471  uint64_t lmc:4;
2472 #else
2473  uint64_t lmc:4;
2474  uint64_t reserved_4_63:60;
2475 #endif
2476  } s;
2477  struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
2478  struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
2479 };
2480 
2481 union cvmx_ciu2_en_ppx_ip3_mio {
2482  uint64_t u64;
2483  struct cvmx_ciu2_en_ppx_ip3_mio_s {
2484 #ifdef __BIG_ENDIAN_BITFIELD
2485  uint64_t rst:1;
2486  uint64_t reserved_49_62:14;
2487  uint64_t ptp:1;
2488  uint64_t reserved_45_47:3;
2489  uint64_t usb_hci:1;
2490  uint64_t reserved_41_43:3;
2491  uint64_t usb_uctl:1;
2492  uint64_t reserved_38_39:2;
2493  uint64_t uart:2;
2494  uint64_t reserved_34_35:2;
2495  uint64_t twsi:2;
2496  uint64_t reserved_19_31:13;
2497  uint64_t bootdma:1;
2498  uint64_t mio:1;
2499  uint64_t nand:1;
2500  uint64_t reserved_12_15:4;
2501  uint64_t timer:4;
2502  uint64_t reserved_3_7:5;
2503  uint64_t ipd_drp:1;
2504  uint64_t ssoiq:1;
2505  uint64_t ipdppthr:1;
2506 #else
2507  uint64_t ipdppthr:1;
2508  uint64_t ssoiq:1;
2509  uint64_t ipd_drp:1;
2510  uint64_t reserved_3_7:5;
2511  uint64_t timer:4;
2512  uint64_t reserved_12_15:4;
2513  uint64_t nand:1;
2514  uint64_t mio:1;
2515  uint64_t bootdma:1;
2516  uint64_t reserved_19_31:13;
2517  uint64_t twsi:2;
2518  uint64_t reserved_34_35:2;
2519  uint64_t uart:2;
2520  uint64_t reserved_38_39:2;
2521  uint64_t usb_uctl:1;
2522  uint64_t reserved_41_43:3;
2523  uint64_t usb_hci:1;
2524  uint64_t reserved_45_47:3;
2525  uint64_t ptp:1;
2526  uint64_t reserved_49_62:14;
2527  uint64_t rst:1;
2528 #endif
2529  } s;
2530  struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx;
2531  struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1;
2532 };
2533 
2534 union cvmx_ciu2_en_ppx_ip3_mio_w1c {
2535  uint64_t u64;
2536  struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
2537 #ifdef __BIG_ENDIAN_BITFIELD
2538  uint64_t rst:1;
2539  uint64_t reserved_49_62:14;
2540  uint64_t ptp:1;
2541  uint64_t reserved_45_47:3;
2542  uint64_t usb_hci:1;
2543  uint64_t reserved_41_43:3;
2544  uint64_t usb_uctl:1;
2545  uint64_t reserved_38_39:2;
2546  uint64_t uart:2;
2547  uint64_t reserved_34_35:2;
2548  uint64_t twsi:2;
2549  uint64_t reserved_19_31:13;
2550  uint64_t bootdma:1;
2551  uint64_t mio:1;
2552  uint64_t nand:1;
2553  uint64_t reserved_12_15:4;
2554  uint64_t timer:4;
2555  uint64_t reserved_3_7:5;
2556  uint64_t ipd_drp:1;
2557  uint64_t ssoiq:1;
2558  uint64_t ipdppthr:1;
2559 #else
2560  uint64_t ipdppthr:1;
2561  uint64_t ssoiq:1;
2562  uint64_t ipd_drp:1;
2563  uint64_t reserved_3_7:5;
2564  uint64_t timer:4;
2565  uint64_t reserved_12_15:4;
2566  uint64_t nand:1;
2567  uint64_t mio:1;
2568  uint64_t bootdma:1;
2569  uint64_t reserved_19_31:13;
2570  uint64_t twsi:2;
2571  uint64_t reserved_34_35:2;
2572  uint64_t uart:2;
2573  uint64_t reserved_38_39:2;
2574  uint64_t usb_uctl:1;
2575  uint64_t reserved_41_43:3;
2576  uint64_t usb_hci:1;
2577  uint64_t reserved_45_47:3;
2578  uint64_t ptp:1;
2579  uint64_t reserved_49_62:14;
2580  uint64_t rst:1;
2581 #endif
2582  } s;
2583  struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
2584  struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
2585 };
2586 
2587 union cvmx_ciu2_en_ppx_ip3_mio_w1s {
2588  uint64_t u64;
2589  struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
2590 #ifdef __BIG_ENDIAN_BITFIELD
2591  uint64_t rst:1;
2592  uint64_t reserved_49_62:14;
2593  uint64_t ptp:1;
2594  uint64_t reserved_45_47:3;
2595  uint64_t usb_hci:1;
2596  uint64_t reserved_41_43:3;
2597  uint64_t usb_uctl:1;
2598  uint64_t reserved_38_39:2;
2599  uint64_t uart:2;
2600  uint64_t reserved_34_35:2;
2601  uint64_t twsi:2;
2602  uint64_t reserved_19_31:13;
2603  uint64_t bootdma:1;
2604  uint64_t mio:1;
2605  uint64_t nand:1;
2606  uint64_t reserved_12_15:4;
2607  uint64_t timer:4;
2608  uint64_t reserved_3_7:5;
2609  uint64_t ipd_drp:1;
2610  uint64_t ssoiq:1;
2611  uint64_t ipdppthr:1;
2612 #else
2613  uint64_t ipdppthr:1;
2614  uint64_t ssoiq:1;
2615  uint64_t ipd_drp:1;
2616  uint64_t reserved_3_7:5;
2617  uint64_t timer:4;
2618  uint64_t reserved_12_15:4;
2619  uint64_t nand:1;
2620  uint64_t mio:1;
2621  uint64_t bootdma:1;
2622  uint64_t reserved_19_31:13;
2623  uint64_t twsi:2;
2624  uint64_t reserved_34_35:2;
2625  uint64_t uart:2;
2626  uint64_t reserved_38_39:2;
2627  uint64_t usb_uctl:1;
2628  uint64_t reserved_41_43:3;
2629  uint64_t usb_hci:1;
2630  uint64_t reserved_45_47:3;
2631  uint64_t ptp:1;
2632  uint64_t reserved_49_62:14;
2633  uint64_t rst:1;
2634 #endif
2635  } s;
2636  struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
2637  struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
2638 };
2639 
2640 union cvmx_ciu2_en_ppx_ip3_pkt {
2641  uint64_t u64;
2642  struct cvmx_ciu2_en_ppx_ip3_pkt_s {
2643 #ifdef __BIG_ENDIAN_BITFIELD
2644  uint64_t reserved_54_63:10;
2645  uint64_t ilk_drp:2;
2646  uint64_t reserved_49_51:3;
2647  uint64_t ilk:1;
2648  uint64_t reserved_41_47:7;
2649  uint64_t mii:1;
2650  uint64_t reserved_33_39:7;
2651  uint64_t agl:1;
2652  uint64_t reserved_13_31:19;
2653  uint64_t gmx_drp:5;
2654  uint64_t reserved_5_7:3;
2655  uint64_t agx:5;
2656 #else
2657  uint64_t agx:5;
2658  uint64_t reserved_5_7:3;
2659  uint64_t gmx_drp:5;
2660  uint64_t reserved_13_31:19;
2661  uint64_t agl:1;
2662  uint64_t reserved_33_39:7;
2663  uint64_t mii:1;
2664  uint64_t reserved_41_47:7;
2665  uint64_t ilk:1;
2666  uint64_t reserved_49_51:3;
2667  uint64_t ilk_drp:2;
2668  uint64_t reserved_54_63:10;
2669 #endif
2670  } s;
2671  struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx;
2672  struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
2673 #ifdef __BIG_ENDIAN_BITFIELD
2674  uint64_t reserved_49_63:15;
2675  uint64_t ilk:1;
2676  uint64_t reserved_41_47:7;
2677  uint64_t mii:1;
2678  uint64_t reserved_33_39:7;
2679  uint64_t agl:1;
2680  uint64_t reserved_13_31:19;
2681  uint64_t gmx_drp:5;
2682  uint64_t reserved_5_7:3;
2683  uint64_t agx:5;
2684 #else
2685  uint64_t agx:5;
2686  uint64_t reserved_5_7:3;
2687  uint64_t gmx_drp:5;
2688  uint64_t reserved_13_31:19;
2689  uint64_t agl:1;
2690  uint64_t reserved_33_39:7;
2691  uint64_t mii:1;
2692  uint64_t reserved_41_47:7;
2693  uint64_t ilk:1;
2694  uint64_t reserved_49_63:15;
2695 #endif
2696  } cn68xxp1;
2697 };
2698 
2699 union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
2700  uint64_t u64;
2701  struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
2702 #ifdef __BIG_ENDIAN_BITFIELD
2703  uint64_t reserved_54_63:10;
2704  uint64_t ilk_drp:2;
2705  uint64_t reserved_49_51:3;
2706  uint64_t ilk:1;
2707  uint64_t reserved_41_47:7;
2708  uint64_t mii:1;
2709  uint64_t reserved_33_39:7;
2710  uint64_t agl:1;
2711  uint64_t reserved_13_31:19;
2712  uint64_t gmx_drp:5;
2713  uint64_t reserved_5_7:3;
2714  uint64_t agx:5;
2715 #else
2716  uint64_t agx:5;
2717  uint64_t reserved_5_7:3;
2718  uint64_t gmx_drp:5;
2719  uint64_t reserved_13_31:19;
2720  uint64_t agl:1;
2721  uint64_t reserved_33_39:7;
2722  uint64_t mii:1;
2723  uint64_t reserved_41_47:7;
2724  uint64_t ilk:1;
2725  uint64_t reserved_49_51:3;
2726  uint64_t ilk_drp:2;
2727  uint64_t reserved_54_63:10;
2728 #endif
2729  } s;
2730  struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
2731  struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
2732 #ifdef __BIG_ENDIAN_BITFIELD
2733  uint64_t reserved_49_63:15;
2734  uint64_t ilk:1;
2735  uint64_t reserved_41_47:7;
2736  uint64_t mii:1;
2737  uint64_t reserved_33_39:7;
2738  uint64_t agl:1;
2739  uint64_t reserved_13_31:19;
2740  uint64_t gmx_drp:5;
2741  uint64_t reserved_5_7:3;
2742  uint64_t agx:5;
2743 #else
2744  uint64_t agx:5;
2745  uint64_t reserved_5_7:3;
2746  uint64_t gmx_drp:5;
2747  uint64_t reserved_13_31:19;
2748  uint64_t agl:1;
2749  uint64_t reserved_33_39:7;
2750  uint64_t mii:1;
2751  uint64_t reserved_41_47:7;
2752  uint64_t ilk:1;
2753  uint64_t reserved_49_63:15;
2754 #endif
2755  } cn68xxp1;
2756 };
2757 
2758 union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
2759  uint64_t u64;
2760  struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
2761 #ifdef __BIG_ENDIAN_BITFIELD
2762  uint64_t reserved_54_63:10;
2763  uint64_t ilk_drp:2;
2764  uint64_t reserved_49_51:3;
2765  uint64_t ilk:1;
2766  uint64_t reserved_41_47:7;
2767  uint64_t mii:1;
2768  uint64_t reserved_33_39:7;
2769  uint64_t agl:1;
2770  uint64_t reserved_13_31:19;
2771  uint64_t gmx_drp:5;
2772  uint64_t reserved_5_7:3;
2773  uint64_t agx:5;
2774 #else
2775  uint64_t agx:5;
2776  uint64_t reserved_5_7:3;
2777  uint64_t gmx_drp:5;
2778  uint64_t reserved_13_31:19;
2779  uint64_t agl:1;
2780  uint64_t reserved_33_39:7;
2781  uint64_t mii:1;
2782  uint64_t reserved_41_47:7;
2783  uint64_t ilk:1;
2784  uint64_t reserved_49_51:3;
2785  uint64_t ilk_drp:2;
2786  uint64_t reserved_54_63:10;
2787 #endif
2788  } s;
2789  struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
2790  struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
2791 #ifdef __BIG_ENDIAN_BITFIELD
2792  uint64_t reserved_49_63:15;
2793  uint64_t ilk:1;
2794  uint64_t reserved_41_47:7;
2795  uint64_t mii:1;
2796  uint64_t reserved_33_39:7;
2797  uint64_t agl:1;
2798  uint64_t reserved_13_31:19;
2799  uint64_t gmx_drp:5;
2800  uint64_t reserved_5_7:3;
2801  uint64_t agx:5;
2802 #else
2803  uint64_t agx:5;
2804  uint64_t reserved_5_7:3;
2805  uint64_t gmx_drp:5;
2806  uint64_t reserved_13_31:19;
2807  uint64_t agl:1;
2808  uint64_t reserved_33_39:7;
2809  uint64_t mii:1;
2810  uint64_t reserved_41_47:7;
2811  uint64_t ilk:1;
2812  uint64_t reserved_49_63:15;
2813 #endif
2814  } cn68xxp1;
2815 };
2816 
2817 union cvmx_ciu2_en_ppx_ip3_rml {
2818  uint64_t u64;
2819  struct cvmx_ciu2_en_ppx_ip3_rml_s {
2820 #ifdef __BIG_ENDIAN_BITFIELD
2821  uint64_t reserved_56_63:8;
2822  uint64_t trace:4;
2823  uint64_t reserved_49_51:3;
2824  uint64_t l2c:1;
2825  uint64_t reserved_41_47:7;
2826  uint64_t dfa:1;
2827  uint64_t reserved_37_39:3;
2828  uint64_t dpi_dma:1;
2829  uint64_t reserved_34_35:2;
2830  uint64_t dpi:1;
2831  uint64_t sli:1;
2832  uint64_t reserved_31_31:1;
2833  uint64_t key:1;
2834  uint64_t rad:1;
2835  uint64_t tim:1;
2836  uint64_t reserved_25_27:3;
2837  uint64_t zip:1;
2838  uint64_t reserved_17_23:7;
2839  uint64_t sso:1;
2840  uint64_t reserved_8_15:8;
2841  uint64_t pko:1;
2842  uint64_t pip:1;
2843  uint64_t ipd:1;
2844  uint64_t fpa:1;
2845  uint64_t reserved_1_3:3;
2846  uint64_t iob:1;
2847 #else
2848  uint64_t iob:1;
2849  uint64_t reserved_1_3:3;
2850  uint64_t fpa:1;
2851  uint64_t ipd:1;
2852  uint64_t pip:1;
2853  uint64_t pko:1;
2854  uint64_t reserved_8_15:8;
2855  uint64_t sso:1;
2856  uint64_t reserved_17_23:7;
2857  uint64_t zip:1;
2858  uint64_t reserved_25_27:3;
2859  uint64_t tim:1;
2860  uint64_t rad:1;
2861  uint64_t key:1;
2862  uint64_t reserved_31_31:1;
2863  uint64_t sli:1;
2864  uint64_t dpi:1;
2865  uint64_t reserved_34_35:2;
2866  uint64_t dpi_dma:1;
2867  uint64_t reserved_37_39:3;
2868  uint64_t dfa:1;
2869  uint64_t reserved_41_47:7;
2870  uint64_t l2c:1;
2871  uint64_t reserved_49_51:3;
2872  uint64_t trace:4;
2873  uint64_t reserved_56_63:8;
2874 #endif
2875  } s;
2876  struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx;
2877  struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
2878 #ifdef __BIG_ENDIAN_BITFIELD
2879  uint64_t reserved_56_63:8;
2880  uint64_t trace:4;
2881  uint64_t reserved_49_51:3;
2882  uint64_t l2c:1;
2883  uint64_t reserved_41_47:7;
2884  uint64_t dfa:1;
2885  uint64_t reserved_34_39:6;
2886  uint64_t dpi:1;
2887  uint64_t sli:1;
2888  uint64_t reserved_31_31:1;
2889  uint64_t key:1;
2890  uint64_t rad:1;
2891  uint64_t tim:1;
2892  uint64_t reserved_25_27:3;
2893  uint64_t zip:1;
2894  uint64_t reserved_17_23:7;
2895  uint64_t sso:1;
2896  uint64_t reserved_8_15:8;
2897  uint64_t pko:1;
2898  uint64_t pip:1;
2899  uint64_t ipd:1;
2900  uint64_t fpa:1;
2901  uint64_t reserved_1_3:3;
2902  uint64_t iob:1;
2903 #else
2904  uint64_t iob:1;
2905  uint64_t reserved_1_3:3;
2906  uint64_t fpa:1;
2907  uint64_t ipd:1;
2908  uint64_t pip:1;
2909  uint64_t pko:1;
2910  uint64_t reserved_8_15:8;
2911  uint64_t sso:1;
2912  uint64_t reserved_17_23:7;
2913  uint64_t zip:1;
2914  uint64_t reserved_25_27:3;
2915  uint64_t tim:1;
2916  uint64_t rad:1;
2917  uint64_t key:1;
2918  uint64_t reserved_31_31:1;
2919  uint64_t sli:1;
2920  uint64_t dpi:1;
2921  uint64_t reserved_34_39:6;
2922  uint64_t dfa:1;
2923  uint64_t reserved_41_47:7;
2924  uint64_t l2c:1;
2925  uint64_t reserved_49_51:3;
2926  uint64_t trace:4;
2927  uint64_t reserved_56_63:8;
2928 #endif
2929  } cn68xxp1;
2930 };
2931 
2932 union cvmx_ciu2_en_ppx_ip3_rml_w1c {
2933  uint64_t u64;
2934  struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
2935 #ifdef __BIG_ENDIAN_BITFIELD
2936  uint64_t reserved_56_63:8;
2937  uint64_t trace:4;
2938  uint64_t reserved_49_51:3;
2939  uint64_t l2c:1;
2940  uint64_t reserved_41_47:7;
2941  uint64_t dfa:1;
2942  uint64_t reserved_37_39:3;
2943  uint64_t dpi_dma:1;
2944  uint64_t reserved_34_35:2;
2945  uint64_t dpi:1;
2946  uint64_t sli:1;
2947  uint64_t reserved_31_31:1;
2948  uint64_t key:1;
2949  uint64_t rad:1;
2950  uint64_t tim:1;
2951  uint64_t reserved_25_27:3;
2952  uint64_t zip:1;
2953  uint64_t reserved_17_23:7;
2954  uint64_t sso:1;
2955  uint64_t reserved_8_15:8;
2956  uint64_t pko:1;
2957  uint64_t pip:1;
2958  uint64_t ipd:1;
2959  uint64_t fpa:1;
2960  uint64_t reserved_1_3:3;
2961  uint64_t iob:1;
2962 #else
2963  uint64_t iob:1;
2964  uint64_t reserved_1_3:3;
2965  uint64_t fpa:1;
2966  uint64_t ipd:1;
2967  uint64_t pip:1;
2968  uint64_t pko:1;
2969  uint64_t reserved_8_15:8;
2970  uint64_t sso:1;
2971  uint64_t reserved_17_23:7;
2972  uint64_t zip:1;
2973  uint64_t reserved_25_27:3;
2974  uint64_t tim:1;
2975  uint64_t rad:1;
2976  uint64_t key:1;
2977  uint64_t reserved_31_31:1;
2978  uint64_t sli:1;
2979  uint64_t dpi:1;
2980  uint64_t reserved_34_35:2;
2981  uint64_t dpi_dma:1;
2982  uint64_t reserved_37_39:3;
2983  uint64_t dfa:1;
2984  uint64_t reserved_41_47:7;
2985  uint64_t l2c:1;
2986  uint64_t reserved_49_51:3;
2987  uint64_t trace:4;
2988  uint64_t reserved_56_63:8;
2989 #endif
2990  } s;
2991  struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
2992  struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
2993 #ifdef __BIG_ENDIAN_BITFIELD
2994  uint64_t reserved_56_63:8;
2995  uint64_t trace:4;
2996  uint64_t reserved_49_51:3;
2997  uint64_t l2c:1;
2998  uint64_t reserved_41_47:7;
2999  uint64_t dfa:1;
3000  uint64_t reserved_34_39:6;
3001  uint64_t dpi:1;
3002  uint64_t sli:1;
3003  uint64_t reserved_31_31:1;
3004  uint64_t key:1;
3005  uint64_t rad:1;
3006  uint64_t tim:1;
3007  uint64_t reserved_25_27:3;
3008  uint64_t zip:1;
3009  uint64_t reserved_17_23:7;
3010  uint64_t sso:1;
3011  uint64_t reserved_8_15:8;
3012  uint64_t pko:1;
3013  uint64_t pip:1;
3014  uint64_t ipd:1;
3015  uint64_t fpa:1;
3016  uint64_t reserved_1_3:3;
3017  uint64_t iob:1;
3018 #else
3019  uint64_t iob:1;
3020  uint64_t reserved_1_3:3;
3021  uint64_t fpa:1;
3022  uint64_t ipd:1;
3023  uint64_t pip:1;
3024  uint64_t pko:1;
3025  uint64_t reserved_8_15:8;
3026  uint64_t sso:1;
3027  uint64_t reserved_17_23:7;
3028  uint64_t zip:1;
3029  uint64_t reserved_25_27:3;
3030  uint64_t tim:1;
3031  uint64_t rad:1;
3032  uint64_t key:1;
3033  uint64_t reserved_31_31:1;
3034  uint64_t sli:1;
3035  uint64_t dpi:1;
3036  uint64_t reserved_34_39:6;
3037  uint64_t dfa:1;
3038  uint64_t reserved_41_47:7;
3039  uint64_t l2c:1;
3040  uint64_t reserved_49_51:3;
3041  uint64_t trace:4;
3042  uint64_t reserved_56_63:8;
3043 #endif
3044  } cn68xxp1;
3045 };
3046 
3047 union cvmx_ciu2_en_ppx_ip3_rml_w1s {
3048  uint64_t u64;
3049  struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
3050 #ifdef __BIG_ENDIAN_BITFIELD
3051  uint64_t reserved_56_63:8;
3052  uint64_t trace:4;
3053  uint64_t reserved_49_51:3;
3054  uint64_t l2c:1;
3055  uint64_t reserved_41_47:7;
3056  uint64_t dfa:1;
3057  uint64_t reserved_37_39:3;
3058  uint64_t dpi_dma:1;
3059  uint64_t reserved_34_35:2;
3060  uint64_t dpi:1;
3061  uint64_t sli:1;
3062  uint64_t reserved_31_31:1;
3063  uint64_t key:1;
3064  uint64_t rad:1;
3065  uint64_t tim:1;
3066  uint64_t reserved_25_27:3;
3067  uint64_t zip:1;
3068  uint64_t reserved_17_23:7;
3069  uint64_t sso:1;
3070  uint64_t reserved_8_15:8;
3071  uint64_t pko:1;
3072  uint64_t pip:1;
3073  uint64_t ipd:1;
3074  uint64_t fpa:1;
3075  uint64_t reserved_1_3:3;
3076  uint64_t iob:1;
3077 #else
3078  uint64_t iob:1;
3079  uint64_t reserved_1_3:3;
3080  uint64_t fpa:1;
3081  uint64_t ipd:1;
3082  uint64_t pip:1;
3083  uint64_t pko:1;
3084  uint64_t reserved_8_15:8;
3085  uint64_t sso:1;
3086  uint64_t reserved_17_23:7;
3087  uint64_t zip:1;
3088  uint64_t reserved_25_27:3;
3089  uint64_t tim:1;
3090  uint64_t rad:1;
3091  uint64_t key:1;
3092  uint64_t reserved_31_31:1;
3093  uint64_t sli:1;
3094  uint64_t dpi:1;
3095  uint64_t reserved_34_35:2;
3096  uint64_t dpi_dma:1;
3097  uint64_t reserved_37_39:3;
3098  uint64_t dfa:1;
3099  uint64_t reserved_41_47:7;
3100  uint64_t l2c:1;
3101  uint64_t reserved_49_51:3;
3102  uint64_t trace:4;
3103  uint64_t reserved_56_63:8;
3104 #endif
3105  } s;
3106  struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
3107  struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
3108 #ifdef __BIG_ENDIAN_BITFIELD
3109  uint64_t reserved_56_63:8;
3110  uint64_t trace:4;
3111  uint64_t reserved_49_51:3;
3112  uint64_t l2c:1;
3113  uint64_t reserved_41_47:7;
3114  uint64_t dfa:1;
3115  uint64_t reserved_34_39:6;
3116  uint64_t dpi:1;
3117  uint64_t sli:1;
3118  uint64_t reserved_31_31:1;
3119  uint64_t key:1;
3120  uint64_t rad:1;
3121  uint64_t tim:1;
3122  uint64_t reserved_25_27:3;
3123  uint64_t zip:1;
3124  uint64_t reserved_17_23:7;
3125  uint64_t sso:1;
3126  uint64_t reserved_8_15:8;
3127  uint64_t pko:1;
3128  uint64_t pip:1;
3129  uint64_t ipd:1;
3130  uint64_t fpa:1;
3131  uint64_t reserved_1_3:3;
3132  uint64_t iob:1;
3133 #else
3134  uint64_t iob:1;
3135  uint64_t reserved_1_3:3;
3136  uint64_t fpa:1;
3137  uint64_t ipd:1;
3138  uint64_t pip:1;
3139  uint64_t pko:1;
3140  uint64_t reserved_8_15:8;
3141  uint64_t sso:1;
3142  uint64_t reserved_17_23:7;
3143  uint64_t zip:1;
3144  uint64_t reserved_25_27:3;
3145  uint64_t tim:1;
3146  uint64_t rad:1;
3147  uint64_t key:1;
3148  uint64_t reserved_31_31:1;
3149  uint64_t sli:1;
3150  uint64_t dpi:1;
3151  uint64_t reserved_34_39:6;
3152  uint64_t dfa:1;
3153  uint64_t reserved_41_47:7;
3154  uint64_t l2c:1;
3155  uint64_t reserved_49_51:3;
3156  uint64_t trace:4;
3157  uint64_t reserved_56_63:8;
3158 #endif
3159  } cn68xxp1;
3160 };
3161 
3162 union cvmx_ciu2_en_ppx_ip3_wdog {
3163  uint64_t u64;
3164  struct cvmx_ciu2_en_ppx_ip3_wdog_s {
3165 #ifdef __BIG_ENDIAN_BITFIELD
3166  uint64_t reserved_32_63:32;
3167  uint64_t wdog:32;
3168 #else
3169  uint64_t wdog:32;
3170  uint64_t reserved_32_63:32;
3171 #endif
3172  } s;
3173  struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx;
3174  struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1;
3175 };
3176 
3177 union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
3178  uint64_t u64;
3179  struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
3180 #ifdef __BIG_ENDIAN_BITFIELD
3181  uint64_t reserved_32_63:32;
3182  uint64_t wdog:32;
3183 #else
3184  uint64_t wdog:32;
3185  uint64_t reserved_32_63:32;
3186 #endif
3187  } s;
3188  struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
3189  struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
3190 };
3191 
3192 union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
3193  uint64_t u64;
3194  struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
3195 #ifdef __BIG_ENDIAN_BITFIELD
3196  uint64_t reserved_32_63:32;
3197  uint64_t wdog:32;
3198 #else
3199  uint64_t wdog:32;
3200  uint64_t reserved_32_63:32;
3201 #endif
3202  } s;
3203  struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
3204  struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
3205 };
3206 
3207 union cvmx_ciu2_en_ppx_ip3_wrkq {
3208  uint64_t u64;
3209  struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
3210 #ifdef __BIG_ENDIAN_BITFIELD
3211  uint64_t workq:64;
3212 #else
3213  uint64_t workq:64;
3214 #endif
3215  } s;
3216  struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx;
3217  struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1;
3218 };
3219 
3220 union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
3221  uint64_t u64;
3222  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
3223 #ifdef __BIG_ENDIAN_BITFIELD
3224  uint64_t workq:64;
3225 #else
3226  uint64_t workq:64;
3227 #endif
3228  } s;
3229  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
3230  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
3231 };
3232 
3233 union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
3234  uint64_t u64;
3235  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
3236 #ifdef __BIG_ENDIAN_BITFIELD
3237  uint64_t workq:64;
3238 #else
3239  uint64_t workq:64;
3240 #endif
3241  } s;
3242  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
3243  struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
3244 };
3245 
3246 union cvmx_ciu2_en_ppx_ip4_gpio {
3247  uint64_t u64;
3248  struct cvmx_ciu2_en_ppx_ip4_gpio_s {
3249 #ifdef __BIG_ENDIAN_BITFIELD
3250  uint64_t reserved_16_63:48;
3251  uint64_t gpio:16;
3252 #else
3253  uint64_t gpio:16;
3254  uint64_t reserved_16_63:48;
3255 #endif
3256  } s;
3257  struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx;
3258  struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1;
3259 };
3260 
3261 union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
3262  uint64_t u64;
3263  struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
3264 #ifdef __BIG_ENDIAN_BITFIELD
3265  uint64_t reserved_16_63:48;
3266  uint64_t gpio:16;
3267 #else
3268  uint64_t gpio:16;
3269  uint64_t reserved_16_63:48;
3270 #endif
3271  } s;
3272  struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
3273  struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
3274 };
3275 
3276 union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
3277  uint64_t u64;
3278  struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
3279 #ifdef __BIG_ENDIAN_BITFIELD
3280  uint64_t reserved_16_63:48;
3281  uint64_t gpio:16;
3282 #else
3283  uint64_t gpio:16;
3284  uint64_t reserved_16_63:48;
3285 #endif
3286  } s;
3287  struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
3288  struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
3289 };
3290 
3291 union cvmx_ciu2_en_ppx_ip4_io {
3292  uint64_t u64;
3293  struct cvmx_ciu2_en_ppx_ip4_io_s {
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295  uint64_t reserved_34_63:30;
3296  uint64_t pem:2;
3297  uint64_t reserved_18_31:14;
3298  uint64_t pci_inta:2;
3299  uint64_t reserved_13_15:3;
3300  uint64_t msired:1;
3301  uint64_t pci_msi:4;
3302  uint64_t reserved_4_7:4;
3303  uint64_t pci_intr:4;
3304 #else
3305  uint64_t pci_intr:4;
3306  uint64_t reserved_4_7:4;
3307  uint64_t pci_msi:4;
3308  uint64_t msired:1;
3309  uint64_t reserved_13_15:3;
3310  uint64_t pci_inta:2;
3311  uint64_t reserved_18_31:14;
3312  uint64_t pem:2;
3313  uint64_t reserved_34_63:30;
3314 #endif
3315  } s;
3316  struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx;
3317  struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1;
3318 };
3319 
3320 union cvmx_ciu2_en_ppx_ip4_io_w1c {
3321  uint64_t u64;
3322  struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
3323 #ifdef __BIG_ENDIAN_BITFIELD
3324  uint64_t reserved_34_63:30;
3325  uint64_t pem:2;
3326  uint64_t reserved_18_31:14;
3327  uint64_t pci_inta:2;
3328  uint64_t reserved_13_15:3;
3329  uint64_t msired:1;
3330  uint64_t pci_msi:4;
3331  uint64_t reserved_4_7:4;
3332  uint64_t pci_intr:4;
3333 #else
3334  uint64_t pci_intr:4;
3335  uint64_t reserved_4_7:4;
3336  uint64_t pci_msi:4;
3337  uint64_t msired:1;
3338  uint64_t reserved_13_15:3;
3339  uint64_t pci_inta:2;
3340  uint64_t reserved_18_31:14;
3341  uint64_t pem:2;
3342  uint64_t reserved_34_63:30;
3343 #endif
3344  } s;
3345  struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx;
3346  struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1;
3347 };
3348 
3349 union cvmx_ciu2_en_ppx_ip4_io_w1s {
3350  uint64_t u64;
3351  struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
3352 #ifdef __BIG_ENDIAN_BITFIELD
3353  uint64_t reserved_34_63:30;
3354  uint64_t pem:2;
3355  uint64_t reserved_18_31:14;
3356  uint64_t pci_inta:2;
3357  uint64_t reserved_13_15:3;
3358  uint64_t msired:1;
3359  uint64_t pci_msi:4;
3360  uint64_t reserved_4_7:4;
3361  uint64_t pci_intr:4;
3362 #else
3363  uint64_t pci_intr:4;
3364  uint64_t reserved_4_7:4;
3365  uint64_t pci_msi:4;
3366  uint64_t msired:1;
3367  uint64_t reserved_13_15:3;
3368  uint64_t pci_inta:2;
3369  uint64_t reserved_18_31:14;
3370  uint64_t pem:2;
3371  uint64_t reserved_34_63:30;
3372 #endif
3373  } s;
3374  struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx;
3375  struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1;
3376 };
3377 
3378 union cvmx_ciu2_en_ppx_ip4_mbox {
3379  uint64_t u64;
3380  struct cvmx_ciu2_en_ppx_ip4_mbox_s {
3381 #ifdef __BIG_ENDIAN_BITFIELD
3382  uint64_t reserved_4_63:60;
3383  uint64_t mbox:4;
3384 #else
3385  uint64_t mbox:4;
3386  uint64_t reserved_4_63:60;
3387 #endif
3388  } s;
3389  struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx;
3390  struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1;
3391 };
3392 
3393 union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
3394  uint64_t u64;
3395  struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
3396 #ifdef __BIG_ENDIAN_BITFIELD
3397  uint64_t reserved_4_63:60;
3398  uint64_t mbox:4;
3399 #else
3400  uint64_t mbox:4;
3401  uint64_t reserved_4_63:60;
3402 #endif
3403  } s;
3404  struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
3405  struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
3406 };
3407 
3408 union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
3409  uint64_t u64;
3410  struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
3411 #ifdef __BIG_ENDIAN_BITFIELD
3412  uint64_t reserved_4_63:60;
3413  uint64_t mbox:4;
3414 #else
3415  uint64_t mbox:4;
3416  uint64_t reserved_4_63:60;
3417 #endif
3418  } s;
3419  struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
3420  struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
3421 };
3422 
3423 union cvmx_ciu2_en_ppx_ip4_mem {
3424  uint64_t u64;
3425  struct cvmx_ciu2_en_ppx_ip4_mem_s {
3426 #ifdef __BIG_ENDIAN_BITFIELD
3427  uint64_t reserved_4_63:60;
3428  uint64_t lmc:4;
3429 #else
3430  uint64_t lmc:4;
3431  uint64_t reserved_4_63:60;
3432 #endif
3433  } s;
3434  struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx;
3435  struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1;
3436 };
3437 
3438 union cvmx_ciu2_en_ppx_ip4_mem_w1c {
3439  uint64_t u64;
3440  struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
3441 #ifdef __BIG_ENDIAN_BITFIELD
3442  uint64_t reserved_4_63:60;
3443  uint64_t lmc:4;
3444 #else
3445  uint64_t lmc:4;
3446  uint64_t reserved_4_63:60;
3447 #endif
3448  } s;
3449  struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
3450  struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
3451 };
3452 
3453 union cvmx_ciu2_en_ppx_ip4_mem_w1s {
3454  uint64_t u64;
3455  struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
3456 #ifdef __BIG_ENDIAN_BITFIELD
3457  uint64_t reserved_4_63:60;
3458  uint64_t lmc:4;
3459 #else
3460  uint64_t lmc:4;
3461  uint64_t reserved_4_63:60;
3462 #endif
3463  } s;
3464  struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
3465  struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
3466 };
3467 
3468 union cvmx_ciu2_en_ppx_ip4_mio {
3469  uint64_t u64;
3470  struct cvmx_ciu2_en_ppx_ip4_mio_s {
3471 #ifdef __BIG_ENDIAN_BITFIELD
3472  uint64_t rst:1;
3473  uint64_t reserved_49_62:14;
3474  uint64_t ptp:1;
3475  uint64_t reserved_45_47:3;
3476  uint64_t usb_hci:1;
3477  uint64_t reserved_41_43:3;
3478  uint64_t usb_uctl:1;
3479  uint64_t reserved_38_39:2;
3480  uint64_t uart:2;
3481  uint64_t reserved_34_35:2;
3482  uint64_t twsi:2;
3483  uint64_t reserved_19_31:13;
3484  uint64_t bootdma:1;
3485  uint64_t mio:1;
3486  uint64_t nand:1;
3487  uint64_t reserved_12_15:4;
3488  uint64_t timer:4;
3489  uint64_t reserved_3_7:5;
3490  uint64_t ipd_drp:1;
3491  uint64_t ssoiq:1;
3492  uint64_t ipdppthr:1;
3493 #else
3494  uint64_t ipdppthr:1;
3495  uint64_t ssoiq:1;
3496  uint64_t ipd_drp:1;
3497  uint64_t reserved_3_7:5;
3498  uint64_t timer:4;
3499  uint64_t reserved_12_15:4;
3500  uint64_t nand:1;
3501  uint64_t mio:1;
3502  uint64_t bootdma:1;
3503  uint64_t reserved_19_31:13;
3504  uint64_t twsi:2;
3505  uint64_t reserved_34_35:2;
3506  uint64_t uart:2;
3507  uint64_t reserved_38_39:2;
3508  uint64_t usb_uctl:1;
3509  uint64_t reserved_41_43:3;
3510  uint64_t usb_hci:1;
3511  uint64_t reserved_45_47:3;
3512  uint64_t ptp:1;
3513  uint64_t reserved_49_62:14;
3514  uint64_t rst:1;
3515 #endif
3516  } s;
3517  struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx;
3518  struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1;
3519 };
3520 
3521 union cvmx_ciu2_en_ppx_ip4_mio_w1c {
3522  uint64_t u64;
3523  struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
3524 #ifdef __BIG_ENDIAN_BITFIELD
3525  uint64_t rst:1;
3526  uint64_t reserved_49_62:14;
3527  uint64_t ptp:1;
3528  uint64_t reserved_45_47:3;
3529  uint64_t usb_hci:1;
3530  uint64_t reserved_41_43:3;
3531  uint64_t usb_uctl:1;
3532  uint64_t reserved_38_39:2;
3533  uint64_t uart:2;
3534  uint64_t reserved_34_35:2;
3535  uint64_t twsi:2;
3536  uint64_t reserved_19_31:13;
3537  uint64_t bootdma:1;
3538  uint64_t mio:1;
3539  uint64_t nand:1;
3540  uint64_t reserved_12_15:4;
3541  uint64_t timer:4;
3542  uint64_t reserved_3_7:5;
3543  uint64_t ipd_drp:1;
3544  uint64_t ssoiq:1;
3545  uint64_t ipdppthr:1;
3546 #else
3547  uint64_t ipdppthr:1;
3548  uint64_t ssoiq:1;
3549  uint64_t ipd_drp:1;
3550  uint64_t reserved_3_7:5;
3551  uint64_t timer:4;
3552  uint64_t reserved_12_15:4;
3553  uint64_t nand:1;
3554  uint64_t mio:1;
3555  uint64_t bootdma:1;
3556  uint64_t reserved_19_31:13;
3557  uint64_t twsi:2;
3558  uint64_t reserved_34_35:2;
3559  uint64_t uart:2;
3560  uint64_t reserved_38_39:2;
3561  uint64_t usb_uctl:1;
3562  uint64_t reserved_41_43:3;
3563  uint64_t usb_hci:1;
3564  uint64_t reserved_45_47:3;
3565  uint64_t ptp:1;
3566  uint64_t reserved_49_62:14;
3567  uint64_t rst:1;
3568 #endif
3569  } s;
3570  struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
3571  struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
3572 };
3573 
3574 union cvmx_ciu2_en_ppx_ip4_mio_w1s {
3575  uint64_t u64;
3576  struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
3577 #ifdef __BIG_ENDIAN_BITFIELD
3578  uint64_t rst:1;
3579  uint64_t reserved_49_62:14;
3580  uint64_t ptp:1;
3581  uint64_t reserved_45_47:3;
3582  uint64_t usb_hci:1;
3583  uint64_t reserved_41_43:3;
3584  uint64_t usb_uctl:1;
3585  uint64_t reserved_38_39:2;
3586  uint64_t uart:2;
3587  uint64_t reserved_34_35:2;
3588  uint64_t twsi:2;
3589  uint64_t reserved_19_31:13;
3590  uint64_t bootdma:1;
3591  uint64_t mio:1;
3592  uint64_t nand:1;
3593  uint64_t reserved_12_15:4;
3594  uint64_t timer:4;
3595  uint64_t reserved_3_7:5;
3596  uint64_t ipd_drp:1;
3597  uint64_t ssoiq:1;
3598  uint64_t ipdppthr:1;
3599 #else
3600  uint64_t ipdppthr:1;
3601  uint64_t ssoiq:1;
3602  uint64_t ipd_drp:1;
3603  uint64_t reserved_3_7:5;
3604  uint64_t timer:4;
3605  uint64_t reserved_12_15:4;
3606  uint64_t nand:1;
3607  uint64_t mio:1;
3608  uint64_t bootdma:1;
3609  uint64_t reserved_19_31:13;
3610  uint64_t twsi:2;
3611  uint64_t reserved_34_35:2;
3612  uint64_t uart:2;
3613  uint64_t reserved_38_39:2;
3614  uint64_t usb_uctl:1;
3615  uint64_t reserved_41_43:3;
3616  uint64_t usb_hci:1;
3617  uint64_t reserved_45_47:3;
3618  uint64_t ptp:1;
3619  uint64_t reserved_49_62:14;
3620  uint64_t rst:1;
3621 #endif
3622  } s;
3623  struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
3624  struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
3625 };
3626 
3627 union cvmx_ciu2_en_ppx_ip4_pkt {
3628  uint64_t u64;
3629  struct cvmx_ciu2_en_ppx_ip4_pkt_s {
3630 #ifdef __BIG_ENDIAN_BITFIELD
3631  uint64_t reserved_54_63:10;
3632  uint64_t ilk_drp:2;
3633  uint64_t reserved_49_51:3;
3634  uint64_t ilk:1;
3635  uint64_t reserved_41_47:7;
3636  uint64_t mii:1;
3637  uint64_t reserved_33_39:7;
3638  uint64_t agl:1;
3639  uint64_t reserved_13_31:19;
3640  uint64_t gmx_drp:5;
3641  uint64_t reserved_5_7:3;
3642  uint64_t agx:5;
3643 #else
3644  uint64_t agx:5;
3645  uint64_t reserved_5_7:3;
3646  uint64_t gmx_drp:5;
3647  uint64_t reserved_13_31:19;
3648  uint64_t agl:1;
3649  uint64_t reserved_33_39:7;
3650  uint64_t mii:1;
3651  uint64_t reserved_41_47:7;
3652  uint64_t ilk:1;
3653  uint64_t reserved_49_51:3;
3654  uint64_t ilk_drp:2;
3655  uint64_t reserved_54_63:10;
3656 #endif
3657  } s;
3658  struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx;
3659  struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
3660 #ifdef __BIG_ENDIAN_BITFIELD
3661  uint64_t reserved_49_63:15;
3662  uint64_t ilk:1;
3663  uint64_t reserved_41_47:7;
3664  uint64_t mii:1;
3665  uint64_t reserved_33_39:7;
3666  uint64_t agl:1;
3667  uint64_t reserved_13_31:19;
3668  uint64_t gmx_drp:5;
3669  uint64_t reserved_5_7:3;
3670  uint64_t agx:5;
3671 #else
3672  uint64_t agx:5;
3673  uint64_t reserved_5_7:3;
3674  uint64_t gmx_drp:5;
3675  uint64_t reserved_13_31:19;
3676  uint64_t agl:1;
3677  uint64_t reserved_33_39:7;
3678  uint64_t mii:1;
3679  uint64_t reserved_41_47:7;
3680  uint64_t ilk:1;
3681  uint64_t reserved_49_63:15;
3682 #endif
3683  } cn68xxp1;
3684 };
3685 
3686 union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
3687  uint64_t u64;
3688  struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
3689 #ifdef __BIG_ENDIAN_BITFIELD
3690  uint64_t reserved_54_63:10;
3691  uint64_t ilk_drp:2;
3692  uint64_t reserved_49_51:3;
3693  uint64_t ilk:1;
3694  uint64_t reserved_41_47:7;
3695  uint64_t mii:1;
3696  uint64_t reserved_33_39:7;
3697  uint64_t agl:1;
3698  uint64_t reserved_13_31:19;
3699  uint64_t gmx_drp:5;
3700  uint64_t reserved_5_7:3;
3701  uint64_t agx:5;
3702 #else
3703  uint64_t agx:5;
3704  uint64_t reserved_5_7:3;
3705  uint64_t gmx_drp:5;
3706  uint64_t reserved_13_31:19;
3707  uint64_t agl:1;
3708  uint64_t reserved_33_39:7;
3709  uint64_t mii:1;
3710  uint64_t reserved_41_47:7;
3711  uint64_t ilk:1;
3712  uint64_t reserved_49_51:3;
3713  uint64_t ilk_drp:2;
3714  uint64_t reserved_54_63:10;
3715 #endif
3716  } s;
3717  struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
3718  struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
3719 #ifdef __BIG_ENDIAN_BITFIELD
3720  uint64_t reserved_49_63:15;
3721  uint64_t ilk:1;
3722  uint64_t reserved_41_47:7;
3723  uint64_t mii:1;
3724  uint64_t reserved_33_39:7;
3725  uint64_t agl:1;
3726  uint64_t reserved_13_31:19;
3727  uint64_t gmx_drp:5;
3728  uint64_t reserved_5_7:3;
3729  uint64_t agx:5;
3730 #else
3731  uint64_t agx:5;
3732  uint64_t reserved_5_7:3;
3733  uint64_t gmx_drp:5;
3734  uint64_t reserved_13_31:19;
3735  uint64_t agl:1;
3736  uint64_t reserved_33_39:7;
3737  uint64_t mii:1;
3738  uint64_t reserved_41_47:7;
3739  uint64_t ilk:1;
3740  uint64_t reserved_49_63:15;
3741 #endif
3742  } cn68xxp1;
3743 };
3744 
3745 union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
3746  uint64_t u64;
3747  struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
3748 #ifdef __BIG_ENDIAN_BITFIELD
3749  uint64_t reserved_54_63:10;
3750  uint64_t ilk_drp:2;
3751  uint64_t reserved_49_51:3;
3752  uint64_t ilk:1;
3753  uint64_t reserved_41_47:7;
3754  uint64_t mii:1;
3755  uint64_t reserved_33_39:7;
3756  uint64_t agl:1;
3757  uint64_t reserved_13_31:19;
3758  uint64_t gmx_drp:5;
3759  uint64_t reserved_5_7:3;
3760  uint64_t agx:5;
3761 #else
3762  uint64_t agx:5;
3763  uint64_t reserved_5_7:3;
3764  uint64_t gmx_drp:5;
3765  uint64_t reserved_13_31:19;
3766  uint64_t agl:1;
3767  uint64_t reserved_33_39:7;
3768  uint64_t mii:1;
3769  uint64_t reserved_41_47:7;
3770  uint64_t ilk:1;
3771  uint64_t reserved_49_51:3;
3772  uint64_t ilk_drp:2;
3773  uint64_t reserved_54_63:10;
3774 #endif
3775  } s;
3776  struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
3777  struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
3778 #ifdef __BIG_ENDIAN_BITFIELD
3779  uint64_t reserved_49_63:15;
3780  uint64_t ilk:1;
3781  uint64_t reserved_41_47:7;
3782  uint64_t mii:1;
3783  uint64_t reserved_33_39:7;
3784  uint64_t agl:1;
3785  uint64_t reserved_13_31:19;
3786  uint64_t gmx_drp:5;
3787  uint64_t reserved_5_7:3;
3788  uint64_t agx:5;
3789 #else
3790  uint64_t agx:5;
3791  uint64_t reserved_5_7:3;
3792  uint64_t gmx_drp:5;
3793  uint64_t reserved_13_31:19;
3794  uint64_t agl:1;
3795  uint64_t reserved_33_39:7;
3796  uint64_t mii:1;
3797  uint64_t reserved_41_47:7;
3798  uint64_t ilk:1;
3799  uint64_t reserved_49_63:15;
3800 #endif
3801  } cn68xxp1;
3802 };
3803 
3804 union cvmx_ciu2_en_ppx_ip4_rml {
3805  uint64_t u64;
3806  struct cvmx_ciu2_en_ppx_ip4_rml_s {
3807 #ifdef __BIG_ENDIAN_BITFIELD
3808  uint64_t reserved_56_63:8;
3809  uint64_t trace:4;
3810  uint64_t reserved_49_51:3;
3811  uint64_t l2c:1;
3812  uint64_t reserved_41_47:7;
3813  uint64_t dfa:1;
3814  uint64_t reserved_37_39:3;
3815  uint64_t dpi_dma:1;
3816  uint64_t reserved_34_35:2;
3817  uint64_t dpi:1;
3818  uint64_t sli:1;
3819  uint64_t reserved_31_31:1;
3820  uint64_t key:1;
3821  uint64_t rad:1;
3822  uint64_t tim:1;
3823  uint64_t reserved_25_27:3;
3824  uint64_t zip:1;
3825  uint64_t reserved_17_23:7;
3826  uint64_t sso:1;
3827  uint64_t reserved_8_15:8;
3828  uint64_t pko:1;
3829  uint64_t pip:1;
3830  uint64_t ipd:1;
3831  uint64_t fpa:1;
3832  uint64_t reserved_1_3:3;
3833  uint64_t iob:1;
3834 #else
3835  uint64_t iob:1;
3836  uint64_t reserved_1_3:3;
3837  uint64_t fpa:1;
3838  uint64_t ipd:1;
3839  uint64_t pip:1;
3840  uint64_t pko:1;
3841  uint64_t reserved_8_15:8;
3842  uint64_t sso:1;
3843  uint64_t reserved_17_23:7;
3844  uint64_t zip:1;
3845  uint64_t reserved_25_27:3;
3846  uint64_t tim:1;
3847  uint64_t rad:1;
3848  uint64_t key:1;
3849  uint64_t reserved_31_31:1;
3850  uint64_t sli:1;
3851  uint64_t dpi:1;
3852  uint64_t reserved_34_35:2;
3853  uint64_t dpi_dma:1;
3854  uint64_t reserved_37_39:3;
3855  uint64_t dfa:1;
3856  uint64_t reserved_41_47:7;
3857  uint64_t l2c:1;
3858  uint64_t reserved_49_51:3;
3859  uint64_t trace:4;
3860  uint64_t reserved_56_63:8;
3861 #endif
3862  } s;
3863  struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx;
3864  struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
3865 #ifdef __BIG_ENDIAN_BITFIELD
3866  uint64_t reserved_56_63:8;
3867  uint64_t trace:4;
3868  uint64_t reserved_49_51:3;
3869  uint64_t l2c:1;
3870  uint64_t reserved_41_47:7;
3871  uint64_t dfa:1;
3872  uint64_t reserved_34_39:6;
3873  uint64_t dpi:1;
3874  uint64_t sli:1;
3875  uint64_t reserved_31_31:1;
3876  uint64_t key:1;
3877  uint64_t rad:1;
3878  uint64_t tim:1;
3879  uint64_t reserved_25_27:3;
3880  uint64_t zip:1;
3881  uint64_t reserved_17_23:7;
3882  uint64_t sso:1;
3883  uint64_t reserved_8_15:8;
3884  uint64_t pko:1;
3885  uint64_t pip:1;
3886  uint64_t ipd:1;
3887  uint64_t fpa:1;
3888  uint64_t reserved_1_3:3;
3889  uint64_t iob:1;
3890 #else
3891  uint64_t iob:1;
3892  uint64_t reserved_1_3:3;
3893  uint64_t fpa:1;
3894  uint64_t ipd:1;
3895  uint64_t pip:1;
3896  uint64_t pko:1;
3897  uint64_t reserved_8_15:8;
3898  uint64_t sso:1;
3899  uint64_t reserved_17_23:7;
3900  uint64_t zip:1;
3901  uint64_t reserved_25_27:3;
3902  uint64_t tim:1;
3903  uint64_t rad:1;
3904  uint64_t key:1;
3905  uint64_t reserved_31_31:1;
3906  uint64_t sli:1;
3907  uint64_t dpi:1;
3908  uint64_t reserved_34_39:6;
3909  uint64_t dfa:1;
3910  uint64_t reserved_41_47:7;
3911  uint64_t l2c:1;
3912  uint64_t reserved_49_51:3;
3913  uint64_t trace:4;
3914  uint64_t reserved_56_63:8;
3915 #endif
3916  } cn68xxp1;
3917 };
3918 
3919 union cvmx_ciu2_en_ppx_ip4_rml_w1c {
3920  uint64_t u64;
3921  struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
3922 #ifdef __BIG_ENDIAN_BITFIELD
3923  uint64_t reserved_56_63:8;
3924  uint64_t trace:4;
3925  uint64_t reserved_49_51:3;
3926  uint64_t l2c:1;
3927  uint64_t reserved_41_47:7;
3928  uint64_t dfa:1;
3929  uint64_t reserved_37_39:3;
3930  uint64_t dpi_dma:1;
3931  uint64_t reserved_34_35:2;
3932  uint64_t dpi:1;
3933  uint64_t sli:1;
3934  uint64_t reserved_31_31:1;
3935  uint64_t key:1;
3936  uint64_t rad:1;
3937  uint64_t tim:1;
3938  uint64_t reserved_25_27:3;
3939  uint64_t zip:1;
3940  uint64_t reserved_17_23:7;
3941  uint64_t sso:1;
3942  uint64_t reserved_8_15:8;
3943  uint64_t pko:1;
3944  uint64_t pip:1;
3945  uint64_t ipd:1;
3946  uint64_t fpa:1;
3947  uint64_t reserved_1_3:3;
3948  uint64_t iob:1;
3949 #else
3950  uint64_t iob:1;
3951  uint64_t reserved_1_3:3;
3952  uint64_t fpa:1;
3953  uint64_t ipd:1;
3954  uint64_t pip:1;
3955  uint64_t pko:1;
3956  uint64_t reserved_8_15:8;
3957  uint64_t sso:1;
3958  uint64_t reserved_17_23:7;
3959  uint64_t zip:1;
3960  uint64_t reserved_25_27:3;
3961  uint64_t tim:1;
3962  uint64_t rad:1;
3963  uint64_t key:1;
3964  uint64_t reserved_31_31:1;
3965  uint64_t sli:1;
3966  uint64_t dpi:1;
3967  uint64_t reserved_34_35:2;
3968  uint64_t dpi_dma:1;
3969  uint64_t reserved_37_39:3;
3970  uint64_t dfa:1;
3971  uint64_t reserved_41_47:7;
3972  uint64_t l2c:1;
3973  uint64_t reserved_49_51:3;
3974  uint64_t trace:4;
3975  uint64_t reserved_56_63:8;
3976 #endif
3977  } s;
3978  struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
3979  struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
3980 #ifdef __BIG_ENDIAN_BITFIELD
3981  uint64_t reserved_56_63:8;
3982  uint64_t trace:4;
3983  uint64_t reserved_49_51:3;
3984  uint64_t l2c:1;
3985  uint64_t reserved_41_47:7;
3986  uint64_t dfa:1;
3987  uint64_t reserved_34_39:6;
3988  uint64_t dpi:1;
3989  uint64_t sli:1;
3990  uint64_t reserved_31_31:1;
3991  uint64_t key:1;
3992  uint64_t rad:1;
3993  uint64_t tim:1;
3994  uint64_t reserved_25_27:3;
3995  uint64_t zip:1;
3996  uint64_t reserved_17_23:7;
3997  uint64_t sso:1;
3998  uint64_t reserved_8_15:8;
3999  uint64_t pko:1;
4000  uint64_t pip:1;
4001  uint64_t ipd:1;
4002  uint64_t fpa:1;
4003  uint64_t reserved_1_3:3;
4004  uint64_t iob:1;
4005 #else
4006  uint64_t iob:1;
4007  uint64_t reserved_1_3:3;
4008  uint64_t fpa:1;
4009  uint64_t ipd:1;
4010  uint64_t pip:1;
4011  uint64_t pko:1;
4012  uint64_t reserved_8_15:8;
4013  uint64_t sso:1;
4014  uint64_t reserved_17_23:7;
4015  uint64_t zip:1;
4016  uint64_t reserved_25_27:3;
4017  uint64_t tim:1;
4018  uint64_t rad:1;
4019  uint64_t key:1;
4020  uint64_t reserved_31_31:1;
4021  uint64_t sli:1;
4022  uint64_t dpi:1;
4023  uint64_t reserved_34_39:6;
4024  uint64_t dfa:1;
4025  uint64_t reserved_41_47:7;
4026  uint64_t l2c:1;
4027  uint64_t reserved_49_51:3;
4028  uint64_t trace:4;
4029  uint64_t reserved_56_63:8;
4030 #endif
4031  } cn68xxp1;
4032 };
4033 
4034 union cvmx_ciu2_en_ppx_ip4_rml_w1s {
4035  uint64_t u64;
4036  struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
4037 #ifdef __BIG_ENDIAN_BITFIELD
4038  uint64_t reserved_56_63:8;
4039  uint64_t trace:4;
4040  uint64_t reserved_49_51:3;
4041  uint64_t l2c:1;
4042  uint64_t reserved_41_47:7;
4043  uint64_t dfa:1;
4044  uint64_t reserved_37_39:3;
4045  uint64_t dpi_dma:1;
4046  uint64_t reserved_34_35:2;
4047  uint64_t dpi:1;
4048  uint64_t sli:1;
4049  uint64_t reserved_31_31:1;
4050  uint64_t key:1;
4051  uint64_t rad:1;
4052  uint64_t tim:1;
4053  uint64_t reserved_25_27:3;
4054  uint64_t zip:1;
4055  uint64_t reserved_17_23:7;
4056  uint64_t sso:1;
4057  uint64_t reserved_8_15:8;
4058  uint64_t pko:1;
4059  uint64_t pip:1;
4060  uint64_t ipd:1;
4061  uint64_t fpa:1;
4062  uint64_t reserved_1_3:3;
4063  uint64_t iob:1;
4064 #else
4065  uint64_t iob:1;
4066  uint64_t reserved_1_3:3;
4067  uint64_t fpa:1;
4068  uint64_t ipd:1;
4069  uint64_t pip:1;
4070  uint64_t pko:1;
4071  uint64_t reserved_8_15:8;
4072  uint64_t sso:1;
4073  uint64_t reserved_17_23:7;
4074  uint64_t zip:1;
4075  uint64_t reserved_25_27:3;
4076  uint64_t tim:1;
4077  uint64_t rad:1;
4078  uint64_t key:1;
4079  uint64_t reserved_31_31:1;
4080  uint64_t sli:1;
4081  uint64_t dpi:1;
4082  uint64_t reserved_34_35:2;
4083  uint64_t dpi_dma:1;
4084  uint64_t reserved_37_39:3;
4085  uint64_t dfa:1;
4086  uint64_t reserved_41_47:7;
4087  uint64_t l2c:1;
4088  uint64_t reserved_49_51:3;
4089  uint64_t trace:4;
4090  uint64_t reserved_56_63:8;
4091 #endif
4092  } s;
4093  struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
4094  struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
4095 #ifdef __BIG_ENDIAN_BITFIELD
4096  uint64_t reserved_56_63:8;
4097  uint64_t trace:4;
4098  uint64_t reserved_49_51:3;
4099  uint64_t l2c:1;
4100  uint64_t reserved_41_47:7;
4101  uint64_t dfa:1;
4102  uint64_t reserved_34_39:6;
4103  uint64_t dpi:1;
4104  uint64_t sli:1;
4105  uint64_t reserved_31_31:1;
4106  uint64_t key:1;
4107  uint64_t rad:1;
4108  uint64_t tim:1;
4109  uint64_t reserved_25_27:3;
4110  uint64_t zip:1;
4111  uint64_t reserved_17_23:7;
4112  uint64_t sso:1;
4113  uint64_t reserved_8_15:8;
4114  uint64_t pko:1;
4115  uint64_t pip:1;
4116  uint64_t ipd:1;
4117  uint64_t fpa:1;
4118  uint64_t reserved_1_3:3;
4119  uint64_t iob:1;
4120 #else
4121  uint64_t iob:1;
4122  uint64_t reserved_1_3:3;
4123  uint64_t fpa:1;
4124  uint64_t ipd:1;
4125  uint64_t pip:1;
4126  uint64_t pko:1;
4127  uint64_t reserved_8_15:8;
4128  uint64_t sso:1;
4129  uint64_t reserved_17_23:7;
4130  uint64_t zip:1;
4131  uint64_t reserved_25_27:3;
4132  uint64_t tim:1;
4133  uint64_t rad:1;
4134  uint64_t key:1;
4135  uint64_t reserved_31_31:1;
4136  uint64_t sli:1;
4137  uint64_t dpi:1;
4138  uint64_t reserved_34_39:6;
4139  uint64_t dfa:1;
4140  uint64_t reserved_41_47:7;
4141  uint64_t l2c:1;
4142  uint64_t reserved_49_51:3;
4143  uint64_t trace:4;
4144  uint64_t reserved_56_63:8;
4145 #endif
4146  } cn68xxp1;
4147 };
4148 
4149 union cvmx_ciu2_en_ppx_ip4_wdog {
4150  uint64_t u64;
4151  struct cvmx_ciu2_en_ppx_ip4_wdog_s {
4152 #ifdef __BIG_ENDIAN_BITFIELD
4153  uint64_t reserved_32_63:32;
4154  uint64_t wdog:32;
4155 #else
4156  uint64_t wdog:32;
4157  uint64_t reserved_32_63:32;
4158 #endif
4159  } s;
4160  struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx;
4161  struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1;
4162 };
4163 
4164 union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
4165  uint64_t u64;
4166  struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
4167 #ifdef __BIG_ENDIAN_BITFIELD
4168  uint64_t reserved_32_63:32;
4169  uint64_t wdog:32;
4170 #else
4171  uint64_t wdog:32;
4172  uint64_t reserved_32_63:32;
4173 #endif
4174  } s;
4175  struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
4176  struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
4177 };
4178 
4179 union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
4180  uint64_t u64;
4181  struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
4182 #ifdef __BIG_ENDIAN_BITFIELD
4183  uint64_t reserved_32_63:32;
4184  uint64_t wdog:32;
4185 #else
4186  uint64_t wdog:32;
4187  uint64_t reserved_32_63:32;
4188 #endif
4189  } s;
4190  struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
4191  struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
4192 };
4193 
4194 union cvmx_ciu2_en_ppx_ip4_wrkq {
4195  uint64_t u64;
4196  struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
4197 #ifdef __BIG_ENDIAN_BITFIELD
4198  uint64_t workq:64;
4199 #else
4200  uint64_t workq:64;
4201 #endif
4202  } s;
4203  struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx;
4204  struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1;
4205 };
4206 
4207 union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
4208  uint64_t u64;
4209  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
4210 #ifdef __BIG_ENDIAN_BITFIELD
4211  uint64_t workq:64;
4212 #else
4213  uint64_t workq:64;
4214 #endif
4215  } s;
4216  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
4217  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
4218 };
4219 
4220 union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
4221  uint64_t u64;
4222  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
4223 #ifdef __BIG_ENDIAN_BITFIELD
4224  uint64_t workq:64;
4225 #else
4226  uint64_t workq:64;
4227 #endif
4228  } s;
4229  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
4230  struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
4231 };
4232 
4233 union cvmx_ciu2_intr_ciu_ready {
4234  uint64_t u64;
4235  struct cvmx_ciu2_intr_ciu_ready_s {
4236 #ifdef __BIG_ENDIAN_BITFIELD
4237  uint64_t reserved_1_63:63;
4238  uint64_t ready:1;
4239 #else
4240  uint64_t ready:1;
4241  uint64_t reserved_1_63:63;
4242 #endif
4243  } s;
4244  struct cvmx_ciu2_intr_ciu_ready_s cn68xx;
4245  struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1;
4246 };
4247 
4248 union cvmx_ciu2_intr_ram_ecc_ctl {
4249  uint64_t u64;
4250  struct cvmx_ciu2_intr_ram_ecc_ctl_s {
4251 #ifdef __BIG_ENDIAN_BITFIELD
4252  uint64_t reserved_3_63:61;
4253  uint64_t flip_synd:2;
4254  uint64_t ecc_ena:1;
4255 #else
4256  uint64_t ecc_ena:1;
4257  uint64_t flip_synd:2;
4258  uint64_t reserved_3_63:61;
4259 #endif
4260  } s;
4261  struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx;
4262  struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1;
4263 };
4264 
4265 union cvmx_ciu2_intr_ram_ecc_st {
4266  uint64_t u64;
4267  struct cvmx_ciu2_intr_ram_ecc_st_s {
4268 #ifdef __BIG_ENDIAN_BITFIELD
4269  uint64_t reserved_23_63:41;
4270  uint64_t addr:7;
4271  uint64_t reserved_13_15:3;
4272  uint64_t syndrom:9;
4273  uint64_t reserved_2_3:2;
4274  uint64_t dbe:1;
4275  uint64_t sbe:1;
4276 #else
4277  uint64_t sbe:1;
4278  uint64_t dbe:1;
4279  uint64_t reserved_2_3:2;
4280  uint64_t syndrom:9;
4281  uint64_t reserved_13_15:3;
4282  uint64_t addr:7;
4283  uint64_t reserved_23_63:41;
4284 #endif
4285  } s;
4286  struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx;
4287  struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1;
4288 };
4289 
4290 union cvmx_ciu2_intr_slowdown {
4291  uint64_t u64;
4292  struct cvmx_ciu2_intr_slowdown_s {
4293 #ifdef __BIG_ENDIAN_BITFIELD
4294  uint64_t reserved_3_63:61;
4295  uint64_t ctl:3;
4296 #else
4297  uint64_t ctl:3;
4298  uint64_t reserved_3_63:61;
4299 #endif
4300  } s;
4301  struct cvmx_ciu2_intr_slowdown_s cn68xx;
4302  struct cvmx_ciu2_intr_slowdown_s cn68xxp1;
4303 };
4304 
4305 union cvmx_ciu2_msi_rcvx {
4306  uint64_t u64;
4307  struct cvmx_ciu2_msi_rcvx_s {
4308 #ifdef __BIG_ENDIAN_BITFIELD
4309  uint64_t reserved_1_63:63;
4310  uint64_t msi_rcv:1;
4311 #else
4312  uint64_t msi_rcv:1;
4313  uint64_t reserved_1_63:63;
4314 #endif
4315  } s;
4316  struct cvmx_ciu2_msi_rcvx_s cn68xx;
4317  struct cvmx_ciu2_msi_rcvx_s cn68xxp1;
4318 };
4319 
4320 union cvmx_ciu2_msi_selx {
4321  uint64_t u64;
4322  struct cvmx_ciu2_msi_selx_s {
4323 #ifdef __BIG_ENDIAN_BITFIELD
4324  uint64_t reserved_13_63:51;
4325  uint64_t pp_num:5;
4326  uint64_t reserved_6_7:2;
4327  uint64_t ip_num:2;
4328  uint64_t reserved_1_3:3;
4329  uint64_t en:1;
4330 #else
4331  uint64_t en:1;
4332  uint64_t reserved_1_3:3;
4333  uint64_t ip_num:2;
4334  uint64_t reserved_6_7:2;
4335  uint64_t pp_num:5;
4336  uint64_t reserved_13_63:51;
4337 #endif
4338  } s;
4339  struct cvmx_ciu2_msi_selx_s cn68xx;
4340  struct cvmx_ciu2_msi_selx_s cn68xxp1;
4341 };
4342 
4343 union cvmx_ciu2_msired_ppx_ip2 {
4344  uint64_t u64;
4345  struct cvmx_ciu2_msired_ppx_ip2_s {
4346 #ifdef __BIG_ENDIAN_BITFIELD
4347  uint64_t reserved_21_63:43;
4348  uint64_t intr:1;
4349  uint64_t reserved_17_19:3;
4350  uint64_t newint:1;
4351  uint64_t reserved_8_15:8;
4352  uint64_t msi_num:8;
4353 #else
4354  uint64_t msi_num:8;
4355  uint64_t reserved_8_15:8;
4356  uint64_t newint:1;
4357  uint64_t reserved_17_19:3;
4358  uint64_t intr:1;
4359  uint64_t reserved_21_63:43;
4360 #endif
4361  } s;
4362  struct cvmx_ciu2_msired_ppx_ip2_s cn68xx;
4363  struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1;
4364 };
4365 
4366 union cvmx_ciu2_msired_ppx_ip3 {
4367  uint64_t u64;
4368  struct cvmx_ciu2_msired_ppx_ip3_s {
4369 #ifdef __BIG_ENDIAN_BITFIELD
4370  uint64_t reserved_21_63:43;
4371  uint64_t intr:1;
4372  uint64_t reserved_17_19:3;
4373  uint64_t newint:1;
4374  uint64_t reserved_8_15:8;
4375  uint64_t msi_num:8;
4376 #else
4377  uint64_t msi_num:8;
4378  uint64_t reserved_8_15:8;
4379  uint64_t newint:1;
4380  uint64_t reserved_17_19:3;
4381  uint64_t intr:1;
4382  uint64_t reserved_21_63:43;
4383 #endif
4384  } s;
4385  struct cvmx_ciu2_msired_ppx_ip3_s cn68xx;
4386  struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1;
4387 };
4388 
4389 union cvmx_ciu2_msired_ppx_ip4 {
4390  uint64_t u64;
4391  struct cvmx_ciu2_msired_ppx_ip4_s {
4392 #ifdef __BIG_ENDIAN_BITFIELD
4393  uint64_t reserved_21_63:43;
4394  uint64_t intr:1;
4395  uint64_t reserved_17_19:3;
4396  uint64_t newint:1;
4397  uint64_t reserved_8_15:8;
4398  uint64_t msi_num:8;
4399 #else
4400  uint64_t msi_num:8;
4401  uint64_t reserved_8_15:8;
4402  uint64_t newint:1;
4403  uint64_t reserved_17_19:3;
4404  uint64_t intr:1;
4405  uint64_t reserved_21_63:43;
4406 #endif
4407  } s;
4408  struct cvmx_ciu2_msired_ppx_ip4_s cn68xx;
4409  struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1;
4410 };
4411 
4412 union cvmx_ciu2_raw_iox_int_gpio {
4413  uint64_t u64;
4414  struct cvmx_ciu2_raw_iox_int_gpio_s {
4415 #ifdef __BIG_ENDIAN_BITFIELD
4416  uint64_t reserved_16_63:48;
4417  uint64_t gpio:16;
4418 #else
4419  uint64_t gpio:16;
4420  uint64_t reserved_16_63:48;
4421 #endif
4422  } s;
4423  struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx;
4424  struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1;
4425 };
4426 
4427 union cvmx_ciu2_raw_iox_int_io {
4428  uint64_t u64;
4429  struct cvmx_ciu2_raw_iox_int_io_s {
4430 #ifdef __BIG_ENDIAN_BITFIELD
4431  uint64_t reserved_34_63:30;
4432  uint64_t pem:2;
4433  uint64_t reserved_18_31:14;
4434  uint64_t pci_inta:2;
4435  uint64_t reserved_13_15:3;
4436  uint64_t msired:1;
4437  uint64_t pci_msi:4;
4438  uint64_t reserved_4_7:4;
4439  uint64_t pci_intr:4;
4440 #else
4441  uint64_t pci_intr:4;
4442  uint64_t reserved_4_7:4;
4443  uint64_t pci_msi:4;
4444  uint64_t msired:1;
4445  uint64_t reserved_13_15:3;
4446  uint64_t pci_inta:2;
4447  uint64_t reserved_18_31:14;
4448  uint64_t pem:2;
4449  uint64_t reserved_34_63:30;
4450 #endif
4451  } s;
4452  struct cvmx_ciu2_raw_iox_int_io_s cn68xx;
4453  struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1;
4454 };
4455 
4456 union cvmx_ciu2_raw_iox_int_mem {
4457  uint64_t u64;
4458  struct cvmx_ciu2_raw_iox_int_mem_s {
4459 #ifdef __BIG_ENDIAN_BITFIELD
4460  uint64_t reserved_4_63:60;
4461  uint64_t lmc:4;
4462 #else
4463  uint64_t lmc:4;
4464  uint64_t reserved_4_63:60;
4465 #endif
4466  } s;
4467  struct cvmx_ciu2_raw_iox_int_mem_s cn68xx;
4468  struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1;
4469 };
4470 
4471 union cvmx_ciu2_raw_iox_int_mio {
4472  uint64_t u64;
4473  struct cvmx_ciu2_raw_iox_int_mio_s {
4474 #ifdef __BIG_ENDIAN_BITFIELD
4475  uint64_t rst:1;
4476  uint64_t reserved_49_62:14;
4477  uint64_t ptp:1;
4478  uint64_t reserved_45_47:3;
4479  uint64_t usb_hci:1;
4480  uint64_t reserved_41_43:3;
4481  uint64_t usb_uctl:1;
4482  uint64_t reserved_38_39:2;
4483  uint64_t uart:2;
4484  uint64_t reserved_34_35:2;
4485  uint64_t twsi:2;
4486  uint64_t reserved_19_31:13;
4487  uint64_t bootdma:1;
4488  uint64_t mio:1;
4489  uint64_t nand:1;
4490  uint64_t reserved_12_15:4;
4491  uint64_t timer:4;
4492  uint64_t reserved_3_7:5;
4493  uint64_t ipd_drp:1;
4494  uint64_t ssoiq:1;
4495  uint64_t ipdppthr:1;
4496 #else
4497  uint64_t ipdppthr:1;
4498  uint64_t ssoiq:1;
4499  uint64_t ipd_drp:1;
4500  uint64_t reserved_3_7:5;
4501  uint64_t timer:4;
4502  uint64_t reserved_12_15:4;
4503  uint64_t nand:1;
4504  uint64_t mio:1;
4505  uint64_t bootdma:1;
4506  uint64_t reserved_19_31:13;
4507  uint64_t twsi:2;
4508  uint64_t reserved_34_35:2;
4509  uint64_t uart:2;
4510  uint64_t reserved_38_39:2;
4511  uint64_t usb_uctl:1;
4512  uint64_t reserved_41_43:3;
4513  uint64_t usb_hci:1;
4514  uint64_t reserved_45_47:3;
4515  uint64_t ptp:1;
4516  uint64_t reserved_49_62:14;
4517  uint64_t rst:1;
4518 #endif
4519  } s;
4520  struct cvmx_ciu2_raw_iox_int_mio_s cn68xx;
4521  struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1;
4522 };
4523 
4524 union cvmx_ciu2_raw_iox_int_pkt {
4525  uint64_t u64;
4526  struct cvmx_ciu2_raw_iox_int_pkt_s {
4527 #ifdef __BIG_ENDIAN_BITFIELD
4528  uint64_t reserved_54_63:10;
4529  uint64_t ilk_drp:2;
4530  uint64_t reserved_49_51:3;
4531  uint64_t ilk:1;
4532  uint64_t reserved_41_47:7;
4533  uint64_t mii:1;
4534  uint64_t reserved_33_39:7;
4535  uint64_t agl:1;
4536  uint64_t reserved_13_31:19;
4537  uint64_t gmx_drp:5;
4538  uint64_t reserved_5_7:3;
4539  uint64_t agx:5;
4540 #else
4541  uint64_t agx:5;
4542  uint64_t reserved_5_7:3;
4543  uint64_t gmx_drp:5;
4544  uint64_t reserved_13_31:19;
4545  uint64_t agl:1;
4546  uint64_t reserved_33_39:7;
4547  uint64_t mii:1;
4548  uint64_t reserved_41_47:7;
4549  uint64_t ilk:1;
4550  uint64_t reserved_49_51:3;
4551  uint64_t ilk_drp:2;
4552  uint64_t reserved_54_63:10;
4553 #endif
4554  } s;
4555  struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx;
4556  struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
4557 #ifdef __BIG_ENDIAN_BITFIELD
4558  uint64_t reserved_49_63:15;
4559  uint64_t ilk:1;
4560  uint64_t reserved_41_47:7;
4561  uint64_t mii:1;
4562  uint64_t reserved_33_39:7;
4563  uint64_t agl:1;
4564  uint64_t reserved_13_31:19;
4565  uint64_t gmx_drp:5;
4566  uint64_t reserved_5_7:3;
4567  uint64_t agx:5;
4568 #else
4569  uint64_t agx:5;
4570  uint64_t reserved_5_7:3;
4571  uint64_t gmx_drp:5;
4572  uint64_t reserved_13_31:19;
4573  uint64_t agl:1;
4574  uint64_t reserved_33_39:7;
4575  uint64_t mii:1;
4576  uint64_t reserved_41_47:7;
4577  uint64_t ilk:1;
4578  uint64_t reserved_49_63:15;
4579 #endif
4580  } cn68xxp1;
4581 };
4582 
4583 union cvmx_ciu2_raw_iox_int_rml {
4584  uint64_t u64;
4585  struct cvmx_ciu2_raw_iox_int_rml_s {
4586 #ifdef __BIG_ENDIAN_BITFIELD
4587  uint64_t reserved_56_63:8;
4588  uint64_t trace:4;
4589  uint64_t reserved_49_51:3;
4590  uint64_t l2c:1;
4591  uint64_t reserved_41_47:7;
4592  uint64_t dfa:1;
4593  uint64_t reserved_37_39:3;
4594  uint64_t dpi_dma:1;
4595  uint64_t reserved_34_35:2;
4596  uint64_t dpi:1;
4597  uint64_t sli:1;
4598  uint64_t reserved_31_31:1;
4599  uint64_t key:1;
4600  uint64_t rad:1;
4601  uint64_t tim:1;
4602  uint64_t reserved_25_27:3;
4603  uint64_t zip:1;
4604  uint64_t reserved_17_23:7;
4605  uint64_t sso:1;
4606  uint64_t reserved_8_15:8;
4607  uint64_t pko:1;
4608  uint64_t pip:1;
4609  uint64_t ipd:1;
4610  uint64_t fpa:1;
4611  uint64_t reserved_1_3:3;
4612  uint64_t iob:1;
4613 #else
4614  uint64_t iob:1;
4615  uint64_t reserved_1_3:3;
4616  uint64_t fpa:1;
4617  uint64_t ipd:1;
4618  uint64_t pip:1;
4619  uint64_t pko:1;
4620  uint64_t reserved_8_15:8;
4621  uint64_t sso:1;
4622  uint64_t reserved_17_23:7;
4623  uint64_t zip:1;
4624  uint64_t reserved_25_27:3;
4625  uint64_t tim:1;
4626  uint64_t rad:1;
4627  uint64_t key:1;
4628  uint64_t reserved_31_31:1;
4629  uint64_t sli:1;
4630  uint64_t dpi:1;
4631  uint64_t reserved_34_35:2;
4632  uint64_t dpi_dma:1;
4633  uint64_t reserved_37_39:3;
4634  uint64_t dfa:1;
4635  uint64_t reserved_41_47:7;
4636  uint64_t l2c:1;
4637  uint64_t reserved_49_51:3;
4638  uint64_t trace:4;
4639  uint64_t reserved_56_63:8;
4640 #endif
4641  } s;
4642  struct cvmx_ciu2_raw_iox_int_rml_s cn68xx;
4643  struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
4644 #ifdef __BIG_ENDIAN_BITFIELD
4645  uint64_t reserved_56_63:8;
4646  uint64_t trace:4;
4647  uint64_t reserved_49_51:3;
4648  uint64_t l2c:1;
4649  uint64_t reserved_41_47:7;
4650  uint64_t dfa:1;
4651  uint64_t reserved_34_39:6;
4652  uint64_t dpi:1;
4653  uint64_t sli:1;
4654  uint64_t reserved_31_31:1;
4655  uint64_t key:1;
4656  uint64_t rad:1;
4657  uint64_t tim:1;
4658  uint64_t reserved_25_27:3;
4659  uint64_t zip:1;
4660  uint64_t reserved_17_23:7;
4661  uint64_t sso:1;
4662  uint64_t reserved_8_15:8;
4663  uint64_t pko:1;
4664  uint64_t pip:1;
4665  uint64_t ipd:1;
4666  uint64_t fpa:1;
4667  uint64_t reserved_1_3:3;
4668  uint64_t iob:1;
4669 #else
4670  uint64_t iob:1;
4671  uint64_t reserved_1_3:3;
4672  uint64_t fpa:1;
4673  uint64_t ipd:1;
4674  uint64_t pip:1;
4675  uint64_t pko:1;
4676  uint64_t reserved_8_15:8;
4677  uint64_t sso:1;
4678  uint64_t reserved_17_23:7;
4679  uint64_t zip:1;
4680  uint64_t reserved_25_27:3;
4681  uint64_t tim:1;
4682  uint64_t rad:1;
4683  uint64_t key:1;
4684  uint64_t reserved_31_31:1;
4685  uint64_t sli:1;
4686  uint64_t dpi:1;
4687  uint64_t reserved_34_39:6;
4688  uint64_t dfa:1;
4689  uint64_t reserved_41_47:7;
4690  uint64_t l2c:1;
4691  uint64_t reserved_49_51:3;
4692  uint64_t trace:4;
4693  uint64_t reserved_56_63:8;
4694 #endif
4695  } cn68xxp1;
4696 };
4697 
4698 union cvmx_ciu2_raw_iox_int_wdog {
4699  uint64_t u64;
4700  struct cvmx_ciu2_raw_iox_int_wdog_s {
4701 #ifdef __BIG_ENDIAN_BITFIELD
4702  uint64_t reserved_32_63:32;
4703  uint64_t wdog:32;
4704 #else
4705  uint64_t wdog:32;
4706  uint64_t reserved_32_63:32;
4707 #endif
4708  } s;
4709  struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx;
4710  struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1;
4711 };
4712 
4713 union cvmx_ciu2_raw_iox_int_wrkq {
4714  uint64_t u64;
4715  struct cvmx_ciu2_raw_iox_int_wrkq_s {
4716 #ifdef __BIG_ENDIAN_BITFIELD
4717  uint64_t workq:64;
4718 #else
4719  uint64_t workq:64;
4720 #endif
4721  } s;
4722  struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx;
4723  struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1;
4724 };
4725 
4726 union cvmx_ciu2_raw_ppx_ip2_gpio {
4727  uint64_t u64;
4728  struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
4729 #ifdef __BIG_ENDIAN_BITFIELD
4730  uint64_t reserved_16_63:48;
4731  uint64_t gpio:16;
4732 #else
4733  uint64_t gpio:16;
4734  uint64_t reserved_16_63:48;
4735 #endif
4736  } s;
4737  struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx;
4738  struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1;
4739 };
4740 
4741 union cvmx_ciu2_raw_ppx_ip2_io {
4742  uint64_t u64;
4743  struct cvmx_ciu2_raw_ppx_ip2_io_s {
4744 #ifdef __BIG_ENDIAN_BITFIELD
4745  uint64_t reserved_34_63:30;
4746  uint64_t pem:2;
4747  uint64_t reserved_18_31:14;
4748  uint64_t pci_inta:2;
4749  uint64_t reserved_13_15:3;
4750  uint64_t msired:1;
4751  uint64_t pci_msi:4;
4752  uint64_t reserved_4_7:4;
4753  uint64_t pci_intr:4;
4754 #else
4755  uint64_t pci_intr:4;
4756  uint64_t reserved_4_7:4;
4757  uint64_t pci_msi:4;
4758  uint64_t msired:1;
4759  uint64_t reserved_13_15:3;
4760  uint64_t pci_inta:2;
4761  uint64_t reserved_18_31:14;
4762  uint64_t pem:2;
4763  uint64_t reserved_34_63:30;
4764 #endif
4765  } s;
4766  struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx;
4767  struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1;
4768 };
4769 
4770 union cvmx_ciu2_raw_ppx_ip2_mem {
4771  uint64_t u64;
4772  struct cvmx_ciu2_raw_ppx_ip2_mem_s {
4773 #ifdef __BIG_ENDIAN_BITFIELD
4774  uint64_t reserved_4_63:60;
4775  uint64_t lmc:4;
4776 #else
4777  uint64_t lmc:4;
4778  uint64_t reserved_4_63:60;
4779 #endif
4780  } s;
4781  struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx;
4782  struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1;
4783 };
4784 
4785 union cvmx_ciu2_raw_ppx_ip2_mio {
4786  uint64_t u64;
4787  struct cvmx_ciu2_raw_ppx_ip2_mio_s {
4788 #ifdef __BIG_ENDIAN_BITFIELD
4789  uint64_t rst:1;
4790  uint64_t reserved_49_62:14;
4791  uint64_t ptp:1;
4792  uint64_t reserved_45_47:3;
4793  uint64_t usb_hci:1;
4794  uint64_t reserved_41_43:3;
4795  uint64_t usb_uctl:1;
4796  uint64_t reserved_38_39:2;
4797  uint64_t uart:2;
4798  uint64_t reserved_34_35:2;
4799  uint64_t twsi:2;
4800  uint64_t reserved_19_31:13;
4801  uint64_t bootdma:1;
4802  uint64_t mio:1;
4803  uint64_t nand:1;
4804  uint64_t reserved_12_15:4;
4805  uint64_t timer:4;
4806  uint64_t reserved_3_7:5;
4807  uint64_t ipd_drp:1;
4808  uint64_t ssoiq:1;
4809  uint64_t ipdppthr:1;
4810 #else
4811  uint64_t ipdppthr:1;
4812  uint64_t ssoiq:1;
4813  uint64_t ipd_drp:1;
4814  uint64_t reserved_3_7:5;
4815  uint64_t timer:4;
4816  uint64_t reserved_12_15:4;
4817  uint64_t nand:1;
4818  uint64_t mio:1;
4819  uint64_t bootdma:1;
4820  uint64_t reserved_19_31:13;
4821  uint64_t twsi:2;
4822  uint64_t reserved_34_35:2;
4823  uint64_t uart:2;
4824  uint64_t reserved_38_39:2;
4825  uint64_t usb_uctl:1;
4826  uint64_t reserved_41_43:3;
4827  uint64_t usb_hci:1;
4828  uint64_t reserved_45_47:3;
4829  uint64_t ptp:1;
4830  uint64_t reserved_49_62:14;
4831  uint64_t rst:1;
4832 #endif
4833  } s;
4834  struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx;
4835  struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1;
4836 };
4837 
4838 union cvmx_ciu2_raw_ppx_ip2_pkt {
4839  uint64_t u64;
4840  struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
4841 #ifdef __BIG_ENDIAN_BITFIELD
4842  uint64_t reserved_54_63:10;
4843  uint64_t ilk_drp:2;
4844  uint64_t reserved_49_51:3;
4845  uint64_t ilk:1;
4846  uint64_t reserved_41_47:7;
4847  uint64_t mii:1;
4848  uint64_t reserved_33_39:7;
4849  uint64_t agl:1;
4850  uint64_t reserved_13_31:19;
4851  uint64_t gmx_drp:5;
4852  uint64_t reserved_5_7:3;
4853  uint64_t agx:5;
4854 #else
4855  uint64_t agx:5;
4856  uint64_t reserved_5_7:3;
4857  uint64_t gmx_drp:5;
4858  uint64_t reserved_13_31:19;
4859  uint64_t agl:1;
4860  uint64_t reserved_33_39:7;
4861  uint64_t mii:1;
4862  uint64_t reserved_41_47:7;
4863  uint64_t ilk:1;
4864  uint64_t reserved_49_51:3;
4865  uint64_t ilk_drp:2;
4866  uint64_t reserved_54_63:10;
4867 #endif
4868  } s;
4869  struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx;
4870  struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
4871 #ifdef __BIG_ENDIAN_BITFIELD
4872  uint64_t reserved_49_63:15;
4873  uint64_t ilk:1;
4874  uint64_t reserved_41_47:7;
4875  uint64_t mii:1;
4876  uint64_t reserved_33_39:7;
4877  uint64_t agl:1;
4878  uint64_t reserved_13_31:19;
4879  uint64_t gmx_drp:5;
4880  uint64_t reserved_5_7:3;
4881  uint64_t agx:5;
4882 #else
4883  uint64_t agx:5;
4884  uint64_t reserved_5_7:3;
4885  uint64_t gmx_drp:5;
4886  uint64_t reserved_13_31:19;
4887  uint64_t agl:1;
4888  uint64_t reserved_33_39:7;
4889  uint64_t mii:1;
4890  uint64_t reserved_41_47:7;
4891  uint64_t ilk:1;
4892  uint64_t reserved_49_63:15;
4893 #endif
4894  } cn68xxp1;
4895 };
4896 
4897 union cvmx_ciu2_raw_ppx_ip2_rml {
4898  uint64_t u64;
4899  struct cvmx_ciu2_raw_ppx_ip2_rml_s {
4900 #ifdef __BIG_ENDIAN_BITFIELD
4901  uint64_t reserved_56_63:8;
4902  uint64_t trace:4;
4903  uint64_t reserved_49_51:3;
4904  uint64_t l2c:1;
4905  uint64_t reserved_41_47:7;
4906  uint64_t dfa:1;
4907  uint64_t reserved_37_39:3;
4908  uint64_t dpi_dma:1;
4909  uint64_t reserved_34_35:2;
4910  uint64_t dpi:1;
4911  uint64_t sli:1;
4912  uint64_t reserved_31_31:1;
4913  uint64_t key:1;
4914  uint64_t rad:1;
4915  uint64_t tim:1;
4916  uint64_t reserved_25_27:3;
4917  uint64_t zip:1;
4918  uint64_t reserved_17_23:7;
4919  uint64_t sso:1;
4920  uint64_t reserved_8_15:8;
4921  uint64_t pko:1;
4922  uint64_t pip:1;
4923  uint64_t ipd:1;
4924  uint64_t fpa:1;
4925  uint64_t reserved_1_3:3;
4926  uint64_t iob:1;
4927 #else
4928  uint64_t iob:1;
4929  uint64_t reserved_1_3:3;
4930  uint64_t fpa:1;
4931  uint64_t ipd:1;
4932  uint64_t pip:1;
4933  uint64_t pko:1;
4934  uint64_t reserved_8_15:8;
4935  uint64_t sso:1;
4936  uint64_t reserved_17_23:7;
4937  uint64_t zip:1;
4938  uint64_t reserved_25_27:3;
4939  uint64_t tim:1;
4940  uint64_t rad:1;
4941  uint64_t key:1;
4942  uint64_t reserved_31_31:1;
4943  uint64_t sli:1;
4944  uint64_t dpi:1;
4945  uint64_t reserved_34_35:2;
4946  uint64_t dpi_dma:1;
4947  uint64_t reserved_37_39:3;
4948  uint64_t dfa:1;
4949  uint64_t reserved_41_47:7;
4950  uint64_t l2c:1;
4951  uint64_t reserved_49_51:3;
4952  uint64_t trace:4;
4953  uint64_t reserved_56_63:8;
4954 #endif
4955  } s;
4956  struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx;
4957  struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
4958 #ifdef __BIG_ENDIAN_BITFIELD
4959  uint64_t reserved_56_63:8;
4960  uint64_t trace:4;
4961  uint64_t reserved_49_51:3;
4962  uint64_t l2c:1;
4963  uint64_t reserved_41_47:7;
4964  uint64_t dfa:1;
4965  uint64_t reserved_34_39:6;
4966  uint64_t dpi:1;
4967  uint64_t sli:1;
4968  uint64_t reserved_31_31:1;
4969  uint64_t key:1;
4970  uint64_t rad:1;
4971  uint64_t tim:1;
4972  uint64_t reserved_25_27:3;
4973  uint64_t zip:1;
4974  uint64_t reserved_17_23:7;
4975  uint64_t sso:1;
4976  uint64_t reserved_8_15:8;
4977  uint64_t pko:1;
4978  uint64_t pip:1;
4979  uint64_t ipd:1;
4980  uint64_t fpa:1;
4981  uint64_t reserved_1_3:3;
4982  uint64_t iob:1;
4983 #else
4984  uint64_t iob:1;
4985  uint64_t reserved_1_3:3;
4986  uint64_t fpa:1;
4987  uint64_t ipd:1;
4988  uint64_t pip:1;
4989  uint64_t pko:1;
4990  uint64_t reserved_8_15:8;
4991  uint64_t sso:1;
4992  uint64_t reserved_17_23:7;
4993  uint64_t zip:1;
4994  uint64_t reserved_25_27:3;
4995  uint64_t tim:1;
4996  uint64_t rad:1;
4997  uint64_t key:1;
4998  uint64_t reserved_31_31:1;
4999  uint64_t sli:1;
5000  uint64_t dpi:1;
5001  uint64_t reserved_34_39:6;
5002  uint64_t dfa:1;
5003  uint64_t reserved_41_47:7;
5004  uint64_t l2c:1;
5005  uint64_t reserved_49_51:3;
5006  uint64_t trace:4;
5007  uint64_t reserved_56_63:8;
5008 #endif
5009  } cn68xxp1;
5010 };
5011 
5012 union cvmx_ciu2_raw_ppx_ip2_wdog {
5013  uint64_t u64;
5014  struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
5015 #ifdef __BIG_ENDIAN_BITFIELD
5016  uint64_t reserved_32_63:32;
5017  uint64_t wdog:32;
5018 #else
5019  uint64_t wdog:32;
5020  uint64_t reserved_32_63:32;
5021 #endif
5022  } s;
5023  struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx;
5024  struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1;
5025 };
5026 
5027 union cvmx_ciu2_raw_ppx_ip2_wrkq {
5028  uint64_t u64;
5029  struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
5030 #ifdef __BIG_ENDIAN_BITFIELD
5031  uint64_t workq:64;
5032 #else
5033  uint64_t workq:64;
5034 #endif
5035  } s;
5036  struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx;
5037  struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1;
5038 };
5039 
5040 union cvmx_ciu2_raw_ppx_ip3_gpio {
5041  uint64_t u64;
5042  struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
5043 #ifdef __BIG_ENDIAN_BITFIELD
5044  uint64_t reserved_16_63:48;
5045  uint64_t gpio:16;
5046 #else
5047  uint64_t gpio:16;
5048  uint64_t reserved_16_63:48;
5049 #endif
5050  } s;
5051  struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx;
5052  struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1;
5053 };
5054 
5055 union cvmx_ciu2_raw_ppx_ip3_io {
5056  uint64_t u64;
5057  struct cvmx_ciu2_raw_ppx_ip3_io_s {
5058 #ifdef __BIG_ENDIAN_BITFIELD
5059  uint64_t reserved_34_63:30;
5060  uint64_t pem:2;
5061  uint64_t reserved_18_31:14;
5062  uint64_t pci_inta:2;
5063  uint64_t reserved_13_15:3;
5064  uint64_t msired:1;
5065  uint64_t pci_msi:4;
5066  uint64_t reserved_4_7:4;
5067  uint64_t pci_intr:4;
5068 #else
5069  uint64_t pci_intr:4;
5070  uint64_t reserved_4_7:4;
5071  uint64_t pci_msi:4;
5072  uint64_t msired:1;
5073  uint64_t reserved_13_15:3;
5074  uint64_t pci_inta:2;
5075  uint64_t reserved_18_31:14;
5076  uint64_t pem:2;
5077  uint64_t reserved_34_63:30;
5078 #endif
5079  } s;
5080  struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx;
5081  struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1;
5082 };
5083 
5084 union cvmx_ciu2_raw_ppx_ip3_mem {
5085  uint64_t u64;
5086  struct cvmx_ciu2_raw_ppx_ip3_mem_s {
5087 #ifdef __BIG_ENDIAN_BITFIELD
5088  uint64_t reserved_4_63:60;
5089  uint64_t lmc:4;
5090 #else
5091  uint64_t lmc:4;
5092  uint64_t reserved_4_63:60;
5093 #endif
5094  } s;
5095  struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx;
5096  struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1;
5097 };
5098 
5099 union cvmx_ciu2_raw_ppx_ip3_mio {
5100  uint64_t u64;
5101  struct cvmx_ciu2_raw_ppx_ip3_mio_s {
5102 #ifdef __BIG_ENDIAN_BITFIELD
5103  uint64_t rst:1;
5104  uint64_t reserved_49_62:14;
5105  uint64_t ptp:1;
5106  uint64_t reserved_45_47:3;
5107  uint64_t usb_hci:1;
5108  uint64_t reserved_41_43:3;
5109  uint64_t usb_uctl:1;
5110  uint64_t reserved_38_39:2;
5111  uint64_t uart:2;
5112  uint64_t reserved_34_35:2;
5113  uint64_t twsi:2;
5114  uint64_t reserved_19_31:13;
5115  uint64_t bootdma:1;
5116  uint64_t mio:1;
5117  uint64_t nand:1;
5118  uint64_t reserved_12_15:4;
5119  uint64_t timer:4;
5120  uint64_t reserved_3_7:5;
5121  uint64_t ipd_drp:1;
5122  uint64_t ssoiq:1;
5123  uint64_t ipdppthr:1;
5124 #else
5125  uint64_t ipdppthr:1;
5126  uint64_t ssoiq:1;
5127  uint64_t ipd_drp:1;
5128  uint64_t reserved_3_7:5;
5129  uint64_t timer:4;
5130  uint64_t reserved_12_15:4;
5131  uint64_t nand:1;
5132  uint64_t mio:1;
5133  uint64_t bootdma:1;
5134  uint64_t reserved_19_31:13;
5135  uint64_t twsi:2;
5136  uint64_t reserved_34_35:2;
5137  uint64_t uart:2;
5138  uint64_t reserved_38_39:2;
5139  uint64_t usb_uctl:1;
5140  uint64_t reserved_41_43:3;
5141  uint64_t usb_hci:1;
5142  uint64_t reserved_45_47:3;
5143  uint64_t ptp:1;
5144  uint64_t reserved_49_62:14;
5145  uint64_t rst:1;
5146 #endif
5147  } s;
5148  struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx;
5149  struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1;
5150 };
5151 
5152 union cvmx_ciu2_raw_ppx_ip3_pkt {
5153  uint64_t u64;
5154  struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
5155 #ifdef __BIG_ENDIAN_BITFIELD
5156  uint64_t reserved_54_63:10;
5157  uint64_t ilk_drp:2;
5158  uint64_t reserved_49_51:3;
5159  uint64_t ilk:1;
5160  uint64_t reserved_41_47:7;
5161  uint64_t mii:1;
5162  uint64_t reserved_33_39:7;
5163  uint64_t agl:1;
5164  uint64_t reserved_13_31:19;
5165  uint64_t gmx_drp:5;
5166  uint64_t reserved_5_7:3;
5167  uint64_t agx:5;
5168 #else
5169  uint64_t agx:5;
5170  uint64_t reserved_5_7:3;
5171  uint64_t gmx_drp:5;
5172  uint64_t reserved_13_31:19;
5173  uint64_t agl:1;
5174  uint64_t reserved_33_39:7;
5175  uint64_t mii:1;
5176  uint64_t reserved_41_47:7;
5177  uint64_t ilk:1;
5178  uint64_t reserved_49_51:3;
5179  uint64_t ilk_drp:2;
5180  uint64_t reserved_54_63:10;
5181 #endif
5182  } s;
5183  struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx;
5184  struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
5185 #ifdef __BIG_ENDIAN_BITFIELD
5186  uint64_t reserved_49_63:15;
5187  uint64_t ilk:1;
5188  uint64_t reserved_41_47:7;
5189  uint64_t mii:1;
5190  uint64_t reserved_33_39:7;
5191  uint64_t agl:1;
5192  uint64_t reserved_13_31:19;
5193  uint64_t gmx_drp:5;
5194  uint64_t reserved_5_7:3;
5195  uint64_t agx:5;
5196 #else
5197  uint64_t agx:5;
5198  uint64_t reserved_5_7:3;
5199  uint64_t gmx_drp:5;
5200  uint64_t reserved_13_31:19;
5201  uint64_t agl:1;
5202  uint64_t reserved_33_39:7;
5203  uint64_t mii:1;
5204  uint64_t reserved_41_47:7;
5205  uint64_t ilk:1;
5206  uint64_t reserved_49_63:15;
5207 #endif
5208  } cn68xxp1;
5209 };
5210 
5211 union cvmx_ciu2_raw_ppx_ip3_rml {
5212  uint64_t u64;
5213  struct cvmx_ciu2_raw_ppx_ip3_rml_s {
5214 #ifdef __BIG_ENDIAN_BITFIELD
5215  uint64_t reserved_56_63:8;
5216  uint64_t trace:4;
5217  uint64_t reserved_49_51:3;
5218  uint64_t l2c:1;
5219  uint64_t reserved_41_47:7;
5220  uint64_t dfa:1;
5221  uint64_t reserved_37_39:3;
5222  uint64_t dpi_dma:1;
5223  uint64_t reserved_34_35:2;
5224  uint64_t dpi:1;
5225  uint64_t sli:1;
5226  uint64_t reserved_31_31:1;
5227  uint64_t key:1;
5228  uint64_t rad:1;
5229  uint64_t tim:1;
5230  uint64_t reserved_25_27:3;
5231  uint64_t zip:1;
5232  uint64_t reserved_17_23:7;
5233  uint64_t sso:1;
5234  uint64_t reserved_8_15:8;
5235  uint64_t pko:1;
5236  uint64_t pip:1;
5237  uint64_t ipd:1;
5238  uint64_t fpa:1;
5239  uint64_t reserved_1_3:3;
5240  uint64_t iob:1;
5241 #else
5242  uint64_t iob:1;
5243  uint64_t reserved_1_3:3;
5244  uint64_t fpa:1;
5245  uint64_t ipd:1;
5246  uint64_t pip:1;
5247  uint64_t pko:1;
5248  uint64_t reserved_8_15:8;
5249  uint64_t sso:1;
5250  uint64_t reserved_17_23:7;
5251  uint64_t zip:1;
5252  uint64_t reserved_25_27:3;
5253  uint64_t tim:1;
5254  uint64_t rad:1;
5255  uint64_t key:1;
5256  uint64_t reserved_31_31:1;
5257  uint64_t sli:1;
5258  uint64_t dpi:1;
5259  uint64_t reserved_34_35:2;
5260  uint64_t dpi_dma:1;
5261  uint64_t reserved_37_39:3;
5262  uint64_t dfa:1;
5263  uint64_t reserved_41_47:7;
5264  uint64_t l2c:1;
5265  uint64_t reserved_49_51:3;
5266  uint64_t trace:4;
5267  uint64_t reserved_56_63:8;
5268 #endif
5269  } s;
5270  struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx;
5271  struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
5272 #ifdef __BIG_ENDIAN_BITFIELD
5273  uint64_t reserved_56_63:8;
5274  uint64_t trace:4;
5275  uint64_t reserved_49_51:3;
5276  uint64_t l2c:1;
5277  uint64_t reserved_41_47:7;
5278  uint64_t dfa:1;
5279  uint64_t reserved_34_39:6;
5280  uint64_t dpi:1;
5281  uint64_t sli:1;
5282  uint64_t reserved_31_31:1;
5283  uint64_t key:1;
5284  uint64_t rad:1;
5285  uint64_t tim:1;
5286  uint64_t reserved_25_27:3;
5287  uint64_t zip:1;
5288  uint64_t reserved_17_23:7;
5289  uint64_t sso:1;
5290  uint64_t reserved_8_15:8;
5291  uint64_t pko:1;
5292  uint64_t pip:1;
5293  uint64_t ipd:1;
5294  uint64_t fpa:1;
5295  uint64_t reserved_1_3:3;
5296  uint64_t iob:1;
5297 #else
5298  uint64_t iob:1;
5299  uint64_t reserved_1_3:3;
5300  uint64_t fpa:1;
5301  uint64_t ipd:1;
5302  uint64_t pip:1;
5303  uint64_t pko:1;
5304  uint64_t reserved_8_15:8;
5305  uint64_t sso:1;
5306  uint64_t reserved_17_23:7;
5307  uint64_t zip:1;
5308  uint64_t reserved_25_27:3;
5309  uint64_t tim:1;
5310  uint64_t rad:1;
5311  uint64_t key:1;
5312  uint64_t reserved_31_31:1;
5313  uint64_t sli:1;
5314  uint64_t dpi:1;
5315  uint64_t reserved_34_39:6;
5316  uint64_t dfa:1;
5317  uint64_t reserved_41_47:7;
5318  uint64_t l2c:1;
5319  uint64_t reserved_49_51:3;
5320  uint64_t trace:4;
5321  uint64_t reserved_56_63:8;
5322 #endif
5323  } cn68xxp1;
5324 };
5325 
5326 union cvmx_ciu2_raw_ppx_ip3_wdog {
5327  uint64_t u64;
5328  struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
5329 #ifdef __BIG_ENDIAN_BITFIELD
5330  uint64_t reserved_32_63:32;
5331  uint64_t wdog:32;
5332 #else
5333  uint64_t wdog:32;
5334  uint64_t reserved_32_63:32;
5335 #endif
5336  } s;
5337  struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx;
5338  struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1;
5339 };
5340 
5341 union cvmx_ciu2_raw_ppx_ip3_wrkq {
5342  uint64_t u64;
5343  struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
5344 #ifdef __BIG_ENDIAN_BITFIELD
5345  uint64_t workq:64;
5346 #else
5347  uint64_t workq:64;
5348 #endif
5349  } s;
5350  struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx;
5351  struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1;
5352 };
5353 
5354 union cvmx_ciu2_raw_ppx_ip4_gpio {
5355  uint64_t u64;
5356  struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
5357 #ifdef __BIG_ENDIAN_BITFIELD
5358  uint64_t reserved_16_63:48;
5359  uint64_t gpio:16;
5360 #else
5361  uint64_t gpio:16;
5362  uint64_t reserved_16_63:48;
5363 #endif
5364  } s;
5365  struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx;
5366  struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1;
5367 };
5368 
5369 union cvmx_ciu2_raw_ppx_ip4_io {
5370  uint64_t u64;
5371  struct cvmx_ciu2_raw_ppx_ip4_io_s {
5372 #ifdef __BIG_ENDIAN_BITFIELD
5373  uint64_t reserved_34_63:30;
5374  uint64_t pem:2;
5375  uint64_t reserved_18_31:14;
5376  uint64_t pci_inta:2;
5377  uint64_t reserved_13_15:3;
5378  uint64_t msired:1;
5379  uint64_t pci_msi:4;
5380  uint64_t reserved_4_7:4;
5381  uint64_t pci_intr:4;
5382 #else
5383  uint64_t pci_intr:4;
5384  uint64_t reserved_4_7:4;
5385  uint64_t pci_msi:4;
5386  uint64_t msired:1;
5387  uint64_t reserved_13_15:3;
5388  uint64_t pci_inta:2;
5389  uint64_t reserved_18_31:14;
5390  uint64_t pem:2;
5391  uint64_t reserved_34_63:30;
5392 #endif
5393  } s;
5394  struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx;
5395  struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1;
5396 };
5397 
5398 union cvmx_ciu2_raw_ppx_ip4_mem {
5399  uint64_t u64;
5400  struct cvmx_ciu2_raw_ppx_ip4_mem_s {
5401 #ifdef __BIG_ENDIAN_BITFIELD
5402  uint64_t reserved_4_63:60;
5403  uint64_t lmc:4;
5404 #else
5405  uint64_t lmc:4;
5406  uint64_t reserved_4_63:60;
5407 #endif
5408  } s;
5409  struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx;
5410  struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1;
5411 };
5412 
5413 union cvmx_ciu2_raw_ppx_ip4_mio {
5414  uint64_t u64;
5415  struct cvmx_ciu2_raw_ppx_ip4_mio_s {
5416 #ifdef __BIG_ENDIAN_BITFIELD
5417  uint64_t rst:1;
5418  uint64_t reserved_49_62:14;
5419  uint64_t ptp:1;
5420  uint64_t reserved_45_47:3;
5421  uint64_t usb_hci:1;
5422  uint64_t reserved_41_43:3;
5423  uint64_t usb_uctl:1;
5424  uint64_t reserved_38_39:2;
5425  uint64_t uart:2;
5426  uint64_t reserved_34_35:2;
5427  uint64_t twsi:2;
5428  uint64_t reserved_19_31:13;
5429  uint64_t bootdma:1;
5430  uint64_t mio:1;
5431  uint64_t nand:1;
5432  uint64_t reserved_12_15:4;
5433  uint64_t timer:4;
5434  uint64_t reserved_3_7:5;
5435  uint64_t ipd_drp:1;
5436  uint64_t ssoiq:1;
5437  uint64_t ipdppthr:1;
5438 #else
5439  uint64_t ipdppthr:1;
5440  uint64_t ssoiq:1;
5441  uint64_t ipd_drp:1;
5442  uint64_t reserved_3_7:5;
5443  uint64_t timer:4;
5444  uint64_t reserved_12_15:4;
5445  uint64_t nand:1;
5446  uint64_t mio:1;
5447  uint64_t bootdma:1;
5448  uint64_t reserved_19_31:13;
5449  uint64_t twsi:2;
5450  uint64_t reserved_34_35:2;
5451  uint64_t uart:2;
5452  uint64_t reserved_38_39:2;
5453  uint64_t usb_uctl:1;
5454  uint64_t reserved_41_43:3;
5455  uint64_t usb_hci:1;
5456  uint64_t reserved_45_47:3;
5457  uint64_t ptp:1;
5458  uint64_t reserved_49_62:14;
5459  uint64_t rst:1;
5460 #endif
5461  } s;
5462  struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx;
5463  struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1;
5464 };
5465 
5466 union cvmx_ciu2_raw_ppx_ip4_pkt {
5467  uint64_t u64;
5468  struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
5469 #ifdef __BIG_ENDIAN_BITFIELD
5470  uint64_t reserved_54_63:10;
5471  uint64_t ilk_drp:2;
5472  uint64_t reserved_49_51:3;
5473  uint64_t ilk:1;
5474  uint64_t reserved_41_47:7;
5475  uint64_t mii:1;
5476  uint64_t reserved_33_39:7;
5477  uint64_t agl:1;
5478  uint64_t reserved_13_31:19;
5479  uint64_t gmx_drp:5;
5480  uint64_t reserved_5_7:3;
5481  uint64_t agx:5;
5482 #else
5483  uint64_t agx:5;
5484  uint64_t reserved_5_7:3;
5485  uint64_t gmx_drp:5;
5486  uint64_t reserved_13_31:19;
5487  uint64_t agl:1;
5488  uint64_t reserved_33_39:7;
5489  uint64_t mii:1;
5490  uint64_t reserved_41_47:7;
5491  uint64_t ilk:1;
5492  uint64_t reserved_49_51:3;
5493  uint64_t ilk_drp:2;
5494  uint64_t reserved_54_63:10;
5495 #endif
5496  } s;
5497  struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx;
5498  struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
5499 #ifdef __BIG_ENDIAN_BITFIELD
5500  uint64_t reserved_49_63:15;
5501  uint64_t ilk:1;
5502  uint64_t reserved_41_47:7;
5503  uint64_t mii:1;
5504  uint64_t reserved_33_39:7;
5505  uint64_t agl:1;
5506  uint64_t reserved_13_31:19;
5507  uint64_t gmx_drp:5;
5508  uint64_t reserved_5_7:3;
5509  uint64_t agx:5;
5510 #else
5511  uint64_t agx:5;
5512  uint64_t reserved_5_7:3;
5513  uint64_t gmx_drp:5;
5514  uint64_t reserved_13_31:19;
5515  uint64_t agl:1;
5516  uint64_t reserved_33_39:7;
5517  uint64_t mii:1;
5518  uint64_t reserved_41_47:7;
5519  uint64_t ilk:1;
5520  uint64_t reserved_49_63:15;
5521 #endif
5522  } cn68xxp1;
5523 };
5524 
5525 union cvmx_ciu2_raw_ppx_ip4_rml {
5526  uint64_t u64;
5527  struct cvmx_ciu2_raw_ppx_ip4_rml_s {
5528 #ifdef __BIG_ENDIAN_BITFIELD
5529  uint64_t reserved_56_63:8;
5530  uint64_t trace:4;
5531  uint64_t reserved_49_51:3;
5532  uint64_t l2c:1;
5533  uint64_t reserved_41_47:7;
5534  uint64_t dfa:1;
5535  uint64_t reserved_37_39:3;
5536  uint64_t dpi_dma:1;
5537  uint64_t reserved_34_35:2;
5538  uint64_t dpi:1;
5539  uint64_t sli:1;
5540  uint64_t reserved_31_31:1;
5541  uint64_t key:1;
5542  uint64_t rad:1;
5543  uint64_t tim:1;
5544  uint64_t reserved_25_27:3;
5545  uint64_t zip:1;
5546  uint64_t reserved_17_23:7;
5547  uint64_t sso:1;
5548  uint64_t reserved_8_15:8;
5549  uint64_t pko:1;
5550  uint64_t pip:1;
5551  uint64_t ipd:1;
5552  uint64_t fpa:1;
5553  uint64_t reserved_1_3:3;
5554  uint64_t iob:1;
5555 #else
5556  uint64_t iob:1;
5557  uint64_t reserved_1_3:3;
5558  uint64_t fpa:1;
5559  uint64_t ipd:1;
5560  uint64_t pip:1;
5561  uint64_t pko:1;
5562  uint64_t reserved_8_15:8;
5563  uint64_t sso:1;
5564  uint64_t reserved_17_23:7;
5565  uint64_t zip:1;
5566  uint64_t reserved_25_27:3;
5567  uint64_t tim:1;
5568  uint64_t rad:1;
5569  uint64_t key:1;
5570  uint64_t reserved_31_31:1;
5571  uint64_t sli:1;
5572  uint64_t dpi:1;
5573  uint64_t reserved_34_35:2;
5574  uint64_t dpi_dma:1;
5575  uint64_t reserved_37_39:3;
5576  uint64_t dfa:1;
5577  uint64_t reserved_41_47:7;
5578  uint64_t l2c:1;
5579  uint64_t reserved_49_51:3;
5580  uint64_t trace:4;
5581  uint64_t reserved_56_63:8;
5582 #endif
5583  } s;
5584  struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx;
5585  struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
5586 #ifdef __BIG_ENDIAN_BITFIELD
5587  uint64_t reserved_56_63:8;
5588  uint64_t trace:4;
5589  uint64_t reserved_49_51:3;
5590  uint64_t l2c:1;
5591  uint64_t reserved_41_47:7;
5592  uint64_t dfa:1;
5593  uint64_t reserved_34_39:6;
5594  uint64_t dpi:1;
5595  uint64_t sli:1;
5596  uint64_t reserved_31_31:1;
5597  uint64_t key:1;
5598  uint64_t rad:1;
5599  uint64_t tim:1;
5600  uint64_t reserved_25_27:3;
5601  uint64_t zip:1;
5602  uint64_t reserved_17_23:7;
5603  uint64_t sso:1;
5604  uint64_t reserved_8_15:8;
5605  uint64_t pko:1;
5606  uint64_t pip:1;
5607  uint64_t ipd:1;
5608  uint64_t fpa:1;
5609  uint64_t reserved_1_3:3;
5610  uint64_t iob:1;
5611 #else
5612  uint64_t iob:1;
5613  uint64_t reserved_1_3:3;
5614  uint64_t fpa:1;
5615  uint64_t ipd:1;
5616  uint64_t pip:1;
5617  uint64_t pko:1;
5618  uint64_t reserved_8_15:8;
5619  uint64_t sso:1;
5620  uint64_t reserved_17_23:7;
5621  uint64_t zip:1;
5622  uint64_t reserved_25_27:3;
5623  uint64_t tim:1;
5624  uint64_t rad:1;
5625  uint64_t key:1;
5626  uint64_t reserved_31_31:1;
5627  uint64_t sli:1;
5628  uint64_t dpi:1;
5629  uint64_t reserved_34_39:6;
5630  uint64_t dfa:1;
5631  uint64_t reserved_41_47:7;
5632  uint64_t l2c:1;
5633  uint64_t reserved_49_51:3;
5634  uint64_t trace:4;
5635  uint64_t reserved_56_63:8;
5636 #endif
5637  } cn68xxp1;
5638 };
5639 
5640 union cvmx_ciu2_raw_ppx_ip4_wdog {
5641  uint64_t u64;
5642  struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
5643 #ifdef __BIG_ENDIAN_BITFIELD
5644  uint64_t reserved_32_63:32;
5645  uint64_t wdog:32;
5646 #else
5647  uint64_t wdog:32;
5648  uint64_t reserved_32_63:32;
5649 #endif
5650  } s;
5651  struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx;
5652  struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1;
5653 };
5654 
5655 union cvmx_ciu2_raw_ppx_ip4_wrkq {
5656  uint64_t u64;
5657  struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
5658 #ifdef __BIG_ENDIAN_BITFIELD
5659  uint64_t workq:64;
5660 #else
5661  uint64_t workq:64;
5662 #endif
5663  } s;
5664  struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx;
5665  struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1;
5666 };
5667 
5668 union cvmx_ciu2_src_iox_int_gpio {
5669  uint64_t u64;
5670  struct cvmx_ciu2_src_iox_int_gpio_s {
5671 #ifdef __BIG_ENDIAN_BITFIELD
5672  uint64_t reserved_16_63:48;
5673  uint64_t gpio:16;
5674 #else
5675  uint64_t gpio:16;
5676  uint64_t reserved_16_63:48;
5677 #endif
5678  } s;
5679  struct cvmx_ciu2_src_iox_int_gpio_s cn68xx;
5680  struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1;
5681 };
5682 
5683 union cvmx_ciu2_src_iox_int_io {
5684  uint64_t u64;
5685  struct cvmx_ciu2_src_iox_int_io_s {
5686 #ifdef __BIG_ENDIAN_BITFIELD
5687  uint64_t reserved_34_63:30;
5688  uint64_t pem:2;
5689  uint64_t reserved_18_31:14;
5690  uint64_t pci_inta:2;
5691  uint64_t reserved_13_15:3;
5692  uint64_t msired:1;
5693  uint64_t pci_msi:4;
5694  uint64_t reserved_4_7:4;
5695  uint64_t pci_intr:4;
5696 #else
5697  uint64_t pci_intr:4;
5698  uint64_t reserved_4_7:4;
5699  uint64_t pci_msi:4;
5700  uint64_t msired:1;
5701  uint64_t reserved_13_15:3;
5702  uint64_t pci_inta:2;
5703  uint64_t reserved_18_31:14;
5704  uint64_t pem:2;
5705  uint64_t reserved_34_63:30;
5706 #endif
5707  } s;
5708  struct cvmx_ciu2_src_iox_int_io_s cn68xx;
5709  struct cvmx_ciu2_src_iox_int_io_s cn68xxp1;
5710 };
5711 
5712 union cvmx_ciu2_src_iox_int_mbox {
5713  uint64_t u64;
5714  struct cvmx_ciu2_src_iox_int_mbox_s {
5715 #ifdef __BIG_ENDIAN_BITFIELD
5716  uint64_t reserved_4_63:60;
5717  uint64_t mbox:4;
5718 #else
5719  uint64_t mbox:4;
5720  uint64_t reserved_4_63:60;
5721 #endif
5722  } s;
5723  struct cvmx_ciu2_src_iox_int_mbox_s cn68xx;
5724  struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1;
5725 };
5726 
5727 union cvmx_ciu2_src_iox_int_mem {
5728  uint64_t u64;
5729  struct cvmx_ciu2_src_iox_int_mem_s {
5730 #ifdef __BIG_ENDIAN_BITFIELD
5731  uint64_t reserved_4_63:60;
5732  uint64_t lmc:4;
5733 #else
5734  uint64_t lmc:4;
5735  uint64_t reserved_4_63:60;
5736 #endif
5737  } s;
5738  struct cvmx_ciu2_src_iox_int_mem_s cn68xx;
5739  struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1;
5740 };
5741 
5742 union cvmx_ciu2_src_iox_int_mio {
5743  uint64_t u64;
5744  struct cvmx_ciu2_src_iox_int_mio_s {
5745 #ifdef __BIG_ENDIAN_BITFIELD
5746  uint64_t rst:1;
5747  uint64_t reserved_49_62:14;
5748  uint64_t ptp:1;
5749  uint64_t reserved_45_47:3;
5750  uint64_t usb_hci:1;
5751  uint64_t reserved_41_43:3;
5752  uint64_t usb_uctl:1;
5753  uint64_t reserved_38_39:2;
5754  uint64_t uart:2;
5755  uint64_t reserved_34_35:2;
5756  uint64_t twsi:2;
5757  uint64_t reserved_19_31:13;
5758  uint64_t bootdma:1;
5759  uint64_t mio:1;
5760  uint64_t nand:1;
5761  uint64_t reserved_12_15:4;
5762  uint64_t timer:4;
5763  uint64_t reserved_3_7:5;
5764  uint64_t ipd_drp:1;
5765  uint64_t ssoiq:1;
5766  uint64_t ipdppthr:1;
5767 #else
5768  uint64_t ipdppthr:1;
5769  uint64_t ssoiq:1;
5770  uint64_t ipd_drp:1;
5771  uint64_t reserved_3_7:5;
5772  uint64_t timer:4;
5773  uint64_t reserved_12_15:4;
5774  uint64_t nand:1;
5775  uint64_t mio:1;
5776  uint64_t bootdma:1;
5777  uint64_t reserved_19_31:13;
5778  uint64_t twsi:2;
5779  uint64_t reserved_34_35:2;
5780  uint64_t uart:2;
5781  uint64_t reserved_38_39:2;
5782  uint64_t usb_uctl:1;
5783  uint64_t reserved_41_43:3;
5784  uint64_t usb_hci:1;
5785  uint64_t reserved_45_47:3;
5786  uint64_t ptp:1;
5787  uint64_t reserved_49_62:14;
5788  uint64_t rst:1;
5789 #endif
5790  } s;
5791  struct cvmx_ciu2_src_iox_int_mio_s cn68xx;
5792  struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1;
5793 };
5794 
5795 union cvmx_ciu2_src_iox_int_pkt {
5796  uint64_t u64;
5797  struct cvmx_ciu2_src_iox_int_pkt_s {
5798 #ifdef __BIG_ENDIAN_BITFIELD
5799  uint64_t reserved_54_63:10;
5800  uint64_t ilk_drp:2;
5801  uint64_t reserved_49_51:3;
5802  uint64_t ilk:1;
5803  uint64_t reserved_41_47:7;
5804  uint64_t mii:1;
5805  uint64_t reserved_33_39:7;
5806  uint64_t agl:1;
5807  uint64_t reserved_13_31:19;
5808  uint64_t gmx_drp:5;
5809  uint64_t reserved_5_7:3;
5810  uint64_t agx:5;
5811 #else
5812  uint64_t agx:5;
5813  uint64_t reserved_5_7:3;
5814  uint64_t gmx_drp:5;
5815  uint64_t reserved_13_31:19;
5816  uint64_t agl:1;
5817  uint64_t reserved_33_39:7;
5818  uint64_t mii:1;
5819  uint64_t reserved_41_47:7;
5820  uint64_t ilk:1;
5821  uint64_t reserved_49_51:3;
5822  uint64_t ilk_drp:2;
5823  uint64_t reserved_54_63:10;
5824 #endif
5825  } s;
5826  struct cvmx_ciu2_src_iox_int_pkt_s cn68xx;
5827  struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
5828 #ifdef __BIG_ENDIAN_BITFIELD
5829  uint64_t reserved_49_63:15;
5830  uint64_t ilk:1;
5831  uint64_t reserved_41_47:7;
5832  uint64_t mii:1;
5833  uint64_t reserved_33_39:7;
5834  uint64_t agl:1;
5835  uint64_t reserved_13_31:19;
5836  uint64_t gmx_drp:5;
5837  uint64_t reserved_5_7:3;
5838  uint64_t agx:5;
5839 #else
5840  uint64_t agx:5;
5841  uint64_t reserved_5_7:3;
5842  uint64_t gmx_drp:5;
5843  uint64_t reserved_13_31:19;
5844  uint64_t agl:1;
5845  uint64_t reserved_33_39:7;
5846  uint64_t mii:1;
5847  uint64_t reserved_41_47:7;
5848  uint64_t ilk:1;
5849  uint64_t reserved_49_63:15;
5850 #endif
5851  } cn68xxp1;
5852 };
5853 
5854 union cvmx_ciu2_src_iox_int_rml {
5855  uint64_t u64;
5856  struct cvmx_ciu2_src_iox_int_rml_s {
5857 #ifdef __BIG_ENDIAN_BITFIELD
5858  uint64_t reserved_56_63:8;
5859  uint64_t trace:4;
5860  uint64_t reserved_49_51:3;
5861  uint64_t l2c:1;
5862  uint64_t reserved_41_47:7;
5863  uint64_t dfa:1;
5864  uint64_t reserved_37_39:3;
5865  uint64_t dpi_dma:1;
5866  uint64_t reserved_34_35:2;
5867  uint64_t dpi:1;
5868  uint64_t sli:1;
5869  uint64_t reserved_31_31:1;
5870  uint64_t key:1;
5871  uint64_t rad:1;
5872  uint64_t tim:1;
5873  uint64_t reserved_25_27:3;
5874  uint64_t zip:1;
5875  uint64_t reserved_17_23:7;
5876  uint64_t sso:1;
5877  uint64_t reserved_8_15:8;
5878  uint64_t pko:1;
5879  uint64_t pip:1;
5880  uint64_t ipd:1;
5881  uint64_t fpa:1;
5882  uint64_t reserved_1_3:3;
5883  uint64_t iob:1;
5884 #else
5885  uint64_t iob:1;
5886  uint64_t reserved_1_3:3;
5887  uint64_t fpa:1;
5888  uint64_t ipd:1;
5889  uint64_t pip:1;
5890  uint64_t pko:1;
5891  uint64_t reserved_8_15:8;
5892  uint64_t sso:1;
5893  uint64_t reserved_17_23:7;
5894  uint64_t zip:1;
5895  uint64_t reserved_25_27:3;
5896  uint64_t tim:1;
5897  uint64_t rad:1;
5898  uint64_t key:1;
5899  uint64_t reserved_31_31:1;
5900  uint64_t sli:1;
5901  uint64_t dpi:1;
5902  uint64_t reserved_34_35:2;
5903  uint64_t dpi_dma:1;
5904  uint64_t reserved_37_39:3;
5905  uint64_t dfa:1;
5906  uint64_t reserved_41_47:7;
5907  uint64_t l2c:1;
5908  uint64_t reserved_49_51:3;
5909  uint64_t trace:4;
5910  uint64_t reserved_56_63:8;
5911 #endif
5912  } s;
5913  struct cvmx_ciu2_src_iox_int_rml_s cn68xx;
5914  struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
5915 #ifdef __BIG_ENDIAN_BITFIELD
5916  uint64_t reserved_56_63:8;
5917  uint64_t trace:4;
5918  uint64_t reserved_49_51:3;
5919  uint64_t l2c:1;
5920  uint64_t reserved_41_47:7;
5921  uint64_t dfa:1;
5922  uint64_t reserved_34_39:6;
5923  uint64_t dpi:1;
5924  uint64_t sli:1;
5925  uint64_t reserved_31_31:1;
5926  uint64_t key:1;
5927  uint64_t rad:1;
5928  uint64_t tim:1;
5929  uint64_t reserved_25_27:3;
5930  uint64_t zip:1;
5931  uint64_t reserved_17_23:7;
5932  uint64_t sso:1;
5933  uint64_t reserved_8_15:8;
5934  uint64_t pko:1;
5935  uint64_t pip:1;
5936  uint64_t ipd:1;
5937  uint64_t fpa:1;
5938  uint64_t reserved_1_3:3;
5939  uint64_t iob:1;
5940 #else
5941  uint64_t iob:1;
5942  uint64_t reserved_1_3:3;
5943  uint64_t fpa:1;
5944  uint64_t ipd:1;
5945  uint64_t pip:1;
5946  uint64_t pko:1;
5947  uint64_t reserved_8_15:8;
5948  uint64_t sso:1;
5949  uint64_t reserved_17_23:7;
5950  uint64_t zip:1;
5951  uint64_t reserved_25_27:3;
5952  uint64_t tim:1;
5953  uint64_t rad:1;
5954  uint64_t key:1;
5955  uint64_t reserved_31_31:1;
5956  uint64_t sli:1;
5957  uint64_t dpi:1;
5958  uint64_t reserved_34_39:6;
5959  uint64_t dfa:1;
5960  uint64_t reserved_41_47:7;
5961  uint64_t l2c:1;
5962  uint64_t reserved_49_51:3;
5963  uint64_t trace:4;
5964  uint64_t reserved_56_63:8;
5965 #endif
5966  } cn68xxp1;
5967 };
5968 
5969 union cvmx_ciu2_src_iox_int_wdog {
5970  uint64_t u64;
5971  struct cvmx_ciu2_src_iox_int_wdog_s {
5972 #ifdef __BIG_ENDIAN_BITFIELD
5973  uint64_t reserved_32_63:32;
5974  uint64_t wdog:32;
5975 #else
5976  uint64_t wdog:32;
5977  uint64_t reserved_32_63:32;
5978 #endif
5979  } s;
5980  struct cvmx_ciu2_src_iox_int_wdog_s cn68xx;
5981  struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1;
5982 };
5983 
5984 union cvmx_ciu2_src_iox_int_wrkq {
5985  uint64_t u64;
5986  struct cvmx_ciu2_src_iox_int_wrkq_s {
5987 #ifdef __BIG_ENDIAN_BITFIELD
5988  uint64_t workq:64;
5989 #else
5990  uint64_t workq:64;
5991 #endif
5992  } s;
5993  struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx;
5994  struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1;
5995 };
5996 
5997 union cvmx_ciu2_src_ppx_ip2_gpio {
5998  uint64_t u64;
5999  struct cvmx_ciu2_src_ppx_ip2_gpio_s {
6000 #ifdef __BIG_ENDIAN_BITFIELD
6001  uint64_t reserved_16_63:48;
6002  uint64_t gpio:16;
6003 #else
6004  uint64_t gpio:16;
6005  uint64_t reserved_16_63:48;
6006 #endif
6007  } s;
6008  struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx;
6009  struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1;
6010 };
6011 
6012 union cvmx_ciu2_src_ppx_ip2_io {
6013  uint64_t u64;
6014  struct cvmx_ciu2_src_ppx_ip2_io_s {
6015 #ifdef __BIG_ENDIAN_BITFIELD
6016  uint64_t reserved_34_63:30;
6017  uint64_t pem:2;
6018  uint64_t reserved_18_31:14;
6019  uint64_t pci_inta:2;
6020  uint64_t reserved_13_15:3;
6021  uint64_t msired:1;
6022  uint64_t pci_msi:4;
6023  uint64_t reserved_4_7:4;
6024  uint64_t pci_intr:4;
6025 #else
6026  uint64_t pci_intr:4;
6027  uint64_t reserved_4_7:4;
6028  uint64_t pci_msi:4;
6029  uint64_t msired:1;
6030  uint64_t reserved_13_15:3;
6031  uint64_t pci_inta:2;
6032  uint64_t reserved_18_31:14;
6033  uint64_t pem:2;
6034  uint64_t reserved_34_63:30;
6035 #endif
6036  } s;
6037  struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx;
6038  struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1;
6039 };
6040 
6041 union cvmx_ciu2_src_ppx_ip2_mbox {
6042  uint64_t u64;
6043  struct cvmx_ciu2_src_ppx_ip2_mbox_s {
6044 #ifdef __BIG_ENDIAN_BITFIELD
6045  uint64_t reserved_4_63:60;
6046  uint64_t mbox:4;
6047 #else
6048  uint64_t mbox:4;
6049  uint64_t reserved_4_63:60;
6050 #endif
6051  } s;
6052  struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx;
6053  struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1;
6054 };
6055 
6056 union cvmx_ciu2_src_ppx_ip2_mem {
6057  uint64_t u64;
6058  struct cvmx_ciu2_src_ppx_ip2_mem_s {
6059 #ifdef __BIG_ENDIAN_BITFIELD
6060  uint64_t reserved_4_63:60;
6061  uint64_t lmc:4;
6062 #else
6063  uint64_t lmc:4;
6064  uint64_t reserved_4_63:60;
6065 #endif
6066  } s;
6067  struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx;
6068  struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1;
6069 };
6070 
6071 union cvmx_ciu2_src_ppx_ip2_mio {
6072  uint64_t u64;
6073  struct cvmx_ciu2_src_ppx_ip2_mio_s {
6074 #ifdef __BIG_ENDIAN_BITFIELD
6075  uint64_t rst:1;
6076  uint64_t reserved_49_62:14;
6077  uint64_t ptp:1;
6078  uint64_t reserved_45_47:3;
6079  uint64_t usb_hci:1;
6080  uint64_t reserved_41_43:3;
6081  uint64_t usb_uctl:1;
6082  uint64_t reserved_38_39:2;
6083  uint64_t uart:2;
6084  uint64_t reserved_34_35:2;
6085  uint64_t twsi:2;
6086  uint64_t reserved_19_31:13;
6087  uint64_t bootdma:1;
6088  uint64_t mio:1;
6089  uint64_t nand:1;
6090  uint64_t reserved_12_15:4;
6091  uint64_t timer:4;
6092  uint64_t reserved_3_7:5;
6093  uint64_t ipd_drp:1;
6094  uint64_t ssoiq:1;
6095  uint64_t ipdppthr:1;
6096 #else
6097  uint64_t ipdppthr:1;
6098  uint64_t ssoiq:1;
6099  uint64_t ipd_drp:1;
6100  uint64_t reserved_3_7:5;
6101  uint64_t timer:4;
6102  uint64_t reserved_12_15:4;
6103  uint64_t nand:1;
6104  uint64_t mio:1;
6105  uint64_t bootdma:1;
6106  uint64_t reserved_19_31:13;
6107  uint64_t twsi:2;
6108  uint64_t reserved_34_35:2;
6109  uint64_t uart:2;
6110  uint64_t reserved_38_39:2;
6111  uint64_t usb_uctl:1;
6112  uint64_t reserved_41_43:3;
6113  uint64_t usb_hci:1;
6114  uint64_t reserved_45_47:3;
6115  uint64_t ptp:1;
6116  uint64_t reserved_49_62:14;
6117  uint64_t rst:1;
6118 #endif
6119  } s;
6120  struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx;
6121  struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1;
6122 };
6123 
6124 union cvmx_ciu2_src_ppx_ip2_pkt {
6125  uint64_t u64;
6126  struct cvmx_ciu2_src_ppx_ip2_pkt_s {
6127 #ifdef __BIG_ENDIAN_BITFIELD
6128  uint64_t reserved_54_63:10;
6129  uint64_t ilk_drp:2;
6130  uint64_t reserved_49_51:3;
6131  uint64_t ilk:1;
6132  uint64_t reserved_41_47:7;
6133  uint64_t mii:1;
6134  uint64_t reserved_33_39:7;
6135  uint64_t agl:1;
6136  uint64_t reserved_13_31:19;
6137  uint64_t gmx_drp:5;
6138  uint64_t reserved_5_7:3;
6139  uint64_t agx:5;
6140 #else
6141  uint64_t agx:5;
6142  uint64_t reserved_5_7:3;
6143  uint64_t gmx_drp:5;
6144  uint64_t reserved_13_31:19;
6145  uint64_t agl:1;
6146  uint64_t reserved_33_39:7;
6147  uint64_t mii:1;
6148  uint64_t reserved_41_47:7;
6149  uint64_t ilk:1;
6150  uint64_t reserved_49_51:3;
6151  uint64_t ilk_drp:2;
6152  uint64_t reserved_54_63:10;
6153 #endif
6154  } s;
6155  struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx;
6156  struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
6157 #ifdef __BIG_ENDIAN_BITFIELD
6158  uint64_t reserved_49_63:15;
6159  uint64_t ilk:1;
6160  uint64_t reserved_41_47:7;
6161  uint64_t mii:1;
6162  uint64_t reserved_33_39:7;
6163  uint64_t agl:1;
6164  uint64_t reserved_13_31:19;
6165  uint64_t gmx_drp:5;
6166  uint64_t reserved_5_7:3;
6167  uint64_t agx:5;
6168 #else
6169  uint64_t agx:5;
6170  uint64_t reserved_5_7:3;
6171  uint64_t gmx_drp:5;
6172  uint64_t reserved_13_31:19;
6173  uint64_t agl:1;
6174  uint64_t reserved_33_39:7;
6175  uint64_t mii:1;
6176  uint64_t reserved_41_47:7;
6177  uint64_t ilk:1;
6178  uint64_t reserved_49_63:15;
6179 #endif
6180  } cn68xxp1;
6181 };
6182 
6183 union cvmx_ciu2_src_ppx_ip2_rml {
6184  uint64_t u64;
6185  struct cvmx_ciu2_src_ppx_ip2_rml_s {
6186 #ifdef __BIG_ENDIAN_BITFIELD
6187  uint64_t reserved_56_63:8;
6188  uint64_t trace:4;
6189  uint64_t reserved_49_51:3;
6190  uint64_t l2c:1;
6191  uint64_t reserved_41_47:7;
6192  uint64_t dfa:1;
6193  uint64_t reserved_37_39:3;
6194  uint64_t dpi_dma:1;
6195  uint64_t reserved_34_35:2;
6196  uint64_t dpi:1;
6197  uint64_t sli:1;
6198  uint64_t reserved_31_31:1;
6199  uint64_t key:1;
6200  uint64_t rad:1;
6201  uint64_t tim:1;
6202  uint64_t reserved_25_27:3;
6203  uint64_t zip:1;
6204  uint64_t reserved_17_23:7;
6205  uint64_t sso:1;
6206  uint64_t reserved_8_15:8;
6207  uint64_t pko:1;
6208  uint64_t pip:1;
6209  uint64_t ipd:1;
6210  uint64_t fpa:1;
6211  uint64_t reserved_1_3:3;
6212  uint64_t iob:1;
6213 #else
6214  uint64_t iob:1;
6215  uint64_t reserved_1_3:3;
6216  uint64_t fpa:1;
6217  uint64_t ipd:1;
6218  uint64_t pip:1;
6219  uint64_t pko:1;
6220  uint64_t reserved_8_15:8;
6221  uint64_t sso:1;
6222  uint64_t reserved_17_23:7;
6223  uint64_t zip:1;
6224  uint64_t reserved_25_27:3;
6225  uint64_t tim:1;
6226  uint64_t rad:1;
6227  uint64_t key:1;
6228  uint64_t reserved_31_31:1;
6229  uint64_t sli:1;
6230  uint64_t dpi:1;
6231  uint64_t reserved_34_35:2;
6232  uint64_t dpi_dma:1;
6233  uint64_t reserved_37_39:3;
6234  uint64_t dfa:1;
6235  uint64_t reserved_41_47:7;
6236  uint64_t l2c:1;
6237  uint64_t reserved_49_51:3;
6238  uint64_t trace:4;
6239  uint64_t reserved_56_63:8;
6240 #endif
6241  } s;
6242  struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx;
6243  struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
6244 #ifdef __BIG_ENDIAN_BITFIELD
6245  uint64_t reserved_56_63:8;
6246  uint64_t trace:4;
6247  uint64_t reserved_49_51:3;
6248  uint64_t l2c:1;
6249  uint64_t reserved_41_47:7;
6250  uint64_t dfa:1;
6251  uint64_t reserved_34_39:6;
6252  uint64_t dpi:1;
6253  uint64_t sli:1;
6254  uint64_t reserved_31_31:1;
6255  uint64_t key:1;
6256  uint64_t rad:1;
6257  uint64_t tim:1;
6258  uint64_t reserved_25_27:3;
6259  uint64_t zip:1;
6260  uint64_t reserved_17_23:7;
6261  uint64_t sso:1;
6262  uint64_t reserved_8_15:8;
6263  uint64_t pko:1;
6264  uint64_t pip:1;
6265  uint64_t ipd:1;
6266  uint64_t fpa:1;
6267  uint64_t reserved_1_3:3;
6268  uint64_t iob:1;
6269 #else
6270  uint64_t iob:1;
6271  uint64_t reserved_1_3:3;
6272  uint64_t fpa:1;
6273  uint64_t ipd:1;
6274  uint64_t pip:1;
6275  uint64_t pko:1;
6276  uint64_t reserved_8_15:8;
6277  uint64_t sso:1;
6278  uint64_t reserved_17_23:7;
6279  uint64_t zip:1;
6280  uint64_t reserved_25_27:3;
6281  uint64_t tim:1;
6282  uint64_t rad:1;
6283  uint64_t key:1;
6284  uint64_t reserved_31_31:1;
6285  uint64_t sli:1;
6286  uint64_t dpi:1;
6287  uint64_t reserved_34_39:6;
6288  uint64_t dfa:1;
6289  uint64_t reserved_41_47:7;
6290  uint64_t l2c:1;
6291  uint64_t reserved_49_51:3;
6292  uint64_t trace:4;
6293  uint64_t reserved_56_63:8;
6294 #endif
6295  } cn68xxp1;
6296 };
6297 
6298 union cvmx_ciu2_src_ppx_ip2_wdog {
6299  uint64_t u64;
6300  struct cvmx_ciu2_src_ppx_ip2_wdog_s {
6301 #ifdef __BIG_ENDIAN_BITFIELD
6302  uint64_t reserved_32_63:32;
6303  uint64_t wdog:32;
6304 #else
6305  uint64_t wdog:32;
6306  uint64_t reserved_32_63:32;
6307 #endif
6308  } s;
6309  struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx;
6310  struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1;
6311 };
6312 
6313 union cvmx_ciu2_src_ppx_ip2_wrkq {
6314  uint64_t u64;
6315  struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
6316 #ifdef __BIG_ENDIAN_BITFIELD
6317  uint64_t workq:64;
6318 #else
6319  uint64_t workq:64;
6320 #endif
6321  } s;
6322  struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx;
6323  struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1;
6324 };
6325 
6326 union cvmx_ciu2_src_ppx_ip3_gpio {
6327  uint64_t u64;
6328  struct cvmx_ciu2_src_ppx_ip3_gpio_s {
6329 #ifdef __BIG_ENDIAN_BITFIELD
6330  uint64_t reserved_16_63:48;
6331  uint64_t gpio:16;
6332 #else
6333  uint64_t gpio:16;
6334  uint64_t reserved_16_63:48;
6335 #endif
6336  } s;
6337  struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx;
6338  struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1;
6339 };
6340 
6341 union cvmx_ciu2_src_ppx_ip3_io {
6342  uint64_t u64;
6343  struct cvmx_ciu2_src_ppx_ip3_io_s {
6344 #ifdef __BIG_ENDIAN_BITFIELD
6345  uint64_t reserved_34_63:30;
6346  uint64_t pem:2;
6347  uint64_t reserved_18_31:14;
6348  uint64_t pci_inta:2;
6349  uint64_t reserved_13_15:3;
6350  uint64_t msired:1;
6351  uint64_t pci_msi:4;
6352  uint64_t reserved_4_7:4;
6353  uint64_t pci_intr:4;
6354 #else
6355  uint64_t pci_intr:4;
6356  uint64_t reserved_4_7:4;
6357  uint64_t pci_msi:4;
6358  uint64_t msired:1;
6359  uint64_t reserved_13_15:3;
6360  uint64_t pci_inta:2;
6361  uint64_t reserved_18_31:14;
6362  uint64_t pem:2;
6363  uint64_t reserved_34_63:30;
6364 #endif
6365  } s;
6366  struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx;
6367  struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1;
6368 };
6369 
6370 union cvmx_ciu2_src_ppx_ip3_mbox {
6371  uint64_t u64;
6372  struct cvmx_ciu2_src_ppx_ip3_mbox_s {
6373 #ifdef __BIG_ENDIAN_BITFIELD
6374  uint64_t reserved_4_63:60;
6375  uint64_t mbox:4;
6376 #else
6377  uint64_t mbox:4;
6378  uint64_t reserved_4_63:60;
6379 #endif
6380  } s;
6381  struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx;
6382  struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1;
6383 };
6384 
6385 union cvmx_ciu2_src_ppx_ip3_mem {
6386  uint64_t u64;
6387  struct cvmx_ciu2_src_ppx_ip3_mem_s {
6388 #ifdef __BIG_ENDIAN_BITFIELD
6389  uint64_t reserved_4_63:60;
6390  uint64_t lmc:4;
6391 #else
6392  uint64_t lmc:4;
6393  uint64_t reserved_4_63:60;
6394 #endif
6395  } s;
6396  struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx;
6397  struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1;
6398 };
6399 
6400 union cvmx_ciu2_src_ppx_ip3_mio {
6401  uint64_t u64;
6402  struct cvmx_ciu2_src_ppx_ip3_mio_s {
6403 #ifdef __BIG_ENDIAN_BITFIELD
6404  uint64_t rst:1;
6405  uint64_t reserved_49_62:14;
6406  uint64_t ptp:1;
6407  uint64_t reserved_45_47:3;
6408  uint64_t usb_hci:1;
6409  uint64_t reserved_41_43:3;
6410  uint64_t usb_uctl:1;
6411  uint64_t reserved_38_39:2;
6412  uint64_t uart:2;
6413  uint64_t reserved_34_35:2;
6414  uint64_t twsi:2;
6415  uint64_t reserved_19_31:13;
6416  uint64_t bootdma:1;
6417  uint64_t mio:1;
6418  uint64_t nand:1;
6419  uint64_t reserved_12_15:4;
6420  uint64_t timer:4;
6421  uint64_t reserved_3_7:5;
6422  uint64_t ipd_drp:1;
6423  uint64_t ssoiq:1;
6424  uint64_t ipdppthr:1;
6425 #else
6426  uint64_t ipdppthr:1;
6427  uint64_t ssoiq:1;
6428  uint64_t ipd_drp:1;
6429  uint64_t reserved_3_7:5;
6430  uint64_t timer:4;
6431  uint64_t reserved_12_15:4;
6432  uint64_t nand:1;
6433  uint64_t mio:1;
6434  uint64_t bootdma:1;
6435  uint64_t reserved_19_31:13;
6436  uint64_t twsi:2;
6437  uint64_t reserved_34_35:2;
6438  uint64_t uart:2;
6439  uint64_t reserved_38_39:2;
6440  uint64_t usb_uctl:1;
6441  uint64_t reserved_41_43:3;
6442  uint64_t usb_hci:1;
6443  uint64_t reserved_45_47:3;
6444  uint64_t ptp:1;
6445  uint64_t reserved_49_62:14;
6446  uint64_t rst:1;
6447 #endif
6448  } s;
6449  struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx;
6450  struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1;
6451 };
6452 
6453 union cvmx_ciu2_src_ppx_ip3_pkt {
6454  uint64_t u64;
6455  struct cvmx_ciu2_src_ppx_ip3_pkt_s {
6456 #ifdef __BIG_ENDIAN_BITFIELD
6457  uint64_t reserved_54_63:10;
6458  uint64_t ilk_drp:2;
6459  uint64_t reserved_49_51:3;
6460  uint64_t ilk:1;
6461  uint64_t reserved_41_47:7;
6462  uint64_t mii:1;
6463  uint64_t reserved_33_39:7;
6464  uint64_t agl:1;
6465  uint64_t reserved_13_31:19;
6466  uint64_t gmx_drp:5;
6467  uint64_t reserved_5_7:3;
6468  uint64_t agx:5;
6469 #else
6470  uint64_t agx:5;
6471  uint64_t reserved_5_7:3;
6472  uint64_t gmx_drp:5;
6473  uint64_t reserved_13_31:19;
6474  uint64_t agl:1;
6475  uint64_t reserved_33_39:7;
6476  uint64_t mii:1;
6477  uint64_t reserved_41_47:7;
6478  uint64_t ilk:1;
6479  uint64_t reserved_49_51:3;
6480  uint64_t ilk_drp:2;
6481  uint64_t reserved_54_63:10;
6482 #endif
6483  } s;
6484  struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx;
6485  struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
6486 #ifdef __BIG_ENDIAN_BITFIELD
6487  uint64_t reserved_49_63:15;
6488  uint64_t ilk:1;
6489  uint64_t reserved_41_47:7;
6490  uint64_t mii:1;
6491  uint64_t reserved_33_39:7;
6492  uint64_t agl:1;
6493  uint64_t reserved_13_31:19;
6494  uint64_t gmx_drp:5;
6495  uint64_t reserved_5_7:3;
6496  uint64_t agx:5;
6497 #else
6498  uint64_t agx:5;
6499  uint64_t reserved_5_7:3;
6500  uint64_t gmx_drp:5;
6501  uint64_t reserved_13_31:19;
6502  uint64_t agl:1;
6503  uint64_t reserved_33_39:7;
6504  uint64_t mii:1;
6505  uint64_t reserved_41_47:7;
6506  uint64_t ilk:1;
6507  uint64_t reserved_49_63:15;
6508 #endif
6509  } cn68xxp1;
6510 };
6511 
6512 union cvmx_ciu2_src_ppx_ip3_rml {
6513  uint64_t u64;
6514  struct cvmx_ciu2_src_ppx_ip3_rml_s {
6515 #ifdef __BIG_ENDIAN_BITFIELD
6516  uint64_t reserved_56_63:8;
6517  uint64_t trace:4;
6518  uint64_t reserved_49_51:3;
6519  uint64_t l2c:1;
6520  uint64_t reserved_41_47:7;
6521  uint64_t dfa:1;
6522  uint64_t reserved_37_39:3;
6523  uint64_t dpi_dma:1;
6524  uint64_t reserved_34_35:2;
6525  uint64_t dpi:1;
6526  uint64_t sli:1;
6527  uint64_t reserved_31_31:1;
6528  uint64_t key:1;
6529  uint64_t rad:1;
6530  uint64_t tim:1;
6531  uint64_t reserved_25_27:3;
6532  uint64_t zip:1;
6533  uint64_t reserved_17_23:7;
6534  uint64_t sso:1;
6535  uint64_t reserved_8_15:8;
6536  uint64_t pko:1;
6537  uint64_t pip:1;
6538  uint64_t ipd:1;
6539  uint64_t fpa:1;
6540  uint64_t reserved_1_3:3;
6541  uint64_t iob:1;
6542 #else
6543  uint64_t iob:1;
6544  uint64_t reserved_1_3:3;
6545  uint64_t fpa:1;
6546  uint64_t ipd:1;
6547  uint64_t pip:1;
6548  uint64_t pko:1;
6549  uint64_t reserved_8_15:8;
6550  uint64_t sso:1;
6551  uint64_t reserved_17_23:7;
6552  uint64_t zip:1;
6553  uint64_t reserved_25_27:3;
6554  uint64_t tim:1;
6555  uint64_t rad:1;
6556  uint64_t key:1;
6557  uint64_t reserved_31_31:1;
6558  uint64_t sli:1;
6559  uint64_t dpi:1;
6560  uint64_t reserved_34_35:2;
6561  uint64_t dpi_dma:1;
6562  uint64_t reserved_37_39:3;
6563  uint64_t dfa:1;
6564  uint64_t reserved_41_47:7;
6565  uint64_t l2c:1;
6566  uint64_t reserved_49_51:3;
6567  uint64_t trace:4;
6568  uint64_t reserved_56_63:8;
6569 #endif
6570  } s;
6571  struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx;
6572  struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
6573 #ifdef __BIG_ENDIAN_BITFIELD
6574  uint64_t reserved_56_63:8;
6575  uint64_t trace:4;
6576  uint64_t reserved_49_51:3;
6577  uint64_t l2c:1;
6578  uint64_t reserved_41_47:7;
6579  uint64_t dfa:1;
6580  uint64_t reserved_34_39:6;
6581  uint64_t dpi:1;
6582  uint64_t sli:1;
6583  uint64_t reserved_31_31:1;
6584  uint64_t key:1;
6585  uint64_t rad:1;
6586  uint64_t tim:1;
6587  uint64_t reserved_25_27:3;
6588  uint64_t zip:1;
6589  uint64_t reserved_17_23:7;
6590  uint64_t sso:1;
6591  uint64_t reserved_8_15:8;
6592  uint64_t pko:1;
6593  uint64_t pip:1;
6594  uint64_t ipd:1;
6595  uint64_t fpa:1;
6596  uint64_t reserved_1_3:3;
6597  uint64_t iob:1;
6598 #else
6599  uint64_t iob:1;
6600  uint64_t reserved_1_3:3;
6601  uint64_t fpa:1;
6602  uint64_t ipd:1;
6603  uint64_t pip:1;
6604  uint64_t pko:1;
6605  uint64_t reserved_8_15:8;
6606  uint64_t sso:1;
6607  uint64_t reserved_17_23:7;
6608  uint64_t zip:1;
6609  uint64_t reserved_25_27:3;
6610  uint64_t tim:1;
6611  uint64_t rad:1;
6612  uint64_t key:1;
6613  uint64_t reserved_31_31:1;
6614  uint64_t sli:1;
6615  uint64_t dpi:1;
6616  uint64_t reserved_34_39:6;
6617  uint64_t dfa:1;
6618  uint64_t reserved_41_47:7;
6619  uint64_t l2c:1;
6620  uint64_t reserved_49_51:3;
6621  uint64_t trace:4;
6622  uint64_t reserved_56_63:8;
6623 #endif
6624  } cn68xxp1;
6625 };
6626 
6627 union cvmx_ciu2_src_ppx_ip3_wdog {
6628  uint64_t u64;
6629  struct cvmx_ciu2_src_ppx_ip3_wdog_s {
6630 #ifdef __BIG_ENDIAN_BITFIELD
6631  uint64_t reserved_32_63:32;
6632  uint64_t wdog:32;
6633 #else
6634  uint64_t wdog:32;
6635  uint64_t reserved_32_63:32;
6636 #endif
6637  } s;
6638  struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx;
6639  struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1;
6640 };
6641 
6642 union cvmx_ciu2_src_ppx_ip3_wrkq {
6643  uint64_t u64;
6644  struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
6645 #ifdef __BIG_ENDIAN_BITFIELD
6646  uint64_t workq:64;
6647 #else
6648  uint64_t workq:64;
6649 #endif
6650  } s;
6651  struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx;
6652  struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1;
6653 };
6654 
6655 union cvmx_ciu2_src_ppx_ip4_gpio {
6656  uint64_t u64;
6657  struct cvmx_ciu2_src_ppx_ip4_gpio_s {
6658 #ifdef __BIG_ENDIAN_BITFIELD
6659  uint64_t reserved_16_63:48;
6660  uint64_t gpio:16;
6661 #else
6662  uint64_t gpio:16;
6663  uint64_t reserved_16_63:48;
6664 #endif
6665  } s;
6666  struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx;
6667  struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1;
6668 };
6669 
6670 union cvmx_ciu2_src_ppx_ip4_io {
6671  uint64_t u64;
6672  struct cvmx_ciu2_src_ppx_ip4_io_s {
6673 #ifdef __BIG_ENDIAN_BITFIELD
6674  uint64_t reserved_34_63:30;
6675  uint64_t pem:2;
6676  uint64_t reserved_18_31:14;
6677  uint64_t pci_inta:2;
6678  uint64_t reserved_13_15:3;
6679  uint64_t msired:1;
6680  uint64_t pci_msi:4;
6681  uint64_t reserved_4_7:4;
6682  uint64_t pci_intr:4;
6683 #else
6684  uint64_t pci_intr:4;
6685  uint64_t reserved_4_7:4;
6686  uint64_t pci_msi:4;
6687  uint64_t msired:1;
6688  uint64_t reserved_13_15:3;
6689  uint64_t pci_inta:2;
6690  uint64_t reserved_18_31:14;
6691  uint64_t pem:2;
6692  uint64_t reserved_34_63:30;
6693 #endif
6694  } s;
6695  struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx;
6696  struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1;
6697 };
6698 
6699 union cvmx_ciu2_src_ppx_ip4_mbox {
6700  uint64_t u64;
6701  struct cvmx_ciu2_src_ppx_ip4_mbox_s {
6702 #ifdef __BIG_ENDIAN_BITFIELD
6703  uint64_t reserved_4_63:60;
6704  uint64_t mbox:4;
6705 #else
6706  uint64_t mbox:4;
6707  uint64_t reserved_4_63:60;
6708 #endif
6709  } s;
6710  struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx;
6711  struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1;
6712 };
6713 
6714 union cvmx_ciu2_src_ppx_ip4_mem {
6715  uint64_t u64;
6716  struct cvmx_ciu2_src_ppx_ip4_mem_s {
6717 #ifdef __BIG_ENDIAN_BITFIELD
6718  uint64_t reserved_4_63:60;
6719  uint64_t lmc:4;
6720 #else
6721  uint64_t lmc:4;
6722  uint64_t reserved_4_63:60;
6723 #endif
6724  } s;
6725  struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx;
6726  struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1;
6727 };
6728 
6729 union cvmx_ciu2_src_ppx_ip4_mio {
6730  uint64_t u64;
6731  struct cvmx_ciu2_src_ppx_ip4_mio_s {
6732 #ifdef __BIG_ENDIAN_BITFIELD
6733  uint64_t rst:1;
6734  uint64_t reserved_49_62:14;
6735  uint64_t ptp:1;
6736  uint64_t reserved_45_47:3;
6737  uint64_t usb_hci:1;
6738  uint64_t reserved_41_43:3;
6739  uint64_t usb_uctl:1;
6740  uint64_t reserved_38_39:2;
6741  uint64_t uart:2;
6742  uint64_t reserved_34_35:2;
6743  uint64_t twsi:2;
6744  uint64_t reserved_19_31:13;
6745  uint64_t bootdma:1;
6746  uint64_t mio:1;
6747  uint64_t nand:1;
6748  uint64_t reserved_12_15:4;
6749  uint64_t timer:4;
6750  uint64_t reserved_3_7:5;
6751  uint64_t ipd_drp:1;
6752  uint64_t ssoiq:1;
6753  uint64_t ipdppthr:1;
6754 #else
6755  uint64_t ipdppthr:1;
6756  uint64_t ssoiq:1;
6757  uint64_t ipd_drp:1;
6758  uint64_t reserved_3_7:5;
6759  uint64_t timer:4;
6760  uint64_t reserved_12_15:4;
6761  uint64_t nand:1;
6762  uint64_t mio:1;
6763  uint64_t bootdma:1;
6764  uint64_t reserved_19_31:13;
6765  uint64_t twsi:2;
6766  uint64_t reserved_34_35:2;
6767  uint64_t uart:2;
6768  uint64_t reserved_38_39:2;
6769  uint64_t usb_uctl:1;
6770  uint64_t reserved_41_43:3;
6771  uint64_t usb_hci:1;
6772  uint64_t reserved_45_47:3;
6773  uint64_t ptp:1;
6774  uint64_t reserved_49_62:14;
6775  uint64_t rst:1;
6776 #endif
6777  } s;
6778  struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx;
6779  struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1;
6780 };
6781 
6782 union cvmx_ciu2_src_ppx_ip4_pkt {
6783  uint64_t u64;
6784  struct cvmx_ciu2_src_ppx_ip4_pkt_s {
6785 #ifdef __BIG_ENDIAN_BITFIELD
6786  uint64_t reserved_54_63:10;
6787  uint64_t ilk_drp:2;
6788  uint64_t reserved_49_51:3;
6789  uint64_t ilk:1;
6790  uint64_t reserved_41_47:7;
6791  uint64_t mii:1;
6792  uint64_t reserved_33_39:7;
6793  uint64_t agl:1;
6794  uint64_t reserved_13_31:19;
6795  uint64_t gmx_drp:5;
6796  uint64_t reserved_5_7:3;
6797  uint64_t agx:5;
6798 #else
6799  uint64_t agx:5;
6800  uint64_t reserved_5_7:3;
6801  uint64_t gmx_drp:5;
6802  uint64_t reserved_13_31:19;
6803  uint64_t agl:1;
6804  uint64_t reserved_33_39:7;
6805  uint64_t mii:1;
6806  uint64_t reserved_41_47:7;
6807  uint64_t ilk:1;
6808  uint64_t reserved_49_51:3;
6809  uint64_t ilk_drp:2;
6810  uint64_t reserved_54_63:10;
6811 #endif
6812  } s;
6813  struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx;
6814  struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
6815 #ifdef __BIG_ENDIAN_BITFIELD
6816  uint64_t reserved_49_63:15;
6817  uint64_t ilk:1;
6818  uint64_t reserved_41_47:7;
6819  uint64_t mii:1;
6820  uint64_t reserved_33_39:7;
6821  uint64_t agl:1;
6822  uint64_t reserved_13_31:19;
6823  uint64_t gmx_drp:5;
6824  uint64_t reserved_5_7:3;
6825  uint64_t agx:5;
6826 #else
6827  uint64_t agx:5;
6828  uint64_t reserved_5_7:3;
6829  uint64_t gmx_drp:5;
6830  uint64_t reserved_13_31:19;
6831  uint64_t agl:1;
6832  uint64_t reserved_33_39:7;
6833  uint64_t mii:1;
6834  uint64_t reserved_41_47:7;
6835  uint64_t ilk:1;
6836  uint64_t reserved_49_63:15;
6837 #endif
6838  } cn68xxp1;
6839 };
6840 
6841 union cvmx_ciu2_src_ppx_ip4_rml {
6842  uint64_t u64;
6843  struct cvmx_ciu2_src_ppx_ip4_rml_s {
6844 #ifdef __BIG_ENDIAN_BITFIELD
6845  uint64_t reserved_56_63:8;
6846  uint64_t trace:4;
6847  uint64_t reserved_49_51:3;
6848  uint64_t l2c:1;
6849  uint64_t reserved_41_47:7;
6850  uint64_t dfa:1;
6851  uint64_t reserved_37_39:3;
6852  uint64_t dpi_dma:1;
6853  uint64_t reserved_34_35:2;
6854  uint64_t dpi:1;
6855  uint64_t sli:1;
6856  uint64_t reserved_31_31:1;
6857  uint64_t key:1;
6858  uint64_t rad:1;
6859  uint64_t tim:1;
6860  uint64_t reserved_25_27:3;
6861  uint64_t zip:1;
6862  uint64_t reserved_17_23:7;
6863  uint64_t sso:1;
6864  uint64_t reserved_8_15:8;
6865  uint64_t pko:1;
6866  uint64_t pip:1;
6867  uint64_t ipd:1;
6868  uint64_t fpa:1;
6869  uint64_t reserved_1_3:3;
6870  uint64_t iob:1;
6871 #else
6872  uint64_t iob:1;
6873  uint64_t reserved_1_3:3;
6874  uint64_t fpa:1;
6875  uint64_t ipd:1;
6876  uint64_t pip:1;
6877  uint64_t pko:1;
6878  uint64_t reserved_8_15:8;
6879  uint64_t sso:1;
6880  uint64_t reserved_17_23:7;
6881  uint64_t zip:1;
6882  uint64_t reserved_25_27:3;
6883  uint64_t tim:1;
6884  uint64_t rad:1;
6885  uint64_t key:1;
6886  uint64_t reserved_31_31:1;
6887  uint64_t sli:1;
6888  uint64_t dpi:1;
6889  uint64_t reserved_34_35:2;
6890  uint64_t dpi_dma:1;
6891  uint64_t reserved_37_39:3;
6892  uint64_t dfa:1;
6893  uint64_t reserved_41_47:7;
6894  uint64_t l2c:1;
6895  uint64_t reserved_49_51:3;
6896  uint64_t trace:4;
6897  uint64_t reserved_56_63:8;
6898 #endif
6899  } s;
6900  struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx;
6901  struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
6902 #ifdef __BIG_ENDIAN_BITFIELD
6903  uint64_t reserved_56_63:8;
6904  uint64_t trace:4;
6905  uint64_t reserved_49_51:3;
6906  uint64_t l2c:1;
6907  uint64_t reserved_41_47:7;
6908  uint64_t dfa:1;
6909  uint64_t reserved_34_39:6;
6910  uint64_t dpi:1;
6911  uint64_t sli:1;
6912  uint64_t reserved_31_31:1;
6913  uint64_t key:1;
6914  uint64_t rad:1;
6915  uint64_t tim:1;
6916  uint64_t reserved_25_27:3;
6917  uint64_t zip:1;
6918  uint64_t reserved_17_23:7;
6919  uint64_t sso:1;
6920  uint64_t reserved_8_15:8;
6921  uint64_t pko:1;
6922  uint64_t pip:1;
6923  uint64_t ipd:1;
6924  uint64_t fpa:1;
6925  uint64_t reserved_1_3:3;
6926  uint64_t iob:1;
6927 #else
6928  uint64_t iob:1;
6929  uint64_t reserved_1_3:3;
6930  uint64_t fpa:1;
6931  uint64_t ipd:1;
6932  uint64_t pip:1;
6933  uint64_t pko:1;
6934  uint64_t reserved_8_15:8;
6935  uint64_t sso:1;
6936  uint64_t reserved_17_23:7;
6937  uint64_t zip:1;
6938  uint64_t reserved_25_27:3;
6939  uint64_t tim:1;
6940  uint64_t rad:1;
6941  uint64_t key:1;
6942  uint64_t reserved_31_31:1;
6943  uint64_t sli:1;
6944  uint64_t dpi:1;
6945  uint64_t reserved_34_39:6;
6946  uint64_t dfa:1;
6947  uint64_t reserved_41_47:7;
6948  uint64_t l2c:1;
6949  uint64_t reserved_49_51:3;
6950  uint64_t trace:4;
6951  uint64_t reserved_56_63:8;
6952 #endif
6953  } cn68xxp1;
6954 };
6955 
6956 union cvmx_ciu2_src_ppx_ip4_wdog {
6957  uint64_t u64;
6958  struct cvmx_ciu2_src_ppx_ip4_wdog_s {
6959 #ifdef __BIG_ENDIAN_BITFIELD
6960  uint64_t reserved_32_63:32;
6961  uint64_t wdog:32;
6962 #else
6963  uint64_t wdog:32;
6964  uint64_t reserved_32_63:32;
6965 #endif
6966  } s;
6967  struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx;
6968  struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1;
6969 };
6970 
6971 union cvmx_ciu2_src_ppx_ip4_wrkq {
6972  uint64_t u64;
6973  struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
6974 #ifdef __BIG_ENDIAN_BITFIELD
6975  uint64_t workq:64;
6976 #else
6977  uint64_t workq:64;
6978 #endif
6979  } s;
6980  struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx;
6981  struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1;
6982 };
6983 
6984 union cvmx_ciu2_sum_iox_int {
6985  uint64_t u64;
6986  struct cvmx_ciu2_sum_iox_int_s {
6987 #ifdef __BIG_ENDIAN_BITFIELD
6988  uint64_t mbox:4;
6989  uint64_t reserved_8_59:52;
6990  uint64_t gpio:1;
6991  uint64_t pkt:1;
6992  uint64_t mem:1;
6993  uint64_t io:1;
6994  uint64_t mio:1;
6995  uint64_t rml:1;
6996  uint64_t wdog:1;
6997  uint64_t workq:1;
6998 #else
6999  uint64_t workq:1;
7000  uint64_t wdog:1;
7001  uint64_t rml:1;
7002  uint64_t mio:1;
7003  uint64_t io:1;
7004  uint64_t mem:1;
7005  uint64_t pkt:1;
7006  uint64_t gpio:1;
7007  uint64_t reserved_8_59:52;
7008  uint64_t mbox:4;
7009 #endif
7010  } s;
7011  struct cvmx_ciu2_sum_iox_int_s cn68xx;
7012  struct cvmx_ciu2_sum_iox_int_s cn68xxp1;
7013 };
7014 
7015 union cvmx_ciu2_sum_ppx_ip2 {
7016  uint64_t u64;
7017  struct cvmx_ciu2_sum_ppx_ip2_s {
7018 #ifdef __BIG_ENDIAN_BITFIELD
7019  uint64_t mbox:4;
7020  uint64_t reserved_8_59:52;
7021  uint64_t gpio:1;
7022  uint64_t pkt:1;
7023  uint64_t mem:1;
7024  uint64_t io:1;
7025  uint64_t mio:1;
7026  uint64_t rml:1;
7027  uint64_t wdog:1;
7028  uint64_t workq:1;
7029 #else
7030  uint64_t workq:1;
7031  uint64_t wdog:1;
7032  uint64_t rml:1;
7033  uint64_t mio:1;
7034  uint64_t io:1;
7035  uint64_t mem:1;
7036  uint64_t pkt:1;
7037  uint64_t gpio:1;
7038  uint64_t reserved_8_59:52;
7039  uint64_t mbox:4;
7040 #endif
7041  } s;
7042  struct cvmx_ciu2_sum_ppx_ip2_s cn68xx;
7043  struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1;
7044 };
7045 
7046 union cvmx_ciu2_sum_ppx_ip3 {
7047  uint64_t u64;
7048  struct cvmx_ciu2_sum_ppx_ip3_s {
7049 #ifdef __BIG_ENDIAN_BITFIELD
7050  uint64_t mbox:4;
7051  uint64_t reserved_8_59:52;
7052  uint64_t gpio:1;
7053  uint64_t pkt:1;
7054  uint64_t mem:1;
7055  uint64_t io:1;
7056  uint64_t mio:1;
7057  uint64_t rml:1;
7058  uint64_t wdog:1;
7059  uint64_t workq:1;
7060 #else
7061  uint64_t workq:1;
7062  uint64_t wdog:1;
7063  uint64_t rml:1;
7064  uint64_t mio:1;
7065  uint64_t io:1;
7066  uint64_t mem:1;
7067  uint64_t pkt:1;
7068  uint64_t gpio:1;
7069  uint64_t reserved_8_59:52;
7070  uint64_t mbox:4;
7071 #endif
7072  } s;
7073  struct cvmx_ciu2_sum_ppx_ip3_s cn68xx;
7074  struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1;
7075 };
7076 
7077 union cvmx_ciu2_sum_ppx_ip4 {
7078  uint64_t u64;
7079  struct cvmx_ciu2_sum_ppx_ip4_s {
7080 #ifdef __BIG_ENDIAN_BITFIELD
7081  uint64_t mbox:4;
7082  uint64_t reserved_8_59:52;
7083  uint64_t gpio:1;
7084  uint64_t pkt:1;
7085  uint64_t mem:1;
7086  uint64_t io:1;
7087  uint64_t mio:1;
7088  uint64_t rml:1;
7089  uint64_t wdog:1;
7090  uint64_t workq:1;
7091 #else
7092  uint64_t workq:1;
7093  uint64_t wdog:1;
7094  uint64_t rml:1;
7095  uint64_t mio:1;
7096  uint64_t io:1;
7097  uint64_t mem:1;
7098  uint64_t pkt:1;
7099  uint64_t gpio:1;
7100  uint64_t reserved_8_59:52;
7101  uint64_t mbox:4;
7102 #endif
7103  } s;
7104  struct cvmx_ciu2_sum_ppx_ip4_s cn68xx;
7105  struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1;
7106 };
7107 
7108 #endif
Generated on Thu Jan 10 2013 13:10:05 for Linux Kernel by   doxygen 1.8.2