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Data Structures | Macros
cvmx-ciu2-defs.h File Reference

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Data Structures

union  cvmx_ciu2_ack_iox_int
 
struct  cvmx_ciu2_ack_iox_int::cvmx_ciu2_ack_iox_int_s
 
union  cvmx_ciu2_ack_ppx_ip2
 
struct  cvmx_ciu2_ack_ppx_ip2::cvmx_ciu2_ack_ppx_ip2_s
 
union  cvmx_ciu2_ack_ppx_ip3
 
struct  cvmx_ciu2_ack_ppx_ip3::cvmx_ciu2_ack_ppx_ip3_s
 
union  cvmx_ciu2_ack_ppx_ip4
 
struct  cvmx_ciu2_ack_ppx_ip4::cvmx_ciu2_ack_ppx_ip4_s
 
union  cvmx_ciu2_en_iox_int_gpio
 
struct  cvmx_ciu2_en_iox_int_gpio::cvmx_ciu2_en_iox_int_gpio_s
 
union  cvmx_ciu2_en_iox_int_gpio_w1c
 
struct  cvmx_ciu2_en_iox_int_gpio_w1c::cvmx_ciu2_en_iox_int_gpio_w1c_s
 
union  cvmx_ciu2_en_iox_int_gpio_w1s
 
struct  cvmx_ciu2_en_iox_int_gpio_w1s::cvmx_ciu2_en_iox_int_gpio_w1s_s
 
union  cvmx_ciu2_en_iox_int_io
 
struct  cvmx_ciu2_en_iox_int_io::cvmx_ciu2_en_iox_int_io_s
 
union  cvmx_ciu2_en_iox_int_io_w1c
 
struct  cvmx_ciu2_en_iox_int_io_w1c::cvmx_ciu2_en_iox_int_io_w1c_s
 
union  cvmx_ciu2_en_iox_int_io_w1s
 
struct  cvmx_ciu2_en_iox_int_io_w1s::cvmx_ciu2_en_iox_int_io_w1s_s
 
union  cvmx_ciu2_en_iox_int_mbox
 
struct  cvmx_ciu2_en_iox_int_mbox::cvmx_ciu2_en_iox_int_mbox_s
 
union  cvmx_ciu2_en_iox_int_mbox_w1c
 
struct  cvmx_ciu2_en_iox_int_mbox_w1c::cvmx_ciu2_en_iox_int_mbox_w1c_s
 
union  cvmx_ciu2_en_iox_int_mbox_w1s
 
struct  cvmx_ciu2_en_iox_int_mbox_w1s::cvmx_ciu2_en_iox_int_mbox_w1s_s
 
union  cvmx_ciu2_en_iox_int_mem
 
struct  cvmx_ciu2_en_iox_int_mem::cvmx_ciu2_en_iox_int_mem_s
 
union  cvmx_ciu2_en_iox_int_mem_w1c
 
struct  cvmx_ciu2_en_iox_int_mem_w1c::cvmx_ciu2_en_iox_int_mem_w1c_s
 
union  cvmx_ciu2_en_iox_int_mem_w1s
 
struct  cvmx_ciu2_en_iox_int_mem_w1s::cvmx_ciu2_en_iox_int_mem_w1s_s
 
union  cvmx_ciu2_en_iox_int_mio
 
struct  cvmx_ciu2_en_iox_int_mio::cvmx_ciu2_en_iox_int_mio_s
 
union  cvmx_ciu2_en_iox_int_mio_w1c
 
struct  cvmx_ciu2_en_iox_int_mio_w1c::cvmx_ciu2_en_iox_int_mio_w1c_s
 
union  cvmx_ciu2_en_iox_int_mio_w1s
 
struct  cvmx_ciu2_en_iox_int_mio_w1s::cvmx_ciu2_en_iox_int_mio_w1s_s
 
union  cvmx_ciu2_en_iox_int_pkt
 
struct  cvmx_ciu2_en_iox_int_pkt::cvmx_ciu2_en_iox_int_pkt_s
 
struct  cvmx_ciu2_en_iox_int_pkt::cvmx_ciu2_en_iox_int_pkt_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_pkt_w1c
 
struct  cvmx_ciu2_en_iox_int_pkt_w1c::cvmx_ciu2_en_iox_int_pkt_w1c_s
 
struct  cvmx_ciu2_en_iox_int_pkt_w1c::cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_pkt_w1s
 
struct  cvmx_ciu2_en_iox_int_pkt_w1s::cvmx_ciu2_en_iox_int_pkt_w1s_s
 
struct  cvmx_ciu2_en_iox_int_pkt_w1s::cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_rml
 
struct  cvmx_ciu2_en_iox_int_rml::cvmx_ciu2_en_iox_int_rml_s
 
struct  cvmx_ciu2_en_iox_int_rml::cvmx_ciu2_en_iox_int_rml_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_rml_w1c
 
struct  cvmx_ciu2_en_iox_int_rml_w1c::cvmx_ciu2_en_iox_int_rml_w1c_s
 
struct  cvmx_ciu2_en_iox_int_rml_w1c::cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_rml_w1s
 
struct  cvmx_ciu2_en_iox_int_rml_w1s::cvmx_ciu2_en_iox_int_rml_w1s_s
 
struct  cvmx_ciu2_en_iox_int_rml_w1s::cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1
 
union  cvmx_ciu2_en_iox_int_wdog
 
struct  cvmx_ciu2_en_iox_int_wdog::cvmx_ciu2_en_iox_int_wdog_s
 
union  cvmx_ciu2_en_iox_int_wdog_w1c
 
struct  cvmx_ciu2_en_iox_int_wdog_w1c::cvmx_ciu2_en_iox_int_wdog_w1c_s
 
union  cvmx_ciu2_en_iox_int_wdog_w1s
 
struct  cvmx_ciu2_en_iox_int_wdog_w1s::cvmx_ciu2_en_iox_int_wdog_w1s_s
 
union  cvmx_ciu2_en_iox_int_wrkq
 
struct  cvmx_ciu2_en_iox_int_wrkq::cvmx_ciu2_en_iox_int_wrkq_s
 
union  cvmx_ciu2_en_iox_int_wrkq_w1c
 
struct  cvmx_ciu2_en_iox_int_wrkq_w1c::cvmx_ciu2_en_iox_int_wrkq_w1c_s
 
union  cvmx_ciu2_en_iox_int_wrkq_w1s
 
struct  cvmx_ciu2_en_iox_int_wrkq_w1s::cvmx_ciu2_en_iox_int_wrkq_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_gpio
 
struct  cvmx_ciu2_en_ppx_ip2_gpio::cvmx_ciu2_en_ppx_ip2_gpio_s
 
union  cvmx_ciu2_en_ppx_ip2_gpio_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_gpio_w1c::cvmx_ciu2_en_ppx_ip2_gpio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_gpio_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_gpio_w1s::cvmx_ciu2_en_ppx_ip2_gpio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_io
 
struct  cvmx_ciu2_en_ppx_ip2_io::cvmx_ciu2_en_ppx_ip2_io_s
 
union  cvmx_ciu2_en_ppx_ip2_io_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_io_w1c::cvmx_ciu2_en_ppx_ip2_io_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_io_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_io_w1s::cvmx_ciu2_en_ppx_ip2_io_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_mbox
 
struct  cvmx_ciu2_en_ppx_ip2_mbox::cvmx_ciu2_en_ppx_ip2_mbox_s
 
union  cvmx_ciu2_en_ppx_ip2_mbox_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_mbox_w1c::cvmx_ciu2_en_ppx_ip2_mbox_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_mbox_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_mbox_w1s::cvmx_ciu2_en_ppx_ip2_mbox_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_mem
 
struct  cvmx_ciu2_en_ppx_ip2_mem::cvmx_ciu2_en_ppx_ip2_mem_s
 
union  cvmx_ciu2_en_ppx_ip2_mem_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_mem_w1c::cvmx_ciu2_en_ppx_ip2_mem_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_mem_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_mem_w1s::cvmx_ciu2_en_ppx_ip2_mem_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_mio
 
struct  cvmx_ciu2_en_ppx_ip2_mio::cvmx_ciu2_en_ppx_ip2_mio_s
 
union  cvmx_ciu2_en_ppx_ip2_mio_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_mio_w1c::cvmx_ciu2_en_ppx_ip2_mio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_mio_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_mio_w1s::cvmx_ciu2_en_ppx_ip2_mio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_pkt
 
struct  cvmx_ciu2_en_ppx_ip2_pkt::cvmx_ciu2_en_ppx_ip2_pkt_s
 
struct  cvmx_ciu2_en_ppx_ip2_pkt::cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_pkt_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_pkt_w1c::cvmx_ciu2_en_ppx_ip2_pkt_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip2_pkt_w1c::cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_pkt_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_pkt_w1s::cvmx_ciu2_en_ppx_ip2_pkt_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip2_pkt_w1s::cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_rml
 
struct  cvmx_ciu2_en_ppx_ip2_rml::cvmx_ciu2_en_ppx_ip2_rml_s
 
struct  cvmx_ciu2_en_ppx_ip2_rml::cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_rml_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_rml_w1c::cvmx_ciu2_en_ppx_ip2_rml_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip2_rml_w1c::cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_rml_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_rml_w1s::cvmx_ciu2_en_ppx_ip2_rml_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip2_rml_w1s::cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip2_wdog
 
struct  cvmx_ciu2_en_ppx_ip2_wdog::cvmx_ciu2_en_ppx_ip2_wdog_s
 
union  cvmx_ciu2_en_ppx_ip2_wdog_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_wdog_w1c::cvmx_ciu2_en_ppx_ip2_wdog_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_wdog_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_wdog_w1s::cvmx_ciu2_en_ppx_ip2_wdog_w1s_s
 
union  cvmx_ciu2_en_ppx_ip2_wrkq
 
struct  cvmx_ciu2_en_ppx_ip2_wrkq::cvmx_ciu2_en_ppx_ip2_wrkq_s
 
union  cvmx_ciu2_en_ppx_ip2_wrkq_w1c
 
struct  cvmx_ciu2_en_ppx_ip2_wrkq_w1c::cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s
 
union  cvmx_ciu2_en_ppx_ip2_wrkq_w1s
 
struct  cvmx_ciu2_en_ppx_ip2_wrkq_w1s::cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_gpio
 
struct  cvmx_ciu2_en_ppx_ip3_gpio::cvmx_ciu2_en_ppx_ip3_gpio_s
 
union  cvmx_ciu2_en_ppx_ip3_gpio_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_gpio_w1c::cvmx_ciu2_en_ppx_ip3_gpio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_gpio_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_gpio_w1s::cvmx_ciu2_en_ppx_ip3_gpio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_io
 
struct  cvmx_ciu2_en_ppx_ip3_io::cvmx_ciu2_en_ppx_ip3_io_s
 
union  cvmx_ciu2_en_ppx_ip3_io_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_io_w1c::cvmx_ciu2_en_ppx_ip3_io_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_io_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_io_w1s::cvmx_ciu2_en_ppx_ip3_io_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_mbox
 
struct  cvmx_ciu2_en_ppx_ip3_mbox::cvmx_ciu2_en_ppx_ip3_mbox_s
 
union  cvmx_ciu2_en_ppx_ip3_mbox_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_mbox_w1c::cvmx_ciu2_en_ppx_ip3_mbox_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_mbox_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_mbox_w1s::cvmx_ciu2_en_ppx_ip3_mbox_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_mem
 
struct  cvmx_ciu2_en_ppx_ip3_mem::cvmx_ciu2_en_ppx_ip3_mem_s
 
union  cvmx_ciu2_en_ppx_ip3_mem_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_mem_w1c::cvmx_ciu2_en_ppx_ip3_mem_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_mem_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_mem_w1s::cvmx_ciu2_en_ppx_ip3_mem_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_mio
 
struct  cvmx_ciu2_en_ppx_ip3_mio::cvmx_ciu2_en_ppx_ip3_mio_s
 
union  cvmx_ciu2_en_ppx_ip3_mio_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_mio_w1c::cvmx_ciu2_en_ppx_ip3_mio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_mio_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_mio_w1s::cvmx_ciu2_en_ppx_ip3_mio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_pkt
 
struct  cvmx_ciu2_en_ppx_ip3_pkt::cvmx_ciu2_en_ppx_ip3_pkt_s
 
struct  cvmx_ciu2_en_ppx_ip3_pkt::cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_pkt_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_pkt_w1c::cvmx_ciu2_en_ppx_ip3_pkt_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip3_pkt_w1c::cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_pkt_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_pkt_w1s::cvmx_ciu2_en_ppx_ip3_pkt_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip3_pkt_w1s::cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_rml
 
struct  cvmx_ciu2_en_ppx_ip3_rml::cvmx_ciu2_en_ppx_ip3_rml_s
 
struct  cvmx_ciu2_en_ppx_ip3_rml::cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_rml_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_rml_w1c::cvmx_ciu2_en_ppx_ip3_rml_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip3_rml_w1c::cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_rml_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_rml_w1s::cvmx_ciu2_en_ppx_ip3_rml_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip3_rml_w1s::cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip3_wdog
 
struct  cvmx_ciu2_en_ppx_ip3_wdog::cvmx_ciu2_en_ppx_ip3_wdog_s
 
union  cvmx_ciu2_en_ppx_ip3_wdog_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_wdog_w1c::cvmx_ciu2_en_ppx_ip3_wdog_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_wdog_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_wdog_w1s::cvmx_ciu2_en_ppx_ip3_wdog_w1s_s
 
union  cvmx_ciu2_en_ppx_ip3_wrkq
 
struct  cvmx_ciu2_en_ppx_ip3_wrkq::cvmx_ciu2_en_ppx_ip3_wrkq_s
 
union  cvmx_ciu2_en_ppx_ip3_wrkq_w1c
 
struct  cvmx_ciu2_en_ppx_ip3_wrkq_w1c::cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s
 
union  cvmx_ciu2_en_ppx_ip3_wrkq_w1s
 
struct  cvmx_ciu2_en_ppx_ip3_wrkq_w1s::cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_gpio
 
struct  cvmx_ciu2_en_ppx_ip4_gpio::cvmx_ciu2_en_ppx_ip4_gpio_s
 
union  cvmx_ciu2_en_ppx_ip4_gpio_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_gpio_w1c::cvmx_ciu2_en_ppx_ip4_gpio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_gpio_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_gpio_w1s::cvmx_ciu2_en_ppx_ip4_gpio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_io
 
struct  cvmx_ciu2_en_ppx_ip4_io::cvmx_ciu2_en_ppx_ip4_io_s
 
union  cvmx_ciu2_en_ppx_ip4_io_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_io_w1c::cvmx_ciu2_en_ppx_ip4_io_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_io_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_io_w1s::cvmx_ciu2_en_ppx_ip4_io_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_mbox
 
struct  cvmx_ciu2_en_ppx_ip4_mbox::cvmx_ciu2_en_ppx_ip4_mbox_s
 
union  cvmx_ciu2_en_ppx_ip4_mbox_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_mbox_w1c::cvmx_ciu2_en_ppx_ip4_mbox_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_mbox_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_mbox_w1s::cvmx_ciu2_en_ppx_ip4_mbox_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_mem
 
struct  cvmx_ciu2_en_ppx_ip4_mem::cvmx_ciu2_en_ppx_ip4_mem_s
 
union  cvmx_ciu2_en_ppx_ip4_mem_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_mem_w1c::cvmx_ciu2_en_ppx_ip4_mem_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_mem_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_mem_w1s::cvmx_ciu2_en_ppx_ip4_mem_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_mio
 
struct  cvmx_ciu2_en_ppx_ip4_mio::cvmx_ciu2_en_ppx_ip4_mio_s
 
union  cvmx_ciu2_en_ppx_ip4_mio_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_mio_w1c::cvmx_ciu2_en_ppx_ip4_mio_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_mio_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_mio_w1s::cvmx_ciu2_en_ppx_ip4_mio_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_pkt
 
struct  cvmx_ciu2_en_ppx_ip4_pkt::cvmx_ciu2_en_ppx_ip4_pkt_s
 
struct  cvmx_ciu2_en_ppx_ip4_pkt::cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_pkt_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_pkt_w1c::cvmx_ciu2_en_ppx_ip4_pkt_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip4_pkt_w1c::cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_pkt_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_pkt_w1s::cvmx_ciu2_en_ppx_ip4_pkt_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip4_pkt_w1s::cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_rml
 
struct  cvmx_ciu2_en_ppx_ip4_rml::cvmx_ciu2_en_ppx_ip4_rml_s
 
struct  cvmx_ciu2_en_ppx_ip4_rml::cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_rml_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_rml_w1c::cvmx_ciu2_en_ppx_ip4_rml_w1c_s
 
struct  cvmx_ciu2_en_ppx_ip4_rml_w1c::cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_rml_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_rml_w1s::cvmx_ciu2_en_ppx_ip4_rml_w1s_s
 
struct  cvmx_ciu2_en_ppx_ip4_rml_w1s::cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1
 
union  cvmx_ciu2_en_ppx_ip4_wdog
 
struct  cvmx_ciu2_en_ppx_ip4_wdog::cvmx_ciu2_en_ppx_ip4_wdog_s
 
union  cvmx_ciu2_en_ppx_ip4_wdog_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_wdog_w1c::cvmx_ciu2_en_ppx_ip4_wdog_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_wdog_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_wdog_w1s::cvmx_ciu2_en_ppx_ip4_wdog_w1s_s
 
union  cvmx_ciu2_en_ppx_ip4_wrkq
 
struct  cvmx_ciu2_en_ppx_ip4_wrkq::cvmx_ciu2_en_ppx_ip4_wrkq_s
 
union  cvmx_ciu2_en_ppx_ip4_wrkq_w1c
 
struct  cvmx_ciu2_en_ppx_ip4_wrkq_w1c::cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s
 
union  cvmx_ciu2_en_ppx_ip4_wrkq_w1s
 
struct  cvmx_ciu2_en_ppx_ip4_wrkq_w1s::cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s
 
union  cvmx_ciu2_intr_ciu_ready
 
struct  cvmx_ciu2_intr_ciu_ready::cvmx_ciu2_intr_ciu_ready_s
 
union  cvmx_ciu2_intr_ram_ecc_ctl
 
struct  cvmx_ciu2_intr_ram_ecc_ctl::cvmx_ciu2_intr_ram_ecc_ctl_s
 
union  cvmx_ciu2_intr_ram_ecc_st
 
struct  cvmx_ciu2_intr_ram_ecc_st::cvmx_ciu2_intr_ram_ecc_st_s
 
union  cvmx_ciu2_intr_slowdown
 
struct  cvmx_ciu2_intr_slowdown::cvmx_ciu2_intr_slowdown_s
 
union  cvmx_ciu2_msi_rcvx
 
struct  cvmx_ciu2_msi_rcvx::cvmx_ciu2_msi_rcvx_s
 
union  cvmx_ciu2_msi_selx
 
struct  cvmx_ciu2_msi_selx::cvmx_ciu2_msi_selx_s
 
union  cvmx_ciu2_msired_ppx_ip2
 
struct  cvmx_ciu2_msired_ppx_ip2::cvmx_ciu2_msired_ppx_ip2_s
 
union  cvmx_ciu2_msired_ppx_ip3
 
struct  cvmx_ciu2_msired_ppx_ip3::cvmx_ciu2_msired_ppx_ip3_s
 
union  cvmx_ciu2_msired_ppx_ip4
 
struct  cvmx_ciu2_msired_ppx_ip4::cvmx_ciu2_msired_ppx_ip4_s
 
union  cvmx_ciu2_raw_iox_int_gpio
 
struct  cvmx_ciu2_raw_iox_int_gpio::cvmx_ciu2_raw_iox_int_gpio_s
 
union  cvmx_ciu2_raw_iox_int_io
 
struct  cvmx_ciu2_raw_iox_int_io::cvmx_ciu2_raw_iox_int_io_s
 
union  cvmx_ciu2_raw_iox_int_mem
 
struct  cvmx_ciu2_raw_iox_int_mem::cvmx_ciu2_raw_iox_int_mem_s
 
union  cvmx_ciu2_raw_iox_int_mio
 
struct  cvmx_ciu2_raw_iox_int_mio::cvmx_ciu2_raw_iox_int_mio_s
 
union  cvmx_ciu2_raw_iox_int_pkt
 
struct  cvmx_ciu2_raw_iox_int_pkt::cvmx_ciu2_raw_iox_int_pkt_s
 
struct  cvmx_ciu2_raw_iox_int_pkt::cvmx_ciu2_raw_iox_int_pkt_cn68xxp1
 
union  cvmx_ciu2_raw_iox_int_rml
 
struct  cvmx_ciu2_raw_iox_int_rml::cvmx_ciu2_raw_iox_int_rml_s
 
struct  cvmx_ciu2_raw_iox_int_rml::cvmx_ciu2_raw_iox_int_rml_cn68xxp1
 
union  cvmx_ciu2_raw_iox_int_wdog
 
struct  cvmx_ciu2_raw_iox_int_wdog::cvmx_ciu2_raw_iox_int_wdog_s
 
union  cvmx_ciu2_raw_iox_int_wrkq
 
struct  cvmx_ciu2_raw_iox_int_wrkq::cvmx_ciu2_raw_iox_int_wrkq_s
 
union  cvmx_ciu2_raw_ppx_ip2_gpio
 
struct  cvmx_ciu2_raw_ppx_ip2_gpio::cvmx_ciu2_raw_ppx_ip2_gpio_s
 
union  cvmx_ciu2_raw_ppx_ip2_io
 
struct  cvmx_ciu2_raw_ppx_ip2_io::cvmx_ciu2_raw_ppx_ip2_io_s
 
union  cvmx_ciu2_raw_ppx_ip2_mem
 
struct  cvmx_ciu2_raw_ppx_ip2_mem::cvmx_ciu2_raw_ppx_ip2_mem_s
 
union  cvmx_ciu2_raw_ppx_ip2_mio
 
struct  cvmx_ciu2_raw_ppx_ip2_mio::cvmx_ciu2_raw_ppx_ip2_mio_s
 
union  cvmx_ciu2_raw_ppx_ip2_pkt
 
struct  cvmx_ciu2_raw_ppx_ip2_pkt::cvmx_ciu2_raw_ppx_ip2_pkt_s
 
struct  cvmx_ciu2_raw_ppx_ip2_pkt::cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip2_rml
 
struct  cvmx_ciu2_raw_ppx_ip2_rml::cvmx_ciu2_raw_ppx_ip2_rml_s
 
struct  cvmx_ciu2_raw_ppx_ip2_rml::cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip2_wdog
 
struct  cvmx_ciu2_raw_ppx_ip2_wdog::cvmx_ciu2_raw_ppx_ip2_wdog_s
 
union  cvmx_ciu2_raw_ppx_ip2_wrkq
 
struct  cvmx_ciu2_raw_ppx_ip2_wrkq::cvmx_ciu2_raw_ppx_ip2_wrkq_s
 
union  cvmx_ciu2_raw_ppx_ip3_gpio
 
struct  cvmx_ciu2_raw_ppx_ip3_gpio::cvmx_ciu2_raw_ppx_ip3_gpio_s
 
union  cvmx_ciu2_raw_ppx_ip3_io
 
struct  cvmx_ciu2_raw_ppx_ip3_io::cvmx_ciu2_raw_ppx_ip3_io_s
 
union  cvmx_ciu2_raw_ppx_ip3_mem
 
struct  cvmx_ciu2_raw_ppx_ip3_mem::cvmx_ciu2_raw_ppx_ip3_mem_s
 
union  cvmx_ciu2_raw_ppx_ip3_mio
 
struct  cvmx_ciu2_raw_ppx_ip3_mio::cvmx_ciu2_raw_ppx_ip3_mio_s
 
union  cvmx_ciu2_raw_ppx_ip3_pkt
 
struct  cvmx_ciu2_raw_ppx_ip3_pkt::cvmx_ciu2_raw_ppx_ip3_pkt_s
 
struct  cvmx_ciu2_raw_ppx_ip3_pkt::cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip3_rml
 
struct  cvmx_ciu2_raw_ppx_ip3_rml::cvmx_ciu2_raw_ppx_ip3_rml_s
 
struct  cvmx_ciu2_raw_ppx_ip3_rml::cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip3_wdog
 
struct  cvmx_ciu2_raw_ppx_ip3_wdog::cvmx_ciu2_raw_ppx_ip3_wdog_s
 
union  cvmx_ciu2_raw_ppx_ip3_wrkq
 
struct  cvmx_ciu2_raw_ppx_ip3_wrkq::cvmx_ciu2_raw_ppx_ip3_wrkq_s
 
union  cvmx_ciu2_raw_ppx_ip4_gpio
 
struct  cvmx_ciu2_raw_ppx_ip4_gpio::cvmx_ciu2_raw_ppx_ip4_gpio_s
 
union  cvmx_ciu2_raw_ppx_ip4_io
 
struct  cvmx_ciu2_raw_ppx_ip4_io::cvmx_ciu2_raw_ppx_ip4_io_s
 
union  cvmx_ciu2_raw_ppx_ip4_mem
 
struct  cvmx_ciu2_raw_ppx_ip4_mem::cvmx_ciu2_raw_ppx_ip4_mem_s
 
union  cvmx_ciu2_raw_ppx_ip4_mio
 
struct  cvmx_ciu2_raw_ppx_ip4_mio::cvmx_ciu2_raw_ppx_ip4_mio_s
 
union  cvmx_ciu2_raw_ppx_ip4_pkt
 
struct  cvmx_ciu2_raw_ppx_ip4_pkt::cvmx_ciu2_raw_ppx_ip4_pkt_s
 
struct  cvmx_ciu2_raw_ppx_ip4_pkt::cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip4_rml
 
struct  cvmx_ciu2_raw_ppx_ip4_rml::cvmx_ciu2_raw_ppx_ip4_rml_s
 
struct  cvmx_ciu2_raw_ppx_ip4_rml::cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1
 
union  cvmx_ciu2_raw_ppx_ip4_wdog
 
struct  cvmx_ciu2_raw_ppx_ip4_wdog::cvmx_ciu2_raw_ppx_ip4_wdog_s
 
union  cvmx_ciu2_raw_ppx_ip4_wrkq
 
struct  cvmx_ciu2_raw_ppx_ip4_wrkq::cvmx_ciu2_raw_ppx_ip4_wrkq_s
 
union  cvmx_ciu2_src_iox_int_gpio
 
struct  cvmx_ciu2_src_iox_int_gpio::cvmx_ciu2_src_iox_int_gpio_s
 
union  cvmx_ciu2_src_iox_int_io
 
struct  cvmx_ciu2_src_iox_int_io::cvmx_ciu2_src_iox_int_io_s
 
union  cvmx_ciu2_src_iox_int_mbox
 
struct  cvmx_ciu2_src_iox_int_mbox::cvmx_ciu2_src_iox_int_mbox_s
 
union  cvmx_ciu2_src_iox_int_mem
 
struct  cvmx_ciu2_src_iox_int_mem::cvmx_ciu2_src_iox_int_mem_s
 
union  cvmx_ciu2_src_iox_int_mio
 
struct  cvmx_ciu2_src_iox_int_mio::cvmx_ciu2_src_iox_int_mio_s
 
union  cvmx_ciu2_src_iox_int_pkt
 
struct  cvmx_ciu2_src_iox_int_pkt::cvmx_ciu2_src_iox_int_pkt_s
 
struct  cvmx_ciu2_src_iox_int_pkt::cvmx_ciu2_src_iox_int_pkt_cn68xxp1
 
union  cvmx_ciu2_src_iox_int_rml
 
struct  cvmx_ciu2_src_iox_int_rml::cvmx_ciu2_src_iox_int_rml_s
 
struct  cvmx_ciu2_src_iox_int_rml::cvmx_ciu2_src_iox_int_rml_cn68xxp1
 
union  cvmx_ciu2_src_iox_int_wdog
 
struct  cvmx_ciu2_src_iox_int_wdog::cvmx_ciu2_src_iox_int_wdog_s
 
union  cvmx_ciu2_src_iox_int_wrkq
 
struct  cvmx_ciu2_src_iox_int_wrkq::cvmx_ciu2_src_iox_int_wrkq_s
 
union  cvmx_ciu2_src_ppx_ip2_gpio
 
struct  cvmx_ciu2_src_ppx_ip2_gpio::cvmx_ciu2_src_ppx_ip2_gpio_s
 
union  cvmx_ciu2_src_ppx_ip2_io
 
struct  cvmx_ciu2_src_ppx_ip2_io::cvmx_ciu2_src_ppx_ip2_io_s
 
union  cvmx_ciu2_src_ppx_ip2_mbox
 
struct  cvmx_ciu2_src_ppx_ip2_mbox::cvmx_ciu2_src_ppx_ip2_mbox_s
 
union  cvmx_ciu2_src_ppx_ip2_mem
 
struct  cvmx_ciu2_src_ppx_ip2_mem::cvmx_ciu2_src_ppx_ip2_mem_s
 
union  cvmx_ciu2_src_ppx_ip2_mio
 
struct  cvmx_ciu2_src_ppx_ip2_mio::cvmx_ciu2_src_ppx_ip2_mio_s
 
union  cvmx_ciu2_src_ppx_ip2_pkt
 
struct  cvmx_ciu2_src_ppx_ip2_pkt::cvmx_ciu2_src_ppx_ip2_pkt_s
 
struct  cvmx_ciu2_src_ppx_ip2_pkt::cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip2_rml
 
struct  cvmx_ciu2_src_ppx_ip2_rml::cvmx_ciu2_src_ppx_ip2_rml_s
 
struct  cvmx_ciu2_src_ppx_ip2_rml::cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip2_wdog
 
struct  cvmx_ciu2_src_ppx_ip2_wdog::cvmx_ciu2_src_ppx_ip2_wdog_s
 
union  cvmx_ciu2_src_ppx_ip2_wrkq
 
struct  cvmx_ciu2_src_ppx_ip2_wrkq::cvmx_ciu2_src_ppx_ip2_wrkq_s
 
union  cvmx_ciu2_src_ppx_ip3_gpio
 
struct  cvmx_ciu2_src_ppx_ip3_gpio::cvmx_ciu2_src_ppx_ip3_gpio_s
 
union  cvmx_ciu2_src_ppx_ip3_io
 
struct  cvmx_ciu2_src_ppx_ip3_io::cvmx_ciu2_src_ppx_ip3_io_s
 
union  cvmx_ciu2_src_ppx_ip3_mbox
 
struct  cvmx_ciu2_src_ppx_ip3_mbox::cvmx_ciu2_src_ppx_ip3_mbox_s
 
union  cvmx_ciu2_src_ppx_ip3_mem
 
struct  cvmx_ciu2_src_ppx_ip3_mem::cvmx_ciu2_src_ppx_ip3_mem_s
 
union  cvmx_ciu2_src_ppx_ip3_mio
 
struct  cvmx_ciu2_src_ppx_ip3_mio::cvmx_ciu2_src_ppx_ip3_mio_s
 
union  cvmx_ciu2_src_ppx_ip3_pkt
 
struct  cvmx_ciu2_src_ppx_ip3_pkt::cvmx_ciu2_src_ppx_ip3_pkt_s
 
struct  cvmx_ciu2_src_ppx_ip3_pkt::cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip3_rml
 
struct  cvmx_ciu2_src_ppx_ip3_rml::cvmx_ciu2_src_ppx_ip3_rml_s
 
struct  cvmx_ciu2_src_ppx_ip3_rml::cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip3_wdog
 
struct  cvmx_ciu2_src_ppx_ip3_wdog::cvmx_ciu2_src_ppx_ip3_wdog_s
 
union  cvmx_ciu2_src_ppx_ip3_wrkq
 
struct  cvmx_ciu2_src_ppx_ip3_wrkq::cvmx_ciu2_src_ppx_ip3_wrkq_s
 
union  cvmx_ciu2_src_ppx_ip4_gpio
 
struct  cvmx_ciu2_src_ppx_ip4_gpio::cvmx_ciu2_src_ppx_ip4_gpio_s
 
union  cvmx_ciu2_src_ppx_ip4_io
 
struct  cvmx_ciu2_src_ppx_ip4_io::cvmx_ciu2_src_ppx_ip4_io_s
 
union  cvmx_ciu2_src_ppx_ip4_mbox
 
struct  cvmx_ciu2_src_ppx_ip4_mbox::cvmx_ciu2_src_ppx_ip4_mbox_s
 
union  cvmx_ciu2_src_ppx_ip4_mem
 
struct  cvmx_ciu2_src_ppx_ip4_mem::cvmx_ciu2_src_ppx_ip4_mem_s
 
union  cvmx_ciu2_src_ppx_ip4_mio
 
struct  cvmx_ciu2_src_ppx_ip4_mio::cvmx_ciu2_src_ppx_ip4_mio_s
 
union  cvmx_ciu2_src_ppx_ip4_pkt
 
struct  cvmx_ciu2_src_ppx_ip4_pkt::cvmx_ciu2_src_ppx_ip4_pkt_s
 
struct  cvmx_ciu2_src_ppx_ip4_pkt::cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip4_rml
 
struct  cvmx_ciu2_src_ppx_ip4_rml::cvmx_ciu2_src_ppx_ip4_rml_s
 
struct  cvmx_ciu2_src_ppx_ip4_rml::cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1
 
union  cvmx_ciu2_src_ppx_ip4_wdog
 
struct  cvmx_ciu2_src_ppx_ip4_wdog::cvmx_ciu2_src_ppx_ip4_wdog_s
 
union  cvmx_ciu2_src_ppx_ip4_wrkq
 
struct  cvmx_ciu2_src_ppx_ip4_wrkq::cvmx_ciu2_src_ppx_ip4_wrkq_s
 
union  cvmx_ciu2_sum_iox_int
 
struct  cvmx_ciu2_sum_iox_int::cvmx_ciu2_sum_iox_int_s
 
union  cvmx_ciu2_sum_ppx_ip2
 
struct  cvmx_ciu2_sum_ppx_ip2::cvmx_ciu2_sum_ppx_ip2_s
 
union  cvmx_ciu2_sum_ppx_ip3
 
struct  cvmx_ciu2_sum_ppx_ip3::cvmx_ciu2_sum_ppx_ip3_s
 
union  cvmx_ciu2_sum_ppx_ip4
 
struct  cvmx_ciu2_sum_ppx_ip4::cvmx_ciu2_sum_ppx_ip4_s
 

Macros

#define CVMX_CIU2_ACK_IOX_INT(block_id)   (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_ACK_PPX_IP2(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_ACK_PPX_IP3(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_ACK_PPX_IP4(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id)   (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id)   (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_INTR_CIU_READY   (CVMX_ADD_IO_SEG(0x0001070100102008ull))
 
#define CVMX_CIU2_INTR_RAM_ECC_CTL   (CVMX_ADD_IO_SEG(0x0001070100102010ull))
 
#define CVMX_CIU2_INTR_RAM_ECC_ST   (CVMX_ADD_IO_SEG(0x0001070100102018ull))
 
#define CVMX_CIU2_INTR_SLOWDOWN   (CVMX_ADD_IO_SEG(0x0001070100102000ull))
 
#define CVMX_CIU2_MSIRED_PPX_IP2(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_MSIRED_PPX_IP3(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_MSIRED_PPX_IP4(block_id)   (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_MSI_RCVX(offset)   (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
 
#define CVMX_CIU2_MSI_SELX(offset)   (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
 
#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id)   (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id)   (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id)   (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id)   (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id)   (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id)   (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id)   (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
 
#define CVMX_CIU2_SUM_IOX_INT(offset)   (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
 
#define CVMX_CIU2_SUM_PPX_IP2(offset)   (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
 
#define CVMX_CIU2_SUM_PPX_IP3(offset)   (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
 
#define CVMX_CIU2_SUM_PPX_IP4(offset)   (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
 

Macro Definition Documentation

#define CVMX_CIU2_ACK_IOX_INT (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 31 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_ACK_PPX_IP2 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 32 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_ACK_PPX_IP3 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 33 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_ACK_PPX_IP4 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 34 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 35 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 36 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 37 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 38 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_IO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 39 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_IO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 40 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 41 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 42 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 43 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 44 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MEM_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 45 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MEM_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 46 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 47 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 48 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_MIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 49 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 50 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_PKT_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 51 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_PKT_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 52 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 53 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_RML_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 54 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_RML_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 55 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 56 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 57 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 58 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 59 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 60 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 61 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 62 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 63 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 64 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 65 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_IO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 66 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_IO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 67 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 68 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 69 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 70 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 71 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 72 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 73 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 74 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 75 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 76 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 77 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 78 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 79 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 80 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_RML_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 81 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_RML_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 82 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 83 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 84 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 85 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 86 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 87 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 88 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 89 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 90 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 91 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 92 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_IO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 93 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_IO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 94 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 95 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 96 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 97 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 98 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 99 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 100 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 101 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 102 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 103 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 104 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 105 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 106 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 107 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_RML_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 108 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_RML_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 109 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 110 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 111 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 112 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 113 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 114 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 115 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 116 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 117 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 118 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 119 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_IO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 120 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_IO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 121 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 122 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 123 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 124 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 125 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 126 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 127 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 128 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 129 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 130 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 131 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 132 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 133 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 134 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_RML_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 135 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_RML_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 136 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 137 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 138 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 139 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 140 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 141 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 142 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_INTR_CIU_READY   (CVMX_ADD_IO_SEG(0x0001070100102008ull))

Definition at line 143 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_INTR_RAM_ECC_CTL   (CVMX_ADD_IO_SEG(0x0001070100102010ull))

Definition at line 144 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_INTR_RAM_ECC_ST   (CVMX_ADD_IO_SEG(0x0001070100102018ull))

Definition at line 145 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_INTR_SLOWDOWN   (CVMX_ADD_IO_SEG(0x0001070100102000ull))

Definition at line 146 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_MSI_RCVX (   offset)    (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)

Definition at line 150 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_MSI_SELX (   offset)    (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)

Definition at line 151 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_MSIRED_PPX_IP2 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 147 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_MSIRED_PPX_IP3 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 148 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_MSIRED_PPX_IP4 (   block_id)    (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 149 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 152 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 153 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 154 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 155 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 156 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 157 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 158 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_IOX_INT_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 159 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 160 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 161 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 162 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 163 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 164 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 165 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 166 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP2_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 167 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 168 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 169 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 170 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 171 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 172 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 173 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 174 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP3_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 175 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 176 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 177 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 178 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 179 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 180 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 181 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 182 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_RAW_PPX_IP4_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 183 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 184 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 185 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 186 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 187 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 188 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 189 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 190 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 191 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_IOX_INT_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)

Definition at line 192 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 193 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 194 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 195 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 196 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 197 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 198 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 199 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 200 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP2_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 201 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 202 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 203 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 204 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 205 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 206 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 207 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 208 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 209 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP3_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 210 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_GPIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 211 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_IO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 212 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_MBOX (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 213 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_MEM (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 214 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_MIO (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 215 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_PKT (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 216 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_RML (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 217 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_WDOG (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 218 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SRC_PPX_IP4_WRKQ (   block_id)    (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)

Definition at line 219 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SUM_IOX_INT (   offset)    (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)

Definition at line 220 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SUM_PPX_IP2 (   offset)    (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)

Definition at line 221 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SUM_PPX_IP3 (   offset)    (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)

Definition at line 222 of file cvmx-ciu2-defs.h.

#define CVMX_CIU2_SUM_PPX_IP4 (   offset)    (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)

Definition at line 223 of file cvmx-ciu2-defs.h.

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