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cvmx-gpio-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT. See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_GPIO_DEFS_H__
29 #define __CVMX_GPIO_DEFS_H__
30 
31 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
32 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
33 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
34 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
35 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
36 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
37 #define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
38 #define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
39 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
40 #define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
41 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
42 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
43 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
44 
45 union cvmx_gpio_bit_cfgx {
46  uint64_t u64;
47  struct cvmx_gpio_bit_cfgx_s {
48 #ifdef __BIG_ENDIAN_BITFIELD
49  uint64_t reserved_17_63:47;
50  uint64_t synce_sel:2;
51  uint64_t clk_gen:1;
52  uint64_t clk_sel:2;
53  uint64_t fil_sel:4;
54  uint64_t fil_cnt:4;
55  uint64_t int_type:1;
56  uint64_t int_en:1;
57  uint64_t rx_xor:1;
58  uint64_t tx_oe:1;
59 #else
60  uint64_t tx_oe:1;
61  uint64_t rx_xor:1;
62  uint64_t int_en:1;
63  uint64_t int_type:1;
64  uint64_t fil_cnt:4;
65  uint64_t fil_sel:4;
66  uint64_t clk_sel:2;
67  uint64_t clk_gen:1;
68  uint64_t synce_sel:2;
69  uint64_t reserved_17_63:47;
70 #endif
71  } s;
72  struct cvmx_gpio_bit_cfgx_cn30xx {
73 #ifdef __BIG_ENDIAN_BITFIELD
74  uint64_t reserved_12_63:52;
75  uint64_t fil_sel:4;
76  uint64_t fil_cnt:4;
77  uint64_t int_type:1;
78  uint64_t int_en:1;
79  uint64_t rx_xor:1;
80  uint64_t tx_oe:1;
81 #else
82  uint64_t tx_oe:1;
83  uint64_t rx_xor:1;
84  uint64_t int_en:1;
85  uint64_t int_type:1;
86  uint64_t fil_cnt:4;
87  uint64_t fil_sel:4;
88  uint64_t reserved_12_63:52;
89 #endif
90  } cn30xx;
91  struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
92  struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
93  struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
94  struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
95  struct cvmx_gpio_bit_cfgx_cn52xx {
96 #ifdef __BIG_ENDIAN_BITFIELD
97  uint64_t reserved_15_63:49;
98  uint64_t clk_gen:1;
99  uint64_t clk_sel:2;
100  uint64_t fil_sel:4;
101  uint64_t fil_cnt:4;
102  uint64_t int_type:1;
103  uint64_t int_en:1;
104  uint64_t rx_xor:1;
105  uint64_t tx_oe:1;
106 #else
107  uint64_t tx_oe:1;
108  uint64_t rx_xor:1;
109  uint64_t int_en:1;
110  uint64_t int_type:1;
111  uint64_t fil_cnt:4;
112  uint64_t fil_sel:4;
113  uint64_t clk_sel:2;
114  uint64_t clk_gen:1;
115  uint64_t reserved_15_63:49;
116 #endif
117  } cn52xx;
118  struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
119  struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
120  struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
121  struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
122  struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
123  struct cvmx_gpio_bit_cfgx_s cn61xx;
124  struct cvmx_gpio_bit_cfgx_s cn63xx;
125  struct cvmx_gpio_bit_cfgx_s cn63xxp1;
126  struct cvmx_gpio_bit_cfgx_s cn66xx;
127  struct cvmx_gpio_bit_cfgx_s cn68xx;
128  struct cvmx_gpio_bit_cfgx_s cn68xxp1;
129  struct cvmx_gpio_bit_cfgx_s cnf71xx;
130 };
131 
132 union cvmx_gpio_boot_ena {
133  uint64_t u64;
134  struct cvmx_gpio_boot_ena_s {
135 #ifdef __BIG_ENDIAN_BITFIELD
136  uint64_t reserved_12_63:52;
137  uint64_t boot_ena:4;
138  uint64_t reserved_0_7:8;
139 #else
140  uint64_t reserved_0_7:8;
141  uint64_t boot_ena:4;
142  uint64_t reserved_12_63:52;
143 #endif
144  } s;
145  struct cvmx_gpio_boot_ena_s cn30xx;
146  struct cvmx_gpio_boot_ena_s cn31xx;
147  struct cvmx_gpio_boot_ena_s cn50xx;
148 };
149 
150 union cvmx_gpio_clk_genx {
151  uint64_t u64;
152  struct cvmx_gpio_clk_genx_s {
153 #ifdef __BIG_ENDIAN_BITFIELD
154  uint64_t reserved_32_63:32;
155  uint64_t n:32;
156 #else
157  uint64_t n:32;
158  uint64_t reserved_32_63:32;
159 #endif
160  } s;
161  struct cvmx_gpio_clk_genx_s cn52xx;
162  struct cvmx_gpio_clk_genx_s cn52xxp1;
163  struct cvmx_gpio_clk_genx_s cn56xx;
164  struct cvmx_gpio_clk_genx_s cn56xxp1;
165  struct cvmx_gpio_clk_genx_s cn61xx;
166  struct cvmx_gpio_clk_genx_s cn63xx;
167  struct cvmx_gpio_clk_genx_s cn63xxp1;
168  struct cvmx_gpio_clk_genx_s cn66xx;
169  struct cvmx_gpio_clk_genx_s cn68xx;
170  struct cvmx_gpio_clk_genx_s cn68xxp1;
171  struct cvmx_gpio_clk_genx_s cnf71xx;
172 };
173 
174 union cvmx_gpio_clk_qlmx {
175  uint64_t u64;
176  struct cvmx_gpio_clk_qlmx_s {
177 #ifdef __BIG_ENDIAN_BITFIELD
178  uint64_t reserved_11_63:53;
179  uint64_t qlm_sel:3;
180  uint64_t reserved_3_7:5;
181  uint64_t div:1;
182  uint64_t lane_sel:2;
183 #else
184  uint64_t lane_sel:2;
185  uint64_t div:1;
186  uint64_t reserved_3_7:5;
187  uint64_t qlm_sel:3;
188  uint64_t reserved_11_63:53;
189 #endif
190  } s;
191  struct cvmx_gpio_clk_qlmx_cn61xx {
192 #ifdef __BIG_ENDIAN_BITFIELD
193  uint64_t reserved_10_63:54;
194  uint64_t qlm_sel:2;
195  uint64_t reserved_3_7:5;
196  uint64_t div:1;
197  uint64_t lane_sel:2;
198 #else
199  uint64_t lane_sel:2;
200  uint64_t div:1;
201  uint64_t reserved_3_7:5;
202  uint64_t qlm_sel:2;
203  uint64_t reserved_10_63:54;
204 #endif
205  } cn61xx;
206  struct cvmx_gpio_clk_qlmx_cn63xx {
207 #ifdef __BIG_ENDIAN_BITFIELD
208  uint64_t reserved_3_63:61;
209  uint64_t div:1;
210  uint64_t lane_sel:2;
211 #else
212  uint64_t lane_sel:2;
213  uint64_t div:1;
214  uint64_t reserved_3_63:61;
215 #endif
216  } cn63xx;
217  struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
218  struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
219  struct cvmx_gpio_clk_qlmx_s cn68xx;
220  struct cvmx_gpio_clk_qlmx_s cn68xxp1;
221  struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
222 };
223 
224 union cvmx_gpio_dbg_ena {
225  uint64_t u64;
226  struct cvmx_gpio_dbg_ena_s {
227 #ifdef __BIG_ENDIAN_BITFIELD
228  uint64_t reserved_21_63:43;
229  uint64_t dbg_ena:21;
230 #else
231  uint64_t dbg_ena:21;
232  uint64_t reserved_21_63:43;
233 #endif
234  } s;
235  struct cvmx_gpio_dbg_ena_s cn30xx;
236  struct cvmx_gpio_dbg_ena_s cn31xx;
237  struct cvmx_gpio_dbg_ena_s cn50xx;
238 };
239 
240 union cvmx_gpio_int_clr {
241  uint64_t u64;
242  struct cvmx_gpio_int_clr_s {
243 #ifdef __BIG_ENDIAN_BITFIELD
244  uint64_t reserved_16_63:48;
245  uint64_t type:16;
246 #else
247  uint64_t type:16;
248  uint64_t reserved_16_63:48;
249 #endif
250  } s;
251  struct cvmx_gpio_int_clr_s cn30xx;
252  struct cvmx_gpio_int_clr_s cn31xx;
253  struct cvmx_gpio_int_clr_s cn38xx;
254  struct cvmx_gpio_int_clr_s cn38xxp2;
255  struct cvmx_gpio_int_clr_s cn50xx;
256  struct cvmx_gpio_int_clr_s cn52xx;
257  struct cvmx_gpio_int_clr_s cn52xxp1;
258  struct cvmx_gpio_int_clr_s cn56xx;
259  struct cvmx_gpio_int_clr_s cn56xxp1;
260  struct cvmx_gpio_int_clr_s cn58xx;
261  struct cvmx_gpio_int_clr_s cn58xxp1;
262  struct cvmx_gpio_int_clr_s cn61xx;
263  struct cvmx_gpio_int_clr_s cn63xx;
264  struct cvmx_gpio_int_clr_s cn63xxp1;
265  struct cvmx_gpio_int_clr_s cn66xx;
266  struct cvmx_gpio_int_clr_s cn68xx;
267  struct cvmx_gpio_int_clr_s cn68xxp1;
268  struct cvmx_gpio_int_clr_s cnf71xx;
269 };
270 
271 union cvmx_gpio_multi_cast {
272  uint64_t u64;
273  struct cvmx_gpio_multi_cast_s {
274 #ifdef __BIG_ENDIAN_BITFIELD
275  uint64_t reserved_1_63:63;
276  uint64_t en:1;
277 #else
278  uint64_t en:1;
279  uint64_t reserved_1_63:63;
280 #endif
281  } s;
282  struct cvmx_gpio_multi_cast_s cn61xx;
283  struct cvmx_gpio_multi_cast_s cnf71xx;
284 };
285 
286 union cvmx_gpio_pin_ena {
287  uint64_t u64;
288  struct cvmx_gpio_pin_ena_s {
289 #ifdef __BIG_ENDIAN_BITFIELD
290  uint64_t reserved_20_63:44;
291  uint64_t ena19:1;
292  uint64_t ena18:1;
293  uint64_t reserved_0_17:18;
294 #else
295  uint64_t reserved_0_17:18;
296  uint64_t ena18:1;
297  uint64_t ena19:1;
298  uint64_t reserved_20_63:44;
299 #endif
300  } s;
301  struct cvmx_gpio_pin_ena_s cn66xx;
302 };
303 
304 union cvmx_gpio_rx_dat {
305  uint64_t u64;
306  struct cvmx_gpio_rx_dat_s {
307 #ifdef __BIG_ENDIAN_BITFIELD
308  uint64_t reserved_24_63:40;
309  uint64_t dat:24;
310 #else
311  uint64_t dat:24;
312  uint64_t reserved_24_63:40;
313 #endif
314  } s;
315  struct cvmx_gpio_rx_dat_s cn30xx;
316  struct cvmx_gpio_rx_dat_s cn31xx;
317  struct cvmx_gpio_rx_dat_cn38xx {
318 #ifdef __BIG_ENDIAN_BITFIELD
319  uint64_t reserved_16_63:48;
320  uint64_t dat:16;
321 #else
322  uint64_t dat:16;
323  uint64_t reserved_16_63:48;
324 #endif
325  } cn38xx;
326  struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
327  struct cvmx_gpio_rx_dat_s cn50xx;
328  struct cvmx_gpio_rx_dat_cn38xx cn52xx;
329  struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
330  struct cvmx_gpio_rx_dat_cn38xx cn56xx;
331  struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
332  struct cvmx_gpio_rx_dat_cn38xx cn58xx;
333  struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
334  struct cvmx_gpio_rx_dat_cn61xx {
335 #ifdef __BIG_ENDIAN_BITFIELD
336  uint64_t reserved_20_63:44;
337  uint64_t dat:20;
338 #else
339  uint64_t dat:20;
340  uint64_t reserved_20_63:44;
341 #endif
342  } cn61xx;
343  struct cvmx_gpio_rx_dat_cn38xx cn63xx;
344  struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
345  struct cvmx_gpio_rx_dat_cn61xx cn66xx;
346  struct cvmx_gpio_rx_dat_cn38xx cn68xx;
347  struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
348  struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
349 };
350 
351 union cvmx_gpio_tim_ctl {
352  uint64_t u64;
353  struct cvmx_gpio_tim_ctl_s {
354 #ifdef __BIG_ENDIAN_BITFIELD
355  uint64_t reserved_4_63:60;
356  uint64_t sel:4;
357 #else
358  uint64_t sel:4;
359  uint64_t reserved_4_63:60;
360 #endif
361  } s;
362  struct cvmx_gpio_tim_ctl_s cn68xx;
363  struct cvmx_gpio_tim_ctl_s cn68xxp1;
364 };
365 
366 union cvmx_gpio_tx_clr {
367  uint64_t u64;
368  struct cvmx_gpio_tx_clr_s {
369 #ifdef __BIG_ENDIAN_BITFIELD
370  uint64_t reserved_24_63:40;
371  uint64_t clr:24;
372 #else
373  uint64_t clr:24;
374  uint64_t reserved_24_63:40;
375 #endif
376  } s;
377  struct cvmx_gpio_tx_clr_s cn30xx;
378  struct cvmx_gpio_tx_clr_s cn31xx;
379  struct cvmx_gpio_tx_clr_cn38xx {
380 #ifdef __BIG_ENDIAN_BITFIELD
381  uint64_t reserved_16_63:48;
382  uint64_t clr:16;
383 #else
384  uint64_t clr:16;
385  uint64_t reserved_16_63:48;
386 #endif
387  } cn38xx;
388  struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
389  struct cvmx_gpio_tx_clr_s cn50xx;
390  struct cvmx_gpio_tx_clr_cn38xx cn52xx;
391  struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
392  struct cvmx_gpio_tx_clr_cn38xx cn56xx;
393  struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
394  struct cvmx_gpio_tx_clr_cn38xx cn58xx;
395  struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
396  struct cvmx_gpio_tx_clr_cn61xx {
397 #ifdef __BIG_ENDIAN_BITFIELD
398  uint64_t reserved_20_63:44;
399  uint64_t clr:20;
400 #else
401  uint64_t clr:20;
402  uint64_t reserved_20_63:44;
403 #endif
404  } cn61xx;
405  struct cvmx_gpio_tx_clr_cn38xx cn63xx;
406  struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
407  struct cvmx_gpio_tx_clr_cn61xx cn66xx;
408  struct cvmx_gpio_tx_clr_cn38xx cn68xx;
409  struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
410  struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
411 };
412 
413 union cvmx_gpio_tx_set {
414  uint64_t u64;
415  struct cvmx_gpio_tx_set_s {
416 #ifdef __BIG_ENDIAN_BITFIELD
417  uint64_t reserved_24_63:40;
418  uint64_t set:24;
419 #else
420  uint64_t set:24;
421  uint64_t reserved_24_63:40;
422 #endif
423  } s;
424  struct cvmx_gpio_tx_set_s cn30xx;
425  struct cvmx_gpio_tx_set_s cn31xx;
426  struct cvmx_gpio_tx_set_cn38xx {
427 #ifdef __BIG_ENDIAN_BITFIELD
428  uint64_t reserved_16_63:48;
429  uint64_t set:16;
430 #else
431  uint64_t set:16;
432  uint64_t reserved_16_63:48;
433 #endif
434  } cn38xx;
435  struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
436  struct cvmx_gpio_tx_set_s cn50xx;
437  struct cvmx_gpio_tx_set_cn38xx cn52xx;
438  struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
439  struct cvmx_gpio_tx_set_cn38xx cn56xx;
440  struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
441  struct cvmx_gpio_tx_set_cn38xx cn58xx;
442  struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
443  struct cvmx_gpio_tx_set_cn61xx {
444 #ifdef __BIG_ENDIAN_BITFIELD
445  uint64_t reserved_20_63:44;
446  uint64_t set:20;
447 #else
448  uint64_t set:20;
449  uint64_t reserved_20_63:44;
450 #endif
451  } cn61xx;
452  struct cvmx_gpio_tx_set_cn38xx cn63xx;
453  struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
454  struct cvmx_gpio_tx_set_cn61xx cn66xx;
455  struct cvmx_gpio_tx_set_cn38xx cn68xx;
456  struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
457  struct cvmx_gpio_tx_set_cn61xx cnf71xx;
458 };
459 
460 union cvmx_gpio_xbit_cfgx {
461  uint64_t u64;
462  struct cvmx_gpio_xbit_cfgx_s {
463 #ifdef __BIG_ENDIAN_BITFIELD
464  uint64_t reserved_17_63:47;
465  uint64_t synce_sel:2;
466  uint64_t clk_gen:1;
467  uint64_t clk_sel:2;
468  uint64_t fil_sel:4;
469  uint64_t fil_cnt:4;
470  uint64_t int_type:1;
471  uint64_t int_en:1;
472  uint64_t rx_xor:1;
473  uint64_t tx_oe:1;
474 #else
475  uint64_t tx_oe:1;
476  uint64_t rx_xor:1;
477  uint64_t int_en:1;
478  uint64_t int_type:1;
479  uint64_t fil_cnt:4;
480  uint64_t fil_sel:4;
481  uint64_t clk_sel:2;
482  uint64_t clk_gen:1;
483  uint64_t synce_sel:2;
484  uint64_t reserved_17_63:47;
485 #endif
486  } s;
487  struct cvmx_gpio_xbit_cfgx_cn30xx {
488 #ifdef __BIG_ENDIAN_BITFIELD
489  uint64_t reserved_12_63:52;
490  uint64_t fil_sel:4;
491  uint64_t fil_cnt:4;
492  uint64_t reserved_2_3:2;
493  uint64_t rx_xor:1;
494  uint64_t tx_oe:1;
495 #else
496  uint64_t tx_oe:1;
497  uint64_t rx_xor:1;
498  uint64_t reserved_2_3:2;
499  uint64_t fil_cnt:4;
500  uint64_t fil_sel:4;
501  uint64_t reserved_12_63:52;
502 #endif
503  } cn30xx;
504  struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
505  struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
506  struct cvmx_gpio_xbit_cfgx_s cn61xx;
507  struct cvmx_gpio_xbit_cfgx_s cn66xx;
508  struct cvmx_gpio_xbit_cfgx_s cnf71xx;
509 };
510 
511 #endif
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