#include <linux/interrupt.h>
#include <linux/bitops.h>

Data Structures
struct	prcmu_auto_pm_config

struct	prcmu_fw_version

Macros
#define	DB8500_PRCM_GPIOCR 0x138

#define	DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)

#define	DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)

#define	DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)

#define	DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)

#define	DB8500_PRCM_LINE_VALUE 0x170

#define	DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)

#define	DB8500_PRCM_DSI_SW_RESET 0x324

#define	DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)

#define	DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)

#define	DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)

#define	PRCMU_AUTO_PM_OFF 0

#define	PRCMU_AUTO_PM_ON 1

#define	PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)

#define	PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)

#define	PRCMU_FW_PROJECT_U8500 2

#define	PRCMU_FW_PROJECT_U9500 4

#define	PRCMU_FW_PROJECT_U8500_C2 7

#define	PRCMU_FW_PROJECT_U9500_C2 11

#define	PRCMU_FW_PROJECT_U8520 13

#define	PRCMU_FW_PROJECT_U8420 14

Enumerations
enum	state { OFF = 0x0, ON = 0x1, Start, Collect, GotHeader, SkipIt, GotName, CopyFile, GotSymlink, Reset }

enum	ret_state { OFFST = 0, ONST = 1, RETST = 2 }

enum	clk_arm { A9_OFF, A9_BOOT, A9_OPPT1, A9_OPPT2, A9_EXTCLK }

enum	clk_gen { GEN_OFF, GEN_BOOT, GEN_OPPT1 }

enum	romcode_write { RDY_2_DS = 0x09, RDY_2_XP70_RST = 0x10 }

enum	romcode_read { INIT = 0x00, FS_2_DS = 0x0A, END_DS = 0x0B, DS_TO_FS = 0x0C, END_FS = 0x0D, SWR = 0x0E, END_SWR = 0x0F }

enum	ap_pwrst { NO_PWRST = 0x00, AP_BOOT = 0x01, AP_EXECUTE = 0x02, AP_DEEP_SLEEP = 0x03, AP_SLEEP = 0x04, AP_IDLE = 0x05, AP_RESET = 0x06 }

enum	ap_pwrst_trans { PRCMU_AP_NO_CHANGE = 0x00, APEXECUTE_TO_APSLEEP = 0x01, APIDLE_TO_APSLEEP = 0x02, PRCMU_AP_SLEEP = 0x01, APBOOT_TO_APEXECUTE = 0x03, APEXECUTE_TO_APDEEPSLEEP = 0x04, PRCMU_AP_DEEP_SLEEP = 0x04, APEXECUTE_TO_APIDLE = 0x05, PRCMU_AP_IDLE = 0x05, PRCMU_AP_DEEP_IDLE = 0x07 }

enum	hw_acc_state { HW_NO_CHANGE = 0x00, HW_OFF = 0x01, HW_OFF_RAMRET = 0x02, HW_ON = 0x04 }

enum	ap_pwrsttr_status { BOOT_TO_EXECUTEOK = 0xFF, DEEPSLEEPOK = 0xFE, SLEEPOK = 0xFD, IDLEOK = 0xFC, SOFTRESETOK = 0xFB, SOFTRESETGO = 0xFA, BOOT_TO_EXECUTE = 0xF9, EXECUTE_TO_DEEPSLEEP = 0xF8, DEEPSLEEP_TO_EXECUTE = 0xF7, DEEPSLEEP_TO_EXECUTEOK = 0xF6, EXECUTE_TO_SLEEP = 0xF5, SLEEP_TO_EXECUTE = 0xF4, SLEEP_TO_EXECUTEOK = 0xF3, EXECUTE_TO_IDLE = 0xF2, IDLE_TO_EXECUTE = 0xF1, IDLE_TO_EXECUTEOK = 0xF0, RDYTODS_RETURNTOEXE = 0xEF, NORDYTODS_RETURNTOEXE = 0xEE, EXETOSLEEP_RETURNTOEXE = 0xED, EXETOIDLE_RETURNTOEXE = 0xEC, INIT_STATUS = 0xEB, INITERROR = 0x00, PLLARMLOCKP_ER = 0x01, PLLDDRLOCKP_ER = 0x02, PLLSOCLOCKP_ER = 0x03, PLLSOCK1LOCKP_ER = 0x04, ARMWFI_ER = 0x05, SYSCLKOK_ER = 0x06, I2C_NACK_DATA_ER = 0x07, BOOT_ER = 0x08, I2C_STATUS_ALWAYS_1 = 0x0A, I2C_NACK_REG_ADDR_ER = 0x0B, I2C_NACK_DATA0123_ER = 0x1B, I2C_NACK_ADDR_ER = 0x1F, CURAPPWRSTISNOT_BOOT = 0x20, CURAPPWRSTISNOT_EXECUTE = 0x21, CURAPPWRSTISNOT_SLEEPMODE = 0x22, CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, FIFO4500WUISNOT_WUPEVENT = 0x24, PLL32KLOCKP_ER = 0x29, DDRDEEPSLEEPOK_ER = 0x2A, ROMCODEREADY_ER = 0x50, WUPBEFOREDS = 0x51, DDRCONFIG_ER = 0x52, WUPBEFORESLEEP = 0x53, WUPBEFOREIDLE = 0x54 }

enum	dvfs_stat { DVFS_GO = 0xFF, DVFS_ARM100OPPOK = 0xFE, DVFS_ARM50OPPOK = 0xFD, DVFS_ARMEXTCLKOK = 0xFC, DVFS_NOCHGTCLKOK = 0xFB, DVFS_INITSTATUS = 0x00 }

enum	sva_mmdsp_stat { SVA_MMDSP_GO = 0xFF, SVA_MMDSP_INIT = 0x00 }

enum	sia_mmdsp_stat { SIA_MMDSP_GO = 0xFF, SIA_MMDSP_INIT = 0x00 }

enum	mbox_to_arm_err { INIT_ERR = 0x00, PLLARMLOCKP_ERR = 0x01, PLLDDRLOCKP_ERR = 0x02, PLLSOC0LOCKP_ERR = 0x03, PLLSOC1LOCKP_ERR = 0x04, ARMWFI_ERR = 0x05, SYSCLKOK_ERR = 0x06, BOOT_ERR = 0x07, ROMCODESAVECONTEXT = 0x08, VARMHIGHSPEEDVALTO_ERR = 0x10, VARMHIGHSPEEDACCESS_ERR = 0x11, VARMLOWSPEEDVALTO_ERR = 0x12, VARMLOWSPEEDACCESS_ERR = 0x13, VARMRETENTIONVALTO_ERR = 0x14, VARMRETENTIONACCESS_ERR = 0x15, VAPEHIGHSPEEDVALTO_ERR = 0x16, VSAFEHPVALTO_ERR = 0x17, VMODSEL1VALTO_ERR = 0x18, VMODSEL2VALTO_ERR = 0x19, VARMOFFACCESS_ERR = 0x1A, VAPEOFFACCESS_ERR = 0x1B, VARMRETACCES_ERR = 0x1C, CURAPPWRSTISNOTBOOT = 0x20, CURAPPWRSTISNOTEXECUTE = 0x21, CURAPPWRSTISNOTSLEEPMODE = 0x22, CURAPPWRSTISNOTCORRECTDBG = 0x23, ARMREGU1VALTO_ERR = 0x24, ARMREGU2VALTO_ERR = 0x25, VAPEREGUVALTO_ERR = 0x26, VSMPS3REGUVALTO_ERR = 0x27, VMODREGUVALTO_ERR = 0x28 }

enum	hw_acc { SVAMMDSP = 0, SVAPIPE = 1, SIAMMDSP = 2, SIAPIPE = 3, SGA = 4, B2R2MCDE = 5, ESRAM12 = 6, ESRAM34 = 7 }

enum	cs_pwrmgt { PWRDNCS0 = 0, WKUPCS0 = 1, PWRDNCS1 = 2, WKUPCS1 = 3 }

enum	sia_sva_pwr_policy { NO_CHGT = 0x0, DSPOFF_HWPOFF = 0x1, DSPOFFRAMRET_HWPOFF = 0x2, DSPCLKOFF_HWPOFF = 0x3, DSPCLKOFF_HWPCLKOFF = 0x4 }

enum	auto_enable { AUTO_OFF = 0x0, AUTO_ON = 0x1 }

enum	prcmu_power_status { PRCMU_SLEEP_OK = 0xf3, PRCMU_DEEP_SLEEP_OK = 0xf6, PRCMU_IDLE_OK = 0xf0, PRCMU_DEEPIDLE_OK = 0xe3, PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91, PRCMU_ARMPENDINGIT_ER = 0x93 }

enum	prcmu_auto_pm_policy { PRCMU_AUTO_PM_POLICY_NO_CHANGE, PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF, PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF, PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF, PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF }

Macro Definition Documentation

#define DB8500_PRCM_DSI_SW_RESET 0x324

Definition at line 28 of file db8500-prcmu.h.

#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)

Definition at line 29 of file db8500-prcmu.h.

#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)

Definition at line 30 of file db8500-prcmu.h.

#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)

Definition at line 31 of file db8500-prcmu.h.

#define DB8500_PRCM_GPIOCR 0x138

Definition at line 19 of file db8500-prcmu.h.

#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)

Definition at line 21 of file db8500-prcmu.h.

#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)

Definition at line 22 of file db8500-prcmu.h.

#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)

Definition at line 20 of file db8500-prcmu.h.

#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)

Definition at line 23 of file db8500-prcmu.h.

#define DB8500_PRCM_LINE_VALUE 0x170

Definition at line 25 of file db8500-prcmu.h.

#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)

Definition at line 26 of file db8500-prcmu.h.

#define PRCMU_AUTO_PM_OFF 0

Definition at line 464 of file db8500-prcmu.h.

#define PRCMU_AUTO_PM_ON 1

Definition at line 465 of file db8500-prcmu.h.

#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)

Definition at line 468 of file db8500-prcmu.h.

#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)

Definition at line 467 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U8420 14

Definition at line 501 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U8500 2

Definition at line 496 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U8500_C2 7

Definition at line 498 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U8520 13

Definition at line 500 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U9500 4

Definition at line 497 of file db8500-prcmu.h.

#define PRCMU_FW_PROJECT_U9500_C2 11

Definition at line 499 of file db8500-prcmu.h.

Enumeration Type Documentation

enum ap_pwrst

enum ap_pwrst - current power states defined in PRCMU firmware : Current power state init : Current power state is apBoot : Current power state is apExecute : Current power state is apDeepSleep : Current power state is apSleep : Current power state is apIdle : Current power state is apReset

Enumerator:

NO_PWRST
AP_BOOT
AP_EXECUTE
AP_DEEP_SLEEP
AP_SLEEP
AP_IDLE
AP_RESET

Definition at line 132 of file db8500-prcmu.h.

enum ap_pwrst_trans

enum ap_pwrst_trans - Transition states defined in PRCMU firmware : No power state transition : Power state transition from ApExecute to ApSleep : Power state transition from ApIdle to ApSleep : Power state transition from ApBoot to ApExecute : Power state transition from ApExecute to ApDeepSleep : Power state transition from ApExecute to ApIdle

Enumerator:

PRCMU_AP_NO_CHANGE
APEXECUTE_TO_APSLEEP
APIDLE_TO_APSLEEP
PRCMU_AP_SLEEP
APBOOT_TO_APEXECUTE
APEXECUTE_TO_APDEEPSLEEP
PRCMU_AP_DEEP_SLEEP
APEXECUTE_TO_APIDLE
PRCMU_AP_IDLE
PRCMU_AP_DEEP_IDLE

Definition at line 152 of file db8500-prcmu.h.

enum ap_pwrsttr_status

enum mbox_2_arm_stat - Status messages definition for mbox_arm : The apBoot to apExecute state transition has been completed : The apExecute to apDeepSleep state transition has been completed : The apExecute to apSleep state transition has been completed : The apExecute to apIdle state transition has been completed : The A9 watchdog/ SoftReset state has been completed : The A9 watchdog/SoftReset state is on going : The apBoot to apExecute state transition is on going : The apExecute to apDeepSleep state transition is on going : The apDeepSleep to apExecute state transition is on going : The apDeepSleep to apExecute state transition has been completed : The apExecute to apSleep state transition is on going : The apSleep to apExecute state transition is on going : The apSleep to apExecute state transition has been completed : The apExecute to apIdle state transition is on going : The apIdle to apExecute state transition is on going : The apIdle to apExecute state transition has been completed : Status init

Enumerator:

BOOT_TO_EXECUTEOK
DEEPSLEEPOK
SLEEPOK
IDLEOK
SOFTRESETOK
SOFTRESETGO
BOOT_TO_EXECUTE
EXECUTE_TO_DEEPSLEEP
DEEPSLEEP_TO_EXECUTE
DEEPSLEEP_TO_EXECUTEOK
EXECUTE_TO_SLEEP
SLEEP_TO_EXECUTE
SLEEP_TO_EXECUTEOK
EXECUTE_TO_IDLE
IDLE_TO_EXECUTE
IDLE_TO_EXECUTEOK
RDYTODS_RETURNTOEXE
NORDYTODS_RETURNTOEXE
EXETOSLEEP_RETURNTOEXE
EXETOIDLE_RETURNTOEXE
INIT_STATUS
INITERROR
PLLARMLOCKP_ER
PLLDDRLOCKP_ER
PLLSOCLOCKP_ER
PLLSOCK1LOCKP_ER
ARMWFI_ER
SYSCLKOK_ER
I2C_NACK_DATA_ER
BOOT_ER
I2C_STATUS_ALWAYS_1
I2C_NACK_REG_ADDR_ER
I2C_NACK_DATA0123_ER
I2C_NACK_ADDR_ER
CURAPPWRSTISNOT_BOOT
CURAPPWRSTISNOT_EXECUTE
CURAPPWRSTISNOT_SLEEPMODE
CURAPPWRSTISNOT_CORRECTFORIT10
FIFO4500WUISNOT_WUPEVENT
PLL32KLOCKP_ER
DDRDEEPSLEEPOK_ER
ROMCODEREADY_ER
WUPBEFOREDS
DDRCONFIG_ER
WUPBEFORESLEEP
WUPBEFOREIDLE

Definition at line 210 of file db8500-prcmu.h.

enum auto_enable

enum auto_enable - Auto Power enable : :

Enumerator:

AUTO_OFF
AUTO_ON

Definition at line 434 of file db8500-prcmu.h.

enum clk_arm

enum clk_arm - ARM Cortex A9 clock schemes : : : : :

Enumerator:

A9_OFF
A9_BOOT
A9_OPPT1
A9_OPPT2
A9_EXTCLK

Definition at line 64 of file db8500-prcmu.h.

enum clk_gen

enum clk_gen - GEN#0/GEN#1 clock schemes : : :

Enumerator:

GEN_OFF
GEN_BOOT
GEN_OPPT1

Definition at line 78 of file db8500-prcmu.h.

enum cs_pwrmgt

Enumerator:

PWRDNCS0
WKUPCS0
PWRDNCS1
WKUPCS1

Definition at line 402 of file db8500-prcmu.h.

enum dvfs_stat

enum dvfs_stat - DVFS status messages definition : A state transition DVFS is on going : The state transition DVFS has been completed for 100OPP : The state transition DVFS has been completed for 50OPP : The state transition DVFS has been completed for EXTCLK : The state transition DVFS has been completed for NOCHGCLK : Value init

Enumerator:

DVFS_GO
DVFS_ARM100OPPOK
DVFS_ARM50OPPOK
DVFS_ARMEXTCLKOK
DVFS_NOCHGTCLKOK
DVFS_INITSTATUS

Definition at line 271 of file db8500-prcmu.h.

enum hw_acc

Enumerator:

SVAMMDSP
SVAPIPE
SIAMMDSP
SIAPIPE
SGA
B2R2MCDE
ESRAM12
ESRAM34

Definition at line 391 of file db8500-prcmu.h.

enum hw_acc_state

enum hw_acc_state - State definition for hardware accelerator : The hardware accelerator state must remain unchanged : The hardware accelerator must be switched off : The hardware accelerator must be switched off with its internal RAM in retention : The hwa hardware accelerator hwa must be switched on

NOTE! Deprecated, to be removed when all users switched over to use the regulator API.

Enumerator:

HW_NO_CHANGE
HW_OFF
HW_OFF_RAMRET
HW_ON

Definition at line 176 of file db8500-prcmu.h.

enum mbox_to_arm_err

enum mbox_to_arm_err - Error messages definition : Init value : PLLARM has not been correctly locked in given time : PLLDDR has not been correctly locked in the given time : PLLSOC0 has not been correctly locked in the given time : PLLSOC1 has not been correctly locked in the given time : The ARM WFI has not been correctly executed in the given time : The SYSCLK is not available in the given time : Romcode has not validated the XP70 self reset in the given time : The Romcode didn.t correctly save it secure context : The ARM high speed supply value transfered through I2C has not been correctly executed in the given time : The command value of VarmHighSpeedVal transfered through I2C has not been correctly executed in the given time :The ARM low speed supply value transfered through I2C has not been correctly executed in the given time : The command value of VarmLowSpeedVal transfered through I2C has not been correctly executed in the given time : The ARM retention supply value transfered through I2C has not been correctly executed in the given time : The command value of VarmRetentionVal transfered through I2C has not been correctly executed in the given time : The APE highspeed supply value transfered through I2C has not been correctly executed in the given time : The SAFE high power supply value transfered through I2C has not been correctly executed in the given time : The MODEM sel1 supply value transfered through I2C has not been correctly executed in the given time : The MODEM sel2 supply value transfered through I2C has not been correctly executed in the given time : The command value of Varm ON/OFF transfered through I2C has not been correctly executed in the given time : The command value of Vape ON/OFF transfered through I2C has not been correctly executed in the given time : The command value of Varm retention ON/OFF transfered through I2C has not been correctly executed in the given time :Generated when Arm want to do power state transition ApBoot to ApExecute but the power current state is not Apboot : Generated when Arm want to do power state transition from ApExecute to others power state but the power current state is not ApExecute : Generated when wake up events are transmitted but the power current state is not ApDeepSleep/ApSleep/ApIdle : Generated when wake up events are transmitted but the power current state is not correct :The ArmRegu1 value transferred through I2C has not been correctly executed in the given time : The ArmRegu2 value transferred through I2C has not been correctly executed in the given time : The VApeRegu value transfered through I2C has not been correctly executed in the given time : The VSmps3Regu value transfered through I2C has not been correctly executed in the given time : The VModemRegu value transfered through I2C has not been correctly executed in the given time

Enumerator:

INIT_ERR
PLLARMLOCKP_ERR
PLLDDRLOCKP_ERR
PLLSOC0LOCKP_ERR
PLLSOC1LOCKP_ERR
ARMWFI_ERR
SYSCLKOK_ERR
BOOT_ERR
ROMCODESAVECONTEXT
VARMHIGHSPEEDVALTO_ERR
VARMHIGHSPEEDACCESS_ERR
VARMLOWSPEEDVALTO_ERR
VARMLOWSPEEDACCESS_ERR
VARMRETENTIONVALTO_ERR
VARMRETENTIONACCESS_ERR
VAPEHIGHSPEEDVALTO_ERR
VSAFEHPVALTO_ERR
VMODSEL1VALTO_ERR
VMODSEL2VALTO_ERR
VARMOFFACCESS_ERR
VAPEOFFACCESS_ERR
VARMRETACCES_ERR
CURAPPWRSTISNOTBOOT
CURAPPWRSTISNOTEXECUTE
CURAPPWRSTISNOTSLEEPMODE
CURAPPWRSTISNOTCORRECTDBG
ARMREGU1VALTO_ERR
ARMREGU2VALTO_ERR
VAPEREGUVALTO_ERR
VSMPS3REGUVALTO_ERR
VMODREGUVALTO_ERR

Definition at line 357 of file db8500-prcmu.h.

enum prcmu_auto_pm_policy

Enumerator:

PRCMU_AUTO_PM_POLICY_NO_CHANGE
PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF
PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF

Definition at line 470 of file db8500-prcmu.h.

enum prcmu_power_status

enum prcmu_power_status - results from set_power_state : Sleep went ok : DeepSleep went ok : Idle went ok : DeepIdle went ok : Pending interrupt detected : Pending interrupt detected

Enumerator:

PRCMU_SLEEP_OK
PRCMU_DEEP_SLEEP_OK
PRCMU_IDLE_OK
PRCMU_DEEPIDLE_OK
PRCMU_PRCMU2ARMPENDINGIT_ER
PRCMU_ARMPENDINGIT_ER

Definition at line 451 of file db8500-prcmu.h.

enum ret_state

enum ret_state - general purpose On/Off/Retention states

Enumerator:

OFFST
ONST
RETST

Definition at line 50 of file db8500-prcmu.h.

enum romcode_read

enum romcode_read - Romcode message written by XP70 and read by A9 : Init value when romcode field is not used : Value set when power state is going from ApExecute to ApDeepSleep : Value set when ApDeepSleep power state is reached coming from ApExecute state : Value set when power state is going from ApDeepSleep to ApExecute : Value set when ApExecute power state is reached coming from ApDeepSleep state : Value set when power state is going to ApReset : Value set when the xp70 finished executing ApReset actions and waits for romcode acknowledgment to go to self-reset

Enumerator:

INIT
FS_2_DS
END_DS
DS_TO_FS
END_FS
SWR
END_SWR

Definition at line 112 of file db8500-prcmu.h.

enum romcode_write

enum romcode_write - Romcode message written by A9 AND read by XP70 : Value set when ApDeepSleep state can be executed by XP70 : Value set when 0x0F has been successfully polled by the romcode. The xp70 will go into self-reset

Enumerator:

RDY_2_DS
RDY_2_XP70_RST

Definition at line 92 of file db8500-prcmu.h.

enum sia_mmdsp_stat

enum sia_mmdsp_stat - SIA MMDSP status messages : SIAMMDSP interrupt has happened : Status init

Enumerator:

SIA_MMDSP_GO
SIA_MMDSP_INIT

Definition at line 295 of file db8500-prcmu.h.

enum sia_sva_pwr_policy

enum sia_sva_pwr_policy - Power policy : No change : : : :

Enumerator:

NO_CHGT
DSPOFF_HWPOFF
DSPOFFRAMRET_HWPOFF
DSPCLKOFF_HWPOFF
DSPCLKOFF_HWPCLKOFF

Definition at line 420 of file db8500-prcmu.h.

enum s32 state

enum state - ON/OFF state definition : State is ON : State is OFF

Enumerator:

OFF
ON
Start
Collect
GotHeader
SkipIt
GotName
CopyFile
GotSymlink
Reset

Definition at line 41 of file db8500-prcmu.h.

enum sva_mmdsp_stat

enum sva_mmdsp_stat - SVA MMDSP status messages : SVAMMDSP interrupt has happened : Status init

Enumerator:

SVA_MMDSP_GO
SVA_MMDSP_INIT

Definition at line 285 of file db8500-prcmu.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation