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cx18-io.h
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1 /*
2  * cx18 driver PCI memory mapped IO access routines
3  *
4  * Copyright (C) 2007 Hans Verkuil <[email protected]>
5  * Copyright (C) 2008 Andy Walls <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  * 02111-1307 USA
21  */
22 
23 #ifndef CX18_IO_H
24 #define CX18_IO_H
25 
26 #include "cx18-driver.h"
27 
28 /*
29  * Readback and retry of MMIO access for reliability:
30  * The concept was suggested by Steve Toth <[email protected]>.
31  * The implmentation is the fault of Andy Walls <[email protected]>.
32  *
33  * *write* functions are implied to retry the mmio unless suffixed with _noretry
34  * *read* functions never retry the mmio (it never helps to do so)
35  */
36 
37 /* Non byteswapping memory mapped IO */
38 static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
39 {
40  return __raw_readl(addr);
41 }
42 
43 static inline
44 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
45 {
46  __raw_writel(val, addr);
47 }
48 
49 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
50 {
51  int i;
52  for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
53  cx18_raw_writel_noretry(cx, val, addr);
54  if (val == cx18_raw_readl(cx, addr))
55  break;
56  }
57 }
58 
59 /* Normal memory mapped IO */
60 static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
61 {
62  return readl(addr);
63 }
64 
65 static inline
66 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
67 {
68  writel(val, addr);
69 }
70 
71 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
72 {
73  int i;
74  for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
75  cx18_writel_noretry(cx, val, addr);
76  if (val == cx18_readl(cx, addr))
77  break;
78  }
79 }
80 
81 static inline
82 void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
83  u32 eval, u32 mask)
84 {
85  int i;
86  u32 r;
87  eval &= mask;
88  for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
89  cx18_writel_noretry(cx, val, addr);
90  r = cx18_readl(cx, addr);
91  if (r == 0xffffffff && eval != 0xffffffff)
92  continue;
93  if (eval == (r & mask))
94  break;
95  }
96 }
97 
98 static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
99 {
100  return readw(addr);
101 }
102 
103 static inline
104 void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
105 {
106  writew(val, addr);
107 }
108 
109 static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
110 {
111  int i;
112  for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
113  cx18_writew_noretry(cx, val, addr);
114  if (val == cx18_readw(cx, addr))
115  break;
116  }
117 }
118 
119 static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
120 {
121  return readb(addr);
122 }
123 
124 static inline
125 void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
126 {
127  writeb(val, addr);
128 }
129 
130 static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
131 {
132  int i;
133  for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
134  cx18_writeb_noretry(cx, val, addr);
135  if (val == cx18_readb(cx, addr))
136  break;
137  }
138 }
139 
140 static inline
141 void cx18_memcpy_fromio(struct cx18 *cx, void *to,
142  const void __iomem *from, unsigned int len)
143 {
144  memcpy_fromio(to, from, len);
145 }
146 
147 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
148 
149 
150 /* Access "register" region of CX23418 memory mapped I/O */
151 static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
152 {
153  cx18_writel_noretry(cx, val, cx->reg_mem + reg);
154 }
155 
156 static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
157 {
158  cx18_writel(cx, val, cx->reg_mem + reg);
159 }
160 
161 static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
162  u32 eval, u32 mask)
163 {
164  cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
165 }
166 
167 static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
168 {
169  return cx18_readl(cx, cx->reg_mem + reg);
170 }
171 
172 
173 /* Access "encoder memory" region of CX23418 memory mapped I/O */
174 static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
175 {
176  cx18_writel(cx, val, cx->enc_mem + addr);
177 }
178 
179 static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
180 {
181  return cx18_readl(cx, cx->enc_mem + addr);
182 }
183 
184 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
185 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
186 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
187 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
188 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val);
189 void cx18_setup_page(struct cx18 *cx, u32 addr);
190 
191 #endif /* CX18_IO_H */