Linux Kernel
3.7.1
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Macros | |
#define | SAV_ACTIVE_VIDEO_FIELD1 0x80 |
#define | EAV_ACTIVE_VIDEO_FIELD1 0x90 |
#define | SAV_ACTIVE_VIDEO_FIELD2 0xc0 |
#define | EAV_ACTIVE_VIDEO_FIELD2 0xd0 |
#define | SAV_VBLANK_FIELD1 0xa0 |
#define | EAV_VBLANK_FIELD1 0xb0 |
#define | SAV_VBLANK_FIELD2 0xe0 |
#define | EAV_VBLANK_FIELD2 0xf0 |
#define | SAV_VBI_FIELD1 0x20 |
#define | EAV_VBI_FIELD1 0x30 |
#define | SAV_VBI_FIELD2 0x60 |
#define | EAV_VBI_FIELD2 0x70 |
#define | CH_PWR_CTRL1 0x0000000e |
#define | CH_PWR_CTRL2 0x0000000f |
#define | HOST_REG1 0x000 |
#define | FLD_FORCE_CHIP_SEL 0x80 |
#define | FLD_AUTO_INC_DIS 0x20 |
#define | FLD_PREFETCH_EN 0x10 |
#define | FLD_DIGITAL_PWR_DN 0x02 |
#define | FLD_SLEEP 0x01 |
#define | HOST_REG2 0x001 |
#define | HOST_REG3 0x002 |
#define | GPIO_PIN_CTL0 0x3 |
#define | GPIO_PIN_CTL1 0x4 |
#define | GPIO_PIN_CTL2 0x5 |
#define | GPIO_PIN_CTL3 0x6 |
#define | TS1_PIN_CTL0 0x7 |
#define | TS1_PIN_CTL1 0x8 |
#define | FLD_CLK_IN_EN 0x80 |
#define | FLD_XTAL_CTRL 0x70 |
#define | FLD_BB_CLK_MODE 0x0C |
#define | FLD_REF_DIV_PLL 0x02 |
#define | FLD_REF_SEL_PLL1 0x01 |
#define | CHIP_CTRL 0x100 |
#define | FLD_CHIP_ACFG_DIS 0x00100000 |
#define | FLD_DUAL_MODE_ADC2 0x00040000 |
#define | FLD_SIF_EN 0x00020000 |
#define | FLD_SOFT_RST 0x00010000 |
#define | FLD_DEVICE_ID 0x0000ffff |
#define | AFE_CTRL 0x104 |
#define | AFE_CTRL_C2HH_SRC_CTRL 0x104 |
#define | FLD_DIF_OUT_SEL 0xc0000000 |
#define | FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000 |
#define | FLD_UV_ORDER_MODE 0x02000000 |
#define | FLD_FUNC_MODE 0x01800000 |
#define | FLD_ROT1_PHASE_CTL 0x007f8000 |
#define | FLD_AUD_IN_SEL 0x00004000 |
#define | FLD_LUMA_IN_SEL 0x00002000 |
#define | FLD_CHROMA_IN_SEL 0x00001000 |
#define | FLD_INV_SPEC_DIS 0x00000200 |
#define | FLD_VGA_SEL_CH3 0x00000100 |
#define | FLD_VGA_SEL_CH2 0x00000080 |
#define | FLD_VGA_SEL_CH1 0x00000040 |
#define | FLD_DCR_BYP_CH1 0x00000020 |
#define | FLD_DCR_BYP_CH2 0x00000010 |
#define | FLD_DCR_BYP_CH3 0x00000008 |
#define | FLD_EN_12DB_CH3 0x00000004 |
#define | FLD_EN_12DB_CH2 0x00000002 |
#define | FLD_EN_12DB_CH1 0x00000001 |
#define | DC_CTRL1 0x108 |
#define | FLD_CLAMP_LVL_CH1 0x3fff8000 |
#define | FLD_CLAMP_LVL_CH2 0x00007fff |
#define | DC_CTRL2 0x10c |
#define | FLD_CLAMP_LVL_CH3 0x00fffe00 |
#define | FLD_CLAMP_WIND_LENTH 0x000001e0 |
#define | FLD_C2HH_SAT_MIN 0x0000001e |
#define | FLD_FLT_BYP_SEL 0x00000001 |
#define | DC_CTRL3 0x110 |
#define | FLD_ERR_GAIN_CTL 0x00070000 |
#define | FLD_LPF_MIN 0x0000ffff |
#define | DC_CTRL4 0x114 |
#define | FLD_INTG_CH1 0x7fffffff |
#define | DC_CTRL5 0x118 |
#define | FLD_INTG_CH2 0x7fffffff |
#define | DC_CTRL6 0x11c |
#define | FLD_INTG_CH3 0x7fffffff |
#define | PIN_CTRL 0x120 |
#define | FLD_OEF_AGC_RF 0x00000001 |
#define | FLD_OEF_AGC_IFVGA 0x00000002 |
#define | FLD_OEF_AGC_IF 0x00000004 |
#define | FLD_REG_BO_PUD 0x80000000 |
#define | FLD_IR_IRQ_STAT 0x40000000 |
#define | FLD_AUD_IRQ_STAT 0x20000000 |
#define | FLD_VID_IRQ_STAT 0x10000000 |
#define | FLD_IRQ_N_OUT_EN 0x02000000 |
#define | FLD_IRQ_N_POLAR 0x01000000 |
#define | FLD_OE_AUX_PLL_CLK 0x00000020 |
#define | FLD_OE_I2S_BCLK 0x00000010 |
#define | FLD_OE_I2S_WCLK 0x00000008 |
#define | FLD_OE_AGC_IF 0x00000004 |
#define | FLD_OE_AGC_IFVGA 0x00000002 |
#define | FLD_OE_AGC_RF 0x00000001 |
#define | AUD_IO_CTRL 0x124 |
#define | FLD_I2S_PORT_DIR 0x00000080 |
#define | FLD_I2S_OUT_SRC 0x00000040 |
#define | FLD_AUD_CHAN3_SRC 0x00000030 |
#define | FLD_AUD_CHAN2_SRC 0x0000000c |
#define | FLD_AUD_CHAN1_SRC 0x00000003 |
#define | AUD_LOCK1 0x128 |
#define | FLD_AUD_LOCK_KI_SHIFT 0xc0000000 |
#define | FLD_AUD_LOCK_KD_SHIFT 0x30000000 |
#define | FLD_EN_AV_LOCK 0x01000000 |
#define | FLD_VID_COUNT 0x00ffffff |
#define | AUD_LOCK2 0x12c |
#define | FLD_AUD_LOCK_KI_MULT 0xf0000000 |
#define | FLD_AUD_LOCK_KD_MULT 0x0F000000 |
#define | FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 |
#define | FLD_AUD_COUNT 0x000fffff |
#define | AFE_DIAG_CTRL1 0x134 |
#define | FLD_CUV_DLY_LENGTH 0x0000ff00 |
#define | FLD_YC_DLY_LENGTH 0x000000ff |
#define | AFE_DIAG_CTRL3 0x138 |
#define | FLD_AUD_DUAL_FLAG_POL 0x02000000 |
#define | FLD_VID_DUAL_FLAG_POL 0x01000000 |
#define | FLD_COL_CLAMP_DIS_CH1 0x00400000 |
#define | FLD_COL_CLAMP_DIS_CH2 0x00200000 |
#define | FLD_COL_CLAMP_DIS_CH3 0x00100000 |
#define | TEST_CTRL1 0x144 |
#define | FLD_LBIST_EN 0x10000000 |
#define | FLD_FI_BIST_INTR_R 0x0000200 |
#define | FLD_FI_BIST_INTR_L 0x0000100 |
#define | FLD_BIST_FAIL_AUD_PLL 0x0000080 |
#define | FLD_BIST_INTR_AUD_PLL 0x0000040 |
#define | FLD_BIST_FAIL_VID_PLL 0x0000020 |
#define | FLD_BIST_INTR_VID_PLL 0x0000010 |
#define | FLD_CIR_TEST_DIS 0x00000001 |
#define | TEST_CTRL2 0x148 |
#define | FLD_TSXCLK_POL_CTL 0x80000000 |
#define | FLD_ISO_CTL_SEL 0x40000000 |
#define | FLD_ISO_CTL_EN 0x20000000 |
#define | FLD_BIST_DEBUGZ 0x10000000 |
#define | FLD_AUD_BIST_TEST_H 0x0f000000 |
#define | FLD_FLTRN_BIST_TEST_H 0x00020000 |
#define | FLD_VID_BIST_TEST_H 0x00010000 |
#define | FLD_BIST_TEST_H 0x00010000 |
#define | FLD_TAB_EN 0x00001000 |
#define | BIST_STAT 0x14c |
#define | FLD_AUD_BIST_FAIL_H 0xfff00000 |
#define | FLD_FLTRN_BIST_FAIL_H 0x00180000 |
#define | FLD_VID_BIST_FAIL_H 0x00070000 |
#define | FLD_AUD_BIST_TST_DONE 0x0000fff0 |
#define | FLD_FLTRN_BIST_TST_DONE 0x00000008 |
#define | FLD_VID_BIST_TST_DONE 0x00000007 |
#define | MODE_CTRL 0x400 |
#define | FLD_AFD_PAL60_DIS 0x20000000 |
#define | FLD_AFD_FORCE_SECAM 0x10000000 |
#define | FLD_AFD_FORCE_PALNC 0x08000000 |
#define | FLD_AFD_FORCE_PAL 0x04000000 |
#define | FLD_AFD_PALM_SEL 0x03000000 |
#define | FLD_CKILL_MODE 0x00300000 |
#define | FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ |
#define | FLD_CLR_LOCK_STAT 0x00020000 |
#define | FLD_FAST_LOCK_MD 0x00010000 |
#define | FLD_WCEN 0x00008000 |
#define | FLD_CAGCEN 0x00004000 |
#define | FLD_CKILLEN 0x00002000 |
#define | FLD_AUTO_SC_LOCK 0x00001000 |
#define | FLD_MAN_SC_FAST_LOCK 0x00000800 |
#define | FLD_INPUT_MODE 0x00000600 |
#define | FLD_AFD_ACQUIRE 0x00000100 |
#define | FLD_AFD_NTSC_SEL 0x00000080 |
#define | FLD_AFD_PAL_SEL 0x00000040 |
#define | FLD_ACFG_DIS 0x00000020 |
#define | FLD_SQ_PIXEL 0x00000010 |
#define | FLD_VID_FMT_SEL 0x0000000f |
#define | OUT_CTRL1 0x404 |
#define | FLD_POLAR 0x7f000000 |
#define | FLD_RND_MODE 0x00600000 |
#define | FLD_VIPCLAMP_EN 0x00100000 |
#define | FLD_VIPBLANK_EN 0x00080000 |
#define | FLD_VIP_OPT_AL 0x00040000 |
#define | FLD_IDID0_SOURCE 0x00020000 |
#define | FLD_DCMODE 0x00010000 |
#define | FLD_CLK_GATING 0x0000c000 |
#define | FLD_CLK_INVERT 0x00002000 |
#define | FLD_HSFMT 0x00001000 |
#define | FLD_VALIDFMT 0x00000800 |
#define | FLD_ACTFMT 0x00000400 |
#define | FLD_SWAPRAW 0x00000200 |
#define | FLD_CLAMPRAW_EN 0x00000100 |
#define | FLD_BLUE_FIELD_EN 0x00000080 |
#define | FLD_BLUE_FIELD_ACT 0x00000040 |
#define | FLD_TASKBIT_VAL 0x00000020 |
#define | FLD_ANC_DATA_EN 0x00000010 |
#define | FLD_VBIHACTRAW_EN 0x00000008 |
#define | FLD_MODE10B 0x00000004 |
#define | FLD_OUT_MODE 0x00000003 |
#define | OUT_CTRL2 0x408 |
#define | FLD_AUD_GRP 0xc0000000 |
#define | FLD_SAMPLE_RATE 0x30000000 |
#define | FLD_AUD_ANC_EN 0x08000000 |
#define | FLD_EN_C 0x04000000 |
#define | FLD_EN_B 0x02000000 |
#define | FLD_EN_A 0x01000000 |
#define | FLD_IDID1_LSB 0x000c0000 |
#define | FLD_IDID0_LSB 0x00030000 |
#define | FLD_IDID1_MSB 0x0000ff00 |
#define | FLD_IDID0_MSB 0x000000ff |
#define | GEN_STAT 0x40c |
#define | FLD_VCR_DETECT 0x00800000 |
#define | FLD_SPECIAL_PLAY_N 0x00400000 |
#define | FLD_VPRES 0x00200000 |
#define | FLD_AGC_LOCK 0x00100000 |
#define | FLD_CSC_LOCK 0x00080000 |
#define | FLD_VLOCK 0x00040000 |
#define | FLD_SRC_LOCK 0x00020000 |
#define | FLD_HLOCK 0x00010000 |
#define | FLD_VSYNC_N 0x00008000 |
#define | FLD_SRC_FIFO_UFLOW 0x00004000 |
#define | FLD_SRC_FIFO_OFLOW 0x00002000 |
#define | FLD_FIELD 0x00001000 |
#define | FLD_AFD_FMT_STAT 0x00000f00 |
#define | FLD_MV_TYPE2_PAIR 0x00000080 |
#define | FLD_MV_T3CS 0x00000040 |
#define | FLD_MV_CS 0x00000020 |
#define | FLD_MV_PSP 0x00000010 |
#define | FLD_MV_CDAT 0x00000003 |
#define | INT_STAT_MASK 0x410 |
#define | FLD_COMB_3D_FIFO_MSK 0x80000000 |
#define | FLD_WSS_DAT_AVAIL_MSK 0x40000000 |
#define | FLD_GS2_DAT_AVAIL_MSK 0x20000000 |
#define | FLD_GS1_DAT_AVAIL_MSK 0x10000000 |
#define | FLD_CC_DAT_AVAIL_MSK 0x08000000 |
#define | FLD_VPRES_CHANGE_MSK 0x04000000 |
#define | FLD_MV_CHANGE_MSK 0x02000000 |
#define | FLD_END_VBI_EVEN_MSK 0x01000000 |
#define | FLD_END_VBI_ODD_MSK 0x00800000 |
#define | FLD_FMT_CHANGE_MSK 0x00400000 |
#define | FLD_VSYNC_TRAIL_MSK 0x00200000 |
#define | FLD_HLOCK_CHANGE_MSK 0x00100000 |
#define | FLD_VLOCK_CHANGE_MSK 0x00080000 |
#define | FLD_CSC_LOCK_CHANGE_MSK 0x00040000 |
#define | FLD_SRC_FIFO_UFLOW_MSK 0x00020000 |
#define | FLD_SRC_FIFO_OFLOW_MSK 0x00010000 |
#define | FLD_COMB_3D_FIFO_STAT 0x00008000 |
#define | FLD_WSS_DAT_AVAIL_STAT 0x00004000 |
#define | FLD_GS2_DAT_AVAIL_STAT 0x00002000 |
#define | FLD_GS1_DAT_AVAIL_STAT 0x00001000 |
#define | FLD_CC_DAT_AVAIL_STAT 0x00000800 |
#define | FLD_VPRES_CHANGE_STAT 0x00000400 |
#define | FLD_MV_CHANGE_STAT 0x00000200 |
#define | FLD_END_VBI_EVEN_STAT 0x00000100 |
#define | FLD_END_VBI_ODD_STAT 0x00000080 |
#define | FLD_FMT_CHANGE_STAT 0x00000040 |
#define | FLD_VSYNC_TRAIL_STAT 0x00000020 |
#define | FLD_HLOCK_CHANGE_STAT 0x00000010 |
#define | FLD_VLOCK_CHANGE_STAT 0x00000008 |
#define | FLD_CSC_LOCK_CHANGE_STAT 0x00000004 |
#define | FLD_SRC_FIFO_UFLOW_STAT 0x00000002 |
#define | FLD_SRC_FIFO_OFLOW_STAT 0x00000001 |
#define | LUMA_CTRL 0x414 |
#define | BRIGHTNESS_CTRL_BYTE 0x414 |
#define | CONTRAST_CTRL_BYTE 0x415 |
#define | LUMA_CTRL_BYTE_3 0x416 |
#define | FLD_LUMA_CORE_SEL 0x00c00000 |
#define | FLD_RANGE 0x00300000 |
#define | FLD_PEAK_EN 0x00040000 |
#define | FLD_PEAK_SEL 0x00030000 |
#define | FLD_CNTRST 0x0000ff00 |
#define | FLD_BRITE 0x000000ff |
#define | HSCALE_CTRL 0x418 |
#define | FLD_HFILT 0x03000000 |
#define | FLD_HSCALE 0x00ffffff |
#define | VSCALE_CTRL 0x41c |
#define | FLD_LINE_AVG_DIS 0x01000000 |
#define | FLD_VS_INTRLACE 0x00080000 |
#define | FLD_VFILT 0x00070000 |
#define | FLD_VSCALE 0x00001fff |
#define | CHROMA_CTRL 0x420 |
#define | USAT_CTRL_BYTE 0x420 |
#define | VSAT_CTRL_BYTE 0x421 |
#define | HUE_CTRL_BYTE 0x422 |
#define | FLD_C_LPF_EN 0x20000000 |
#define | FLD_CHR_DELAY 0x1c000000 |
#define | FLD_C_CORE_SEL 0x03000000 |
#define | FLD_HUE 0x00ff0000 |
#define | FLD_VSAT 0x0000ff00 |
#define | FLD_USAT 0x000000ff |
#define | VBI_LINE_CTRL1 0x424 |
#define | FLD_VBI_MD_LINE4 0xff000000 |
#define | FLD_VBI_MD_LINE3 0x00ff0000 |
#define | FLD_VBI_MD_LINE2 0x0000ff00 |
#define | FLD_VBI_MD_LINE1 0x000000ff |
#define | VBI_LINE_CTRL2 0x428 |
#define | FLD_VBI_MD_LINE8 0xff000000 |
#define | FLD_VBI_MD_LINE7 0x00ff0000 |
#define | FLD_VBI_MD_LINE6 0x0000ff00 |
#define | FLD_VBI_MD_LINE5 0x000000ff |
#define | VBI_LINE_CTRL3 0x42c |
#define | FLD_VBI_MD_LINE12 0xff000000 |
#define | FLD_VBI_MD_LINE11 0x00ff0000 |
#define | FLD_VBI_MD_LINE10 0x0000ff00 |
#define | FLD_VBI_MD_LINE9 0x000000ff |
#define | VBI_LINE_CTRL4 0x430 |
#define | FLD_VBI_MD_LINE16 0xff000000 |
#define | FLD_VBI_MD_LINE15 0x00ff0000 |
#define | FLD_VBI_MD_LINE14 0x0000ff00 |
#define | FLD_VBI_MD_LINE13 0x000000ff |
#define | VBI_LINE_CTRL5 0x434 |
#define | FLD_VBI_MD_LINE17 0x000000ff |
#define | VBI_FC_CFG 0x438 |
#define | FLD_FC_ALT2 0xff000000 |
#define | FLD_FC_ALT1 0x00ff0000 |
#define | FLD_FC_ALT2_TYPE 0x0000f000 |
#define | FLD_FC_ALT1_TYPE 0x00000f00 |
#define | FLD_FC_SEARCH_MODE 0x00000001 |
#define | VBI_MISC_CFG1 0x43c |
#define | FLD_TTX_PKTADRU 0xfff00000 |
#define | FLD_TTX_PKTADRL 0x000fff00 |
#define | FLD_MOJI_PACK_DIS 0x00000020 |
#define | FLD_VPS_DEC_DIS 0x00000010 |
#define | FLD_CRI_MARG_SCALE 0x0000000c |
#define | FLD_EDGE_RESYNC_EN 0x00000002 |
#define | FLD_ADAPT_SLICE_DIS 0x00000001 |
#define | VBI_MISC_CFG2 0x440 |
#define | FLD_HAMMING_TYPE 0x0f000000 |
#define | FLD_WSS_FIFO_RST 0x00080000 |
#define | FLD_GS2_FIFO_RST 0x00040000 |
#define | FLD_GS1_FIFO_RST 0x00020000 |
#define | FLD_CC_FIFO_RST 0x00010000 |
#define | FLD_VBI3_SDID 0x00000f00 |
#define | FLD_VBI2_SDID 0x000000f0 |
#define | FLD_VBI1_SDID 0x0000000f |
#define | VBI_PAY1 0x444 |
#define | FLD_GS1_FIFO_DAT 0xFF000000 |
#define | FLD_GS1_STAT 0x00FF0000 |
#define | FLD_CC_FIFO_DAT 0x0000FF00 |
#define | FLD_CC_STAT 0x000000FF |
#define | VBI_PAY2 0x448 |
#define | FLD_WSS_FIFO_DAT 0xff000000 |
#define | FLD_WSS_STAT 0x00ff0000 |
#define | FLD_GS2_FIFO_DAT 0x0000ff00 |
#define | FLD_GS2_STAT 0x000000ff |
#define | VBI_CUST1_CFG1 0x44c |
#define | FLD_VBI1_CRIWIN 0x7f000000 |
#define | FLD_VBI1_SLICE_DIST 0x00f00000 |
#define | FLD_VBI1_BITINC 0x000fff00 |
#define | FLD_VBI1_HDELAY 0x000000ff |
#define | VBI_CUST1_CFG2 0x450 |
#define | FLD_VBI1_FC_LENGTH 0x1f000000 |
#define | FLD_VBI1_FRAME_CODE 0x00ffffff |
#define | VBI_CUST1_CFG3 0x454 |
#define | FLD_VBI1_HAM_EN 0x80000000 |
#define | FLD_VBI1_FIFO_MODE 0x70000000 |
#define | FLD_VBI1_FORMAT_TYPE 0x0f000000 |
#define | FLD_VBI1_PAYLD_LENGTH 0x00ff0000 |
#define | FLD_VBI1_CRI_LENGTH 0x0000f000 |
#define | FLD_VBI1_CRI_MARGIN 0x00000f00 |
#define | FLD_VBI1_CRI_TIME 0x000000ff |
#define | VBI_CUST2_CFG1 0x458 |
#define | FLD_VBI2_CRIWIN 0x7f000000 |
#define | FLD_VBI2_SLICE_DIST 0x00f00000 |
#define | FLD_VBI2_BITINC 0x000fff00 |
#define | FLD_VBI2_HDELAY 0x000000ff |
#define | VBI_CUST2_CFG2 0x45c |
#define | FLD_VBI2_FC_LENGTH 0x1f000000 |
#define | FLD_VBI2_FRAME_CODE 0x00ffffff |
#define | VBI_CUST2_CFG3 0x460 |
#define | FLD_VBI2_HAM_EN 0x80000000 |
#define | FLD_VBI2_FIFO_MODE 0x70000000 |
#define | FLD_VBI2_FORMAT_TYPE 0x0f000000 |
#define | FLD_VBI2_PAYLD_LENGTH 0x00ff0000 |
#define | FLD_VBI2_CRI_LENGTH 0x0000f000 |
#define | FLD_VBI2_CRI_MARGIN 0x00000f00 |
#define | FLD_VBI2_CRI_TIME 0x000000ff |
#define | VBI_CUST3_CFG1 0x464 |
#define | FLD_VBI3_CRIWIN 0x7f000000 |
#define | FLD_VBI3_SLICE_DIST 0x00f00000 |
#define | FLD_VBI3_BITINC 0x000fff00 |
#define | FLD_VBI3_HDELAY 0x000000ff |
#define | VBI_CUST3_CFG2 0x468 |
#define | FLD_VBI3_FC_LENGTH 0x1f000000 |
#define | FLD_VBI3_FRAME_CODE 0x00ffffff |
#define | VBI_CUST3_CFG3 0x46c |
#define | FLD_VBI3_HAM_EN 0x80000000 |
#define | FLD_VBI3_FIFO_MODE 0x70000000 |
#define | FLD_VBI3_FORMAT_TYPE 0x0f000000 |
#define | FLD_VBI3_PAYLD_LENGTH 0x00ff0000 |
#define | FLD_VBI3_CRI_LENGTH 0x0000f000 |
#define | FLD_VBI3_CRI_MARGIN 0x00000f00 |
#define | FLD_VBI3_CRI_TIME 0x000000ff |
#define | HORIZ_TIM_CTRL 0x470 |
#define | FLD_BGDEL_CNT 0xff000000 |
#define | FLD_HACTIVE_CNT 0x003ff000 |
#define | FLD_HBLANK_CNT 0x000003ff |
#define | VERT_TIM_CTRL 0x474 |
#define | FLD_V656BLANK_CNT 0xff000000 |
#define | FLD_VACTIVE_CNT 0x003ff000 |
#define | FLD_VBLANK_CNT 0x000003ff |
#define | SRC_COMB_CFG 0x478 |
#define | FLD_CCOMB_2LN_CHECK 0x80000000 |
#define | FLD_CCOMB_3LN_EN 0x40000000 |
#define | FLD_CCOMB_2LN_EN 0x20000000 |
#define | FLD_CCOMB_3D_EN 0x10000000 |
#define | FLD_LCOMB_3LN_EN 0x04000000 |
#define | FLD_LCOMB_2LN_EN 0x02000000 |
#define | FLD_LCOMB_3D_EN 0x01000000 |
#define | FLD_LUMA_LPF_SEL 0x00c00000 |
#define | FLD_UV_LPF_SEL 0x00300000 |
#define | FLD_BLEND_SLOPE 0x000f0000 |
#define | FLD_CCOMB_REDUCE_EN 0x00008000 |
#define | FLD_SRC_DECIM_RATIO 0x000003ff |
#define | CHROMA_VBIOFF_CFG 0x47c |
#define | FLD_VBI_VOFFSET 0x1f000000 |
#define | FLD_SC_STEP 0x000fffff |
#define | FIELD_COUNT 0x480 |
#define | FLD_FIELD_COUNT_FLD 0x000003ff |
#define | MISC_TIM_CTRL 0x484 |
#define | FLD_DEBOUNCE_COUNT 0xc0000000 |
#define | FLD_VT_LINE_CNT_HYST 0x30000000 |
#define | FLD_AFD_STAT 0x07ff0000 |
#define | FLD_VPRES_VERT_EN 0x00008000 |
#define | FLD_HR32 0x00000800 |
#define | FLD_TDALGN 0x00000400 |
#define | FLD_TDFIELD 0x00000200 |
#define | FLD_TEMPDEC 0x0000003f |
#define | DFE_CTRL1 0x488 |
#define | FLD_CLAMP_AUTO_EN 0x80000000 |
#define | FLD_AGC_AUTO_EN 0x40000000 |
#define | FLD_VGA_CRUSH_EN 0x20000000 |
#define | FLD_VGA_AUTO_EN 0x10000000 |
#define | FLD_VBI_GATE_EN 0x08000000 |
#define | FLD_CLAMP_LEVEL 0x07000000 |
#define | FLD_CLAMP_SKIP_CNT 0x00300000 |
#define | FLD_AGC_GAIN 0x000fff00 |
#define | FLD_VGA_GAIN 0x0000003f |
#define | DFE_CTRL2 0x48c |
#define | FLD_VGA_ACQUIRE_RANGE 0x00ff0000 |
#define | FLD_VGA_TRACK_RANGE 0x0000ff00 |
#define | FLD_VGA_SYNC 0x000000ff |
#define | DFE_CTRL3 0x490 |
#define | FLD_BP_PERCENT 0xff000000 |
#define | FLD_DFT_THRESHOLD 0x00ff0000 |
#define | FLD_SYNC_WIDTH_SEL 0x00000600 |
#define | FLD_BP_LOOP_GAIN 0x00000300 |
#define | FLD_SYNC_LOOP_GAIN 0x000000c0 |
#define | FLD_AGC_LOOP_GAIN 0x0000000c |
#define | FLD_DCC_LOOP_GAIN 0x00000003 |
#define | PLL_CTRL 0x494 |
#define | FLD_PLL_KD 0xff000000 |
#define | FLD_PLL_KI 0x00ff0000 |
#define | FLD_PLL_MAX_OFFSET 0x0000ffff |
#define | HTL_CTRL 0x498 |
#define | FLD_AUTO_LOCK_SPD 0x00080000 |
#define | FLD_MAN_FAST_LOCK 0x00040000 |
#define | FLD_HTL_15K_EN 0x00020000 |
#define | FLD_HTL_500K_EN 0x00010000 |
#define | FLD_HTL_KD 0x0000ff00 |
#define | FLD_HTL_KI 0x000000ff |
#define | COMB_CTRL 0x49c |
#define | FLD_COMB_PHASE_LIMIT 0xff000000 |
#define | FLD_CCOMB_ERR_LIMIT 0x00ff0000 |
#define | FLD_LUMA_THRESHOLD 0x0000ff00 |
#define | FLD_LCOMB_ERR_LIMIT 0x000000ff |
#define | CRUSH_CTRL 0x4a0 |
#define | FLD_WTW_EN 0x00400000 |
#define | FLD_CRUSH_FREQ 0x00200000 |
#define | FLD_MAJ_SEL_EN 0x00100000 |
#define | FLD_MAJ_SEL 0x000c0000 |
#define | FLD_SYNC_TIP_REDUCE 0x00007e00 |
#define | FLD_SYNC_TIP_INC 0x0000003f |
#define | SOFT_RST_CTRL 0x4a4 |
#define | FLD_VD_SOFT_RST 0x00008000 |
#define | FLD_REG_RST_MSK 0x00000800 |
#define | FLD_VOF_RST_MSK 0x00000400 |
#define | FLD_MVDET_RST_MSK 0x00000200 |
#define | FLD_VBI_RST_MSK 0x00000100 |
#define | FLD_SCALE_RST_MSK 0x00000080 |
#define | FLD_CHROMA_RST_MSK 0x00000040 |
#define | FLD_LUMA_RST_MSK 0x00000020 |
#define | FLD_VTG_RST_MSK 0x00000010 |
#define | FLD_YCSEP_RST_MSK 0x00000008 |
#define | FLD_SRC_RST_MSK 0x00000004 |
#define | FLD_DFE_RST_MSK 0x00000002 |
#define | MV_DT_CTRL1 0x4a8 |
#define | FLD_PSP_STOP_LINE 0x1f000000 |
#define | FLD_PSP_STRT_LINE 0x001f0000 |
#define | FLD_PSP_LLIMW 0x00007f00 |
#define | FLD_PSP_ULIMW 0x0000007f |
#define | MV_DT_CTRL2 0x4aC |
#define | FLD_CS_STOPWIN 0xff000000 |
#define | FLD_CS_STRTWIN 0x00ff0000 |
#define | FLD_CS_WIDTH 0x0000ff00 |
#define | FLD_PSP_SPEC_VAL 0x000000ff |
#define | MV_DT_CTRL3 0x4B0 |
#define | FLD_AUTO_RATE_DIS 0x80000000 |
#define | FLD_HLOCK_DIS 0x40000000 |
#define | FLD_SEL_FIELD_CNT 0x20000000 |
#define | FLD_CS_TYPE2_SEL 0x10000000 |
#define | FLD_CS_LINE_THRSH_SEL 0x08000000 |
#define | FLD_CS_ATHRESH_SEL 0x04000000 |
#define | FLD_PSP_SPEC_SEL 0x02000000 |
#define | FLD_PSP_LINES_SEL 0x01000000 |
#define | FLD_FIELD_CNT 0x00f00000 |
#define | FLD_CS_TYPE2_CNT 0x000fc000 |
#define | FLD_CS_LINE_CNT 0x00003f00 |
#define | FLD_CS_ATHRESH_LEV 0x000000ff |
#define | CHIP_VERSION 0x4b4 |
#define | VERSION 0x4b4 |
#define | FLD_REV_ID 0x000000ff |
#define | MISC_DIAG_CTRL 0x4b8 |
#define | FLD_SC_CONVERGE_THRESH 0x00ff0000 |
#define | FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00 |
#define | FLD_LCOMB_ERR_LIMIT_3D 0x000000ff |
#define | VBI_PASS_CTRL 0x4bc |
#define | FLD_VBI_PASS_MD 0x00200000 |
#define | FLD_VBI_SETUP_DIS 0x00100000 |
#define | FLD_PASS_LINE_CTRL 0x000fffff |
#define | VCR_DET_CTRL 0x4c0 |
#define | FLD_EN_FIELD_PHASE_DET 0x80000000 |
#define | FLD_EN_HEAD_SW_DET 0x40000000 |
#define | FLD_FIELD_PHASE_LENGTH 0x01ff0000 |
#define | FLD_FIELD_PHASE_DELAY 0x0000ff00 |
#define | FLD_FIELD_PHASE_LIMIT 0x000000f0 |
#define | FLD_HEAD_SW_DET_LIMIT 0x0000000f |
#define | DL_CTL 0x800 |
#define | DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ |
#define | DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ |
#define | DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ |
#define | DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ |
#define | FLD_START_8051 0x10000000 |
#define | FLD_DL_ENABLE 0x08000000 |
#define | FLD_DL_AUTO_INC 0x04000000 |
#define | FLD_DL_MAP 0x03000000 |
#define | STD_DET_STATUS 0x804 |
#define | FLD_SPARE_STATUS1 0xff000000 |
#define | FLD_SPARE_STATUS0 0x00ff0000 |
#define | FLD_MOD_DET_STATUS1 0x0000ff00 |
#define | FLD_MOD_DET_STATUS0 0x000000ff |
#define | AUD_BUILD_NUM 0x806 |
#define | AUD_VER_NUM 0x807 |
#define | STD_DET_CTL 0x808 |
#define | STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ |
#define | STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ |
#define | FLD_SPARE_CTL0 0xff000000 |
#define | FLD_DIS_DBX 0x00800000 |
#define | FLD_DIS_BTSC 0x00400000 |
#define | FLD_DIS_NICAM_A2 0x00200000 |
#define | FLD_VIDEO_PRESENT 0x00100000 |
#define | FLD_DW8051_VIDEO_FORMAT 0x000f0000 |
#define | FLD_PREF_DEC_MODE 0x0000ff00 |
#define | FLD_AUD_CONFIG 0x000000ff |
#define | DW8051_INT 0x80c |
#define | FLD_VIDEO_PRESENT_CHANGE 0x80000000 |
#define | FLD_VIDEO_CHANGE 0x40000000 |
#define | FLD_RDS_READY 0x20000000 |
#define | FLD_AC97_INT 0x10000000 |
#define | FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000 |
#define | FLD_NICAM_LOCK 0x04000000 |
#define | FLD_NICAM_UNLOCK 0x02000000 |
#define | FLD_DFT4_TH_CMP 0x01000000 |
#define | FLD_LOCK_IND_INT 0x00200000 |
#define | FLD_DFT3_TH_CMP 0x00100000 |
#define | FLD_DFT2_TH_CMP 0x00080000 |
#define | FLD_DFT1_TH_CMP 0x00040000 |
#define | FLD_FM2_DFT_TH_CMP 0x00020000 |
#define | FLD_FM1_DFT_TH_CMP 0x00010000 |
#define | FLD_VIDEO_PRESENT_EN 0x00008000 |
#define | FLD_VIDEO_CHANGE_EN 0x00004000 |
#define | FLD_RDS_READY_EN 0x00002000 |
#define | FLD_AC97_INT_EN 0x00001000 |
#define | FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800 |
#define | FLD_NICAM_LOCK_EN 0x00000400 |
#define | FLD_NICAM_UNLOCK_EN 0x00000200 |
#define | FLD_DFT4_TH_CMP_EN 0x00000100 |
#define | FLD_DW8051_INT6_CTL1 0x00000040 |
#define | FLD_DW8051_INT5_CTL1 0x00000020 |
#define | FLD_DW8051_INT4_CTL1 0x00000010 |
#define | FLD_DW8051_INT3_CTL1 0x00000008 |
#define | FLD_DW8051_INT2_CTL1 0x00000004 |
#define | FLD_DW8051_INT1_CTL1 0x00000002 |
#define | FLD_DW8051_INT0_CTL1 0x00000001 |
#define | GENERAL_CTL 0x810 |
#define | FLD_RDS_INT 0x80000000 |
#define | FLD_NBER_INT 0x40000000 |
#define | FLD_NLL_INT 0x20000000 |
#define | FLD_IFL_INT 0x10000000 |
#define | FLD_FDL_INT 0x08000000 |
#define | FLD_AFC_INT 0x04000000 |
#define | FLD_AMC_INT 0x02000000 |
#define | FLD_AC97_INT_CTL 0x01000000 |
#define | FLD_RDS_INT_DIS 0x00800000 |
#define | FLD_NBER_INT_DIS 0x00400000 |
#define | FLD_NLL_INT_DIS 0x00200000 |
#define | FLD_IFL_INT_DIS 0x00100000 |
#define | FLD_FDL_INT_DIS 0x00080000 |
#define | FLD_FC_INT_DIS 0x00040000 |
#define | FLD_AMC_INT_DIS 0x00020000 |
#define | FLD_AC97_INT_DIS 0x00010000 |
#define | FLD_REV_NUM 0x0000ff00 |
#define | FLD_DBX_SOFT_RESET_REG 0x00000010 |
#define | FLD_AD_SOFT_RESET_REG 0x00000008 |
#define | FLD_SRC_SOFT_RESET_REG 0x00000004 |
#define | FLD_CDMOD_SOFT_RESET 0x00000002 |
#define | FLD_8051_SOFT_RESET 0x00000001 |
#define | AAGC_CTL 0x814 |
#define | FLD_AFE_12DB_EN 0x80000000 |
#define | FLD_AAGC_DEFAULT_EN 0x40000000 |
#define | FLD_AAGC_DEFAULT 0x3f000000 |
#define | FLD_AAGC_GAIN 0x00600000 |
#define | FLD_AAGC_TH 0x001f0000 |
#define | FLD_AAGC_HYST2 0x00003f00 |
#define | FLD_AAGC_HYST1 0x0000003f |
#define | IF_SRC_CTL 0x818 |
#define | FLD_DBX_BYPASS 0x80000000 |
#define | FLD_IF_SRC_MODE 0x01000000 |
#define | FLD_IF_SRC_PHASE_INC 0x0001ffff |
#define | ANALOG_DEMOD_CTL 0x81c |
#define | FLD_ROT1_PHACC_PROG 0xffff0000 |
#define | FLD_FM1_DELAY_FIX 0x00007000 |
#define | FLD_PDF4_SHIFT 0x00000c00 |
#define | FLD_PDF3_SHIFT 0x00000300 |
#define | FLD_PDF2_SHIFT 0x000000c0 |
#define | FLD_PDF1_SHIFT 0x00000030 |
#define | FLD_FMBYPASS_MODE2 0x00000008 |
#define | FLD_FMBYPASS_MODE1 0x00000004 |
#define | FLD_NICAM_MODE 0x00000002 |
#define | FLD_BTSC_FMRADIO_MODE 0x00000001 |
#define | ROT_FREQ_CTL 0x820 |
#define | FLD_ROT3_PHACC_PROG 0xffff0000 |
#define | FLD_ROT2_PHACC_PROG 0x0000ffff |
#define | FM_CTL 0x824 |
#define | FLD_FM2_DC_FB_SHIFT 0xf0000000 |
#define | FLD_FM2_DC_INT_SHIFT 0x0f000000 |
#define | FLD_FM2_AFC_RESET 0x00800000 |
#define | FLD_FM2_DC_PASS_IN 0x00400000 |
#define | FLD_FM2_DAGC_SHIFT 0x00380000 |
#define | FLD_FM2_CORDIC_SHIFT 0x00070000 |
#define | FLD_FM1_DC_FB_SHIFT 0x0000f000 |
#define | FLD_FM1_DC_INT_SHIFT 0x00000f00 |
#define | FLD_FM1_AFC_RESET 0x00000080 |
#define | FLD_FM1_DC_PASS_IN 0x00000040 |
#define | FLD_FM1_DAGC_SHIFT 0x00000038 |
#define | FLD_FM1_CORDIC_SHIFT 0x00000007 |
#define | LPF_PDF_CTL 0x828 |
#define | FLD_LPF32_SHIFT1 0x30000000 |
#define | FLD_LPF32_SHIFT2 0x0c000000 |
#define | FLD_LPF160_SHIFTA 0x03000000 |
#define | FLD_LPF160_SHIFTB 0x00c00000 |
#define | FLD_LPF160_SHIFTC 0x00300000 |
#define | FLD_LPF32_COEF_SEL2 0x000c0000 |
#define | FLD_LPF32_COEF_SEL1 0x00030000 |
#define | FLD_LPF160_COEF_SELC 0x0000c000 |
#define | FLD_LPF160_COEF_SELB 0x00003000 |
#define | FLD_LPF160_COEF_SELA 0x00000c00 |
#define | FLD_LPF160_IN_EN_REG 0x00000300 |
#define | FLD_PDF4_PDF_SEL 0x000000c0 |
#define | FLD_PDF3_PDF_SEL 0x00000030 |
#define | FLD_PDF2_PDF_SEL 0x0000000c |
#define | FLD_PDF1_PDF_SEL 0x00000003 |
#define | DFT1_CTL1 0x82c |
#define | FLD_DFT1_DWELL 0xffff0000 |
#define | FLD_DFT1_FREQ 0x0000ffff |
#define | DFT1_CTL2 0x830 |
#define | FLD_DFT1_THRESHOLD 0xffffff00 |
#define | FLD_DFT1_CMP_CTL 0x00000080 |
#define | FLD_DFT1_AVG 0x00000070 |
#define | FLD_DFT1_START 0x00000001 |
#define | DFT1_STATUS 0x834 |
#define | FLD_DFT1_DONE 0x80000000 |
#define | FLD_DFT1_TH_CMP_STAT 0x40000000 |
#define | FLD_DFT1_RESULT 0x3fffffff |
#define | DFT2_CTL1 0x838 |
#define | FLD_DFT2_DWELL 0xffff0000 |
#define | FLD_DFT2_FREQ 0x0000ffff |
#define | DFT2_CTL2 0x83C |
#define | FLD_DFT2_THRESHOLD 0xffffff00 |
#define | FLD_DFT2_CMP_CTL 0x00000080 |
#define | FLD_DFT2_AVG 0x00000070 |
#define | FLD_DFT2_START 0x00000001 |
#define | DFT2_STATUS 0x840 |
#define | FLD_DFT2_DONE 0x80000000 |
#define | FLD_DFT2_TH_CMP_STAT 0x40000000 |
#define | FLD_DFT2_RESULT 0x3fffffff |
#define | DFT3_CTL1 0x844 |
#define | FLD_DFT3_DWELL 0xffff0000 |
#define | FLD_DFT3_FREQ 0x0000ffff |
#define | DFT3_CTL2 0x848 |
#define | FLD_DFT3_THRESHOLD 0xffffff00 |
#define | FLD_DFT3_CMP_CTL 0x00000080 |
#define | FLD_DFT3_AVG 0x00000070 |
#define | FLD_DFT3_START 0x00000001 |
#define | DFT3_STATUS 0x84c |
#define | FLD_DFT3_DONE 0x80000000 |
#define | FLD_DFT3_TH_CMP_STAT 0x40000000 |
#define | FLD_DFT3_RESULT 0x3fffffff |
#define | DFT4_CTL1 0x850 |
#define | FLD_DFT4_DWELL 0xffff0000 |
#define | FLD_DFT4_FREQ 0x0000ffff |
#define | DFT4_CTL2 0x854 |
#define | FLD_DFT4_THRESHOLD 0xffffff00 |
#define | FLD_DFT4_CMP_CTL 0x00000080 |
#define | FLD_DFT4_AVG 0x00000070 |
#define | FLD_DFT4_START 0x00000001 |
#define | DFT4_STATUS 0x858 |
#define | FLD_DFT4_DONE 0x80000000 |
#define | FLD_DFT4_TH_CMP_STAT 0x40000000 |
#define | FLD_DFT4_RESULT 0x3fffffff |
#define | AM_MTS_DET 0x85c |
#define | FLD_AM_MTS_MODE 0x80000000 |
#define | FLD_AM_SUB 0x02000000 |
#define | FLD_AM_GAIN_EN 0x01000000 |
#define | FLD_AMMTS_GAIN_SCALE 0x0000e000 |
#define | FLD_MTS_PDF_SHIFT 0x00001800 |
#define | FLD_AM_REG_GAIN 0x00000700 |
#define | FLD_AGC_REF 0x000000ff |
#define | ANALOG_MUX_CTL 0x860 |
#define | FLD_MUX21_SEL 0x10000000 |
#define | FLD_MUX20_SEL 0x08000000 |
#define | FLD_MUX19_SEL 0x04000000 |
#define | FLD_MUX18_SEL 0x02000000 |
#define | FLD_MUX17_SEL 0x01000000 |
#define | FLD_MUX16_SEL 0x00800000 |
#define | FLD_MUX15_SEL 0x00400000 |
#define | FLD_MUX14_SEL 0x00300000 |
#define | FLD_MUX13_SEL 0x000C0000 |
#define | FLD_MUX12_SEL 0x00020000 |
#define | FLD_MUX11_SEL 0x00018000 |
#define | FLD_MUX10_SEL 0x00004000 |
#define | FLD_MUX9_SEL 0x00002000 |
#define | FLD_MUX8_SEL 0x00001000 |
#define | FLD_MUX7_SEL 0x00000800 |
#define | FLD_MUX6_SEL 0x00000600 |
#define | FLD_MUX5_SEL 0x00000100 |
#define | FLD_MUX4_SEL 0x000000c0 |
#define | FLD_MUX3_SEL 0x00000030 |
#define | FLD_MUX2_SEL 0x0000000c |
#define | FLD_MUX1_SEL 0x00000003 |
#define | DPLL_CTRL1 0x864 |
#define | DIG_PLL_CTL1 0x864 |
#define | FLD_PLL_STATUS 0x07000000 |
#define | FLD_BANDWIDTH_SELECT 0x00030000 |
#define | FLD_PLL_SHIFT_REG 0x00007000 |
#define | FLD_PHASE_SHIFT 0x000007ff |
#define | DPLL_CTRL2 0x868 |
#define | DIG_PLL_CTL2 0x868 |
#define | FLD_PLL_UNLOCK_THR 0xff000000 |
#define | FLD_PLL_LOCK_THR 0x00ff0000 |
#define | FLD_AM_PDF_SEL2 0x000000c0 |
#define | FLD_AM_PDF_SEL1 0x00000030 |
#define | FLD_DPLL_FSM_CTRL 0x0000000c |
#define | FLD_PLL_PILOT_DET 0x00000001 |
#define | DPLL_CTRL3 0x86c |
#define | DIG_PLL_CTL3 0x86c |
#define | FLD_DISABLE_LOOP 0x01000000 |
#define | FLD_A1_DS1_SEL 0x000c0000 |
#define | FLD_A1_DS2_SEL 0x00030000 |
#define | FLD_A1_KI 0x0000ff00 |
#define | FLD_A1_KD 0x000000ff |
#define | DPLL_CTRL4 0x870 |
#define | DIG_PLL_CTL4 0x870 |
#define | FLD_A2_DS1_SEL 0x000c0000 |
#define | FLD_A2_DS2_SEL 0x00030000 |
#define | FLD_A2_KI 0x0000ff00 |
#define | FLD_A2_KD 0x000000ff |
#define | DPLL_CTRL5 0x874 |
#define | DIG_PLL_CTL5 0x874 |
#define | FLD_TRK_DS1_SEL 0x000c0000 |
#define | FLD_TRK_DS2_SEL 0x00030000 |
#define | FLD_TRK_KI 0x0000ff00 |
#define | FLD_TRK_KD 0x000000ff |
#define | DEEMPH_GAIN_CTL 0x878 |
#define | FLD_DEEMPH2_GAIN 0xFFFF0000 |
#define | FLD_DEEMPH1_GAIN 0x0000FFFF |
#define | DEEMPH_COEFF1 0x87c |
#define | DEEMPH_COEF1 0x87c |
#define | FLD_DEEMPH_B0 0xffff0000 |
#define | FLD_DEEMPH_A0 0x0000ffff |
#define | DEEMPH_COEFF2 0x880 |
#define | DEEMPH_COEF2 0x880 |
#define | FLD_DEEMPH_B1 0xFFFF0000 |
#define | FLD_DEEMPH_A1 0x0000FFFF |
#define | DBX1_CTL1 0x884 |
#define | FLD_DBX1_WBE_GAIN 0xffff0000 |
#define | FLD_DBX1_IN_GAIN 0x0000ffff |
#define | DBX1_CTL2 0x888 |
#define | FLD_DBX1_SE_BYPASS 0xffff0000 |
#define | FLD_DBX1_SE_GAIN 0x0000ffff |
#define | DBX1_RMS_SE 0x88C |
#define | FLD_DBX1_RMS_WBE 0xffff0000 |
#define | FLD_DBX1_RMS_SE_FLD 0x0000ffff |
#define | DBX2_CTL1 0x890 |
#define | FLD_DBX2_WBE_GAIN 0xffff0000 |
#define | FLD_DBX2_IN_GAIN 0x0000ffff |
#define | DBX2_CTL2 0x894 |
#define | FLD_DBX2_SE_BYPASS 0xffff0000 |
#define | FLD_DBX2_SE_GAIN 0x0000ffff |
#define | DBX2_RMS_SE 0x898 |
#define | FLD_DBX2_RMS_WBE 0xffff0000 |
#define | FLD_DBX2_RMS_SE_FLD 0x0000ffff |
#define | AM_FM_DIFF 0x89c |
#define | FLD_FM_DIFF_OUT 0x7fff0000 |
#define | FLD_AM_DIFF_OUT 0x00007fff |
#define | NICAM_FAW 0x8a0 |
#define | FLD_FAWDETWINEND 0xFc000000 |
#define | FLD_FAWDETWINSTR 0x03ff0000 |
#define | FLD_FAWDETTHRSHLD3 0x00000f00 |
#define | FLD_FAWDETTHRSHLD2 0x000000f0 |
#define | FLD_FAWDETTHRSHLD1 0x0000000f |
#define | DEEMPH_GAIN 0x8a4 |
#define | NICAM_DEEMPHGAIN 0x8a4 |
#define | FLD_DEEMPHGAIN 0x0003ffff |
#define | DEEMPH_NUMER1 0x8a8 |
#define | NICAM_DEEMPHNUMER1 0x8a8 |
#define | FLD_DEEMPHNUMER1 0x0003ffff |
#define | DEEMPH_NUMER2 0x8ac |
#define | NICAM_DEEMPHNUMER2 0x8ac |
#define | FLD_DEEMPHNUMER2 0x0003ffff |
#define | DEEMPH_DENOM1 0x8b0 |
#define | NICAM_DEEMPHDENOM1 0x8b0 |
#define | FLD_DEEMPHDENOM1 0x0003ffff |
#define | DEEMPH_DENOM2 0x8b4 |
#define | NICAM_DEEMPHDENOM2 0x8b4 |
#define | FLD_DEEMPHDENOM2 0x0003ffff |
#define | NICAM_ERRLOG_CTL1 0x8B8 |
#define | FLD_ERRINTRPTTHSHLD1 0x0fff0000 |
#define | FLD_ERRLOGPERIOD 0x00000fff |
#define | NICAM_ERRLOG_CTL2 0x8bc |
#define | FLD_ERRINTRPTTHSHLD3 0x0fff0000 |
#define | FLD_ERRINTRPTTHSHLD2 0x00000fff |
#define | NICAM_ERRLOG_STS1 0x8c0 |
#define | FLD_ERRLOG2 0x0fff0000 |
#define | FLD_ERRLOG1 0x00000fff |
#define | NICAM_ERRLOG_STS2 0x8c4 |
#define | FLD_ERRLOG3 0x00000fff |
#define | NICAM_STATUS 0x8c8 |
#define | FLD_NICAM_CIB 0x000c0000 |
#define | FLD_NICAM_LOCK_STAT 0x00020000 |
#define | FLD_NICAM_MUTE 0x00010000 |
#define | FLD_NICAMADDIT_DATA 0x0000ffe0 |
#define | FLD_NICAMCNTRL 0x0000001f |
#define | DEMATRIX_CTL 0x8cc |
#define | FLD_AC97_IN_SHIFT 0xf0000000 |
#define | FLD_I2S_IN_SHIFT 0x0f000000 |
#define | FLD_DEMATRIX_SEL_CTL 0x00ff0000 |
#define | FLD_DMTRX_BYPASS 0x00000400 |
#define | FLD_DEMATRIX_MODE 0x00000300 |
#define | FLD_PH_DBX_SEL 0x00000020 |
#define | FLD_PH_CH_SEL 0x00000010 |
#define | FLD_PHASE_FIX 0x0000000f |
#define | PATH1_CTL1 0x8d0 |
#define | FLD_PATH1_MUTE_CTL 0x1f000000 |
#define | FLD_PATH1_AVC_CG 0x00300000 |
#define | FLD_PATH1_AVC_RT 0x000f0000 |
#define | FLD_PATH1_AVC_AT 0x0000f000 |
#define | FLD_PATH1_AVC_STEREO 0x00000800 |
#define | FLD_PATH1_AVC_CR 0x00000700 |
#define | FLD_PATH1_AVC_RMS_CON 0x000000f0 |
#define | FLD_PATH1_SEL_CTL 0x0000000f |
#define | PATH1_VOL_CTL 0x8d4 |
#define | FLD_PATH1_AVC_THRESHOLD 0x7fff0000 |
#define | FLD_PATH1_BAL_LEFT 0x00008000 |
#define | FLD_PATH1_BAL_LEVEL 0x00007f00 |
#define | FLD_PATH1_VOLUME 0x000000ff |
#define | PATH1_EQ_CTL 0x8d8 |
#define | FLD_PATH1_EQ_TREBLE_VOL 0x3f000000 |
#define | FLD_PATH1_EQ_MID_VOL 0x003f0000 |
#define | FLD_PATH1_EQ_BASS_VOL 0x00003f00 |
#define | FLD_PATH1_EQ_BAND_SEL 0x00000001 |
#define | PATH1_SC_CTL 0x8dc |
#define | FLD_PATH1_SC_THRESHOLD 0x7fff0000 |
#define | FLD_PATH1_SC_RT 0x0000f000 |
#define | FLD_PATH1_SC_AT 0x00000f00 |
#define | FLD_PATH1_SC_STEREO 0x00000080 |
#define | FLD_PATH1_SC_CR 0x00000070 |
#define | FLD_PATH1_SC_RMS_CON 0x0000000f |
#define | PATH2_CTL1 0x8e0 |
#define | FLD_PATH2_MUTE_CTL 0x03000000 |
#define | FLD_PATH2_AVC_CG 0x00300000 |
#define | FLD_PATH2_AVC_RT 0x000f0000 |
#define | FLD_PATH2_AVC_AT 0x0000f000 |
#define | FLD_PATH2_AVC_STEREO 0x00000800 |
#define | FLD_PATH2_AVC_CR 0x00000700 |
#define | FLD_PATH2_AVC_RMS_CON 0x000000f0 |
#define | FLD_PATH2_SEL_CTL 0x0000000f |
#define | PATH2_VOL_CTL 0x8e4 |
#define | FLD_PATH2_AVC_THRESHOLD 0xffff0000 |
#define | FLD_PATH2_BAL_LEFT 0x00008000 |
#define | FLD_PATH2_BAL_LEVEL 0x00007f00 |
#define | FLD_PATH2_VOLUME 0x000000ff |
#define | PATH2_EQ_CTL 0x8e8 |
#define | FLD_PATH2_EQ_TREBLE_VOL 0x3f000000 |
#define | FLD_PATH2_EQ_MID_VOL 0x003f0000 |
#define | FLD_PATH2_EQ_BASS_VOL 0x00003f00 |
#define | FLD_PATH2_EQ_BAND_SEL 0x00000001 |
#define | PATH2_SC_CTL 0x8eC |
#define | FLD_PATH2_SC_THRESHOLD 0xffff0000 |
#define | FLD_PATH2_SC_RT 0x0000f000 |
#define | FLD_PATH2_SC_AT 0x00000f00 |
#define | FLD_PATH2_SC_STEREO 0x00000080 |
#define | FLD_PATH2_SC_CR 0x00000070 |
#define | FLD_PATH2_SC_RMS_CON 0x0000000f |
#define | SRC_CTL 0x8f0 |
#define | FLD_SRC_STATUS 0xffffff00 |
#define | FLD_FIFO_LF_EN 0x000000fc |
#define | FLD_BYPASS_LI 0x00000002 |
#define | FLD_BYPASS_PF 0x00000001 |
#define | SRC_LF_COEF 0x8f4 |
#define | FLD_LOOP_FILTER_COEF2 0xffff0000 |
#define | FLD_LOOP_FILTER_COEF1 0x0000ffff |
#define | SRC1_CTL 0x8f8 |
#define | FLD_SRC1_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC1_PHASE_INC 0x0003ffff |
#define | SRC2_CTL 0x8fc |
#define | FLD_SRC2_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC2_PHASE_INC 0x0003ffff |
#define | SRC3_CTL 0x900 |
#define | FLD_SRC3_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC3_PHASE_INC 0x0003ffff |
#define | SRC4_CTL 0x904 |
#define | FLD_SRC4_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC4_PHASE_INC 0x0003ffff |
#define | SRC5_CTL 0x908 |
#define | FLD_SRC5_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC5_PHASE_INC 0x0003ffff |
#define | SRC6_CTL 0x90c |
#define | FLD_SRC6_FIFO_RD_TH 0x0f000000 |
#define | FLD_SRC6_PHASE_INC 0x0003ffff |
#define | BAND_OUT_SEL 0x910 |
#define | FLD_SRC6_IN_SEL 0xc0000000 |
#define | FLD_SRC6_CLK_SEL 0x30000000 |
#define | FLD_SRC5_IN_SEL 0x0c000000 |
#define | FLD_SRC5_CLK_SEL 0x03000000 |
#define | FLD_SRC4_IN_SEL 0x00c00000 |
#define | FLD_SRC4_CLK_SEL 0x00300000 |
#define | FLD_SRC3_IN_SEL 0x000c0000 |
#define | FLD_SRC3_CLK_SEL 0x00030000 |
#define | FLD_BASEBAND_BYPASS_CTL 0x0000ff00 |
#define | FLD_AC97_SRC_SEL 0x000000c0 |
#define | FLD_I2S_SRC_SEL 0x00000030 |
#define | FLD_PARALLEL2_SRC_SEL 0x0000000c |
#define | FLD_PARALLEL1_SRC_SEL 0x00000003 |
#define | I2S_IN_CTL 0x914 |
#define | FLD_I2S_UP2X_BW20K 0x00000400 |
#define | FLD_I2S_UP2X_BYPASS 0x00000200 |
#define | FLD_I2S_IN_MASTER_MODE 0x00000100 |
#define | FLD_I2S_IN_SONY_MODE 0x00000080 |
#define | FLD_I2S_IN_RIGHT_JUST 0x00000040 |
#define | FLD_I2S_IN_WS_SEL 0x00000020 |
#define | FLD_I2S_IN_BCN_DEL 0x0000001f |
#define | I2S_OUT_CTL 0x918 |
#define | FLD_I2S_OUT_SOFT_RESET_EN 0x00010000 |
#define | FLD_I2S_OUT_MASTER_MODE 0x00000100 |
#define | FLD_I2S_OUT_SONY_MODE 0x00000080 |
#define | FLD_I2S_OUT_RIGHT_JUST 0x00000040 |
#define | FLD_I2S_OUT_WS_SEL 0x00000020 |
#define | FLD_I2S_OUT_BCN_DEL 0x0000001f |
#define | AC97_CTL 0x91c |
#define | FLD_AC97_UP2X_BW20K 0x02000000 |
#define | FLD_AC97_UP2X_BYPASS 0x01000000 |
#define | FLD_AC97_RST_ACL 0x00010000 |
#define | FLD_AC97_WAKE_UP_SYNC 0x00000100 |
#define | FLD_AC97_SHUTDOWN 0x00000001 |
#define | QPSK_IAGC_CTL1 0x94c |
#define | QPSK_IAGC_CTL2 0x950 |
#define | QPSK_FEPR_FREQ 0x954 |
#define | QPSK_BTL_CTL1 0x958 |
#define | QPSK_BTL_CTL2 0x95c |
#define | QPSK_CTL_CTL1 0x960 |
#define | QPSK_CTL_CTL2 0x964 |
#define | QPSK_MF_FAGC_CTL 0x968 |
#define | QPSK_EQ_CTL 0x96c |
#define | QPSK_LOCK_CTL 0x970 |
#define | FM1_DFT_CTL 0x9a8 |
#define | FLD_FM1_DFT_THRESHOLD 0xffff0000 |
#define | FLD_FM1_DFT_CMP_CTL 0x00000080 |
#define | FLD_FM1_DFT_AVG 0x00000070 |
#define | FLD_FM1_DFT_START 0x00000001 |
#define | FM1_DFT_STATUS 0x9ac |
#define | FLD_FM1_DFT_DONE 0x80000000 |
#define | FLD_FM_DFT_TH_CMP 0x00040000 |
#define | FLD_FM1_DFT 0x0003ffff |
#define | FM2_DFT_CTL 0x9b0 |
#define | FLD_FM2_DFT_THRESHOLD 0xffff0000 |
#define | FLD_FM2_DFT_CMP_CTL 0x00000080 |
#define | FLD_FM2_DFT_AVG 0x00000070 |
#define | FLD_FM2_DFT_START 0x00000001 |
#define | FM2_DFT_STATUS 0x9b4 |
#define | FLD_FM2_DFT_DONE 0x80000000 |
#define | FLD_FM2_DFT_TH_CMP_STAT 0x00040000 |
#define | FLD_FM2_DFT 0x0003ffff |
#define | AAGC_STATUS_REG 0x9b8 |
#define | AAGC_STATUS 0x9b8 |
#define | FLD_FM2_DAGC_OUT 0x07000000 |
#define | FLD_FM1_DAGC_OUT 0x00070000 |
#define | FLD_AFE_VGA_OUT 0x0000003f |
#define | MTS_GAIN_STATUS 0x9bc |
#define | FLD_MTS_GAIN 0x00003fff |
#define | RDS_OUT 0x9c0 |
#define | FLD_RDS_Q 0xffff0000 |
#define | FLD_RDS_I 0x0000ffff |
#define | AUTOCONFIG_REG 0x9c4 |
#define | FLD_AUTOCONFIG_MODE 0x0000000f |
#define | FM_AFC 0x9c8 |
#define | FLD_FM2_AFC 0xffff0000 |
#define | FLD_FM1_AFC 0x0000ffff |
#define | NEW_SPARE 0x9cc |
#define | NEW_SPARE_REG 0x9cc |
#define | DBX_ADJ 0x9d0 |
#define | FLD_DBX2_ADJ 0x0fff0000 |
#define | FLD_DBX1_ADJ 0x00000fff |
#define | VID_FMT_AUTO 0 |
#define | VID_FMT_NTSC_M 1 |
#define | VID_FMT_NTSC_J 2 |
#define | VID_FMT_NTSC_443 3 |
#define | VID_FMT_PAL_BDGHI 4 |
#define | VID_FMT_PAL_M 5 |
#define | VID_FMT_PAL_N 6 |
#define | VID_FMT_PAL_NC 7 |
#define | VID_FMT_PAL_60 8 |
#define | VID_FMT_SECAM 12 |
#define | VID_FMT_SECAM_60 13 |
#define | INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ |
#define | INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ |
#define | INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ |
#define | INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ |
#define | LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ |
#define | LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ |
#define | LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ |
#define | UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ |
#define | UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ |
#define | UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ |
#define | TWO_TAP_FILT 0 |
#define | THREE_TAP_FILT 1 |
#define | FOUR_TAP_FILT 2 |
#define | FIVE_TAP_FILT 3 |
#define | AUD_CHAN_SRC_PARALLEL 0 |
#define | AUD_CHAN_SRC_I2S_INPUT 1 |
#define | AUD_CHAN_SRC_FLATIRON 2 |
#define | AUD_CHAN_SRC_PARALLEL3 3 |
#define | OUT_MODE_601 0 |
#define | OUT_MODE_656 1 |
#define | OUT_MODE_VIP11 2 |
#define | OUT_MODE_VIP20 3 |
#define | PHASE_INC_49MHZ 0x0df22 |
#define | PHASE_INC_56MHZ 0x0fa5b |
#define | PHASE_INC_28MHZ 0x010000 |
#define AAGC_CTL 0x814 |
Definition at line 866 of file cx231xx-reg.h.
#define AAGC_STATUS 0x9b8 |
Definition at line 1482 of file cx231xx-reg.h.
#define AAGC_STATUS_REG 0x9b8 |
Definition at line 1481 of file cx231xx-reg.h.
#define AC97_CTL 0x91c |
Definition at line 1424 of file cx231xx-reg.h.
#define AFE_CTRL 0x104 |
Definition at line 95 of file cx231xx-reg.h.
#define AFE_CTRL_C2HH_SRC_CTRL 0x104 |
Definition at line 96 of file cx231xx-reg.h.
#define AFE_DIAG_CTRL1 0x134 |
Definition at line 205 of file cx231xx-reg.h.
#define AFE_DIAG_CTRL3 0x138 |
Definition at line 212 of file cx231xx-reg.h.
#define AM_FM_DIFF 0x89c |
Definition at line 1153 of file cx231xx-reg.h.
#define AM_MTS_DET 0x85c |
Definition at line 1016 of file cx231xx-reg.h.
#define ANALOG_DEMOD_CTL 0x81c |
Definition at line 887 of file cx231xx-reg.h.
#define ANALOG_MUX_CTL 0x860 |
Definition at line 1028 of file cx231xx-reg.h.
#define AUD_BUILD_NUM 0x806 |
Definition at line 791 of file cx231xx-reg.h.
#define AUD_CHAN_SRC_FLATIRON 2 |
Definition at line 1552 of file cx231xx-reg.h.
#define AUD_CHAN_SRC_I2S_INPUT 1 |
Definition at line 1551 of file cx231xx-reg.h.
#define AUD_CHAN_SRC_PARALLEL 0 |
Definition at line 1550 of file cx231xx-reg.h.
#define AUD_CHAN_SRC_PARALLEL3 3 |
Definition at line 1553 of file cx231xx-reg.h.
#define AUD_IO_CTRL 0x124 |
Definition at line 180 of file cx231xx-reg.h.
#define AUD_LOCK1 0x128 |
Definition at line 189 of file cx231xx-reg.h.
#define AUD_LOCK2 0x12c |
Definition at line 197 of file cx231xx-reg.h.
#define AUD_VER_NUM 0x807 |
Definition at line 792 of file cx231xx-reg.h.
#define AUTOCONFIG_REG 0x9c4 |
Definition at line 1500 of file cx231xx-reg.h.
#define BAND_OUT_SEL 0x910 |
Definition at line 1386 of file cx231xx-reg.h.
#define BIST_STAT 0x14c |
Definition at line 251 of file cx231xx-reg.h.
#define BRIGHTNESS_CTRL_BYTE 0x414 |
Definition at line 383 of file cx231xx-reg.h.
#define CH_PWR_CTRL1 0x0000000e |
Definition at line 49 of file cx231xx-reg.h.
#define CH_PWR_CTRL2 0x0000000f |
Definition at line 50 of file cx231xx-reg.h.
#define CHIP_CTRL 0x100 |
Definition at line 84 of file cx231xx-reg.h.
#define CHIP_VERSION 0x4b4 |
Definition at line 742 of file cx231xx-reg.h.
#define CHROMA_CTRL 0x420 |
Definition at line 409 of file cx231xx-reg.h.
#define CHROMA_VBIOFF_CFG 0x47c |
Definition at line 602 of file cx231xx-reg.h.
#define COMB_CTRL 0x49c |
Definition at line 674 of file cx231xx-reg.h.
#define CONTRAST_CTRL_BYTE 0x415 |
Definition at line 384 of file cx231xx-reg.h.
#define CRUSH_CTRL 0x4a0 |
Definition at line 681 of file cx231xx-reg.h.
#define DBX1_CTL1 0x884 |
Definition at line 1123 of file cx231xx-reg.h.
#define DBX1_CTL2 0x888 |
Definition at line 1128 of file cx231xx-reg.h.
#define DBX1_RMS_SE 0x88C |
Definition at line 1133 of file cx231xx-reg.h.
#define DBX2_CTL1 0x890 |
Definition at line 1138 of file cx231xx-reg.h.
#define DBX2_CTL2 0x894 |
Definition at line 1143 of file cx231xx-reg.h.
#define DBX2_RMS_SE 0x898 |
Definition at line 1148 of file cx231xx-reg.h.
#define DBX_ADJ 0x9d0 |
Definition at line 1514 of file cx231xx-reg.h.
#define DC_CTRL1 0x108 |
Definition at line 119 of file cx231xx-reg.h.
#define DC_CTRL2 0x10c |
Definition at line 126 of file cx231xx-reg.h.
#define DC_CTRL3 0x110 |
Definition at line 135 of file cx231xx-reg.h.
#define DC_CTRL4 0x114 |
Definition at line 142 of file cx231xx-reg.h.
#define DC_CTRL5 0x118 |
Definition at line 148 of file cx231xx-reg.h.
#define DC_CTRL6 0x11c |
Definition at line 154 of file cx231xx-reg.h.
#define DEEMPH_COEF1 0x87c |
Definition at line 1111 of file cx231xx-reg.h.
#define DEEMPH_COEF2 0x880 |
Definition at line 1118 of file cx231xx-reg.h.
#define DEEMPH_COEFF1 0x87c |
Definition at line 1110 of file cx231xx-reg.h.
#define DEEMPH_COEFF2 0x880 |
Definition at line 1117 of file cx231xx-reg.h.
#define DEEMPH_DENOM1 0x8b0 |
Definition at line 1191 of file cx231xx-reg.h.
#define DEEMPH_DENOM2 0x8b4 |
Definition at line 1198 of file cx231xx-reg.h.
#define DEEMPH_GAIN 0x8a4 |
Definition at line 1170 of file cx231xx-reg.h.
#define DEEMPH_GAIN_CTL 0x878 |
Definition at line 1104 of file cx231xx-reg.h.
#define DEEMPH_NUMER1 0x8a8 |
Definition at line 1177 of file cx231xx-reg.h.
#define DEEMPH_NUMER2 0x8ac |
Definition at line 1184 of file cx231xx-reg.h.
#define DEMATRIX_CTL 0x8cc |
Definition at line 1239 of file cx231xx-reg.h.
#define DFE_CTRL1 0x488 |
Definition at line 626 of file cx231xx-reg.h.
#define DFE_CTRL2 0x48c |
Definition at line 640 of file cx231xx-reg.h.
#define DFE_CTRL3 0x490 |
Definition at line 646 of file cx231xx-reg.h.
#define DFT1_CTL1 0x82c |
Definition at line 940 of file cx231xx-reg.h.
#define DFT1_CTL2 0x830 |
Definition at line 945 of file cx231xx-reg.h.
#define DFT1_STATUS 0x834 |
Definition at line 953 of file cx231xx-reg.h.
#define DFT2_CTL1 0x838 |
Definition at line 959 of file cx231xx-reg.h.
#define DFT2_CTL2 0x83C |
Definition at line 964 of file cx231xx-reg.h.
#define DFT2_STATUS 0x840 |
Definition at line 972 of file cx231xx-reg.h.
#define DFT3_CTL1 0x844 |
Definition at line 978 of file cx231xx-reg.h.
#define DFT3_CTL2 0x848 |
Definition at line 983 of file cx231xx-reg.h.
#define DFT3_STATUS 0x84c |
Definition at line 991 of file cx231xx-reg.h.
#define DFT4_CTL1 0x850 |
Definition at line 997 of file cx231xx-reg.h.
#define DFT4_CTL2 0x854 |
Definition at line 1002 of file cx231xx-reg.h.
#define DFT4_STATUS 0x858 |
Definition at line 1010 of file cx231xx-reg.h.
#define DIG_PLL_CTL1 0x864 |
Definition at line 1055 of file cx231xx-reg.h.
#define DIG_PLL_CTL2 0x868 |
Definition at line 1065 of file cx231xx-reg.h.
#define DIG_PLL_CTL3 0x86c |
Definition at line 1078 of file cx231xx-reg.h.
#define DIG_PLL_CTL4 0x870 |
Definition at line 1088 of file cx231xx-reg.h.
#define DIG_PLL_CTL5 0x874 |
Definition at line 1097 of file cx231xx-reg.h.
#define DL_CTL 0x800 |
Definition at line 772 of file cx231xx-reg.h.
#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ |
Definition at line 774 of file cx231xx-reg.h.
#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ |
Definition at line 773 of file cx231xx-reg.h.
#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ |
Definition at line 776 of file cx231xx-reg.h.
#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ |
Definition at line 775 of file cx231xx-reg.h.
#define DPLL_CTRL1 0x864 |
Definition at line 1054 of file cx231xx-reg.h.
#define DPLL_CTRL2 0x868 |
Definition at line 1064 of file cx231xx-reg.h.
#define DPLL_CTRL3 0x86c |
Definition at line 1077 of file cx231xx-reg.h.
#define DPLL_CTRL4 0x870 |
Definition at line 1087 of file cx231xx-reg.h.
#define DPLL_CTRL5 0x874 |
Definition at line 1096 of file cx231xx-reg.h.
#define DW8051_INT 0x80c |
Definition at line 806 of file cx231xx-reg.h.
#define EAV_ACTIVE_VIDEO_FIELD1 0x90 |
Definition at line 30 of file cx231xx-reg.h.
#define EAV_ACTIVE_VIDEO_FIELD2 0xd0 |
Definition at line 33 of file cx231xx-reg.h.
#define EAV_VBI_FIELD1 0x30 |
Definition at line 42 of file cx231xx-reg.h.
#define EAV_VBI_FIELD2 0x70 |
Definition at line 45 of file cx231xx-reg.h.
#define EAV_VBLANK_FIELD1 0xb0 |
Definition at line 36 of file cx231xx-reg.h.
#define EAV_VBLANK_FIELD2 0xf0 |
Definition at line 39 of file cx231xx-reg.h.
#define FIELD_COUNT 0x480 |
Definition at line 608 of file cx231xx-reg.h.
#define FIVE_TAP_FILT 3 |
Definition at line 1548 of file cx231xx-reg.h.
#define FLD_8051_SOFT_RESET 0x00000001 |
Definition at line 863 of file cx231xx-reg.h.
#define FLD_A1_DS1_SEL 0x000c0000 |
Definition at line 1080 of file cx231xx-reg.h.
#define FLD_A1_DS2_SEL 0x00030000 |
Definition at line 1081 of file cx231xx-reg.h.
#define FLD_A1_KD 0x000000ff |
Definition at line 1083 of file cx231xx-reg.h.
#define FLD_A1_KI 0x0000ff00 |
Definition at line 1082 of file cx231xx-reg.h.
#define FLD_A2_DS1_SEL 0x000c0000 |
Definition at line 1089 of file cx231xx-reg.h.
#define FLD_A2_DS2_SEL 0x00030000 |
Definition at line 1090 of file cx231xx-reg.h.
#define FLD_A2_KD 0x000000ff |
Definition at line 1092 of file cx231xx-reg.h.
#define FLD_A2_KI 0x0000ff00 |
Definition at line 1091 of file cx231xx-reg.h.
#define FLD_AAGC_DEFAULT 0x3f000000 |
Definition at line 869 of file cx231xx-reg.h.
#define FLD_AAGC_DEFAULT_EN 0x40000000 |
Definition at line 868 of file cx231xx-reg.h.
#define FLD_AAGC_GAIN 0x00600000 |
Definition at line 871 of file cx231xx-reg.h.
#define FLD_AAGC_HYST1 0x0000003f |
Definition at line 876 of file cx231xx-reg.h.
#define FLD_AAGC_HYST2 0x00003f00 |
Definition at line 874 of file cx231xx-reg.h.
#define FLD_AAGC_TH 0x001f0000 |
Definition at line 872 of file cx231xx-reg.h.
#define FLD_AC97_IN_SHIFT 0xf0000000 |
Definition at line 1240 of file cx231xx-reg.h.
#define FLD_AC97_INT 0x10000000 |
Definition at line 810 of file cx231xx-reg.h.
#define FLD_AC97_INT_CTL 0x01000000 |
Definition at line 848 of file cx231xx-reg.h.
#define FLD_AC97_INT_DIS 0x00010000 |
Definition at line 856 of file cx231xx-reg.h.
#define FLD_AC97_INT_EN 0x00001000 |
Definition at line 825 of file cx231xx-reg.h.
#define FLD_AC97_RST_ACL 0x00010000 |
Definition at line 1429 of file cx231xx-reg.h.
#define FLD_AC97_SHUTDOWN 0x00000001 |
Definition at line 1433 of file cx231xx-reg.h.
#define FLD_AC97_SRC_SEL 0x000000c0 |
Definition at line 1396 of file cx231xx-reg.h.
#define FLD_AC97_UP2X_BW20K 0x02000000 |
Definition at line 1426 of file cx231xx-reg.h.
#define FLD_AC97_UP2X_BYPASS 0x01000000 |
Definition at line 1427 of file cx231xx-reg.h.
#define FLD_AC97_WAKE_UP_SYNC 0x00000100 |
Definition at line 1431 of file cx231xx-reg.h.
#define FLD_ACFG_DIS 0x00000020 |
Definition at line 281 of file cx231xx-reg.h.
#define FLD_ACTFMT 0x00000400 |
Definition at line 299 of file cx231xx-reg.h.
#define FLD_AD_SOFT_RESET_REG 0x00000008 |
Definition at line 860 of file cx231xx-reg.h.
#define FLD_ADAPT_SLICE_DIS 0x00000001 |
Definition at line 470 of file cx231xx-reg.h.
#define FLD_AFC_INT 0x04000000 |
Definition at line 846 of file cx231xx-reg.h.
#define FLD_AFD_ACQUIRE 0x00000100 |
Definition at line 278 of file cx231xx-reg.h.
#define FLD_AFD_FMT_STAT 0x00000f00 |
Definition at line 338 of file cx231xx-reg.h.
#define FLD_AFD_FORCE_PAL 0x04000000 |
Definition at line 266 of file cx231xx-reg.h.
#define FLD_AFD_FORCE_PALNC 0x08000000 |
Definition at line 265 of file cx231xx-reg.h.
#define FLD_AFD_FORCE_SECAM 0x10000000 |
Definition at line 264 of file cx231xx-reg.h.
#define FLD_AFD_NTSC_SEL 0x00000080 |
Definition at line 279 of file cx231xx-reg.h.
#define FLD_AFD_PAL60_DIS 0x20000000 |
Definition at line 263 of file cx231xx-reg.h.
#define FLD_AFD_PAL_SEL 0x00000040 |
Definition at line 280 of file cx231xx-reg.h.
#define FLD_AFD_PALM_SEL 0x03000000 |
Definition at line 267 of file cx231xx-reg.h.
#define FLD_AFD_STAT 0x07ff0000 |
Definition at line 616 of file cx231xx-reg.h.
#define FLD_AFE_12DB_EN 0x80000000 |
Definition at line 867 of file cx231xx-reg.h.
#define FLD_AFE_VGA_OUT 0x0000003f |
Definition at line 1488 of file cx231xx-reg.h.
#define FLD_AGC_AUTO_EN 0x40000000 |
Definition at line 628 of file cx231xx-reg.h.
#define FLD_AGC_GAIN 0x000fff00 |
Definition at line 635 of file cx231xx-reg.h.
#define FLD_AGC_LOCK 0x00100000 |
Definition at line 329 of file cx231xx-reg.h.
#define FLD_AGC_LOOP_GAIN 0x0000000c |
Definition at line 654 of file cx231xx-reg.h.
#define FLD_AGC_REF 0x000000ff |
Definition at line 1025 of file cx231xx-reg.h.
#define FLD_AM_DIFF_OUT 0x00007fff |
Definition at line 1157 of file cx231xx-reg.h.
#define FLD_AM_GAIN_EN 0x01000000 |
Definition at line 1020 of file cx231xx-reg.h.
#define FLD_AM_MTS_MODE 0x80000000 |
Definition at line 1017 of file cx231xx-reg.h.
#define FLD_AM_PDF_SEL1 0x00000030 |
Definition at line 1070 of file cx231xx-reg.h.
#define FLD_AM_PDF_SEL2 0x000000c0 |
Definition at line 1069 of file cx231xx-reg.h.
#define FLD_AM_REG_GAIN 0x00000700 |
Definition at line 1024 of file cx231xx-reg.h.
#define FLD_AM_SUB 0x02000000 |
Definition at line 1019 of file cx231xx-reg.h.
#define FLD_AMC_INT 0x02000000 |
Definition at line 847 of file cx231xx-reg.h.
#define FLD_AMC_INT_DIS 0x00020000 |
Definition at line 855 of file cx231xx-reg.h.
#define FLD_AMMTS_GAIN_SCALE 0x0000e000 |
Definition at line 1022 of file cx231xx-reg.h.
#define FLD_ANC_DATA_EN 0x00000010 |
Definition at line 305 of file cx231xx-reg.h.
#define FLD_AUD_ANC_EN 0x08000000 |
Definition at line 314 of file cx231xx-reg.h.
#define FLD_AUD_BIST_FAIL_H 0xfff00000 |
Definition at line 252 of file cx231xx-reg.h.
#define FLD_AUD_BIST_TEST_H 0x0f000000 |
Definition at line 240 of file cx231xx-reg.h.
#define FLD_AUD_BIST_TST_DONE 0x0000fff0 |
Definition at line 255 of file cx231xx-reg.h.
#define FLD_AUD_CHAN1_SRC 0x00000003 |
Definition at line 186 of file cx231xx-reg.h.
#define FLD_AUD_CHAN2_SRC 0x0000000c |
Definition at line 185 of file cx231xx-reg.h.
#define FLD_AUD_CHAN3_SRC 0x00000030 |
Definition at line 184 of file cx231xx-reg.h.
#define FLD_AUD_CONFIG 0x000000ff |
Definition at line 803 of file cx231xx-reg.h.
#define FLD_AUD_COUNT 0x000fffff |
Definition at line 202 of file cx231xx-reg.h.
#define FLD_AUD_DUAL_FLAG_POL 0x02000000 |
Definition at line 214 of file cx231xx-reg.h.
#define FLD_AUD_GRP 0xc0000000 |
Definition at line 312 of file cx231xx-reg.h.
#define FLD_AUD_IN_SEL 0x00004000 |
Definition at line 102 of file cx231xx-reg.h.
#define FLD_AUD_IRQ_STAT 0x20000000 |
Definition at line 166 of file cx231xx-reg.h.
#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 |
Definition at line 201 of file cx231xx-reg.h.
#define FLD_AUD_LOCK_KD_MULT 0x0F000000 |
Definition at line 199 of file cx231xx-reg.h.
#define FLD_AUD_LOCK_KD_SHIFT 0x30000000 |
Definition at line 191 of file cx231xx-reg.h.
#define FLD_AUD_LOCK_KI_MULT 0xf0000000 |
Definition at line 198 of file cx231xx-reg.h.
#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000 |
Definition at line 190 of file cx231xx-reg.h.
#define FLD_AUTO_INC_DIS 0x20 |
Definition at line 55 of file cx231xx-reg.h.
#define FLD_AUTO_LOCK_SPD 0x00080000 |
Definition at line 666 of file cx231xx-reg.h.
#define FLD_AUTO_RATE_DIS 0x80000000 |
Definition at line 728 of file cx231xx-reg.h.
#define FLD_AUTO_SC_LOCK 0x00001000 |
Definition at line 275 of file cx231xx-reg.h.
#define FLD_AUTOCONFIG_MODE 0x0000000f |
Definition at line 1502 of file cx231xx-reg.h.
#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000 |
Definition at line 98 of file cx231xx-reg.h.
#define FLD_BANDWIDTH_SELECT 0x00030000 |
Definition at line 1058 of file cx231xx-reg.h.
#define FLD_BASEBAND_BYPASS_CTL 0x0000ff00 |
Definition at line 1395 of file cx231xx-reg.h.
#define FLD_BB_CLK_MODE 0x0C |
Definition at line 79 of file cx231xx-reg.h.
#define FLD_BGDEL_CNT 0xff000000 |
Definition at line 570 of file cx231xx-reg.h.
#define FLD_BIST_DEBUGZ 0x10000000 |
Definition at line 239 of file cx231xx-reg.h.
#define FLD_BIST_FAIL_AUD_PLL 0x0000080 |
Definition at line 227 of file cx231xx-reg.h.
#define FLD_BIST_FAIL_VID_PLL 0x0000020 |
Definition at line 229 of file cx231xx-reg.h.
#define FLD_BIST_INTR_AUD_PLL 0x0000040 |
Definition at line 228 of file cx231xx-reg.h.
#define FLD_BIST_INTR_VID_PLL 0x0000010 |
Definition at line 230 of file cx231xx-reg.h.
#define FLD_BIST_TEST_H 0x00010000 |
Definition at line 245 of file cx231xx-reg.h.
#define FLD_BLEND_SLOPE 0x000f0000 |
Definition at line 596 of file cx231xx-reg.h.
#define FLD_BLUE_FIELD_ACT 0x00000040 |
Definition at line 303 of file cx231xx-reg.h.
#define FLD_BLUE_FIELD_EN 0x00000080 |
Definition at line 302 of file cx231xx-reg.h.
#define FLD_BP_LOOP_GAIN 0x00000300 |
Definition at line 651 of file cx231xx-reg.h.
#define FLD_BP_PERCENT 0xff000000 |
Definition at line 647 of file cx231xx-reg.h.
#define FLD_BRITE 0x000000ff |
Definition at line 392 of file cx231xx-reg.h.
#define FLD_BTSC_FMRADIO_MODE 0x00000001 |
Definition at line 898 of file cx231xx-reg.h.
#define FLD_BYPASS_LI 0x00000002 |
Definition at line 1335 of file cx231xx-reg.h.
#define FLD_BYPASS_PF 0x00000001 |
Definition at line 1336 of file cx231xx-reg.h.
#define FLD_C2HH_SAT_MIN 0x0000001e |
Definition at line 130 of file cx231xx-reg.h.
#define FLD_C_CORE_SEL 0x03000000 |
Definition at line 415 of file cx231xx-reg.h.
#define FLD_C_LPF_EN 0x20000000 |
Definition at line 413 of file cx231xx-reg.h.
#define FLD_CAGCEN 0x00004000 |
Definition at line 273 of file cx231xx-reg.h.
#define FLD_CC_DAT_AVAIL_MSK 0x08000000 |
Definition at line 352 of file cx231xx-reg.h.
#define FLD_CC_DAT_AVAIL_STAT 0x00000800 |
Definition at line 368 of file cx231xx-reg.h.
#define FLD_CC_FIFO_DAT 0x0000FF00 |
Definition at line 489 of file cx231xx-reg.h.
#define FLD_CC_FIFO_RST 0x00010000 |
Definition at line 479 of file cx231xx-reg.h.
#define FLD_CC_STAT 0x000000FF |
Definition at line 490 of file cx231xx-reg.h.
#define FLD_CCOMB_2LN_CHECK 0x80000000 |
Definition at line 586 of file cx231xx-reg.h.
#define FLD_CCOMB_2LN_EN 0x20000000 |
Definition at line 588 of file cx231xx-reg.h.
#define FLD_CCOMB_3D_EN 0x10000000 |
Definition at line 589 of file cx231xx-reg.h.
#define FLD_CCOMB_3LN_EN 0x40000000 |
Definition at line 587 of file cx231xx-reg.h.
#define FLD_CCOMB_ERR_LIMIT 0x00ff0000 |
Definition at line 676 of file cx231xx-reg.h.
#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00 |
Definition at line 751 of file cx231xx-reg.h.
#define FLD_CCOMB_REDUCE_EN 0x00008000 |
Definition at line 597 of file cx231xx-reg.h.
#define FLD_CDMOD_SOFT_RESET 0x00000002 |
Definition at line 862 of file cx231xx-reg.h.
#define FLD_CHIP_ACFG_DIS 0x00100000 |
Definition at line 87 of file cx231xx-reg.h.
#define FLD_CHR_DELAY 0x1c000000 |
Definition at line 414 of file cx231xx-reg.h.
#define FLD_CHROMA_IN_SEL 0x00001000 |
Definition at line 104 of file cx231xx-reg.h.
#define FLD_CHROMA_RST_MSK 0x00000040 |
Definition at line 700 of file cx231xx-reg.h.
#define FLD_CIR_TEST_DIS 0x00000001 |
Definition at line 232 of file cx231xx-reg.h.
#define FLD_CKILL_MODE 0x00300000 |
Definition at line 268 of file cx231xx-reg.h.
#define FLD_CKILLEN 0x00002000 |
Definition at line 274 of file cx231xx-reg.h.
#define FLD_CLAMP_AUTO_EN 0x80000000 |
Definition at line 627 of file cx231xx-reg.h.
#define FLD_CLAMP_LEVEL 0x07000000 |
Definition at line 632 of file cx231xx-reg.h.
#define FLD_CLAMP_LVL_CH1 0x3fff8000 |
Definition at line 121 of file cx231xx-reg.h.
#define FLD_CLAMP_LVL_CH2 0x00007fff |
Definition at line 122 of file cx231xx-reg.h.
#define FLD_CLAMP_LVL_CH3 0x00fffe00 |
Definition at line 128 of file cx231xx-reg.h.
#define FLD_CLAMP_SKIP_CNT 0x00300000 |
Definition at line 634 of file cx231xx-reg.h.
#define FLD_CLAMP_WIND_LENTH 0x000001e0 |
Definition at line 129 of file cx231xx-reg.h.
#define FLD_CLAMPRAW_EN 0x00000100 |
Definition at line 301 of file cx231xx-reg.h.
#define FLD_CLK_GATING 0x0000c000 |
Definition at line 295 of file cx231xx-reg.h.
#define FLD_CLK_IN_EN 0x80 |
Definition at line 77 of file cx231xx-reg.h.
#define FLD_CLK_INVERT 0x00002000 |
Definition at line 296 of file cx231xx-reg.h.
#define FLD_CLR_LOCK_STAT 0x00020000 |
Definition at line 270 of file cx231xx-reg.h.
#define FLD_CNTRST 0x0000ff00 |
Definition at line 391 of file cx231xx-reg.h.
#define FLD_COL_CLAMP_DIS_CH1 0x00400000 |
Definition at line 217 of file cx231xx-reg.h.
#define FLD_COL_CLAMP_DIS_CH2 0x00200000 |
Definition at line 218 of file cx231xx-reg.h.
#define FLD_COL_CLAMP_DIS_CH3 0x00100000 |
Definition at line 219 of file cx231xx-reg.h.
#define FLD_COMB_3D_FIFO_MSK 0x80000000 |
Definition at line 348 of file cx231xx-reg.h.
#define FLD_COMB_3D_FIFO_STAT 0x00008000 |
Definition at line 364 of file cx231xx-reg.h.
#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ |
Definition at line 269 of file cx231xx-reg.h.
#define FLD_COMB_PHASE_LIMIT 0xff000000 |
Definition at line 675 of file cx231xx-reg.h.
#define FLD_CRI_MARG_SCALE 0x0000000c |
Definition at line 468 of file cx231xx-reg.h.
#define FLD_CRUSH_FREQ 0x00200000 |
Definition at line 683 of file cx231xx-reg.h.
#define FLD_CS_ATHRESH_LEV 0x000000ff |
Definition at line 739 of file cx231xx-reg.h.
#define FLD_CS_ATHRESH_SEL 0x04000000 |
Definition at line 733 of file cx231xx-reg.h.
#define FLD_CS_LINE_CNT 0x00003f00 |
Definition at line 738 of file cx231xx-reg.h.
#define FLD_CS_LINE_THRSH_SEL 0x08000000 |
Definition at line 732 of file cx231xx-reg.h.
#define FLD_CS_STOPWIN 0xff000000 |
Definition at line 721 of file cx231xx-reg.h.
#define FLD_CS_STRTWIN 0x00ff0000 |
Definition at line 722 of file cx231xx-reg.h.
#define FLD_CS_TYPE2_CNT 0x000fc000 |
Definition at line 737 of file cx231xx-reg.h.
#define FLD_CS_TYPE2_SEL 0x10000000 |
Definition at line 731 of file cx231xx-reg.h.
#define FLD_CS_WIDTH 0x0000ff00 |
Definition at line 723 of file cx231xx-reg.h.
#define FLD_CSC_LOCK 0x00080000 |
Definition at line 330 of file cx231xx-reg.h.
#define FLD_CSC_LOCK_CHANGE_MSK 0x00040000 |
Definition at line 361 of file cx231xx-reg.h.
#define FLD_CSC_LOCK_CHANGE_STAT 0x00000004 |
Definition at line 377 of file cx231xx-reg.h.
#define FLD_CUV_DLY_LENGTH 0x0000ff00 |
Definition at line 207 of file cx231xx-reg.h.
#define FLD_DBX1_ADJ 0x00000fff |
Definition at line 1518 of file cx231xx-reg.h.
#define FLD_DBX1_IN_GAIN 0x0000ffff |
Definition at line 1125 of file cx231xx-reg.h.
#define FLD_DBX1_RMS_SE_FLD 0x0000ffff |
Definition at line 1135 of file cx231xx-reg.h.
#define FLD_DBX1_RMS_WBE 0xffff0000 |
Definition at line 1134 of file cx231xx-reg.h.
#define FLD_DBX1_SE_BYPASS 0xffff0000 |
Definition at line 1129 of file cx231xx-reg.h.
#define FLD_DBX1_SE_GAIN 0x0000ffff |
Definition at line 1130 of file cx231xx-reg.h.
#define FLD_DBX1_WBE_GAIN 0xffff0000 |
Definition at line 1124 of file cx231xx-reg.h.
#define FLD_DBX2_ADJ 0x0fff0000 |
Definition at line 1516 of file cx231xx-reg.h.
#define FLD_DBX2_IN_GAIN 0x0000ffff |
Definition at line 1140 of file cx231xx-reg.h.
#define FLD_DBX2_RMS_SE_FLD 0x0000ffff |
Definition at line 1150 of file cx231xx-reg.h.
#define FLD_DBX2_RMS_WBE 0xffff0000 |
Definition at line 1149 of file cx231xx-reg.h.
#define FLD_DBX2_SE_BYPASS 0xffff0000 |
Definition at line 1144 of file cx231xx-reg.h.
#define FLD_DBX2_SE_GAIN 0x0000ffff |
Definition at line 1145 of file cx231xx-reg.h.
#define FLD_DBX2_WBE_GAIN 0xffff0000 |
Definition at line 1139 of file cx231xx-reg.h.
#define FLD_DBX_BYPASS 0x80000000 |
Definition at line 880 of file cx231xx-reg.h.
#define FLD_DBX_SOFT_RESET_REG 0x00000010 |
Definition at line 859 of file cx231xx-reg.h.
#define FLD_DCC_LOOP_GAIN 0x00000003 |
Definition at line 655 of file cx231xx-reg.h.
#define FLD_DCMODE 0x00010000 |
Definition at line 294 of file cx231xx-reg.h.
#define FLD_DCR_BYP_CH1 0x00000020 |
Definition at line 110 of file cx231xx-reg.h.
#define FLD_DCR_BYP_CH2 0x00000010 |
Definition at line 111 of file cx231xx-reg.h.
#define FLD_DCR_BYP_CH3 0x00000008 |
Definition at line 112 of file cx231xx-reg.h.
#define FLD_DEBOUNCE_COUNT 0xc0000000 |
Definition at line 613 of file cx231xx-reg.h.
#define FLD_DEEMPH1_GAIN 0x0000FFFF |
Definition at line 1106 of file cx231xx-reg.h.
#define FLD_DEEMPH2_GAIN 0xFFFF0000 |
Definition at line 1105 of file cx231xx-reg.h.
#define FLD_DEEMPH_A0 0x0000ffff |
Definition at line 1113 of file cx231xx-reg.h.
#define FLD_DEEMPH_A1 0x0000FFFF |
Definition at line 1120 of file cx231xx-reg.h.
#define FLD_DEEMPH_B0 0xffff0000 |
Definition at line 1112 of file cx231xx-reg.h.
#define FLD_DEEMPH_B1 0xFFFF0000 |
Definition at line 1119 of file cx231xx-reg.h.
#define FLD_DEEMPHDENOM1 0x0003ffff |
Definition at line 1194 of file cx231xx-reg.h.
#define FLD_DEEMPHDENOM2 0x0003ffff |
Definition at line 1201 of file cx231xx-reg.h.
#define FLD_DEEMPHGAIN 0x0003ffff |
Definition at line 1173 of file cx231xx-reg.h.
#define FLD_DEEMPHNUMER1 0x0003ffff |
Definition at line 1180 of file cx231xx-reg.h.
#define FLD_DEEMPHNUMER2 0x0003ffff |
Definition at line 1187 of file cx231xx-reg.h.
#define FLD_DEMATRIX_MODE 0x00000300 |
Definition at line 1245 of file cx231xx-reg.h.
#define FLD_DEMATRIX_SEL_CTL 0x00ff0000 |
Definition at line 1242 of file cx231xx-reg.h.
#define FLD_DEVICE_ID 0x0000ffff |
Definition at line 92 of file cx231xx-reg.h.
#define FLD_DFE_RST_MSK 0x00000002 |
Definition at line 705 of file cx231xx-reg.h.
#define FLD_DFT1_AVG 0x00000070 |
Definition at line 948 of file cx231xx-reg.h.
#define FLD_DFT1_CMP_CTL 0x00000080 |
Definition at line 947 of file cx231xx-reg.h.
#define FLD_DFT1_DONE 0x80000000 |
Definition at line 954 of file cx231xx-reg.h.
#define FLD_DFT1_DWELL 0xffff0000 |
Definition at line 941 of file cx231xx-reg.h.
#define FLD_DFT1_FREQ 0x0000ffff |
Definition at line 942 of file cx231xx-reg.h.
#define FLD_DFT1_RESULT 0x3fffffff |
Definition at line 956 of file cx231xx-reg.h.
#define FLD_DFT1_START 0x00000001 |
Definition at line 950 of file cx231xx-reg.h.
#define FLD_DFT1_TH_CMP 0x00040000 |
Definition at line 819 of file cx231xx-reg.h.
#define FLD_DFT1_TH_CMP_STAT 0x40000000 |
Definition at line 955 of file cx231xx-reg.h.
#define FLD_DFT1_THRESHOLD 0xffffff00 |
Definition at line 946 of file cx231xx-reg.h.
#define FLD_DFT2_AVG 0x00000070 |
Definition at line 967 of file cx231xx-reg.h.
#define FLD_DFT2_CMP_CTL 0x00000080 |
Definition at line 966 of file cx231xx-reg.h.
#define FLD_DFT2_DONE 0x80000000 |
Definition at line 973 of file cx231xx-reg.h.
#define FLD_DFT2_DWELL 0xffff0000 |
Definition at line 960 of file cx231xx-reg.h.
#define FLD_DFT2_FREQ 0x0000ffff |
Definition at line 961 of file cx231xx-reg.h.
#define FLD_DFT2_RESULT 0x3fffffff |
Definition at line 975 of file cx231xx-reg.h.
#define FLD_DFT2_START 0x00000001 |
Definition at line 969 of file cx231xx-reg.h.
#define FLD_DFT2_TH_CMP 0x00080000 |
Definition at line 818 of file cx231xx-reg.h.
#define FLD_DFT2_TH_CMP_STAT 0x40000000 |
Definition at line 974 of file cx231xx-reg.h.
#define FLD_DFT2_THRESHOLD 0xffffff00 |
Definition at line 965 of file cx231xx-reg.h.
#define FLD_DFT3_AVG 0x00000070 |
Definition at line 986 of file cx231xx-reg.h.
#define FLD_DFT3_CMP_CTL 0x00000080 |
Definition at line 985 of file cx231xx-reg.h.
#define FLD_DFT3_DONE 0x80000000 |
Definition at line 992 of file cx231xx-reg.h.
#define FLD_DFT3_DWELL 0xffff0000 |
Definition at line 979 of file cx231xx-reg.h.
#define FLD_DFT3_FREQ 0x0000ffff |
Definition at line 980 of file cx231xx-reg.h.
#define FLD_DFT3_RESULT 0x3fffffff |
Definition at line 994 of file cx231xx-reg.h.
#define FLD_DFT3_START 0x00000001 |
Definition at line 988 of file cx231xx-reg.h.
#define FLD_DFT3_TH_CMP 0x00100000 |
Definition at line 817 of file cx231xx-reg.h.
#define FLD_DFT3_TH_CMP_STAT 0x40000000 |
Definition at line 993 of file cx231xx-reg.h.
#define FLD_DFT3_THRESHOLD 0xffffff00 |
Definition at line 984 of file cx231xx-reg.h.
#define FLD_DFT4_AVG 0x00000070 |
Definition at line 1005 of file cx231xx-reg.h.
#define FLD_DFT4_CMP_CTL 0x00000080 |
Definition at line 1004 of file cx231xx-reg.h.
#define FLD_DFT4_DONE 0x80000000 |
Definition at line 1011 of file cx231xx-reg.h.
#define FLD_DFT4_DWELL 0xffff0000 |
Definition at line 998 of file cx231xx-reg.h.
#define FLD_DFT4_FREQ 0x0000ffff |
Definition at line 999 of file cx231xx-reg.h.
#define FLD_DFT4_RESULT 0x3fffffff |
Definition at line 1013 of file cx231xx-reg.h.
#define FLD_DFT4_START 0x00000001 |
Definition at line 1007 of file cx231xx-reg.h.
#define FLD_DFT4_TH_CMP 0x01000000 |
Definition at line 814 of file cx231xx-reg.h.
#define FLD_DFT4_TH_CMP_EN 0x00000100 |
Definition at line 829 of file cx231xx-reg.h.
#define FLD_DFT4_TH_CMP_STAT 0x40000000 |
Definition at line 1012 of file cx231xx-reg.h.
#define FLD_DFT4_THRESHOLD 0xffffff00 |
Definition at line 1003 of file cx231xx-reg.h.
#define FLD_DFT_THRESHOLD 0x00ff0000 |
Definition at line 648 of file cx231xx-reg.h.
#define FLD_DIF_OUT_SEL 0xc0000000 |
Definition at line 97 of file cx231xx-reg.h.
#define FLD_DIGITAL_PWR_DN 0x02 |
Definition at line 58 of file cx231xx-reg.h.
#define FLD_DIS_BTSC 0x00400000 |
Definition at line 798 of file cx231xx-reg.h.
#define FLD_DIS_DBX 0x00800000 |
Definition at line 797 of file cx231xx-reg.h.
#define FLD_DIS_NICAM_A2 0x00200000 |
Definition at line 799 of file cx231xx-reg.h.
#define FLD_DISABLE_LOOP 0x01000000 |
Definition at line 1079 of file cx231xx-reg.h.
#define FLD_DL_AUTO_INC 0x04000000 |
Definition at line 780 of file cx231xx-reg.h.
#define FLD_DL_ENABLE 0x08000000 |
Definition at line 779 of file cx231xx-reg.h.
#define FLD_DL_MAP 0x03000000 |
Definition at line 781 of file cx231xx-reg.h.
#define FLD_DMTRX_BYPASS 0x00000400 |
Definition at line 1244 of file cx231xx-reg.h.
#define FLD_DPLL_FSM_CTRL 0x0000000c |
Definition at line 1071 of file cx231xx-reg.h.
#define FLD_DUAL_MODE_ADC2 0x00040000 |
Definition at line 89 of file cx231xx-reg.h.
#define FLD_DW8051_INT0_CTL1 0x00000001 |
Definition at line 837 of file cx231xx-reg.h.
#define FLD_DW8051_INT1_CTL1 0x00000002 |
Definition at line 836 of file cx231xx-reg.h.
#define FLD_DW8051_INT2_CTL1 0x00000004 |
Definition at line 835 of file cx231xx-reg.h.
#define FLD_DW8051_INT3_CTL1 0x00000008 |
Definition at line 834 of file cx231xx-reg.h.
#define FLD_DW8051_INT4_CTL1 0x00000010 |
Definition at line 833 of file cx231xx-reg.h.
#define FLD_DW8051_INT5_CTL1 0x00000020 |
Definition at line 832 of file cx231xx-reg.h.
#define FLD_DW8051_INT6_CTL1 0x00000040 |
Definition at line 831 of file cx231xx-reg.h.
#define FLD_DW8051_VIDEO_FORMAT 0x000f0000 |
Definition at line 801 of file cx231xx-reg.h.
#define FLD_EDGE_RESYNC_EN 0x00000002 |
Definition at line 469 of file cx231xx-reg.h.
#define FLD_EN_12DB_CH1 0x00000001 |
Definition at line 115 of file cx231xx-reg.h.
#define FLD_EN_12DB_CH2 0x00000002 |
Definition at line 114 of file cx231xx-reg.h.
#define FLD_EN_12DB_CH3 0x00000004 |
Definition at line 113 of file cx231xx-reg.h.
#define FLD_EN_A 0x01000000 |
Definition at line 317 of file cx231xx-reg.h.
#define FLD_EN_AV_LOCK 0x01000000 |
Definition at line 193 of file cx231xx-reg.h.
#define FLD_EN_B 0x02000000 |
Definition at line 316 of file cx231xx-reg.h.
#define FLD_EN_C 0x04000000 |
Definition at line 315 of file cx231xx-reg.h.
#define FLD_EN_FIELD_PHASE_DET 0x80000000 |
Definition at line 763 of file cx231xx-reg.h.
#define FLD_EN_HEAD_SW_DET 0x40000000 |
Definition at line 764 of file cx231xx-reg.h.
#define FLD_END_VBI_EVEN_MSK 0x01000000 |
Definition at line 355 of file cx231xx-reg.h.
#define FLD_END_VBI_EVEN_STAT 0x00000100 |
Definition at line 371 of file cx231xx-reg.h.
#define FLD_END_VBI_ODD_MSK 0x00800000 |
Definition at line 356 of file cx231xx-reg.h.
#define FLD_END_VBI_ODD_STAT 0x00000080 |
Definition at line 372 of file cx231xx-reg.h.
#define FLD_ERR_GAIN_CTL 0x00070000 |
Definition at line 137 of file cx231xx-reg.h.
#define FLD_ERRINTRPTTHSHLD1 0x0fff0000 |
Definition at line 1206 of file cx231xx-reg.h.
#define FLD_ERRINTRPTTHSHLD2 0x00000fff |
Definition at line 1215 of file cx231xx-reg.h.
#define FLD_ERRINTRPTTHSHLD3 0x0fff0000 |
Definition at line 1213 of file cx231xx-reg.h.
#define FLD_ERRLOG1 0x00000fff |
Definition at line 1222 of file cx231xx-reg.h.
#define FLD_ERRLOG2 0x0fff0000 |
Definition at line 1220 of file cx231xx-reg.h.
#define FLD_ERRLOG3 0x00000fff |
Definition at line 1227 of file cx231xx-reg.h.
#define FLD_ERRLOGPERIOD 0x00000fff |
Definition at line 1208 of file cx231xx-reg.h.
#define FLD_FAST_LOCK_MD 0x00010000 |
Definition at line 271 of file cx231xx-reg.h.
#define FLD_FAWDETTHRSHLD1 0x0000000f |
Definition at line 1166 of file cx231xx-reg.h.
#define FLD_FAWDETTHRSHLD2 0x000000f0 |
Definition at line 1165 of file cx231xx-reg.h.
#define FLD_FAWDETTHRSHLD3 0x00000f00 |
Definition at line 1164 of file cx231xx-reg.h.
#define FLD_FAWDETWINEND 0xFc000000 |
Definition at line 1161 of file cx231xx-reg.h.
#define FLD_FAWDETWINSTR 0x03ff0000 |
Definition at line 1162 of file cx231xx-reg.h.
#define FLD_FC_ALT1 0x00ff0000 |
Definition at line 455 of file cx231xx-reg.h.
#define FLD_FC_ALT1_TYPE 0x00000f00 |
Definition at line 457 of file cx231xx-reg.h.
#define FLD_FC_ALT2 0xff000000 |
Definition at line 454 of file cx231xx-reg.h.
#define FLD_FC_ALT2_TYPE 0x0000f000 |
Definition at line 456 of file cx231xx-reg.h.
#define FLD_FC_INT_DIS 0x00040000 |
Definition at line 854 of file cx231xx-reg.h.
#define FLD_FC_SEARCH_MODE 0x00000001 |
Definition at line 459 of file cx231xx-reg.h.
#define FLD_FDL_INT 0x08000000 |
Definition at line 845 of file cx231xx-reg.h.
#define FLD_FDL_INT_DIS 0x00080000 |
Definition at line 853 of file cx231xx-reg.h.
#define FLD_FI_BIST_INTR_L 0x0000100 |
Definition at line 226 of file cx231xx-reg.h.
#define FLD_FI_BIST_INTR_R 0x0000200 |
Definition at line 225 of file cx231xx-reg.h.
#define FLD_FIELD 0x00001000 |
Definition at line 337 of file cx231xx-reg.h.
#define FLD_FIELD_CNT 0x00f00000 |
Definition at line 736 of file cx231xx-reg.h.
#define FLD_FIELD_COUNT_FLD 0x000003ff |
Definition at line 609 of file cx231xx-reg.h.
#define FLD_FIELD_PHASE_DELAY 0x0000ff00 |
Definition at line 767 of file cx231xx-reg.h.
#define FLD_FIELD_PHASE_LENGTH 0x01ff0000 |
Definition at line 765 of file cx231xx-reg.h.
#define FLD_FIELD_PHASE_LIMIT 0x000000f0 |
Definition at line 768 of file cx231xx-reg.h.
#define FLD_FIFO_LF_EN 0x000000fc |
Definition at line 1334 of file cx231xx-reg.h.
#define FLD_FLT_BYP_SEL 0x00000001 |
Definition at line 131 of file cx231xx-reg.h.
#define FLD_FLTRN_BIST_FAIL_H 0x00180000 |
Definition at line 253 of file cx231xx-reg.h.
#define FLD_FLTRN_BIST_TEST_H 0x00020000 |
Definition at line 242 of file cx231xx-reg.h.
#define FLD_FLTRN_BIST_TST_DONE 0x00000008 |
Definition at line 256 of file cx231xx-reg.h.
#define FLD_FM1_AFC 0x0000ffff |
Definition at line 1506 of file cx231xx-reg.h.
#define FLD_FM1_AFC_RESET 0x00000080 |
Definition at line 915 of file cx231xx-reg.h.
#define FLD_FM1_CORDIC_SHIFT 0x00000007 |
Definition at line 918 of file cx231xx-reg.h.
#define FLD_FM1_DAGC_OUT 0x00070000 |
Definition at line 1486 of file cx231xx-reg.h.
#define FLD_FM1_DAGC_SHIFT 0x00000038 |
Definition at line 917 of file cx231xx-reg.h.
#define FLD_FM1_DC_FB_SHIFT 0x0000f000 |
Definition at line 913 of file cx231xx-reg.h.
#define FLD_FM1_DC_INT_SHIFT 0x00000f00 |
Definition at line 914 of file cx231xx-reg.h.
#define FLD_FM1_DC_PASS_IN 0x00000040 |
Definition at line 916 of file cx231xx-reg.h.
#define FLD_FM1_DELAY_FIX 0x00007000 |
Definition at line 890 of file cx231xx-reg.h.
#define FLD_FM1_DFT 0x0003ffff |
Definition at line 1461 of file cx231xx-reg.h.
#define FLD_FM1_DFT_AVG 0x00000070 |
Definition at line 1452 of file cx231xx-reg.h.
#define FLD_FM1_DFT_CMP_CTL 0x00000080 |
Definition at line 1451 of file cx231xx-reg.h.
#define FLD_FM1_DFT_DONE 0x80000000 |
Definition at line 1458 of file cx231xx-reg.h.
#define FLD_FM1_DFT_START 0x00000001 |
Definition at line 1454 of file cx231xx-reg.h.
#define FLD_FM1_DFT_TH_CMP 0x00010000 |
Definition at line 821 of file cx231xx-reg.h.
#define FLD_FM1_DFT_THRESHOLD 0xffff0000 |
Definition at line 1449 of file cx231xx-reg.h.
#define FLD_FM2_AFC 0xffff0000 |
Definition at line 1505 of file cx231xx-reg.h.
#define FLD_FM2_AFC_RESET 0x00800000 |
Definition at line 909 of file cx231xx-reg.h.
#define FLD_FM2_CORDIC_SHIFT 0x00070000 |
Definition at line 912 of file cx231xx-reg.h.
#define FLD_FM2_DAGC_OUT 0x07000000 |
Definition at line 1484 of file cx231xx-reg.h.
#define FLD_FM2_DAGC_SHIFT 0x00380000 |
Definition at line 911 of file cx231xx-reg.h.
#define FLD_FM2_DC_FB_SHIFT 0xf0000000 |
Definition at line 907 of file cx231xx-reg.h.
#define FLD_FM2_DC_INT_SHIFT 0x0f000000 |
Definition at line 908 of file cx231xx-reg.h.
#define FLD_FM2_DC_PASS_IN 0x00400000 |
Definition at line 910 of file cx231xx-reg.h.
#define FLD_FM2_DFT 0x0003ffff |
Definition at line 1477 of file cx231xx-reg.h.
#define FLD_FM2_DFT_AVG 0x00000070 |
Definition at line 1468 of file cx231xx-reg.h.
#define FLD_FM2_DFT_CMP_CTL 0x00000080 |
Definition at line 1467 of file cx231xx-reg.h.
#define FLD_FM2_DFT_DONE 0x80000000 |
Definition at line 1474 of file cx231xx-reg.h.
#define FLD_FM2_DFT_START 0x00000001 |
Definition at line 1470 of file cx231xx-reg.h.
#define FLD_FM2_DFT_TH_CMP 0x00020000 |
Definition at line 820 of file cx231xx-reg.h.
#define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 |
Definition at line 1476 of file cx231xx-reg.h.
#define FLD_FM2_DFT_THRESHOLD 0xffff0000 |
Definition at line 1465 of file cx231xx-reg.h.
#define FLD_FM_DFT_TH_CMP 0x00040000 |
Definition at line 1460 of file cx231xx-reg.h.
#define FLD_FM_DIFF_OUT 0x7fff0000 |
Definition at line 1155 of file cx231xx-reg.h.
#define FLD_FMBYPASS_MODE1 0x00000004 |
Definition at line 896 of file cx231xx-reg.h.
#define FLD_FMBYPASS_MODE2 0x00000008 |
Definition at line 895 of file cx231xx-reg.h.
#define FLD_FMT_CHANGE_MSK 0x00400000 |
Definition at line 357 of file cx231xx-reg.h.
#define FLD_FMT_CHANGE_STAT 0x00000040 |
Definition at line 373 of file cx231xx-reg.h.
#define FLD_FORCE_CHIP_SEL 0x80 |
Definition at line 54 of file cx231xx-reg.h.
#define FLD_FUNC_MODE 0x01800000 |
Definition at line 100 of file cx231xx-reg.h.
#define FLD_GS1_DAT_AVAIL_MSK 0x10000000 |
Definition at line 351 of file cx231xx-reg.h.
#define FLD_GS1_DAT_AVAIL_STAT 0x00001000 |
Definition at line 367 of file cx231xx-reg.h.
#define FLD_GS1_FIFO_DAT 0xFF000000 |
Definition at line 487 of file cx231xx-reg.h.
#define FLD_GS1_FIFO_RST 0x00020000 |
Definition at line 478 of file cx231xx-reg.h.
#define FLD_GS1_STAT 0x00FF0000 |
Definition at line 488 of file cx231xx-reg.h.
#define FLD_GS2_DAT_AVAIL_MSK 0x20000000 |
Definition at line 350 of file cx231xx-reg.h.
#define FLD_GS2_DAT_AVAIL_STAT 0x00002000 |
Definition at line 366 of file cx231xx-reg.h.
#define FLD_GS2_FIFO_DAT 0x0000ff00 |
Definition at line 496 of file cx231xx-reg.h.
#define FLD_GS2_FIFO_RST 0x00040000 |
Definition at line 477 of file cx231xx-reg.h.
#define FLD_GS2_STAT 0x000000ff |
Definition at line 497 of file cx231xx-reg.h.
#define FLD_HACTIVE_CNT 0x003ff000 |
Definition at line 572 of file cx231xx-reg.h.
#define FLD_HAMMING_TYPE 0x0f000000 |
Definition at line 474 of file cx231xx-reg.h.
#define FLD_HBLANK_CNT 0x000003ff |
Definition at line 574 of file cx231xx-reg.h.
#define FLD_HEAD_SW_DET_LIMIT 0x0000000f |
Definition at line 769 of file cx231xx-reg.h.
#define FLD_HFILT 0x03000000 |
Definition at line 396 of file cx231xx-reg.h.
#define FLD_HLOCK 0x00010000 |
Definition at line 333 of file cx231xx-reg.h.
#define FLD_HLOCK_CHANGE_MSK 0x00100000 |
Definition at line 359 of file cx231xx-reg.h.
#define FLD_HLOCK_CHANGE_STAT 0x00000010 |
Definition at line 375 of file cx231xx-reg.h.
#define FLD_HLOCK_DIS 0x40000000 |
Definition at line 729 of file cx231xx-reg.h.
#define FLD_HR32 0x00000800 |
Definition at line 619 of file cx231xx-reg.h.
#define FLD_HSCALE 0x00ffffff |
Definition at line 397 of file cx231xx-reg.h.
#define FLD_HSFMT 0x00001000 |
Definition at line 297 of file cx231xx-reg.h.
#define FLD_HTL_15K_EN 0x00020000 |
Definition at line 668 of file cx231xx-reg.h.
#define FLD_HTL_500K_EN 0x00010000 |
Definition at line 669 of file cx231xx-reg.h.
#define FLD_HTL_KD 0x0000ff00 |
Definition at line 670 of file cx231xx-reg.h.
#define FLD_HTL_KI 0x000000ff |
Definition at line 671 of file cx231xx-reg.h.
#define FLD_HUE 0x00ff0000 |
Definition at line 416 of file cx231xx-reg.h.
#define FLD_I2S_IN_BCN_DEL 0x0000001f |
Definition at line 1410 of file cx231xx-reg.h.
#define FLD_I2S_IN_MASTER_MODE 0x00000100 |
Definition at line 1406 of file cx231xx-reg.h.
#define FLD_I2S_IN_RIGHT_JUST 0x00000040 |
Definition at line 1408 of file cx231xx-reg.h.
#define FLD_I2S_IN_SHIFT 0x0f000000 |
Definition at line 1241 of file cx231xx-reg.h.
#define FLD_I2S_IN_SONY_MODE 0x00000080 |
Definition at line 1407 of file cx231xx-reg.h.
#define FLD_I2S_IN_WS_SEL 0x00000020 |
Definition at line 1409 of file cx231xx-reg.h.
#define FLD_I2S_OUT_BCN_DEL 0x0000001f |
Definition at line 1421 of file cx231xx-reg.h.
#define FLD_I2S_OUT_MASTER_MODE 0x00000100 |
Definition at line 1417 of file cx231xx-reg.h.
#define FLD_I2S_OUT_RIGHT_JUST 0x00000040 |
Definition at line 1419 of file cx231xx-reg.h.
#define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000 |
Definition at line 1415 of file cx231xx-reg.h.
#define FLD_I2S_OUT_SONY_MODE 0x00000080 |
Definition at line 1418 of file cx231xx-reg.h.
#define FLD_I2S_OUT_SRC 0x00000040 |
Definition at line 183 of file cx231xx-reg.h.
#define FLD_I2S_OUT_WS_SEL 0x00000020 |
Definition at line 1420 of file cx231xx-reg.h.
#define FLD_I2S_PORT_DIR 0x00000080 |
Definition at line 182 of file cx231xx-reg.h.
#define FLD_I2S_SRC_SEL 0x00000030 |
Definition at line 1397 of file cx231xx-reg.h.
#define FLD_I2S_UP2X_BW20K 0x00000400 |
Definition at line 1404 of file cx231xx-reg.h.
#define FLD_I2S_UP2X_BYPASS 0x00000200 |
Definition at line 1405 of file cx231xx-reg.h.
#define FLD_IDID0_LSB 0x00030000 |
Definition at line 320 of file cx231xx-reg.h.
#define FLD_IDID0_MSB 0x000000ff |
Definition at line 322 of file cx231xx-reg.h.
#define FLD_IDID0_SOURCE 0x00020000 |
Definition at line 293 of file cx231xx-reg.h.
#define FLD_IDID1_LSB 0x000c0000 |
Definition at line 319 of file cx231xx-reg.h.
#define FLD_IDID1_MSB 0x0000ff00 |
Definition at line 321 of file cx231xx-reg.h.
#define FLD_IF_SRC_MODE 0x01000000 |
Definition at line 882 of file cx231xx-reg.h.
#define FLD_IF_SRC_PHASE_INC 0x0001ffff |
Definition at line 884 of file cx231xx-reg.h.
#define FLD_IFL_INT 0x10000000 |
Definition at line 844 of file cx231xx-reg.h.
#define FLD_IFL_INT_DIS 0x00100000 |
Definition at line 852 of file cx231xx-reg.h.
#define FLD_INPUT_MODE 0x00000600 |
Definition at line 277 of file cx231xx-reg.h.
#define FLD_INTG_CH1 0x7fffffff |
Definition at line 144 of file cx231xx-reg.h.
#define FLD_INTG_CH2 0x7fffffff |
Definition at line 150 of file cx231xx-reg.h.
#define FLD_INTG_CH3 0x7fffffff |
Definition at line 156 of file cx231xx-reg.h.
#define FLD_INV_SPEC_DIS 0x00000200 |
Definition at line 106 of file cx231xx-reg.h.
#define FLD_IR_IRQ_STAT 0x40000000 |
Definition at line 165 of file cx231xx-reg.h.
#define FLD_IRQ_N_OUT_EN 0x02000000 |
Definition at line 169 of file cx231xx-reg.h.
#define FLD_IRQ_N_POLAR 0x01000000 |
Definition at line 170 of file cx231xx-reg.h.
#define FLD_ISO_CTL_EN 0x20000000 |
Definition at line 238 of file cx231xx-reg.h.
#define FLD_ISO_CTL_SEL 0x40000000 |
Definition at line 237 of file cx231xx-reg.h.
#define FLD_LBIST_EN 0x10000000 |
Definition at line 223 of file cx231xx-reg.h.
#define FLD_LCOMB_2LN_EN 0x02000000 |
Definition at line 592 of file cx231xx-reg.h.
#define FLD_LCOMB_3D_EN 0x01000000 |
Definition at line 593 of file cx231xx-reg.h.
#define FLD_LCOMB_3LN_EN 0x04000000 |
Definition at line 591 of file cx231xx-reg.h.
#define FLD_LCOMB_ERR_LIMIT 0x000000ff |
Definition at line 678 of file cx231xx-reg.h.
#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff |
Definition at line 752 of file cx231xx-reg.h.
#define FLD_LINE_AVG_DIS 0x01000000 |
Definition at line 401 of file cx231xx-reg.h.
#define FLD_LOCK_IND_INT 0x00200000 |
Definition at line 816 of file cx231xx-reg.h.
#define FLD_LOOP_FILTER_COEF1 0x0000ffff |
Definition at line 1341 of file cx231xx-reg.h.
#define FLD_LOOP_FILTER_COEF2 0xffff0000 |
Definition at line 1340 of file cx231xx-reg.h.
#define FLD_LPF160_COEF_SELA 0x00000c00 |
Definition at line 932 of file cx231xx-reg.h.
#define FLD_LPF160_COEF_SELB 0x00003000 |
Definition at line 931 of file cx231xx-reg.h.
#define FLD_LPF160_COEF_SELC 0x0000c000 |
Definition at line 930 of file cx231xx-reg.h.
#define FLD_LPF160_IN_EN_REG 0x00000300 |
Definition at line 933 of file cx231xx-reg.h.
#define FLD_LPF160_SHIFTA 0x03000000 |
Definition at line 925 of file cx231xx-reg.h.
#define FLD_LPF160_SHIFTB 0x00c00000 |
Definition at line 926 of file cx231xx-reg.h.
#define FLD_LPF160_SHIFTC 0x00300000 |
Definition at line 927 of file cx231xx-reg.h.
#define FLD_LPF32_COEF_SEL1 0x00030000 |
Definition at line 929 of file cx231xx-reg.h.
#define FLD_LPF32_COEF_SEL2 0x000c0000 |
Definition at line 928 of file cx231xx-reg.h.
#define FLD_LPF32_SHIFT1 0x30000000 |
Definition at line 923 of file cx231xx-reg.h.
#define FLD_LPF32_SHIFT2 0x0c000000 |
Definition at line 924 of file cx231xx-reg.h.
#define FLD_LPF_MIN 0x0000ffff |
Definition at line 138 of file cx231xx-reg.h.
#define FLD_LUMA_CORE_SEL 0x00c00000 |
Definition at line 386 of file cx231xx-reg.h.
#define FLD_LUMA_IN_SEL 0x00002000 |
Definition at line 103 of file cx231xx-reg.h.
#define FLD_LUMA_LPF_SEL 0x00c00000 |
Definition at line 594 of file cx231xx-reg.h.
#define FLD_LUMA_RST_MSK 0x00000020 |
Definition at line 701 of file cx231xx-reg.h.
#define FLD_LUMA_THRESHOLD 0x0000ff00 |
Definition at line 677 of file cx231xx-reg.h.
#define FLD_MAJ_SEL 0x000c0000 |
Definition at line 685 of file cx231xx-reg.h.
#define FLD_MAJ_SEL_EN 0x00100000 |
Definition at line 684 of file cx231xx-reg.h.
#define FLD_MAN_FAST_LOCK 0x00040000 |
Definition at line 667 of file cx231xx-reg.h.
#define FLD_MAN_SC_FAST_LOCK 0x00000800 |
Definition at line 276 of file cx231xx-reg.h.
#define FLD_MOD_DET_STATUS0 0x000000ff |
Definition at line 788 of file cx231xx-reg.h.
#define FLD_MOD_DET_STATUS1 0x0000ff00 |
Definition at line 787 of file cx231xx-reg.h.
#define FLD_MODE10B 0x00000004 |
Definition at line 307 of file cx231xx-reg.h.
#define FLD_MOJI_PACK_DIS 0x00000020 |
Definition at line 466 of file cx231xx-reg.h.
#define FLD_MTS_GAIN 0x00003fff |
Definition at line 1493 of file cx231xx-reg.h.
#define FLD_MTS_PDF_SHIFT 0x00001800 |
Definition at line 1023 of file cx231xx-reg.h.
#define FLD_MUX10_SEL 0x00004000 |
Definition at line 1041 of file cx231xx-reg.h.
#define FLD_MUX11_SEL 0x00018000 |
Definition at line 1040 of file cx231xx-reg.h.
#define FLD_MUX12_SEL 0x00020000 |
Definition at line 1039 of file cx231xx-reg.h.
#define FLD_MUX13_SEL 0x000C0000 |
Definition at line 1038 of file cx231xx-reg.h.
#define FLD_MUX14_SEL 0x00300000 |
Definition at line 1037 of file cx231xx-reg.h.
#define FLD_MUX15_SEL 0x00400000 |
Definition at line 1036 of file cx231xx-reg.h.
#define FLD_MUX16_SEL 0x00800000 |
Definition at line 1035 of file cx231xx-reg.h.
#define FLD_MUX17_SEL 0x01000000 |
Definition at line 1034 of file cx231xx-reg.h.
#define FLD_MUX18_SEL 0x02000000 |
Definition at line 1033 of file cx231xx-reg.h.
#define FLD_MUX19_SEL 0x04000000 |
Definition at line 1032 of file cx231xx-reg.h.
#define FLD_MUX1_SEL 0x00000003 |
Definition at line 1050 of file cx231xx-reg.h.
#define FLD_MUX20_SEL 0x08000000 |
Definition at line 1031 of file cx231xx-reg.h.
#define FLD_MUX21_SEL 0x10000000 |
Definition at line 1030 of file cx231xx-reg.h.
#define FLD_MUX2_SEL 0x0000000c |
Definition at line 1049 of file cx231xx-reg.h.
#define FLD_MUX3_SEL 0x00000030 |
Definition at line 1048 of file cx231xx-reg.h.
#define FLD_MUX4_SEL 0x000000c0 |
Definition at line 1047 of file cx231xx-reg.h.
#define FLD_MUX5_SEL 0x00000100 |
Definition at line 1046 of file cx231xx-reg.h.
#define FLD_MUX6_SEL 0x00000600 |
Definition at line 1045 of file cx231xx-reg.h.
#define FLD_MUX7_SEL 0x00000800 |
Definition at line 1044 of file cx231xx-reg.h.
#define FLD_MUX8_SEL 0x00001000 |
Definition at line 1043 of file cx231xx-reg.h.
#define FLD_MUX9_SEL 0x00002000 |
Definition at line 1042 of file cx231xx-reg.h.
#define FLD_MV_CDAT 0x00000003 |
Definition at line 344 of file cx231xx-reg.h.
#define FLD_MV_CHANGE_MSK 0x02000000 |
Definition at line 354 of file cx231xx-reg.h.
#define FLD_MV_CHANGE_STAT 0x00000200 |
Definition at line 370 of file cx231xx-reg.h.
#define FLD_MV_CS 0x00000020 |
Definition at line 341 of file cx231xx-reg.h.
#define FLD_MV_PSP 0x00000010 |
Definition at line 342 of file cx231xx-reg.h.
#define FLD_MV_T3CS 0x00000040 |
Definition at line 340 of file cx231xx-reg.h.
#define FLD_MV_TYPE2_PAIR 0x00000080 |
Definition at line 339 of file cx231xx-reg.h.
#define FLD_MVDET_RST_MSK 0x00000200 |
Definition at line 697 of file cx231xx-reg.h.
#define FLD_NBER_INT 0x40000000 |
Definition at line 842 of file cx231xx-reg.h.
#define FLD_NBER_INT_DIS 0x00400000 |
Definition at line 850 of file cx231xx-reg.h.
#define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000 |
Definition at line 811 of file cx231xx-reg.h.
#define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800 |
Definition at line 826 of file cx231xx-reg.h.
#define FLD_NICAM_CIB 0x000c0000 |
Definition at line 1232 of file cx231xx-reg.h.
#define FLD_NICAM_LOCK 0x04000000 |
Definition at line 812 of file cx231xx-reg.h.
#define FLD_NICAM_LOCK_EN 0x00000400 |
Definition at line 827 of file cx231xx-reg.h.
#define FLD_NICAM_LOCK_STAT 0x00020000 |
Definition at line 1233 of file cx231xx-reg.h.
#define FLD_NICAM_MODE 0x00000002 |
Definition at line 897 of file cx231xx-reg.h.
#define FLD_NICAM_MUTE 0x00010000 |
Definition at line 1234 of file cx231xx-reg.h.
#define FLD_NICAM_UNLOCK 0x02000000 |
Definition at line 813 of file cx231xx-reg.h.
#define FLD_NICAM_UNLOCK_EN 0x00000200 |
Definition at line 828 of file cx231xx-reg.h.
#define FLD_NICAMADDIT_DATA 0x0000ffe0 |
Definition at line 1235 of file cx231xx-reg.h.
#define FLD_NICAMCNTRL 0x0000001f |
Definition at line 1236 of file cx231xx-reg.h.
#define FLD_NLL_INT 0x20000000 |
Definition at line 843 of file cx231xx-reg.h.
#define FLD_NLL_INT_DIS 0x00200000 |
Definition at line 851 of file cx231xx-reg.h.
#define FLD_OE_AGC_IF 0x00000004 |
Definition at line 175 of file cx231xx-reg.h.
#define FLD_OE_AGC_IFVGA 0x00000002 |
Definition at line 176 of file cx231xx-reg.h.
#define FLD_OE_AGC_RF 0x00000001 |
Definition at line 177 of file cx231xx-reg.h.
#define FLD_OE_AUX_PLL_CLK 0x00000020 |
Definition at line 172 of file cx231xx-reg.h.
#define FLD_OE_I2S_BCLK 0x00000010 |
Definition at line 173 of file cx231xx-reg.h.
#define FLD_OE_I2S_WCLK 0x00000008 |
Definition at line 174 of file cx231xx-reg.h.
#define FLD_OEF_AGC_IF 0x00000004 |
Definition at line 163 of file cx231xx-reg.h.
#define FLD_OEF_AGC_IFVGA 0x00000002 |
Definition at line 162 of file cx231xx-reg.h.
#define FLD_OEF_AGC_RF 0x00000001 |
Definition at line 161 of file cx231xx-reg.h.
#define FLD_OUT_MODE 0x00000003 |
Definition at line 308 of file cx231xx-reg.h.
#define FLD_PARALLEL1_SRC_SEL 0x00000003 |
Definition at line 1399 of file cx231xx-reg.h.
#define FLD_PARALLEL2_SRC_SEL 0x0000000c |
Definition at line 1398 of file cx231xx-reg.h.
#define FLD_PASS_LINE_CTRL 0x000fffff |
Definition at line 758 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_AT 0x0000f000 |
Definition at line 1258 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_CG 0x00300000 |
Definition at line 1256 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_CR 0x00000700 |
Definition at line 1260 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_RMS_CON 0x000000f0 |
Definition at line 1261 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_RT 0x000f0000 |
Definition at line 1257 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_STEREO 0x00000800 |
Definition at line 1259 of file cx231xx-reg.h.
#define FLD_PATH1_AVC_THRESHOLD 0x7fff0000 |
Definition at line 1266 of file cx231xx-reg.h.
#define FLD_PATH1_BAL_LEFT 0x00008000 |
Definition at line 1267 of file cx231xx-reg.h.
#define FLD_PATH1_BAL_LEVEL 0x00007f00 |
Definition at line 1268 of file cx231xx-reg.h.
#define FLD_PATH1_EQ_BAND_SEL 0x00000001 |
Definition at line 1280 of file cx231xx-reg.h.
#define FLD_PATH1_EQ_BASS_VOL 0x00003f00 |
Definition at line 1278 of file cx231xx-reg.h.
#define FLD_PATH1_EQ_MID_VOL 0x003f0000 |
Definition at line 1276 of file cx231xx-reg.h.
#define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000 |
Definition at line 1274 of file cx231xx-reg.h.
#define FLD_PATH1_MUTE_CTL 0x1f000000 |
Definition at line 1254 of file cx231xx-reg.h.
#define FLD_PATH1_SC_AT 0x00000f00 |
Definition at line 1286 of file cx231xx-reg.h.
#define FLD_PATH1_SC_CR 0x00000070 |
Definition at line 1288 of file cx231xx-reg.h.
#define FLD_PATH1_SC_RMS_CON 0x0000000f |
Definition at line 1289 of file cx231xx-reg.h.
#define FLD_PATH1_SC_RT 0x0000f000 |
Definition at line 1285 of file cx231xx-reg.h.
#define FLD_PATH1_SC_STEREO 0x00000080 |
Definition at line 1287 of file cx231xx-reg.h.
#define FLD_PATH1_SC_THRESHOLD 0x7fff0000 |
Definition at line 1284 of file cx231xx-reg.h.
#define FLD_PATH1_SEL_CTL 0x0000000f |
Definition at line 1262 of file cx231xx-reg.h.
#define FLD_PATH1_VOLUME 0x000000ff |
Definition at line 1269 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_AT 0x0000f000 |
Definition at line 1298 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_CG 0x00300000 |
Definition at line 1296 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_CR 0x00000700 |
Definition at line 1300 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_RMS_CON 0x000000f0 |
Definition at line 1301 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_RT 0x000f0000 |
Definition at line 1297 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_STEREO 0x00000800 |
Definition at line 1299 of file cx231xx-reg.h.
#define FLD_PATH2_AVC_THRESHOLD 0xffff0000 |
Definition at line 1306 of file cx231xx-reg.h.
#define FLD_PATH2_BAL_LEFT 0x00008000 |
Definition at line 1307 of file cx231xx-reg.h.
#define FLD_PATH2_BAL_LEVEL 0x00007f00 |
Definition at line 1308 of file cx231xx-reg.h.
#define FLD_PATH2_EQ_BAND_SEL 0x00000001 |
Definition at line 1320 of file cx231xx-reg.h.
#define FLD_PATH2_EQ_BASS_VOL 0x00003f00 |
Definition at line 1318 of file cx231xx-reg.h.
#define FLD_PATH2_EQ_MID_VOL 0x003f0000 |
Definition at line 1316 of file cx231xx-reg.h.
#define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000 |
Definition at line 1314 of file cx231xx-reg.h.
#define FLD_PATH2_MUTE_CTL 0x03000000 |
Definition at line 1294 of file cx231xx-reg.h.
#define FLD_PATH2_SC_AT 0x00000f00 |
Definition at line 1326 of file cx231xx-reg.h.
#define FLD_PATH2_SC_CR 0x00000070 |
Definition at line 1328 of file cx231xx-reg.h.
#define FLD_PATH2_SC_RMS_CON 0x0000000f |
Definition at line 1329 of file cx231xx-reg.h.
#define FLD_PATH2_SC_RT 0x0000f000 |
Definition at line 1325 of file cx231xx-reg.h.
#define FLD_PATH2_SC_STEREO 0x00000080 |
Definition at line 1327 of file cx231xx-reg.h.
#define FLD_PATH2_SC_THRESHOLD 0xffff0000 |
Definition at line 1324 of file cx231xx-reg.h.
#define FLD_PATH2_SEL_CTL 0x0000000f |
Definition at line 1302 of file cx231xx-reg.h.
#define FLD_PATH2_VOLUME 0x000000ff |
Definition at line 1309 of file cx231xx-reg.h.
#define FLD_PDF1_PDF_SEL 0x00000003 |
Definition at line 937 of file cx231xx-reg.h.
#define FLD_PDF1_SHIFT 0x00000030 |
Definition at line 894 of file cx231xx-reg.h.
#define FLD_PDF2_PDF_SEL 0x0000000c |
Definition at line 936 of file cx231xx-reg.h.
#define FLD_PDF2_SHIFT 0x000000c0 |
Definition at line 893 of file cx231xx-reg.h.
#define FLD_PDF3_PDF_SEL 0x00000030 |
Definition at line 935 of file cx231xx-reg.h.
#define FLD_PDF3_SHIFT 0x00000300 |
Definition at line 892 of file cx231xx-reg.h.
#define FLD_PDF4_PDF_SEL 0x000000c0 |
Definition at line 934 of file cx231xx-reg.h.
#define FLD_PDF4_SHIFT 0x00000c00 |
Definition at line 891 of file cx231xx-reg.h.
#define FLD_PEAK_EN 0x00040000 |
Definition at line 389 of file cx231xx-reg.h.
#define FLD_PEAK_SEL 0x00030000 |
Definition at line 390 of file cx231xx-reg.h.
#define FLD_PH_CH_SEL 0x00000010 |
Definition at line 1248 of file cx231xx-reg.h.
#define FLD_PH_DBX_SEL 0x00000020 |
Definition at line 1247 of file cx231xx-reg.h.
#define FLD_PHASE_FIX 0x0000000f |
Definition at line 1249 of file cx231xx-reg.h.
#define FLD_PHASE_SHIFT 0x000007ff |
Definition at line 1060 of file cx231xx-reg.h.
#define FLD_PLL_KD 0xff000000 |
Definition at line 659 of file cx231xx-reg.h.
#define FLD_PLL_KI 0x00ff0000 |
Definition at line 660 of file cx231xx-reg.h.
#define FLD_PLL_LOCK_THR 0x00ff0000 |
Definition at line 1067 of file cx231xx-reg.h.
#define FLD_PLL_MAX_OFFSET 0x0000ffff |
Definition at line 661 of file cx231xx-reg.h.
#define FLD_PLL_PILOT_DET 0x00000001 |
Definition at line 1073 of file cx231xx-reg.h.
#define FLD_PLL_SHIFT_REG 0x00007000 |
Definition at line 1059 of file cx231xx-reg.h.
#define FLD_PLL_STATUS 0x07000000 |
Definition at line 1057 of file cx231xx-reg.h.
#define FLD_PLL_UNLOCK_THR 0xff000000 |
Definition at line 1066 of file cx231xx-reg.h.
#define FLD_POLAR 0x7f000000 |
Definition at line 287 of file cx231xx-reg.h.
#define FLD_PREF_DEC_MODE 0x0000ff00 |
Definition at line 802 of file cx231xx-reg.h.
#define FLD_PREFETCH_EN 0x10 |
Definition at line 56 of file cx231xx-reg.h.
#define FLD_PSP_LINES_SEL 0x01000000 |
Definition at line 735 of file cx231xx-reg.h.
#define FLD_PSP_LLIMW 0x00007f00 |
Definition at line 715 of file cx231xx-reg.h.
#define FLD_PSP_SPEC_SEL 0x02000000 |
Definition at line 734 of file cx231xx-reg.h.
#define FLD_PSP_SPEC_VAL 0x000000ff |
Definition at line 724 of file cx231xx-reg.h.
#define FLD_PSP_STOP_LINE 0x1f000000 |
Definition at line 711 of file cx231xx-reg.h.
#define FLD_PSP_STRT_LINE 0x001f0000 |
Definition at line 713 of file cx231xx-reg.h.
#define FLD_PSP_ULIMW 0x0000007f |
Definition at line 717 of file cx231xx-reg.h.
#define FLD_RANGE 0x00300000 |
Definition at line 387 of file cx231xx-reg.h.
#define FLD_RDS_I 0x0000ffff |
Definition at line 1497 of file cx231xx-reg.h.
#define FLD_RDS_INT 0x80000000 |
Definition at line 841 of file cx231xx-reg.h.
#define FLD_RDS_INT_DIS 0x00800000 |
Definition at line 849 of file cx231xx-reg.h.
#define FLD_RDS_Q 0xffff0000 |
Definition at line 1496 of file cx231xx-reg.h.
#define FLD_RDS_READY 0x20000000 |
Definition at line 809 of file cx231xx-reg.h.
#define FLD_RDS_READY_EN 0x00002000 |
Definition at line 824 of file cx231xx-reg.h.
#define FLD_REF_DIV_PLL 0x02 |
Definition at line 80 of file cx231xx-reg.h.
#define FLD_REF_SEL_PLL1 0x01 |
Definition at line 81 of file cx231xx-reg.h.
#define FLD_REG_BO_PUD 0x80000000 |
Definition at line 164 of file cx231xx-reg.h.
#define FLD_REG_RST_MSK 0x00000800 |
Definition at line 695 of file cx231xx-reg.h.
#define FLD_REV_ID 0x000000ff |
Definition at line 745 of file cx231xx-reg.h.
#define FLD_REV_NUM 0x0000ff00 |
Definition at line 857 of file cx231xx-reg.h.
#define FLD_RND_MODE 0x00600000 |
Definition at line 289 of file cx231xx-reg.h.
#define FLD_ROT1_PHACC_PROG 0xffff0000 |
Definition at line 888 of file cx231xx-reg.h.
#define FLD_ROT1_PHASE_CTL 0x007f8000 |
Definition at line 101 of file cx231xx-reg.h.
#define FLD_ROT2_PHACC_PROG 0x0000ffff |
Definition at line 903 of file cx231xx-reg.h.
#define FLD_ROT3_PHACC_PROG 0xffff0000 |
Definition at line 902 of file cx231xx-reg.h.
#define FLD_SAMPLE_RATE 0x30000000 |
Definition at line 313 of file cx231xx-reg.h.
#define FLD_SC_CONVERGE_THRESH 0x00ff0000 |
Definition at line 750 of file cx231xx-reg.h.
#define FLD_SC_STEP 0x000fffff |
Definition at line 605 of file cx231xx-reg.h.
#define FLD_SCALE_RST_MSK 0x00000080 |
Definition at line 699 of file cx231xx-reg.h.
#define FLD_SEL_FIELD_CNT 0x20000000 |
Definition at line 730 of file cx231xx-reg.h.
#define FLD_SIF_EN 0x00020000 |
Definition at line 90 of file cx231xx-reg.h.
#define FLD_SLEEP 0x01 |
Definition at line 59 of file cx231xx-reg.h.
#define FLD_SOFT_RST 0x00010000 |
Definition at line 91 of file cx231xx-reg.h.
#define FLD_SPARE_CTL0 0xff000000 |
Definition at line 796 of file cx231xx-reg.h.
#define FLD_SPARE_STATUS0 0x00ff0000 |
Definition at line 786 of file cx231xx-reg.h.
#define FLD_SPARE_STATUS1 0xff000000 |
Definition at line 785 of file cx231xx-reg.h.
#define FLD_SPECIAL_PLAY_N 0x00400000 |
Definition at line 327 of file cx231xx-reg.h.
#define FLD_SQ_PIXEL 0x00000010 |
Definition at line 282 of file cx231xx-reg.h.
#define FLD_SRC1_FIFO_RD_TH 0x0f000000 |
Definition at line 1346 of file cx231xx-reg.h.
#define FLD_SRC1_PHASE_INC 0x0003ffff |
Definition at line 1348 of file cx231xx-reg.h.
#define FLD_SRC2_FIFO_RD_TH 0x0f000000 |
Definition at line 1353 of file cx231xx-reg.h.
#define FLD_SRC2_PHASE_INC 0x0003ffff |
Definition at line 1355 of file cx231xx-reg.h.
#define FLD_SRC3_CLK_SEL 0x00030000 |
Definition at line 1394 of file cx231xx-reg.h.
#define FLD_SRC3_FIFO_RD_TH 0x0f000000 |
Definition at line 1360 of file cx231xx-reg.h.
#define FLD_SRC3_IN_SEL 0x000c0000 |
Definition at line 1393 of file cx231xx-reg.h.
#define FLD_SRC3_PHASE_INC 0x0003ffff |
Definition at line 1362 of file cx231xx-reg.h.
#define FLD_SRC4_CLK_SEL 0x00300000 |
Definition at line 1392 of file cx231xx-reg.h.
#define FLD_SRC4_FIFO_RD_TH 0x0f000000 |
Definition at line 1367 of file cx231xx-reg.h.
#define FLD_SRC4_IN_SEL 0x00c00000 |
Definition at line 1391 of file cx231xx-reg.h.
#define FLD_SRC4_PHASE_INC 0x0003ffff |
Definition at line 1369 of file cx231xx-reg.h.
#define FLD_SRC5_CLK_SEL 0x03000000 |
Definition at line 1390 of file cx231xx-reg.h.
#define FLD_SRC5_FIFO_RD_TH 0x0f000000 |
Definition at line 1374 of file cx231xx-reg.h.
#define FLD_SRC5_IN_SEL 0x0c000000 |
Definition at line 1389 of file cx231xx-reg.h.
#define FLD_SRC5_PHASE_INC 0x0003ffff |
Definition at line 1376 of file cx231xx-reg.h.
#define FLD_SRC6_CLK_SEL 0x30000000 |
Definition at line 1388 of file cx231xx-reg.h.
#define FLD_SRC6_FIFO_RD_TH 0x0f000000 |
Definition at line 1381 of file cx231xx-reg.h.
#define FLD_SRC6_IN_SEL 0xc0000000 |
Definition at line 1387 of file cx231xx-reg.h.
#define FLD_SRC6_PHASE_INC 0x0003ffff |
Definition at line 1383 of file cx231xx-reg.h.
#define FLD_SRC_DECIM_RATIO 0x000003ff |
Definition at line 599 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_OFLOW 0x00002000 |
Definition at line 336 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_OFLOW_MSK 0x00010000 |
Definition at line 363 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_OFLOW_STAT 0x00000001 |
Definition at line 379 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_UFLOW 0x00004000 |
Definition at line 335 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_UFLOW_MSK 0x00020000 |
Definition at line 362 of file cx231xx-reg.h.
#define FLD_SRC_FIFO_UFLOW_STAT 0x00000002 |
Definition at line 378 of file cx231xx-reg.h.
#define FLD_SRC_LOCK 0x00020000 |
Definition at line 332 of file cx231xx-reg.h.
#define FLD_SRC_RST_MSK 0x00000004 |
Definition at line 704 of file cx231xx-reg.h.
#define FLD_SRC_SOFT_RESET_REG 0x00000004 |
Definition at line 861 of file cx231xx-reg.h.
#define FLD_SRC_STATUS 0xffffff00 |
Definition at line 1333 of file cx231xx-reg.h.
#define FLD_START_8051 0x10000000 |
Definition at line 778 of file cx231xx-reg.h.
#define FLD_SWAPRAW 0x00000200 |
Definition at line 300 of file cx231xx-reg.h.
#define FLD_SYNC_LOOP_GAIN 0x000000c0 |
Definition at line 652 of file cx231xx-reg.h.
#define FLD_SYNC_TIP_INC 0x0000003f |
Definition at line 689 of file cx231xx-reg.h.
#define FLD_SYNC_TIP_REDUCE 0x00007e00 |
Definition at line 687 of file cx231xx-reg.h.
#define FLD_SYNC_WIDTH_SEL 0x00000600 |
Definition at line 650 of file cx231xx-reg.h.
#define FLD_TAB_EN 0x00001000 |
Definition at line 247 of file cx231xx-reg.h.
#define FLD_TASKBIT_VAL 0x00000020 |
Definition at line 304 of file cx231xx-reg.h.
#define FLD_TDALGN 0x00000400 |
Definition at line 620 of file cx231xx-reg.h.
#define FLD_TDFIELD 0x00000200 |
Definition at line 621 of file cx231xx-reg.h.
#define FLD_TEMPDEC 0x0000003f |
Definition at line 623 of file cx231xx-reg.h.
#define FLD_TRK_DS1_SEL 0x000c0000 |
Definition at line 1098 of file cx231xx-reg.h.
#define FLD_TRK_DS2_SEL 0x00030000 |
Definition at line 1099 of file cx231xx-reg.h.
#define FLD_TRK_KD 0x000000ff |
Definition at line 1101 of file cx231xx-reg.h.
#define FLD_TRK_KI 0x0000ff00 |
Definition at line 1100 of file cx231xx-reg.h.
#define FLD_TSXCLK_POL_CTL 0x80000000 |
Definition at line 236 of file cx231xx-reg.h.
#define FLD_TTX_PKTADRL 0x000fff00 |
Definition at line 464 of file cx231xx-reg.h.
#define FLD_TTX_PKTADRU 0xfff00000 |
Definition at line 463 of file cx231xx-reg.h.
#define FLD_USAT 0x000000ff |
Definition at line 418 of file cx231xx-reg.h.
#define FLD_UV_LPF_SEL 0x00300000 |
Definition at line 595 of file cx231xx-reg.h.
#define FLD_UV_ORDER_MODE 0x02000000 |
Definition at line 99 of file cx231xx-reg.h.
#define FLD_V656BLANK_CNT 0xff000000 |
Definition at line 578 of file cx231xx-reg.h.
#define FLD_VACTIVE_CNT 0x003ff000 |
Definition at line 580 of file cx231xx-reg.h.
#define FLD_VALIDFMT 0x00000800 |
Definition at line 298 of file cx231xx-reg.h.
#define FLD_VBI1_BITINC 0x000fff00 |
Definition at line 504 of file cx231xx-reg.h.
#define FLD_VBI1_CRI_LENGTH 0x0000f000 |
Definition at line 518 of file cx231xx-reg.h.
#define FLD_VBI1_CRI_MARGIN 0x00000f00 |
Definition at line 519 of file cx231xx-reg.h.
#define FLD_VBI1_CRI_TIME 0x000000ff |
Definition at line 520 of file cx231xx-reg.h.
#define FLD_VBI1_CRIWIN 0x7f000000 |
Definition at line 502 of file cx231xx-reg.h.
#define FLD_VBI1_FC_LENGTH 0x1f000000 |
Definition at line 509 of file cx231xx-reg.h.
#define FLD_VBI1_FIFO_MODE 0x70000000 |
Definition at line 515 of file cx231xx-reg.h.
#define FLD_VBI1_FORMAT_TYPE 0x0f000000 |
Definition at line 516 of file cx231xx-reg.h.
#define FLD_VBI1_FRAME_CODE 0x00ffffff |
Definition at line 510 of file cx231xx-reg.h.
#define FLD_VBI1_HAM_EN 0x80000000 |
Definition at line 514 of file cx231xx-reg.h.
#define FLD_VBI1_HDELAY 0x000000ff |
Definition at line 505 of file cx231xx-reg.h.
#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000 |
Definition at line 517 of file cx231xx-reg.h.
#define FLD_VBI1_SDID 0x0000000f |
Definition at line 483 of file cx231xx-reg.h.
#define FLD_VBI1_SLICE_DIST 0x00f00000 |
Definition at line 503 of file cx231xx-reg.h.
#define FLD_VBI2_BITINC 0x000fff00 |
Definition at line 527 of file cx231xx-reg.h.
#define FLD_VBI2_CRI_LENGTH 0x0000f000 |
Definition at line 541 of file cx231xx-reg.h.
#define FLD_VBI2_CRI_MARGIN 0x00000f00 |
Definition at line 542 of file cx231xx-reg.h.
#define FLD_VBI2_CRI_TIME 0x000000ff |
Definition at line 543 of file cx231xx-reg.h.
#define FLD_VBI2_CRIWIN 0x7f000000 |
Definition at line 525 of file cx231xx-reg.h.
#define FLD_VBI2_FC_LENGTH 0x1f000000 |
Definition at line 532 of file cx231xx-reg.h.
#define FLD_VBI2_FIFO_MODE 0x70000000 |
Definition at line 538 of file cx231xx-reg.h.
#define FLD_VBI2_FORMAT_TYPE 0x0f000000 |
Definition at line 539 of file cx231xx-reg.h.
#define FLD_VBI2_FRAME_CODE 0x00ffffff |
Definition at line 533 of file cx231xx-reg.h.
#define FLD_VBI2_HAM_EN 0x80000000 |
Definition at line 537 of file cx231xx-reg.h.
#define FLD_VBI2_HDELAY 0x000000ff |
Definition at line 528 of file cx231xx-reg.h.
#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000 |
Definition at line 540 of file cx231xx-reg.h.
#define FLD_VBI2_SDID 0x000000f0 |
Definition at line 482 of file cx231xx-reg.h.
#define FLD_VBI2_SLICE_DIST 0x00f00000 |
Definition at line 526 of file cx231xx-reg.h.
#define FLD_VBI3_BITINC 0x000fff00 |
Definition at line 550 of file cx231xx-reg.h.
#define FLD_VBI3_CRI_LENGTH 0x0000f000 |
Definition at line 564 of file cx231xx-reg.h.
#define FLD_VBI3_CRI_MARGIN 0x00000f00 |
Definition at line 565 of file cx231xx-reg.h.
#define FLD_VBI3_CRI_TIME 0x000000ff |
Definition at line 566 of file cx231xx-reg.h.
#define FLD_VBI3_CRIWIN 0x7f000000 |
Definition at line 548 of file cx231xx-reg.h.
#define FLD_VBI3_FC_LENGTH 0x1f000000 |
Definition at line 555 of file cx231xx-reg.h.
#define FLD_VBI3_FIFO_MODE 0x70000000 |
Definition at line 561 of file cx231xx-reg.h.
#define FLD_VBI3_FORMAT_TYPE 0x0f000000 |
Definition at line 562 of file cx231xx-reg.h.
#define FLD_VBI3_FRAME_CODE 0x00ffffff |
Definition at line 556 of file cx231xx-reg.h.
#define FLD_VBI3_HAM_EN 0x80000000 |
Definition at line 560 of file cx231xx-reg.h.
#define FLD_VBI3_HDELAY 0x000000ff |
Definition at line 551 of file cx231xx-reg.h.
#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000 |
Definition at line 563 of file cx231xx-reg.h.
#define FLD_VBI3_SDID 0x00000f00 |
Definition at line 481 of file cx231xx-reg.h.
#define FLD_VBI3_SLICE_DIST 0x00f00000 |
Definition at line 549 of file cx231xx-reg.h.
#define FLD_VBI_GATE_EN 0x08000000 |
Definition at line 631 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE1 0x000000ff |
Definition at line 425 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE10 0x0000ff00 |
Definition at line 438 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE11 0x00ff0000 |
Definition at line 437 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE12 0xff000000 |
Definition at line 436 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE13 0x000000ff |
Definition at line 446 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE14 0x0000ff00 |
Definition at line 445 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE15 0x00ff0000 |
Definition at line 444 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE16 0xff000000 |
Definition at line 443 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE17 0x000000ff |
Definition at line 450 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE2 0x0000ff00 |
Definition at line 424 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE3 0x00ff0000 |
Definition at line 423 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE4 0xff000000 |
Definition at line 422 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE5 0x000000ff |
Definition at line 432 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE6 0x0000ff00 |
Definition at line 431 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE7 0x00ff0000 |
Definition at line 430 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE8 0xff000000 |
Definition at line 429 of file cx231xx-reg.h.
#define FLD_VBI_MD_LINE9 0x000000ff |
Definition at line 439 of file cx231xx-reg.h.
#define FLD_VBI_PASS_MD 0x00200000 |
Definition at line 756 of file cx231xx-reg.h.
#define FLD_VBI_RST_MSK 0x00000100 |
Definition at line 698 of file cx231xx-reg.h.
#define FLD_VBI_SETUP_DIS 0x00100000 |
Definition at line 757 of file cx231xx-reg.h.
#define FLD_VBI_VOFFSET 0x1f000000 |
Definition at line 603 of file cx231xx-reg.h.
#define FLD_VBIHACTRAW_EN 0x00000008 |
Definition at line 306 of file cx231xx-reg.h.
#define FLD_VBLANK_CNT 0x000003ff |
Definition at line 582 of file cx231xx-reg.h.
#define FLD_VCR_DETECT 0x00800000 |
Definition at line 326 of file cx231xx-reg.h.
#define FLD_VD_SOFT_RST 0x00008000 |
Definition at line 693 of file cx231xx-reg.h.
#define FLD_VFILT 0x00070000 |
Definition at line 404 of file cx231xx-reg.h.
#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000 |
Definition at line 641 of file cx231xx-reg.h.
#define FLD_VGA_AUTO_EN 0x10000000 |
Definition at line 630 of file cx231xx-reg.h.
#define FLD_VGA_CRUSH_EN 0x20000000 |
Definition at line 629 of file cx231xx-reg.h.
#define FLD_VGA_GAIN 0x0000003f |
Definition at line 637 of file cx231xx-reg.h.
#define FLD_VGA_SEL_CH1 0x00000040 |
Definition at line 109 of file cx231xx-reg.h.
#define FLD_VGA_SEL_CH2 0x00000080 |
Definition at line 108 of file cx231xx-reg.h.
#define FLD_VGA_SEL_CH3 0x00000100 |
Definition at line 107 of file cx231xx-reg.h.
#define FLD_VGA_SYNC 0x000000ff |
Definition at line 643 of file cx231xx-reg.h.
#define FLD_VGA_TRACK_RANGE 0x0000ff00 |
Definition at line 642 of file cx231xx-reg.h.
#define FLD_VID_BIST_FAIL_H 0x00070000 |
Definition at line 254 of file cx231xx-reg.h.
#define FLD_VID_BIST_TEST_H 0x00010000 |
Definition at line 243 of file cx231xx-reg.h.
#define FLD_VID_BIST_TST_DONE 0x00000007 |
Definition at line 257 of file cx231xx-reg.h.
#define FLD_VID_COUNT 0x00ffffff |
Definition at line 194 of file cx231xx-reg.h.
#define FLD_VID_DUAL_FLAG_POL 0x01000000 |
Definition at line 215 of file cx231xx-reg.h.
#define FLD_VID_FMT_SEL 0x0000000f |
Definition at line 283 of file cx231xx-reg.h.
#define FLD_VID_IRQ_STAT 0x10000000 |
Definition at line 167 of file cx231xx-reg.h.
#define FLD_VIDEO_CHANGE 0x40000000 |
Definition at line 808 of file cx231xx-reg.h.
#define FLD_VIDEO_CHANGE_EN 0x00004000 |
Definition at line 823 of file cx231xx-reg.h.
#define FLD_VIDEO_PRESENT 0x00100000 |
Definition at line 800 of file cx231xx-reg.h.
#define FLD_VIDEO_PRESENT_CHANGE 0x80000000 |
Definition at line 807 of file cx231xx-reg.h.
#define FLD_VIDEO_PRESENT_EN 0x00008000 |
Definition at line 822 of file cx231xx-reg.h.
#define FLD_VIP_OPT_AL 0x00040000 |
Definition at line 292 of file cx231xx-reg.h.
#define FLD_VIPBLANK_EN 0x00080000 |
Definition at line 291 of file cx231xx-reg.h.
#define FLD_VIPCLAMP_EN 0x00100000 |
Definition at line 290 of file cx231xx-reg.h.
#define FLD_VLOCK 0x00040000 |
Definition at line 331 of file cx231xx-reg.h.
#define FLD_VLOCK_CHANGE_MSK 0x00080000 |
Definition at line 360 of file cx231xx-reg.h.
#define FLD_VLOCK_CHANGE_STAT 0x00000008 |
Definition at line 376 of file cx231xx-reg.h.
#define FLD_VOF_RST_MSK 0x00000400 |
Definition at line 696 of file cx231xx-reg.h.
#define FLD_VPRES 0x00200000 |
Definition at line 328 of file cx231xx-reg.h.
#define FLD_VPRES_CHANGE_MSK 0x04000000 |
Definition at line 353 of file cx231xx-reg.h.
#define FLD_VPRES_CHANGE_STAT 0x00000400 |
Definition at line 369 of file cx231xx-reg.h.
#define FLD_VPRES_VERT_EN 0x00008000 |
Definition at line 617 of file cx231xx-reg.h.
#define FLD_VPS_DEC_DIS 0x00000010 |
Definition at line 467 of file cx231xx-reg.h.
#define FLD_VS_INTRLACE 0x00080000 |
Definition at line 403 of file cx231xx-reg.h.
#define FLD_VSAT 0x0000ff00 |
Definition at line 417 of file cx231xx-reg.h.
#define FLD_VSCALE 0x00001fff |
Definition at line 406 of file cx231xx-reg.h.
#define FLD_VSYNC_N 0x00008000 |
Definition at line 334 of file cx231xx-reg.h.
#define FLD_VSYNC_TRAIL_MSK 0x00200000 |
Definition at line 358 of file cx231xx-reg.h.
#define FLD_VSYNC_TRAIL_STAT 0x00000020 |
Definition at line 374 of file cx231xx-reg.h.
#define FLD_VT_LINE_CNT_HYST 0x30000000 |
Definition at line 614 of file cx231xx-reg.h.
#define FLD_VTG_RST_MSK 0x00000010 |
Definition at line 702 of file cx231xx-reg.h.
#define FLD_WCEN 0x00008000 |
Definition at line 272 of file cx231xx-reg.h.
#define FLD_WSS_DAT_AVAIL_MSK 0x40000000 |
Definition at line 349 of file cx231xx-reg.h.
#define FLD_WSS_DAT_AVAIL_STAT 0x00004000 |
Definition at line 365 of file cx231xx-reg.h.
#define FLD_WSS_FIFO_DAT 0xff000000 |
Definition at line 494 of file cx231xx-reg.h.
#define FLD_WSS_FIFO_RST 0x00080000 |
Definition at line 476 of file cx231xx-reg.h.
#define FLD_WSS_STAT 0x00ff0000 |
Definition at line 495 of file cx231xx-reg.h.
#define FLD_WTW_EN 0x00400000 |
Definition at line 682 of file cx231xx-reg.h.
#define FLD_XTAL_CTRL 0x70 |
Definition at line 78 of file cx231xx-reg.h.
#define FLD_YC_DLY_LENGTH 0x000000ff |
Definition at line 208 of file cx231xx-reg.h.
#define FLD_YCSEP_RST_MSK 0x00000008 |
Definition at line 703 of file cx231xx-reg.h.
#define FM1_DFT_CTL 0x9a8 |
Definition at line 1448 of file cx231xx-reg.h.
#define FM1_DFT_STATUS 0x9ac |
Definition at line 1457 of file cx231xx-reg.h.
#define FM2_DFT_CTL 0x9b0 |
Definition at line 1464 of file cx231xx-reg.h.
#define FM2_DFT_STATUS 0x9b4 |
Definition at line 1473 of file cx231xx-reg.h.
#define FM_AFC 0x9c8 |
Definition at line 1504 of file cx231xx-reg.h.
#define FM_CTL 0x824 |
Definition at line 906 of file cx231xx-reg.h.
#define FOUR_TAP_FILT 2 |
Definition at line 1547 of file cx231xx-reg.h.
#define GEN_STAT 0x40c |
Definition at line 325 of file cx231xx-reg.h.
#define GENERAL_CTL 0x810 |
Definition at line 840 of file cx231xx-reg.h.
#define GPIO_PIN_CTL0 0x3 |
Definition at line 69 of file cx231xx-reg.h.
#define GPIO_PIN_CTL1 0x4 |
Definition at line 70 of file cx231xx-reg.h.
#define GPIO_PIN_CTL2 0x5 |
Definition at line 71 of file cx231xx-reg.h.
#define GPIO_PIN_CTL3 0x6 |
Definition at line 72 of file cx231xx-reg.h.
#define HORIZ_TIM_CTRL 0x470 |
Definition at line 569 of file cx231xx-reg.h.
#define HOST_REG1 0x000 |
Definition at line 53 of file cx231xx-reg.h.
#define HOST_REG2 0x001 |
Definition at line 62 of file cx231xx-reg.h.
#define HOST_REG3 0x002 |
Definition at line 65 of file cx231xx-reg.h.
#define HSCALE_CTRL 0x418 |
Definition at line 395 of file cx231xx-reg.h.
#define HTL_CTRL 0x498 |
Definition at line 664 of file cx231xx-reg.h.
#define HUE_CTRL_BYTE 0x422 |
Definition at line 412 of file cx231xx-reg.h.
#define I2S_IN_CTL 0x914 |
Definition at line 1402 of file cx231xx-reg.h.
#define I2S_OUT_CTL 0x918 |
Definition at line 1413 of file cx231xx-reg.h.
#define IF_SRC_CTL 0x818 |
Definition at line 879 of file cx231xx-reg.h.
#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ |
Definition at line 1532 of file cx231xx-reg.h.
#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ |
Definition at line 1534 of file cx231xx-reg.h.
#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ |
Definition at line 1533 of file cx231xx-reg.h.
#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ |
Definition at line 1535 of file cx231xx-reg.h.
#define INT_STAT_MASK 0x410 |
Definition at line 347 of file cx231xx-reg.h.
#define LPF_PDF_CTL 0x828 |
Definition at line 921 of file cx231xx-reg.h.
#define LUMA_CTRL 0x414 |
Definition at line 382 of file cx231xx-reg.h.
#define LUMA_CTRL_BYTE_3 0x416 |
Definition at line 385 of file cx231xx-reg.h.
#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ |
Definition at line 1539 of file cx231xx-reg.h.
#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ |
Definition at line 1537 of file cx231xx-reg.h.
#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ |
Definition at line 1538 of file cx231xx-reg.h.
#define MISC_DIAG_CTRL 0x4b8 |
Definition at line 748 of file cx231xx-reg.h.
#define MISC_TIM_CTRL 0x484 |
Definition at line 612 of file cx231xx-reg.h.
#define MODE_CTRL 0x400 |
Definition at line 262 of file cx231xx-reg.h.
#define MTS_GAIN_STATUS 0x9bc |
Definition at line 1491 of file cx231xx-reg.h.
#define MV_DT_CTRL1 0x4a8 |
Definition at line 709 of file cx231xx-reg.h.
#define MV_DT_CTRL2 0x4aC |
Definition at line 720 of file cx231xx-reg.h.
#define MV_DT_CTRL3 0x4B0 |
Definition at line 727 of file cx231xx-reg.h.
#define NEW_SPARE 0x9cc |
Definition at line 1510 of file cx231xx-reg.h.
#define NEW_SPARE_REG 0x9cc |
Definition at line 1511 of file cx231xx-reg.h.
#define NICAM_DEEMPHDENOM1 0x8b0 |
Definition at line 1192 of file cx231xx-reg.h.
#define NICAM_DEEMPHDENOM2 0x8b4 |
Definition at line 1199 of file cx231xx-reg.h.
#define NICAM_DEEMPHGAIN 0x8a4 |
Definition at line 1171 of file cx231xx-reg.h.
#define NICAM_DEEMPHNUMER1 0x8a8 |
Definition at line 1178 of file cx231xx-reg.h.
#define NICAM_DEEMPHNUMER2 0x8ac |
Definition at line 1185 of file cx231xx-reg.h.
#define NICAM_ERRLOG_CTL1 0x8B8 |
Definition at line 1204 of file cx231xx-reg.h.
#define NICAM_ERRLOG_CTL2 0x8bc |
Definition at line 1211 of file cx231xx-reg.h.
#define NICAM_ERRLOG_STS1 0x8c0 |
Definition at line 1218 of file cx231xx-reg.h.
#define NICAM_ERRLOG_STS2 0x8c4 |
Definition at line 1225 of file cx231xx-reg.h.
#define NICAM_FAW 0x8a0 |
Definition at line 1160 of file cx231xx-reg.h.
#define NICAM_STATUS 0x8c8 |
Definition at line 1230 of file cx231xx-reg.h.
#define OUT_CTRL1 0x404 |
Definition at line 286 of file cx231xx-reg.h.
#define OUT_CTRL2 0x408 |
Definition at line 311 of file cx231xx-reg.h.
#define OUT_MODE_601 0 |
Definition at line 1555 of file cx231xx-reg.h.
#define OUT_MODE_656 1 |
Definition at line 1556 of file cx231xx-reg.h.
#define OUT_MODE_VIP11 2 |
Definition at line 1557 of file cx231xx-reg.h.
#define OUT_MODE_VIP20 3 |
Definition at line 1558 of file cx231xx-reg.h.
#define PATH1_CTL1 0x8d0 |
Definition at line 1252 of file cx231xx-reg.h.
#define PATH1_EQ_CTL 0x8d8 |
Definition at line 1272 of file cx231xx-reg.h.
#define PATH1_SC_CTL 0x8dc |
Definition at line 1283 of file cx231xx-reg.h.
#define PATH1_VOL_CTL 0x8d4 |
Definition at line 1265 of file cx231xx-reg.h.
#define PATH2_CTL1 0x8e0 |
Definition at line 1292 of file cx231xx-reg.h.
#define PATH2_EQ_CTL 0x8e8 |
Definition at line 1312 of file cx231xx-reg.h.
#define PATH2_SC_CTL 0x8eC |
Definition at line 1323 of file cx231xx-reg.h.
#define PATH2_VOL_CTL 0x8e4 |
Definition at line 1305 of file cx231xx-reg.h.
#define PHASE_INC_28MHZ 0x010000 |
Definition at line 1562 of file cx231xx-reg.h.
#define PHASE_INC_49MHZ 0x0df22 |
Definition at line 1560 of file cx231xx-reg.h.
#define PHASE_INC_56MHZ 0x0fa5b |
Definition at line 1561 of file cx231xx-reg.h.
#define PIN_CTRL 0x120 |
Definition at line 160 of file cx231xx-reg.h.
#define PLL_CTRL 0x494 |
Definition at line 658 of file cx231xx-reg.h.
#define QPSK_BTL_CTL1 0x958 |
Definition at line 1439 of file cx231xx-reg.h.
#define QPSK_BTL_CTL2 0x95c |
Definition at line 1440 of file cx231xx-reg.h.
#define QPSK_CTL_CTL1 0x960 |
Definition at line 1441 of file cx231xx-reg.h.
#define QPSK_CTL_CTL2 0x964 |
Definition at line 1442 of file cx231xx-reg.h.
#define QPSK_EQ_CTL 0x96c |
Definition at line 1444 of file cx231xx-reg.h.
#define QPSK_FEPR_FREQ 0x954 |
Definition at line 1438 of file cx231xx-reg.h.
#define QPSK_IAGC_CTL1 0x94c |
Definition at line 1436 of file cx231xx-reg.h.
#define QPSK_IAGC_CTL2 0x950 |
Definition at line 1437 of file cx231xx-reg.h.
#define QPSK_LOCK_CTL 0x970 |
Definition at line 1445 of file cx231xx-reg.h.
#define QPSK_MF_FAGC_CTL 0x968 |
Definition at line 1443 of file cx231xx-reg.h.
#define RDS_OUT 0x9c0 |
Definition at line 1495 of file cx231xx-reg.h.
#define ROT_FREQ_CTL 0x820 |
Definition at line 901 of file cx231xx-reg.h.
#define SAV_ACTIVE_VIDEO_FIELD1 0x80 |
Definition at line 29 of file cx231xx-reg.h.
#define SAV_ACTIVE_VIDEO_FIELD2 0xc0 |
Definition at line 32 of file cx231xx-reg.h.
#define SAV_VBI_FIELD1 0x20 |
Definition at line 41 of file cx231xx-reg.h.
#define SAV_VBI_FIELD2 0x60 |
Definition at line 44 of file cx231xx-reg.h.
#define SAV_VBLANK_FIELD1 0xa0 |
Definition at line 35 of file cx231xx-reg.h.
#define SAV_VBLANK_FIELD2 0xe0 |
Definition at line 38 of file cx231xx-reg.h.
#define SOFT_RST_CTRL 0x4a4 |
Definition at line 692 of file cx231xx-reg.h.
#define SRC1_CTL 0x8f8 |
Definition at line 1344 of file cx231xx-reg.h.
#define SRC2_CTL 0x8fc |
Definition at line 1351 of file cx231xx-reg.h.
#define SRC3_CTL 0x900 |
Definition at line 1358 of file cx231xx-reg.h.
#define SRC4_CTL 0x904 |
Definition at line 1365 of file cx231xx-reg.h.
#define SRC5_CTL 0x908 |
Definition at line 1372 of file cx231xx-reg.h.
#define SRC6_CTL 0x90c |
Definition at line 1379 of file cx231xx-reg.h.
#define SRC_COMB_CFG 0x478 |
Definition at line 585 of file cx231xx-reg.h.
#define SRC_CTL 0x8f0 |
Definition at line 1332 of file cx231xx-reg.h.
#define SRC_LF_COEF 0x8f4 |
Definition at line 1339 of file cx231xx-reg.h.
#define STD_DET_CTL 0x808 |
Definition at line 793 of file cx231xx-reg.h.
#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ |
Definition at line 794 of file cx231xx-reg.h.
#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ |
Definition at line 795 of file cx231xx-reg.h.
#define STD_DET_STATUS 0x804 |
Definition at line 784 of file cx231xx-reg.h.
#define TEST_CTRL1 0x144 |
Definition at line 221 of file cx231xx-reg.h.
#define TEST_CTRL2 0x148 |
Definition at line 235 of file cx231xx-reg.h.
#define THREE_TAP_FILT 1 |
Definition at line 1546 of file cx231xx-reg.h.
#define TS1_PIN_CTL0 0x7 |
Definition at line 73 of file cx231xx-reg.h.
#define TS1_PIN_CTL1 0x8 |
Definition at line 74 of file cx231xx-reg.h.
#define TWO_TAP_FILT 0 |
Definition at line 1545 of file cx231xx-reg.h.
#define USAT_CTRL_BYTE 0x420 |
Definition at line 410 of file cx231xx-reg.h.
#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ |
Definition at line 1543 of file cx231xx-reg.h.
#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ |
Definition at line 1541 of file cx231xx-reg.h.
#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ |
Definition at line 1542 of file cx231xx-reg.h.
#define VBI_CUST1_CFG1 0x44c |
Definition at line 500 of file cx231xx-reg.h.
#define VBI_CUST1_CFG2 0x450 |
Definition at line 508 of file cx231xx-reg.h.
#define VBI_CUST1_CFG3 0x454 |
Definition at line 513 of file cx231xx-reg.h.
#define VBI_CUST2_CFG1 0x458 |
Definition at line 523 of file cx231xx-reg.h.
#define VBI_CUST2_CFG2 0x45c |
Definition at line 531 of file cx231xx-reg.h.
#define VBI_CUST2_CFG3 0x460 |
Definition at line 536 of file cx231xx-reg.h.
#define VBI_CUST3_CFG1 0x464 |
Definition at line 546 of file cx231xx-reg.h.
#define VBI_CUST3_CFG2 0x468 |
Definition at line 554 of file cx231xx-reg.h.
#define VBI_CUST3_CFG3 0x46c |
Definition at line 559 of file cx231xx-reg.h.
#define VBI_FC_CFG 0x438 |
Definition at line 453 of file cx231xx-reg.h.
#define VBI_LINE_CTRL1 0x424 |
Definition at line 421 of file cx231xx-reg.h.
#define VBI_LINE_CTRL2 0x428 |
Definition at line 428 of file cx231xx-reg.h.
#define VBI_LINE_CTRL3 0x42c |
Definition at line 435 of file cx231xx-reg.h.
#define VBI_LINE_CTRL4 0x430 |
Definition at line 442 of file cx231xx-reg.h.
#define VBI_LINE_CTRL5 0x434 |
Definition at line 449 of file cx231xx-reg.h.
#define VBI_MISC_CFG1 0x43c |
Definition at line 462 of file cx231xx-reg.h.
#define VBI_MISC_CFG2 0x440 |
Definition at line 473 of file cx231xx-reg.h.
#define VBI_PASS_CTRL 0x4bc |
Definition at line 755 of file cx231xx-reg.h.
#define VBI_PAY1 0x444 |
Definition at line 486 of file cx231xx-reg.h.
#define VBI_PAY2 0x448 |
Definition at line 493 of file cx231xx-reg.h.
#define VCR_DET_CTRL 0x4c0 |
Definition at line 762 of file cx231xx-reg.h.
#define VERSION 0x4b4 |
Definition at line 744 of file cx231xx-reg.h.
#define VERT_TIM_CTRL 0x474 |
Definition at line 577 of file cx231xx-reg.h.
#define VID_FMT_AUTO 0 |
Definition at line 1520 of file cx231xx-reg.h.
#define VID_FMT_NTSC_443 3 |
Definition at line 1523 of file cx231xx-reg.h.
#define VID_FMT_NTSC_J 2 |
Definition at line 1522 of file cx231xx-reg.h.
#define VID_FMT_NTSC_M 1 |
Definition at line 1521 of file cx231xx-reg.h.
#define VID_FMT_PAL_60 8 |
Definition at line 1528 of file cx231xx-reg.h.
#define VID_FMT_PAL_BDGHI 4 |
Definition at line 1524 of file cx231xx-reg.h.
#define VID_FMT_PAL_M 5 |
Definition at line 1525 of file cx231xx-reg.h.
#define VID_FMT_PAL_N 6 |
Definition at line 1526 of file cx231xx-reg.h.
#define VID_FMT_PAL_NC 7 |
Definition at line 1527 of file cx231xx-reg.h.
#define VID_FMT_SECAM 12 |
Definition at line 1529 of file cx231xx-reg.h.
#define VID_FMT_SECAM_60 13 |
Definition at line 1530 of file cx231xx-reg.h.
#define VSAT_CTRL_BYTE 0x421 |
Definition at line 411 of file cx231xx-reg.h.
#define VSCALE_CTRL 0x41c |
Definition at line 400 of file cx231xx-reg.h.