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Macros
cx25821-reg.h File Reference

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Macros

#define RISC_CNT_INC   0x00010000
 
#define RISC_CNT_RESET   0x00030000
 
#define RISC_IRQ1   0x01000000
 
#define RISC_IRQ2   0x02000000
 
#define RISC_EOL   0x04000000
 
#define RISC_SOL   0x08000000
 
#define RISC_WRITE   0x10000000
 
#define RISC_SKIP   0x20000000
 
#define RISC_JUMP   0x70000000
 
#define RISC_SYNC   0x80000000
 
#define RISC_RESYNC   0x80008000
 
#define RISC_READ   0x90000000
 
#define RISC_WRITERM   0xB0000000
 
#define RISC_WRITECM   0xC0000000
 
#define RISC_WRITECR   0xD0000000
 
#define RISC_WRITEC   0x50000000
 
#define RISC_READC   0xA0000000
 
#define RISC_SYNC_ODD   0x00000000
 
#define RISC_SYNC_EVEN   0x00000200
 
#define RISC_SYNC_ODD_VBI   0x00000006
 
#define RISC_SYNC_EVEN_VBI   0x00000207
 
#define RISC_NOOP   0xF0000000
 
#define TX_SRAM   0x000000 /* Transmit SRAM */
 
#define RX_RAM   0x010000 /* Receive SRAM */
 
#define DEV_CNTRL2   0x040000 /* Device control */
 
#define FLD_RUN_RISC   0x00000020
 
#define PCI_INT_MSK   0x040010 /* PCI interrupt mask */
 
#define PCI_INT_STAT   0x040014 /* PCI interrupt status */
 
#define PCI_INT_MSTAT   0x040018 /* PCI interrupt masked status */
 
#define FLD_HAMMERHEAD_INT   (1 << 27)
 
#define FLD_UART_INT   (1 << 26)
 
#define FLD_IRQN_INT   (1 << 25)
 
#define FLD_TM_INT   (1 << 28)
 
#define FLD_I2C_3_RACK   (1 << 27)
 
#define FLD_I2C_3_INT   (1 << 26)
 
#define FLD_I2C_2_RACK   (1 << 25)
 
#define FLD_I2C_2_INT   (1 << 24)
 
#define FLD_I2C_1_RACK   (1 << 23)
 
#define FLD_I2C_1_INT   (1 << 22)
 
#define FLD_APB_DMA_BERR_INT   (1 << 21)
 
#define FLD_AL_WR_BERR_INT   (1 << 20)
 
#define FLD_AL_RD_BERR_INT   (1 << 19)
 
#define FLD_RISC_WR_BERR_INT   (1 << 18)
 
#define FLD_RISC_RD_BERR_INT   (1 << 17)
 
#define FLD_VID_I_INT   (1 << 8)
 
#define FLD_VID_H_INT   (1 << 7)
 
#define FLD_VID_G_INT   (1 << 6)
 
#define FLD_VID_F_INT   (1 << 5)
 
#define FLD_VID_E_INT   (1 << 4)
 
#define FLD_VID_D_INT   (1 << 3)
 
#define FLD_VID_C_INT   (1 << 2)
 
#define FLD_VID_B_INT   (1 << 1)
 
#define FLD_VID_A_INT   (1 << 0)
 
#define VID_A_INT_MSK   0x040020 /* Video A interrupt mask */
 
#define VID_A_INT_STAT   0x040024 /* Video A interrupt status */
 
#define VID_A_INT_MSTAT   0x040028 /* Video A interrupt masked status */
 
#define VID_A_INT_SSTAT   0x04002C /* Video A interrupt set status */
 
#define VID_B_INT_MSK   0x040030 /* Video B interrupt mask */
 
#define VID_B_INT_STAT   0x040034 /* Video B interrupt status */
 
#define VID_B_INT_MSTAT   0x040038 /* Video B interrupt masked status */
 
#define VID_B_INT_SSTAT   0x04003C /* Video B interrupt set status */
 
#define VID_C_INT_MSK   0x040040 /* Video C interrupt mask */
 
#define VID_C_INT_STAT   0x040044 /* Video C interrupt status */
 
#define VID_C_INT_MSTAT   0x040048 /* Video C interrupt masked status */
 
#define VID_C_INT_SSTAT   0x04004C /* Video C interrupt set status */
 
#define VID_D_INT_MSK   0x040050 /* Video D interrupt mask */
 
#define VID_D_INT_STAT   0x040054 /* Video D interrupt status */
 
#define VID_D_INT_MSTAT   0x040058 /* Video D interrupt masked status */
 
#define VID_D_INT_SSTAT   0x04005C /* Video D interrupt set status */
 
#define VID_E_INT_MSK   0x040060 /* Video E interrupt mask */
 
#define VID_E_INT_STAT   0x040064 /* Video E interrupt status */
 
#define VID_E_INT_MSTAT   0x040068 /* Video E interrupt masked status */
 
#define VID_E_INT_SSTAT   0x04006C /* Video E interrupt set status */
 
#define VID_F_INT_MSK   0x040070 /* Video F interrupt mask */
 
#define VID_F_INT_STAT   0x040074 /* Video F interrupt status */
 
#define VID_F_INT_MSTAT   0x040078 /* Video F interrupt masked status */
 
#define VID_F_INT_SSTAT   0x04007C /* Video F interrupt set status */
 
#define VID_G_INT_MSK   0x040080 /* Video G interrupt mask */
 
#define VID_G_INT_STAT   0x040084 /* Video G interrupt status */
 
#define VID_G_INT_MSTAT   0x040088 /* Video G interrupt masked status */
 
#define VID_G_INT_SSTAT   0x04008C /* Video G interrupt set status */
 
#define VID_H_INT_MSK   0x040090 /* Video H interrupt mask */
 
#define VID_H_INT_STAT   0x040094 /* Video H interrupt status */
 
#define VID_H_INT_MSTAT   0x040098 /* Video H interrupt masked status */
 
#define VID_H_INT_SSTAT   0x04009C /* Video H interrupt set status */
 
#define VID_I_INT_MSK   0x0400A0 /* Video I interrupt mask */
 
#define VID_I_INT_STAT   0x0400A4 /* Video I interrupt status */
 
#define VID_I_INT_MSTAT   0x0400A8 /* Video I interrupt masked status */
 
#define VID_I_INT_SSTAT   0x0400AC /* Video I interrupt set status */
 
#define VID_J_INT_MSK   0x0400B0 /* Video J interrupt mask */
 
#define VID_J_INT_STAT   0x0400B4 /* Video J interrupt status */
 
#define VID_J_INT_MSTAT   0x0400B8 /* Video J interrupt masked status */
 
#define VID_J_INT_SSTAT   0x0400BC /* Video J interrupt set status */
 
#define FLD_VID_SRC_OPC_ERR   0x00020000
 
#define FLD_VID_DST_OPC_ERR   0x00010000
 
#define FLD_VID_SRC_SYNC   0x00002000
 
#define FLD_VID_DST_SYNC   0x00001000
 
#define FLD_VID_SRC_UF   0x00000200
 
#define FLD_VID_DST_OF   0x00000100
 
#define FLD_VID_SRC_RISC2   0x00000020
 
#define FLD_VID_DST_RISC2   0x00000010
 
#define FLD_VID_SRC_RISC1   0x00000002
 
#define FLD_VID_DST_RISC1   0x00000001
 
#define FLD_VID_SRC_ERRORS   (FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF)
 
#define FLD_VID_DST_ERRORS   (FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF)
 
#define AUD_A_INT_MSK   0x0400C0 /* Audio Int interrupt mask */
 
#define AUD_A_INT_STAT   0x0400C4 /* Audio Int interrupt status */
 
#define AUD_A_INT_MSTAT   0x0400C8 /* Audio Int interrupt masked status */
 
#define AUD_A_INT_SSTAT   0x0400CC /* Audio Int interrupt set status */
 
#define AUD_B_INT_MSK   0x0400D0 /* Audio Int interrupt mask */
 
#define AUD_B_INT_STAT   0x0400D4 /* Audio Int interrupt status */
 
#define AUD_B_INT_MSTAT   0x0400D8 /* Audio Int interrupt masked status */
 
#define AUD_B_INT_SSTAT   0x0400DC /* Audio Int interrupt set status */
 
#define AUD_C_INT_MSK   0x0400E0 /* Audio Int interrupt mask */
 
#define AUD_C_INT_STAT   0x0400E4 /* Audio Int interrupt status */
 
#define AUD_C_INT_MSTAT   0x0400E8 /* Audio Int interrupt masked status */
 
#define AUD_C_INT_SSTAT   0x0400EC /* Audio Int interrupt set status */
 
#define AUD_D_INT_MSK   0x0400F0 /* Audio Int interrupt mask */
 
#define AUD_D_INT_STAT   0x0400F4 /* Audio Int interrupt status */
 
#define AUD_D_INT_MSTAT   0x0400F8 /* Audio Int interrupt masked status */
 
#define AUD_D_INT_SSTAT   0x0400FC /* Audio Int interrupt set status */
 
#define AUD_E_INT_MSK   0x040100 /* Audio Int interrupt mask */
 
#define AUD_E_INT_STAT   0x040104 /* Audio Int interrupt status */
 
#define AUD_E_INT_MSTAT   0x040108 /* Audio Int interrupt masked status */
 
#define AUD_E_INT_SSTAT   0x04010C /* Audio Int interrupt set status */
 
#define FLD_AUD_SRC_OPC_ERR   0x00020000
 
#define FLD_AUD_DST_OPC_ERR   0x00010000
 
#define FLD_AUD_SRC_SYNC   0x00002000
 
#define FLD_AUD_DST_SYNC   0x00001000
 
#define FLD_AUD_SRC_OF   0x00000200
 
#define FLD_AUD_DST_OF   0x00000100
 
#define FLD_AUD_SRC_RISCI2   0x00000020
 
#define FLD_AUD_DST_RISCI2   0x00000010
 
#define FLD_AUD_SRC_RISCI1   0x00000002
 
#define FLD_AUD_DST_RISCI1   0x00000001
 
#define MBIF_A_INT_MSK   0x040110 /* MBIF Int interrupt mask */
 
#define MBIF_A_INT_STAT   0x040114 /* MBIF Int interrupt status */
 
#define MBIF_A_INT_MSTAT   0x040118 /* MBIF Int interrupt masked status */
 
#define MBIF_A_INT_SSTAT   0x04011C /* MBIF Int interrupt set status */
 
#define MBIF_B_INT_MSK   0x040120 /* MBIF Int interrupt mask */
 
#define MBIF_B_INT_STAT   0x040124 /* MBIF Int interrupt status */
 
#define MBIF_B_INT_MSTAT   0x040128 /* MBIF Int interrupt masked status */
 
#define MBIF_B_INT_SSTAT   0x04012C /* MBIF Int interrupt set status */
 
#define FLD_MBIF_DST_OPC_ERR   0x00010000
 
#define FLD_MBIF_DST_SYNC   0x00001000
 
#define FLD_MBIF_DST_OF   0x00000100
 
#define FLD_MBIF_DST_RISCI2   0x00000010
 
#define FLD_MBIF_DST_RISCI1   0x00000001
 
#define AUD_EXT_INT_MSK   0x040060 /* Audio Ext interrupt mask */
 
#define AUD_EXT_INT_STAT   0x040064 /* Audio Ext interrupt status */
 
#define AUD_EXT_INT_MSTAT   0x040068 /* Audio Ext interrupt masked status */
 
#define AUD_EXT_INT_SSTAT   0x04006C /* Audio Ext interrupt set status */
 
#define FLD_AUD_EXT_OPC_ERR   0x00010000
 
#define FLD_AUD_EXT_SYNC   0x00001000
 
#define FLD_AUD_EXT_OF   0x00000100
 
#define FLD_AUD_EXT_RISCI2   0x00000010
 
#define FLD_AUD_EXT_RISCI1   0x00000001
 
#define GPIO_LO   0x110010 /* Lower of GPIO pins [31:0] */
 
#define GPIO_HI   0x110014 /* Upper WORD of GPIO pins [47:31] */
 
#define GPIO_LO_OE   0x110018 /* Lower of GPIO output enable [31:0] */
 
#define GPIO_HI_OE   0x11001C /* Upper word of GPIO output enable [47:32] */
 
#define GPIO_LO_INT_MSK   0x11003C /* GPIO interrupt mask */
 
#define GPIO_LO_INT_STAT   0x110044 /* GPIO interrupt status */
 
#define GPIO_LO_INT_MSTAT   0x11004C /* GPIO interrupt masked status */
 
#define GPIO_LO_ISM_SNS   0x110054 /* GPIO interrupt sensitivity */
 
#define GPIO_LO_ISM_POL   0x11005C /* GPIO interrupt polarity */
 
#define GPIO_HI_INT_MSK   0x110040 /* GPIO interrupt mask */
 
#define GPIO_HI_INT_STAT   0x110048 /* GPIO interrupt status */
 
#define GPIO_HI_INT_MSTAT   0x110050 /* GPIO interrupt masked status */
 
#define GPIO_HI_ISM_SNS   0x110058 /* GPIO interrupt sensitivity */
 
#define GPIO_HI_ISM_POL   0x110060 /* GPIO interrupt polarity */
 
#define FLD_GPIO43_INT   (1 << 11)
 
#define FLD_GPIO42_INT   (1 << 10)
 
#define FLD_GPIO41_INT   (1 << 9)
 
#define FLD_GPIO40_INT   (1 << 8)
 
#define FLD_GPIO9_INT   (1 << 9)
 
#define FLD_GPIO8_INT   (1 << 8)
 
#define FLD_GPIO7_INT   (1 << 7)
 
#define FLD_GPIO6_INT   (1 << 6)
 
#define FLD_GPIO5_INT   (1 << 5)
 
#define FLD_GPIO4_INT   (1 << 4)
 
#define FLD_GPIO3_INT   (1 << 3)
 
#define FLD_GPIO2_INT   (1 << 2)
 
#define FLD_GPIO1_INT   (1 << 1)
 
#define FLD_GPIO0_INT   (1 << 0)
 
#define TC_REQ   0x040090 /* Rider PCI Express traFFic class request */
 
#define TC_REQ_SET   0x040094 /* Rider PCI Express traFFic class request set */
 
#define RDR_CFG0   0x050000
 
#define RDR_VENDOR_DEVICE_ID_CFG   0x050000
 
#define RDR_CFG1   0x050004
 
#define RDR_CFG2   0x050008
 
#define RDR_CFG3   0x05000C
 
#define RDR_CFG4   0x050010
 
#define RDR_CFG5   0x050014
 
#define RDR_CFG6   0x050018
 
#define RDR_CFG7   0x05001C
 
#define RDR_CFG8   0x050020
 
#define RDR_CFG9   0x050024
 
#define RDR_CFGA   0x050028
 
#define RDR_CFGB   0x05002C
 
#define RDR_SUSSYSTEM_ID_CFG   0x05002C
 
#define RDR_CFGC   0x050030
 
#define RDR_CFGD   0x050034
 
#define RDR_CFGE   0x050038
 
#define RDR_CFGF   0x05003C
 
#define RDR_PECAP   0x050040
 
#define RDR_PEDEVCAP   0x050044
 
#define RDR_PEDEVSC   0x050048
 
#define RDR_PELINKCAP   0x05004C
 
#define RDR_PELINKSC   0x050050
 
#define RDR_PMICAP   0x050080
 
#define RDR_PMCSR   0x050084
 
#define RDR_VPDCAP   0x050090
 
#define RDR_VPDDATA   0x050094
 
#define RDR_MSICAP   0x0500A0
 
#define RDR_MSIARL   0x0500A4
 
#define RDR_MSIARU   0x0500A8
 
#define RDR_MSIDATA   0x0500AC
 
#define RDR_AERXCAP   0x050100
 
#define RDR_AERUESTA   0x050104
 
#define RDR_AERUEMSK   0x050108
 
#define RDR_AERUESEV   0x05010C
 
#define RDR_AERCESTA   0x050110
 
#define RDR_AERCEMSK   0x050114
 
#define RDR_AERCC   0x050118
 
#define RDR_AERHL0   0x05011C
 
#define RDR_AERHL1   0x050120
 
#define RDR_AERHL2   0x050124
 
#define RDR_AERHL3   0x050128
 
#define RDR_VCXCAP   0x050200
 
#define RDR_VCCAP1   0x050204
 
#define RDR_VCCAP2   0x050208
 
#define RDR_VCSC   0x05020C
 
#define RDR_VCR0_CAP   0x050210
 
#define RDR_VCR0_CTRL   0x050214
 
#define RDR_VCR0_STAT   0x050218
 
#define RDR_VCR1_CAP   0x05021C
 
#define RDR_VCR1_CTRL   0x050220
 
#define RDR_VCR1_STAT   0x050224
 
#define RDR_VCR2_CAP   0x050228
 
#define RDR_VCR2_CTRL   0x05022C
 
#define RDR_VCR2_STAT   0x050230
 
#define RDR_VCR3_CAP   0x050234
 
#define RDR_VCR3_CTRL   0x050238
 
#define RDR_VCR3_STAT   0x05023C
 
#define RDR_VCARB0   0x050240
 
#define RDR_VCARB1   0x050244
 
#define RDR_VCARB2   0x050248
 
#define RDR_VCARB3   0x05024C
 
#define RDR_VCARB4   0x050250
 
#define RDR_VCARB5   0x050254
 
#define RDR_VCARB6   0x050258
 
#define RDR_VCARB7   0x05025C
 
#define RDR_RDRSTAT0   0x050300
 
#define RDR_RDRSTAT1   0x050304
 
#define RDR_RDRCTL0   0x050308
 
#define RDR_RDRCTL1   0x05030C
 
#define RDR_TLSTAT0   0x050310
 
#define RDR_TLSTAT1   0x050314
 
#define RDR_TLCTL0   0x050318
 
#define FLD_CFG_UR_CPL_MODE   0x00000040
 
#define FLD_CFG_CORR_ERR_QUITE   0x00000020
 
#define FLD_CFG_RCB_CK_EN   0x00000010
 
#define FLD_CFG_BNDRY_CK_EN   0x00000008
 
#define FLD_CFG_BYTE_EN_CK_EN   0x00000004
 
#define FLD_CFG_RELAX_ORDER_MSK   0x00000002
 
#define FLD_CFG_TAG_ORDER_EN   0x00000001
 
#define RDR_TLCTL1   0x05031C
 
#define RDR_REQRCAL   0x050320
 
#define RDR_REQRCAU   0x050324
 
#define RDR_REQEPA   0x050328
 
#define RDR_REQCTRL   0x05032C
 
#define RDR_REQSTAT   0x050330
 
#define RDR_TL_TEST   0x050334
 
#define RDR_VCR01_CTL   0x050348
 
#define RDR_VCR23_CTL   0x05034C
 
#define RDR_RX_VCR0_FC   0x050350
 
#define RDR_RX_VCR1_FC   0x050354
 
#define RDR_RX_VCR2_FC   0x050358
 
#define RDR_RX_VCR3_FC   0x05035C
 
#define RDR_DLLSTAT   0x050360
 
#define RDR_DLLCTRL   0x050364
 
#define RDR_REPLAYTO   0x050368
 
#define RDR_ACKLATTO   0x05036C
 
#define RDR_MACSTAT0   0x050380
 
#define RDR_MACSTAT1   0x050384
 
#define RDR_MACCTRL0   0x050388
 
#define RDR_MACCTRL1   0x05038C
 
#define RDR_MACCTRL2   0x050390
 
#define RDR_MAC_LB_DATA   0x050394
 
#define RDR_L0S_EXIT_LAT   0x050398
 
#define DMA1_PTR1   0x100000 /* DMA Current Ptr : Ch#1 */
 
#define DMA2_PTR1   0x100004 /* DMA Current Ptr : Ch#2 */
 
#define DMA3_PTR1   0x100008 /* DMA Current Ptr : Ch#3 */
 
#define DMA4_PTR1   0x10000C /* DMA Current Ptr : Ch#4 */
 
#define DMA5_PTR1   0x100010 /* DMA Current Ptr : Ch#5 */
 
#define DMA6_PTR1   0x100014 /* DMA Current Ptr : Ch#6 */
 
#define DMA7_PTR1   0x100018 /* DMA Current Ptr : Ch#7 */
 
#define DMA8_PTR1   0x10001C /* DMA Current Ptr : Ch#8 */
 
#define DMA9_PTR1   0x100020 /* DMA Current Ptr : Ch#9 */
 
#define DMA10_PTR1   0x100024 /* DMA Current Ptr : Ch#10 */
 
#define DMA11_PTR1   0x100028 /* DMA Current Ptr : Ch#11 */
 
#define DMA12_PTR1   0x10002C /* DMA Current Ptr : Ch#12 */
 
#define DMA13_PTR1   0x100030 /* DMA Current Ptr : Ch#13 */
 
#define DMA14_PTR1   0x100034 /* DMA Current Ptr : Ch#14 */
 
#define DMA15_PTR1   0x100038 /* DMA Current Ptr : Ch#15 */
 
#define DMA16_PTR1   0x10003C /* DMA Current Ptr : Ch#16 */
 
#define DMA17_PTR1   0x100040 /* DMA Current Ptr : Ch#17 */
 
#define DMA18_PTR1   0x100044 /* DMA Current Ptr : Ch#18 */
 
#define DMA19_PTR1   0x100048 /* DMA Current Ptr : Ch#19 */
 
#define DMA20_PTR1   0x10004C /* DMA Current Ptr : Ch#20 */
 
#define DMA21_PTR1   0x100050 /* DMA Current Ptr : Ch#21 */
 
#define DMA22_PTR1   0x100054 /* DMA Current Ptr : Ch#22 */
 
#define DMA23_PTR1   0x100058 /* DMA Current Ptr : Ch#23 */
 
#define DMA24_PTR1   0x10005C /* DMA Current Ptr : Ch#24 */
 
#define DMA25_PTR1   0x100060 /* DMA Current Ptr : Ch#25 */
 
#define DMA26_PTR1   0x100064 /* DMA Current Ptr : Ch#26 */
 
#define DMA1_PTR2   0x100080 /* DMA Tab Ptr : Ch#1 */
 
#define DMA2_PTR2   0x100084 /* DMA Tab Ptr : Ch#2 */
 
#define DMA3_PTR2   0x100088 /* DMA Tab Ptr : Ch#3 */
 
#define DMA4_PTR2   0x10008C /* DMA Tab Ptr : Ch#4 */
 
#define DMA5_PTR2   0x100090 /* DMA Tab Ptr : Ch#5 */
 
#define DMA6_PTR2   0x100094 /* DMA Tab Ptr : Ch#6 */
 
#define DMA7_PTR2   0x100098 /* DMA Tab Ptr : Ch#7 */
 
#define DMA8_PTR2   0x10009C /* DMA Tab Ptr : Ch#8 */
 
#define DMA9_PTR2   0x1000A0 /* DMA Tab Ptr : Ch#9 */
 
#define DMA10_PTR2   0x1000A4 /* DMA Tab Ptr : Ch#10 */
 
#define DMA11_PTR2   0x1000A8 /* DMA Tab Ptr : Ch#11 */
 
#define DMA12_PTR2   0x1000AC /* DMA Tab Ptr : Ch#12 */
 
#define DMA13_PTR2   0x1000B0 /* DMA Tab Ptr : Ch#13 */
 
#define DMA14_PTR2   0x1000B4 /* DMA Tab Ptr : Ch#14 */
 
#define DMA15_PTR2   0x1000B8 /* DMA Tab Ptr : Ch#15 */
 
#define DMA16_PTR2   0x1000BC /* DMA Tab Ptr : Ch#16 */
 
#define DMA17_PTR2   0x1000C0 /* DMA Tab Ptr : Ch#17 */
 
#define DMA18_PTR2   0x1000C4 /* DMA Tab Ptr : Ch#18 */
 
#define DMA19_PTR2   0x1000C8 /* DMA Tab Ptr : Ch#19 */
 
#define DMA20_PTR2   0x1000CC /* DMA Tab Ptr : Ch#20 */
 
#define DMA21_PTR2   0x1000D0 /* DMA Tab Ptr : Ch#21 */
 
#define DMA22_PTR2   0x1000D4 /* DMA Tab Ptr : Ch#22 */
 
#define DMA23_PTR2   0x1000D8 /* DMA Tab Ptr : Ch#23 */
 
#define DMA24_PTR2   0x1000DC /* DMA Tab Ptr : Ch#24 */
 
#define DMA25_PTR2   0x1000E0 /* DMA Tab Ptr : Ch#25 */
 
#define DMA26_PTR2   0x1000E4 /* DMA Tab Ptr : Ch#26 */
 
#define DMA1_CNT1   0x100100 /* DMA BuFFer Size : Ch#1 */
 
#define DMA2_CNT1   0x100104 /* DMA BuFFer Size : Ch#2 */
 
#define DMA3_CNT1   0x100108 /* DMA BuFFer Size : Ch#3 */
 
#define DMA4_CNT1   0x10010C /* DMA BuFFer Size : Ch#4 */
 
#define DMA5_CNT1   0x100110 /* DMA BuFFer Size : Ch#5 */
 
#define DMA6_CNT1   0x100114 /* DMA BuFFer Size : Ch#6 */
 
#define DMA7_CNT1   0x100118 /* DMA BuFFer Size : Ch#7 */
 
#define DMA8_CNT1   0x10011C /* DMA BuFFer Size : Ch#8 */
 
#define DMA9_CNT1   0x100120 /* DMA BuFFer Size : Ch#9 */
 
#define DMA10_CNT1   0x100124 /* DMA BuFFer Size : Ch#10 */
 
#define DMA11_CNT1   0x100128 /* DMA BuFFer Size : Ch#11 */
 
#define DMA12_CNT1   0x10012C /* DMA BuFFer Size : Ch#12 */
 
#define DMA13_CNT1   0x100130 /* DMA BuFFer Size : Ch#13 */
 
#define DMA14_CNT1   0x100134 /* DMA BuFFer Size : Ch#14 */
 
#define DMA15_CNT1   0x100138 /* DMA BuFFer Size : Ch#15 */
 
#define DMA16_CNT1   0x10013C /* DMA BuFFer Size : Ch#16 */
 
#define DMA17_CNT1   0x100140 /* DMA BuFFer Size : Ch#17 */
 
#define DMA18_CNT1   0x100144 /* DMA BuFFer Size : Ch#18 */
 
#define DMA19_CNT1   0x100148 /* DMA BuFFer Size : Ch#19 */
 
#define DMA20_CNT1   0x10014C /* DMA BuFFer Size : Ch#20 */
 
#define DMA21_CNT1   0x100150 /* DMA BuFFer Size : Ch#21 */
 
#define DMA22_CNT1   0x100154 /* DMA BuFFer Size : Ch#22 */
 
#define DMA23_CNT1   0x100158 /* DMA BuFFer Size : Ch#23 */
 
#define DMA24_CNT1   0x10015C /* DMA BuFFer Size : Ch#24 */
 
#define DMA25_CNT1   0x100160 /* DMA BuFFer Size : Ch#25 */
 
#define DMA26_CNT1   0x100164 /* DMA BuFFer Size : Ch#26 */
 
#define DMA1_CNT2   0x100180 /* DMA Table Size : Ch#1 */
 
#define DMA2_CNT2   0x100184 /* DMA Table Size : Ch#2 */
 
#define DMA3_CNT2   0x100188 /* DMA Table Size : Ch#3 */
 
#define DMA4_CNT2   0x10018C /* DMA Table Size : Ch#4 */
 
#define DMA5_CNT2   0x100190 /* DMA Table Size : Ch#5 */
 
#define DMA6_CNT2   0x100194 /* DMA Table Size : Ch#6 */
 
#define DMA7_CNT2   0x100198 /* DMA Table Size : Ch#7 */
 
#define DMA8_CNT2   0x10019C /* DMA Table Size : Ch#8 */
 
#define DMA9_CNT2   0x1001A0 /* DMA Table Size : Ch#9 */
 
#define DMA10_CNT2   0x1001A4 /* DMA Table Size : Ch#10 */
 
#define DMA11_CNT2   0x1001A8 /* DMA Table Size : Ch#11 */
 
#define DMA12_CNT2   0x1001AC /* DMA Table Size : Ch#12 */
 
#define DMA13_CNT2   0x1001B0 /* DMA Table Size : Ch#13 */
 
#define DMA14_CNT2   0x1001B4 /* DMA Table Size : Ch#14 */
 
#define DMA15_CNT2   0x1001B8 /* DMA Table Size : Ch#15 */
 
#define DMA16_CNT2   0x1001BC /* DMA Table Size : Ch#16 */
 
#define DMA17_CNT2   0x1001C0 /* DMA Table Size : Ch#17 */
 
#define DMA18_CNT2   0x1001C4 /* DMA Table Size : Ch#18 */
 
#define DMA19_CNT2   0x1001C8 /* DMA Table Size : Ch#19 */
 
#define DMA20_CNT2   0x1001CC /* DMA Table Size : Ch#20 */
 
#define DMA21_CNT2   0x1001D0 /* DMA Table Size : Ch#21 */
 
#define DMA22_CNT2   0x1001D4 /* DMA Table Size : Ch#22 */
 
#define DMA23_CNT2   0x1001D8 /* DMA Table Size : Ch#23 */
 
#define DMA24_CNT2   0x1001DC /* DMA Table Size : Ch#24 */
 
#define DMA25_CNT2   0x1001E0 /* DMA Table Size : Ch#25 */
 
#define DMA26_CNT2   0x1001E4 /* DMA Table Size : Ch#26 */
 
#define TM_CNT_LDW   0x110000 /* Timer : Counter low */
 
#define TM_CNT_UW   0x110004 /* Timer : Counter high word */
 
#define TM_LMT_LDW   0x110008 /* Timer : Limit low */
 
#define TM_LMT_UW   0x11000C /* Timer : Limit high word */
 
#define GP0_IO   0x110010 /* GPIO output enables data I/O */
 
#define FLD_GP_OE   0x00FF0000 /* GPIO: GP_OE output enable */
 
#define FLD_GP_IN   0x0000FF00 /* GPIO: GP_IN status */
 
#define FLD_GP_OUT   0x000000FF /* GPIO: GP_OUT control */
 
#define GPIO_ISM   0x110014 /* GPIO interrupt sensitivity mode */
 
#define FLD_GP_ISM_SNS   0x00000070
 
#define FLD_GP_ISM_POL   0x00000007
 
#define SOFT_RESET   0x11001C /* Output system reset reg */
 
#define FLD_PECOS_SOFT_RESET   0x00000001
 
#define MC416_RWD   0x110020 /* MC416 GPIO[18:3] pin */
 
#define MC416_OEN   0x110024 /* Output enable of GPIO[18:3] */
 
#define MC416_CTL   0x110028
 
#define ALT_PIN_OUT_SEL   0x11002C /* Alternate GPIO output select */
 
#define FLD_ALT_GPIO_OUT_SEL   0xF0000000
 
#define FLD_AUX_PLL_CLK_ALT_SEL   0x0F000000
 
#define FLD_IR_TX_ALT_SEL   0x00F00000
 
#define FLD_IR_RX_ALT_SEL   0x000F0000
 
#define FLD_GPIO10_ALT_SEL   0x0000F000
 
#define FLD_GPIO2_ALT_SEL   0x00000F00
 
#define FLD_GPIO1_ALT_SEL   0x000000F0
 
#define FLD_GPIO0_ALT_SEL   0x0000000F
 
#define ALT_PIN_IN_SEL   0x110030 /* Alternate GPIO input select */
 
#define FLD_GPIO10_ALT_IN_SEL   0x0000F000
 
#define FLD_GPIO2_ALT_IN_SEL   0x00000F00
 
#define FLD_GPIO1_ALT_IN_SEL   0x000000F0
 
#define FLD_GPIO0_ALT_IN_SEL   0x0000000F
 
#define TEST_BUS_CTL1   0x110040 /* Test bus control register #1 */
 
#define TEST_BUS_CTL2   0x110044 /* Test bus control register #2 */
 
#define CLK_DELAY   0x110048 /* Clock delay */
 
#define FLD_MOE_CLK_DIS   0x80000000 /* Disable MoE clock */
 
#define PAD_CTRL   0x110068 /* Pad drive strength control */
 
#define MBIST_CTRL   0x110050 /* SRAM memory built-in self test control */
 
#define MBIST_STAT   0x110054 /* SRAM memory built-in self test status */
 
#define PLL_A_INT_FRAC   0x110088
 
#define PLL_A_POST_STAT_BIST   0x11008C
 
#define PLL_B_INT_FRAC   0x110090
 
#define PLL_B_POST_STAT_BIST   0x110094
 
#define PLL_C_INT_FRAC   0x110098
 
#define PLL_C_POST_STAT_BIST   0x11009C
 
#define PLL_D_INT_FRAC   0x1100A0
 
#define PLL_D_POST_STAT_BIST   0x1100A4
 
#define CLK_RST   0x11002C
 
#define FLD_VID_I_CLK_NOE   0x00001000
 
#define FLD_VID_J_CLK_NOE   0x00002000
 
#define FLD_USE_ALT_PLL_REF   0x00004000
 
#define VID_CH_MODE_SEL   0x110078
 
#define VID_CH_CLK_SEL   0x11007C
 
#define VBI_A_DMA   0x130008 /* VBI A DMA data port */
 
#define VID_A_VIP_CTL   0x130080 /* Video A VIP format control */
 
#define FLD_VIP_MODE   0x00000001
 
#define VID_A_PIXEL_FRMT   0x130084 /* Video A pixel format */
 
#define FLD_VID_A_GAMMA_DIS   0x00000008
 
#define FLD_VID_A_FORMAT   0x00000007
 
#define FLD_VID_A_GAMMA_FACTOR   0x00000010
 
#define VID_A_VBI_CTL   0x130088 /* Video A VBI miscellaneous control */
 
#define FLD_VID_A_VIP_EXT   0x00000003
 
#define VID_B_DMA   0x130100 /* Video B DMA data port */
 
#define VBI_B_DMA   0x130108 /* VBI B DMA data port */
 
#define VID_B_SRC_SEL   0x130144 /* Video B source select */
 
#define FLD_VID_B_SRC_SEL   0x00000000
 
#define VID_B_LNGTH   0x130150 /* Video B line length */
 
#define FLD_VID_B_LN_LNGTH   0x00000FFF
 
#define VID_B_VIP_CTL   0x130180 /* Video B VIP format control */
 
#define VID_B_PIXEL_FRMT   0x130184 /* Video B pixel format */
 
#define FLD_VID_B_GAMMA_DIS   0x00000008
 
#define FLD_VID_B_FORMAT   0x00000007
 
#define FLD_VID_B_GAMMA_FACTOR   0x00000010
 
#define VID_C_DMA   0x130200 /* Video C DMA data port */
 
#define VID_C_LNGTH   0x130250 /* Video C line length */
 
#define FLD_VID_C_LN_LNGTH   0x00000FFF
 
#define VID_DST_A_GPCNT   0x130020 /* Video A general purpose counter */
 
#define VID_DST_B_GPCNT   0x130120 /* Video B general purpose counter */
 
#define VID_DST_C_GPCNT   0x130220 /* Video C general purpose counter */
 
#define VID_DST_D_GPCNT   0x130320 /* Video D general purpose counter */
 
#define VID_DST_E_GPCNT   0x130420 /* Video E general purpose counter */
 
#define VID_DST_F_GPCNT   0x130520 /* Video F general purpose counter */
 
#define VID_DST_G_GPCNT   0x130620 /* Video G general purpose counter */
 
#define VID_DST_H_GPCNT   0x130720 /* Video H general purpose counter */
 
#define VID_DST_A_GPCNT_CTL   0x130030 /* Video A general purpose control */
 
#define VID_DST_B_GPCNT_CTL   0x130130 /* Video B general purpose control */
 
#define VID_DST_C_GPCNT_CTL   0x130230 /* Video C general purpose control */
 
#define VID_DST_D_GPCNT_CTL   0x130330 /* Video D general purpose control */
 
#define VID_DST_E_GPCNT_CTL   0x130430 /* Video E general purpose control */
 
#define VID_DST_F_GPCNT_CTL   0x130530 /* Video F general purpose control */
 
#define VID_DST_G_GPCNT_CTL   0x130630 /* Video G general purpose control */
 
#define VID_DST_H_GPCNT_CTL   0x130730 /* Video H general purpose control */
 
#define VID_DST_A_DMA_CTL   0x130040 /* Video A DMA control */
 
#define VID_DST_B_DMA_CTL   0x130140 /* Video B DMA control */
 
#define VID_DST_C_DMA_CTL   0x130240 /* Video C DMA control */
 
#define VID_DST_D_DMA_CTL   0x130340 /* Video D DMA control */
 
#define VID_DST_E_DMA_CTL   0x130440 /* Video E DMA control */
 
#define VID_DST_F_DMA_CTL   0x130540 /* Video F DMA control */
 
#define VID_DST_G_DMA_CTL   0x130640 /* Video G DMA control */
 
#define VID_DST_H_DMA_CTL   0x130740 /* Video H DMA control */
 
#define FLD_VID_RISC_EN   0x00000010
 
#define FLD_VID_FIFO_EN   0x00000001
 
#define VID_DST_A_VIP_CTL   0x130080 /* Video A VIP control */
 
#define VID_DST_B_VIP_CTL   0x130180 /* Video B VIP control */
 
#define VID_DST_C_VIP_CTL   0x130280 /* Video C VIP control */
 
#define VID_DST_D_VIP_CTL   0x130380 /* Video D VIP control */
 
#define VID_DST_E_VIP_CTL   0x130480 /* Video E VIP control */
 
#define VID_DST_F_VIP_CTL   0x130580 /* Video F VIP control */
 
#define VID_DST_G_VIP_CTL   0x130680 /* Video G VIP control */
 
#define VID_DST_H_VIP_CTL   0x130780 /* Video H VIP control */
 
#define VID_DST_A_PIX_FRMT   0x130084 /* Video A Pixel format */
 
#define VID_DST_B_PIX_FRMT   0x130184 /* Video B Pixel format */
 
#define VID_DST_C_PIX_FRMT   0x130284 /* Video C Pixel format */
 
#define VID_DST_D_PIX_FRMT   0x130384 /* Video D Pixel format */
 
#define VID_DST_E_PIX_FRMT   0x130484 /* Video E Pixel format */
 
#define VID_DST_F_PIX_FRMT   0x130584 /* Video F Pixel format */
 
#define VID_DST_G_PIX_FRMT   0x130684 /* Video G Pixel format */
 
#define VID_DST_H_PIX_FRMT   0x130784 /* Video H Pixel format */
 
#define VID_SRC_A_GPCNT_CTL   0x130804 /* Video A general purpose control */
 
#define VID_SRC_B_GPCNT_CTL   0x130904 /* Video B general purpose control */
 
#define VID_SRC_C_GPCNT_CTL   0x130A04 /* Video C general purpose control */
 
#define VID_SRC_D_GPCNT_CTL   0x130B04 /* Video D general purpose control */
 
#define VID_SRC_E_GPCNT_CTL   0x130C04 /* Video E general purpose control */
 
#define VID_SRC_F_GPCNT_CTL   0x130D04 /* Video F general purpose control */
 
#define VID_SRC_I_GPCNT_CTL   0x130E04 /* Video I general purpose control */
 
#define VID_SRC_J_GPCNT_CTL   0x130F04 /* Video J general purpose control */
 
#define VID_SRC_A_GPCNT   0x130808 /* Video A general purpose counter */
 
#define VID_SRC_B_GPCNT   0x130908 /* Video B general purpose counter */
 
#define VID_SRC_C_GPCNT   0x130A08 /* Video C general purpose counter */
 
#define VID_SRC_D_GPCNT   0x130B08 /* Video D general purpose counter */
 
#define VID_SRC_E_GPCNT   0x130C08 /* Video E general purpose counter */
 
#define VID_SRC_F_GPCNT   0x130D08 /* Video F general purpose counter */
 
#define VID_SRC_I_GPCNT   0x130E08 /* Video I general purpose counter */
 
#define VID_SRC_J_GPCNT   0x130F08 /* Video J general purpose counter */
 
#define VID_SRC_A_DMA_CTL   0x13080C /* Video A DMA control */
 
#define VID_SRC_B_DMA_CTL   0x13090C /* Video B DMA control */
 
#define VID_SRC_C_DMA_CTL   0x130A0C /* Video C DMA control */
 
#define VID_SRC_D_DMA_CTL   0x130B0C /* Video D DMA control */
 
#define VID_SRC_E_DMA_CTL   0x130C0C /* Video E DMA control */
 
#define VID_SRC_F_DMA_CTL   0x130D0C /* Video F DMA control */
 
#define VID_SRC_I_DMA_CTL   0x130E0C /* Video I DMA control */
 
#define VID_SRC_J_DMA_CTL   0x130F0C /* Video J DMA control */
 
#define FLD_APB_RISC_EN   0x00000010
 
#define FLD_APB_FIFO_EN   0x00000001
 
#define VID_SRC_A_FMT_CTL   0x130810 /* Video A format control */
 
#define VID_SRC_B_FMT_CTL   0x130910 /* Video B format control */
 
#define VID_SRC_C_FMT_CTL   0x130A10 /* Video C format control */
 
#define VID_SRC_D_FMT_CTL   0x130B10 /* Video D format control */
 
#define VID_SRC_E_FMT_CTL   0x130C10 /* Video E format control */
 
#define VID_SRC_F_FMT_CTL   0x130D10 /* Video F format control */
 
#define VID_SRC_I_FMT_CTL   0x130E10 /* Video I format control */
 
#define VID_SRC_J_FMT_CTL   0x130F10 /* Video J format control */
 
#define VID_SRC_A_ACTIVE_CTL1   0x130814 /* Video A active control 1 */
 
#define VID_SRC_B_ACTIVE_CTL1   0x130914 /* Video B active control 1 */
 
#define VID_SRC_C_ACTIVE_CTL1   0x130A14 /* Video C active control 1 */
 
#define VID_SRC_D_ACTIVE_CTL1   0x130B14 /* Video D active control 1 */
 
#define VID_SRC_E_ACTIVE_CTL1   0x130C14 /* Video E active control 1 */
 
#define VID_SRC_F_ACTIVE_CTL1   0x130D14 /* Video F active control 1 */
 
#define VID_SRC_I_ACTIVE_CTL1   0x130E14 /* Video I active control 1 */
 
#define VID_SRC_J_ACTIVE_CTL1   0x130F14 /* Video J active control 1 */
 
#define VID_SRC_A_ACTIVE_CTL2   0x130818 /* Video A active control 2 */
 
#define VID_SRC_B_ACTIVE_CTL2   0x130918 /* Video B active control 2 */
 
#define VID_SRC_C_ACTIVE_CTL2   0x130A18 /* Video C active control 2 */
 
#define VID_SRC_D_ACTIVE_CTL2   0x130B18 /* Video D active control 2 */
 
#define VID_SRC_E_ACTIVE_CTL2   0x130C18 /* Video E active control 2 */
 
#define VID_SRC_F_ACTIVE_CTL2   0x130D18 /* Video F active control 2 */
 
#define VID_SRC_I_ACTIVE_CTL2   0x130E18 /* Video I active control 2 */
 
#define VID_SRC_J_ACTIVE_CTL2   0x130F18 /* Video J active control 2 */
 
#define VID_SRC_A_CDT_SZ   0x13081C /* Video A CDT size */
 
#define VID_SRC_B_CDT_SZ   0x13091C /* Video B CDT size */
 
#define VID_SRC_C_CDT_SZ   0x130A1C /* Video C CDT size */
 
#define VID_SRC_D_CDT_SZ   0x130B1C /* Video D CDT size */
 
#define VID_SRC_E_CDT_SZ   0x130C1C /* Video E CDT size */
 
#define VID_SRC_F_CDT_SZ   0x130D1C /* Video F CDT size */
 
#define VID_SRC_I_CDT_SZ   0x130E1C /* Video I CDT size */
 
#define VID_SRC_J_CDT_SZ   0x130F1C /* Video J CDT size */
 
#define AUD_DST_A_DMA   0x140000 /* Audio Int A DMA data port */
 
#define AUD_SRC_A_DMA   0x140008 /* Audio Int A DMA data port */
 
#define AUD_A_GPCNT   0x140010 /* Audio Int A gp counter */
 
#define FLD_AUD_A_GP_CNT   0x0000FFFF
 
#define AUD_A_GPCNT_CTL   0x140014 /* Audio Int A gp control */
 
#define AUD_A_LNGTH   0x140018 /* Audio Int A line length */
 
#define AUD_A_CFG   0x14001C /* Audio Int A configuration */
 
#define AUD_DST_B_DMA   0x140100 /* Audio Int B DMA data port */
 
#define AUD_SRC_B_DMA   0x140108 /* Audio Int B DMA data port */
 
#define AUD_B_GPCNT   0x140110 /* Audio Int B gp counter */
 
#define FLD_AUD_B_GP_CNT   0x0000FFFF
 
#define AUD_B_GPCNT_CTL   0x140114 /* Audio Int B gp control */
 
#define AUD_B_LNGTH   0x140118 /* Audio Int B line length */
 
#define AUD_B_CFG   0x14011C /* Audio Int B configuration */
 
#define AUD_DST_C_DMA   0x140200 /* Audio Int C DMA data port */
 
#define AUD_SRC_C_DMA   0x140208 /* Audio Int C DMA data port */
 
#define AUD_C_GPCNT   0x140210 /* Audio Int C gp counter */
 
#define FLD_AUD_C_GP_CNT   0x0000FFFF
 
#define AUD_C_GPCNT_CTL   0x140214 /* Audio Int C gp control */
 
#define AUD_C_LNGTH   0x140218 /* Audio Int C line length */
 
#define AUD_C_CFG   0x14021C /* Audio Int C configuration */
 
#define AUD_DST_D_DMA   0x140300 /* Audio Int D DMA data port */
 
#define AUD_SRC_D_DMA   0x140308 /* Audio Int D DMA data port */
 
#define AUD_D_GPCNT   0x140310 /* Audio Int D gp counter */
 
#define FLD_AUD_D_GP_CNT   0x0000FFFF
 
#define AUD_D_GPCNT_CTL   0x140314 /* Audio Int D gp control */
 
#define AUD_D_LNGTH   0x140318 /* Audio Int D line length */
 
#define AUD_D_CFG   0x14031C /* Audio Int D configuration */
 
#define AUD_SRC_E_DMA   0x140400 /* Audio Int E DMA data port */
 
#define AUD_E_GPCNT   0x140410 /* Audio Int E gp counter */
 
#define FLD_AUD_E_GP_CNT   0x0000FFFF
 
#define AUD_E_GPCNT_CTL   0x140414 /* Audio Int E gp control */
 
#define AUD_E_CFG   0x14041C /* Audio Int E configuration */
 
#define FLD_AUD_DST_LN_LNGTH   0x00000FFF
 
#define FLD_AUD_DST_PK_MODE   0x00004000
 
#define FLD_AUD_CLK_ENABLE   0x00000200
 
#define FLD_AUD_MASTER_MODE   0x00000002
 
#define FLD_AUD_SONY_MODE   0x00000001
 
#define FLD_AUD_CLK_SELECT_PLL_D   0x00001800
 
#define FLD_AUD_DST_ENABLE   0x00020000
 
#define FLD_AUD_SRC_ENABLE   0x00010000
 
#define AUD_INT_DMA_CTL   0x140500 /* Audio Int DMA control */
 
#define FLD_AUD_SRC_E_RISC_EN   0x00008000
 
#define FLD_AUD_SRC_C_RISC_EN   0x00004000
 
#define FLD_AUD_SRC_B_RISC_EN   0x00002000
 
#define FLD_AUD_SRC_A_RISC_EN   0x00001000
 
#define FLD_AUD_DST_D_RISC_EN   0x00000800
 
#define FLD_AUD_DST_C_RISC_EN   0x00000400
 
#define FLD_AUD_DST_B_RISC_EN   0x00000200
 
#define FLD_AUD_DST_A_RISC_EN   0x00000100
 
#define FLD_AUD_SRC_E_FIFO_EN   0x00000080
 
#define FLD_AUD_SRC_C_FIFO_EN   0x00000040
 
#define FLD_AUD_SRC_B_FIFO_EN   0x00000020
 
#define FLD_AUD_SRC_A_FIFO_EN   0x00000010
 
#define FLD_AUD_DST_D_FIFO_EN   0x00000008
 
#define FLD_AUD_DST_C_FIFO_EN   0x00000004
 
#define FLD_AUD_DST_B_FIFO_EN   0x00000002
 
#define FLD_AUD_DST_A_FIFO_EN   0x00000001
 
#define MB_IF_A_DMA   0x150000 /* MBIF A DMA data port */
 
#define MB_IF_A_GPCN   0x150008 /* MBIF A GP counter */
 
#define MB_IF_A_GPCN_CTRL   0x15000C
 
#define MB_IF_A_DMA_CTRL   0x150010
 
#define MB_IF_A_LENGTH   0x150014
 
#define MB_IF_A_HDMA_XFER_SZ   0x150018
 
#define MB_IF_A_HCMD   0x15001C
 
#define MB_IF_A_HCONFIG   0x150020
 
#define MB_IF_A_DATA_STRUCT_0   0x150024
 
#define MB_IF_A_DATA_STRUCT_1   0x150028
 
#define MB_IF_A_DATA_STRUCT_2   0x15002C
 
#define MB_IF_A_DATA_STRUCT_3   0x150030
 
#define MB_IF_A_DATA_STRUCT_4   0x150034
 
#define MB_IF_A_DATA_STRUCT_5   0x150038
 
#define MB_IF_A_DATA_STRUCT_6   0x15003C
 
#define MB_IF_A_DATA_STRUCT_7   0x150040
 
#define MB_IF_A_DATA_STRUCT_8   0x150044
 
#define MB_IF_A_DATA_STRUCT_9   0x150048
 
#define MB_IF_A_DATA_STRUCT_A   0x15004C
 
#define MB_IF_A_DATA_STRUCT_B   0x150050
 
#define MB_IF_A_DATA_STRUCT_C   0x150054
 
#define MB_IF_A_DATA_STRUCT_D   0x150058
 
#define MB_IF_A_DATA_STRUCT_E   0x15005C
 
#define MB_IF_A_DATA_STRUCT_F   0x150060
 
#define MB_IF_B_DMA   0x160000 /* MBIF A DMA data port */
 
#define MB_IF_B_GPCN   0x160008 /* MBIF A GP counter */
 
#define MB_IF_B_GPCN_CTRL   0x16000C
 
#define MB_IF_B_DMA_CTRL   0x160010
 
#define MB_IF_B_LENGTH   0x160014
 
#define MB_IF_B_HDMA_XFER_SZ   0x160018
 
#define MB_IF_B_HCMD   0x16001C
 
#define MB_IF_B_HCONFIG   0x160020
 
#define MB_IF_B_DATA_STRUCT_0   0x160024
 
#define MB_IF_B_DATA_STRUCT_1   0x160028
 
#define MB_IF_B_DATA_STRUCT_2   0x16002C
 
#define MB_IF_B_DATA_STRUCT_3   0x160030
 
#define MB_IF_B_DATA_STRUCT_4   0x160034
 
#define MB_IF_B_DATA_STRUCT_5   0x160038
 
#define MB_IF_B_DATA_STRUCT_6   0x16003C
 
#define MB_IF_B_DATA_STRUCT_7   0x160040
 
#define MB_IF_B_DATA_STRUCT_8   0x160044
 
#define MB_IF_B_DATA_STRUCT_9   0x160048
 
#define MB_IF_B_DATA_STRUCT_A   0x16004C
 
#define MB_IF_B_DATA_STRUCT_B   0x160050
 
#define MB_IF_B_DATA_STRUCT_C   0x160054
 
#define MB_IF_B_DATA_STRUCT_D   0x160058
 
#define MB_IF_B_DATA_STRUCT_E   0x16005C
 
#define MB_IF_B_DATA_STRUCT_F   0x160060
 
#define FLD_MB_IF_RISC_EN   0x00000010
 
#define FLD_MB_IF_FIFO_EN   0x00000001
 
#define FLD_MB_IF_LN_LNGTH   0x00000FFF
 
#define FLD_MB_HCMD_H_GO   0x80000000
 
#define FLD_MB_HCMD_H_BUSY   0x40000000
 
#define FLD_MB_HCMD_H_DMA_HOLD   0x10000000
 
#define FLD_MB_HCMD_H_DMA_BUSY   0x08000000
 
#define FLD_MB_HCMD_H_DMA_TYPE   0x04000000
 
#define FLD_MB_HCMD_H_DMA_XACT   0x02000000
 
#define FLD_MB_HCMD_H_RW_N   0x01000000
 
#define FLD_MB_HCMD_H_ADDR   0x00FF0000
 
#define FLD_MB_HCMD_H_DATA   0x0000FFFF
 
#define I2C1_ADDR   0x180000 /* I2C #1 address */
 
#define FLD_I2C_DADDR   0xfe000000 /* RW [31:25] I2C Device Address */
 
#define FLD_I2C_SADDR   0x00FFFFFF /* RW [23:0] I2C Sub-address */
 
#define I2C1_WDATA   0x180004 /* I2C #1 write data */
 
#define FLD_I2C_WDATA   0xFFFFFFFF /* RW [31:0] */
 
#define I2C1_CTRL   0x180008 /* I2C #1 control */
 
#define FLD_I2C_PERIOD   0xFF000000 /* RW [31:24] */
 
#define FLD_I2C_SCL_IN   0x00200000 /* RW [21] */
 
#define FLD_I2C_SDA_IN   0x00100000 /* RW [20] */
 
#define FLD_I2C_SCL_OUT   0x00020000 /* RW [17] */
 
#define FLD_I2C_SDA_OUT   0x00010000 /* RW [16] */
 
#define FLD_I2C_DATA_LEN   0x00007000 /* RW [14:12] */
 
#define FLD_I2C_SADDR_INC   0x00000800 /* RW [11] */
 
#define FLD_I2C_SADDR_LEN   0x00000300 /* RW [9:8] */
 
#define FLD_I2C_SOFT   0x00000020 /* RW [5] */
 
#define FLD_I2C_NOSTOP   0x00000010 /* RW [4] */
 
#define FLD_I2C_EXTEND   0x00000008 /* RW [3] */
 
#define FLD_I2C_SYNC   0x00000004 /* RW [2] */
 
#define FLD_I2C_READ_SA   0x00000002 /* RW [1] */
 
#define FLD_I2C_READ_WRN   0x00000001 /* RW [0] */
 
#define I2C1_RDATA   0x18000C /* I2C #1 read data */
 
#define FLD_I2C_RDATA   0xFFFFFFFF /* RO [31:0] */
 
#define I2C1_STAT   0x180010 /* I2C #1 status */
 
#define FLD_I2C_XFER_IN_PROG   0x00000002 /* RO [1] */
 
#define FLD_I2C_RACK   0x00000001 /* RO [0] */
 
#define I2C2_ADDR   0x190000 /* I2C #2 address */
 
#define I2C2_WDATA   0x190004 /* I2C #2 write data */
 
#define I2C2_CTRL   0x190008 /* I2C #2 control */
 
#define I2C2_RDATA   0x19000C /* I2C #2 read data */
 
#define I2C2_STAT   0x190010 /* I2C #2 status */
 
#define I2C3_ADDR   0x1A0000 /* I2C #3 address */
 
#define I2C3_WDATA   0x1A0004 /* I2C #3 write data */
 
#define I2C3_CTRL   0x1A0008 /* I2C #3 control */
 
#define I2C3_RDATA   0x1A000C /* I2C #3 read data */
 
#define I2C3_STAT   0x1A0010 /* I2C #3 status */
 
#define UART_CTL   0x1B0000 /* UART Control Register */
 
#define FLD_LOOP_BACK_EN   (1 << 7) /* RW field - default 0 */
 
#define FLD_RX_TRG_SZ   (3 << 2) /* RW field - default 0 */
 
#define FLD_RX_EN   (1 << 1) /* RW field - default 0 */
 
#define FLD_TX_EN   (1 << 0) /* RW field - default 0 */
 
#define UART_BRD   0x1B0004 /* UART Baud Rate Divisor */
 
#define FLD_BRD   0x0000FFFF /* RW field - default 0x197 */
 
#define UART_DBUF   0x1B0008 /* UART Tx/Rx Data BuFFer */
 
#define FLD_DB   0xFFFFFFFF /* RW field - default 0 */
 
#define UART_ISR   0x1B000C /* UART Interrupt Status */
 
#define FLD_RXD_TIMEOUT_EN   (1 << 7) /* RW field - default 0 */
 
#define FLD_FRM_ERR_EN   (1 << 6) /* RW field - default 0 */
 
#define FLD_RXD_RDY_EN   (1 << 5) /* RW field - default 0 */
 
#define FLD_TXD_EMPTY_EN   (1 << 4) /* RW field - default 0 */
 
#define FLD_RXD_OVERFLOW   (1 << 3) /* RW field - default 0 */
 
#define FLD_FRM_ERR   (1 << 2) /* RW field - default 0 */
 
#define FLD_RXD_RDY   (1 << 1) /* RW field - default 0 */
 
#define FLD_TXD_EMPTY   (1 << 0) /* RW field - default 0 */
 
#define UART_CNT   0x1B0010 /* UART Tx/Rx FIFO Byte Count */
 
#define FLD_TXD_CNT   (0x1F << 8) /* RW field - default 0 */
 
#define FLD_RXD_CNT   (0x1F << 0) /* RW field - default 0 */
 
#define MD_CH0_GRID_BLOCK_YCNT   0x170014
 
#define MD_CH1_GRID_BLOCK_YCNT   0x170094
 
#define MD_CH2_GRID_BLOCK_YCNT   0x170114
 
#define MD_CH3_GRID_BLOCK_YCNT   0x170194
 
#define MD_CH4_GRID_BLOCK_YCNT   0x170214
 
#define MD_CH5_GRID_BLOCK_YCNT   0x170294
 
#define MD_CH6_GRID_BLOCK_YCNT   0x170314
 
#define MD_CH7_GRID_BLOCK_YCNT   0x170394
 
#define PIXEL_FRMT_422   4
 
#define PIXEL_FRMT_411   5
 
#define PIXEL_FRMT_Y8   6
 
#define PIXEL_ENGINE_VIP1   0
 
#define PIXEL_ENGINE_VIP2   1
 

Macro Definition Documentation

#define ALT_PIN_IN_SEL   0x110030 /* Alternate GPIO input select */

Definition at line 1021 of file cx25821-reg.h.

#define ALT_PIN_OUT_SEL   0x11002C /* Alternate GPIO output select */

Definition at line 938 of file cx25821-reg.h.

#define AUD_A_CFG   0x14001C /* Audio Int A configuration */

Definition at line 1295 of file cx25821-reg.h.

#define AUD_A_GPCNT   0x140010 /* Audio Int A gp counter */

Definition at line 1288 of file cx25821-reg.h.

#define AUD_A_GPCNT_CTL   0x140014 /* Audio Int A gp control */

Definition at line 1291 of file cx25821-reg.h.

#define AUD_A_INT_MSK   0x0400C0 /* Audio Int interrupt mask */

Definition at line 170 of file cx25821-reg.h.

#define AUD_A_INT_MSTAT   0x0400C8 /* Audio Int interrupt masked status */

Definition at line 172 of file cx25821-reg.h.

#define AUD_A_INT_SSTAT   0x0400CC /* Audio Int interrupt set status */

Definition at line 173 of file cx25821-reg.h.

#define AUD_A_INT_STAT   0x0400C4 /* Audio Int interrupt status */

Definition at line 171 of file cx25821-reg.h.

#define AUD_A_LNGTH   0x140018 /* Audio Int A line length */

Definition at line 1293 of file cx25821-reg.h.

#define AUD_B_CFG   0x14011C /* Audio Int B configuration */

Definition at line 1308 of file cx25821-reg.h.

#define AUD_B_GPCNT   0x140110 /* Audio Int B gp counter */

Definition at line 1301 of file cx25821-reg.h.

#define AUD_B_GPCNT_CTL   0x140114 /* Audio Int B gp control */

Definition at line 1304 of file cx25821-reg.h.

#define AUD_B_INT_MSK   0x0400D0 /* Audio Int interrupt mask */

Definition at line 176 of file cx25821-reg.h.

#define AUD_B_INT_MSTAT   0x0400D8 /* Audio Int interrupt masked status */

Definition at line 178 of file cx25821-reg.h.

#define AUD_B_INT_SSTAT   0x0400DC /* Audio Int interrupt set status */

Definition at line 179 of file cx25821-reg.h.

#define AUD_B_INT_STAT   0x0400D4 /* Audio Int interrupt status */

Definition at line 177 of file cx25821-reg.h.

#define AUD_B_LNGTH   0x140118 /* Audio Int B line length */

Definition at line 1306 of file cx25821-reg.h.

#define AUD_C_CFG   0x14021C /* Audio Int C configuration */

Definition at line 1321 of file cx25821-reg.h.

#define AUD_C_GPCNT   0x140210 /* Audio Int C gp counter */

Definition at line 1314 of file cx25821-reg.h.

#define AUD_C_GPCNT_CTL   0x140214 /* Audio Int C gp control */

Definition at line 1317 of file cx25821-reg.h.

#define AUD_C_INT_MSK   0x0400E0 /* Audio Int interrupt mask */

Definition at line 182 of file cx25821-reg.h.

#define AUD_C_INT_MSTAT   0x0400E8 /* Audio Int interrupt masked status */

Definition at line 184 of file cx25821-reg.h.

#define AUD_C_INT_SSTAT   0x0400EC /* Audio Int interrupt set status */

Definition at line 185 of file cx25821-reg.h.

#define AUD_C_INT_STAT   0x0400E4 /* Audio Int interrupt status */

Definition at line 183 of file cx25821-reg.h.

#define AUD_C_LNGTH   0x140218 /* Audio Int C line length */

Definition at line 1319 of file cx25821-reg.h.

#define AUD_D_CFG   0x14031C /* Audio Int D configuration */

Definition at line 1334 of file cx25821-reg.h.

#define AUD_D_GPCNT   0x140310 /* Audio Int D gp counter */

Definition at line 1327 of file cx25821-reg.h.

#define AUD_D_GPCNT_CTL   0x140314 /* Audio Int D gp control */

Definition at line 1330 of file cx25821-reg.h.

#define AUD_D_INT_MSK   0x0400F0 /* Audio Int interrupt mask */

Definition at line 188 of file cx25821-reg.h.

#define AUD_D_INT_MSTAT   0x0400F8 /* Audio Int interrupt masked status */

Definition at line 190 of file cx25821-reg.h.

#define AUD_D_INT_SSTAT   0x0400FC /* Audio Int interrupt set status */

Definition at line 191 of file cx25821-reg.h.

#define AUD_D_INT_STAT   0x0400F4 /* Audio Int interrupt status */

Definition at line 189 of file cx25821-reg.h.

#define AUD_D_LNGTH   0x140318 /* Audio Int D line length */

Definition at line 1332 of file cx25821-reg.h.

#define AUD_DST_A_DMA   0x140000 /* Audio Int A DMA data port */

Definition at line 1285 of file cx25821-reg.h.

#define AUD_DST_B_DMA   0x140100 /* Audio Int B DMA data port */

Definition at line 1298 of file cx25821-reg.h.

#define AUD_DST_C_DMA   0x140200 /* Audio Int C DMA data port */

Definition at line 1311 of file cx25821-reg.h.

#define AUD_DST_D_DMA   0x140300 /* Audio Int D DMA data port */

Definition at line 1324 of file cx25821-reg.h.

#define AUD_E_CFG   0x14041C /* Audio Int E configuration */

Definition at line 1344 of file cx25821-reg.h.

#define AUD_E_GPCNT   0x140410 /* Audio Int E gp counter */

Definition at line 1339 of file cx25821-reg.h.

#define AUD_E_GPCNT_CTL   0x140414 /* Audio Int E gp control */

Definition at line 1342 of file cx25821-reg.h.

#define AUD_E_INT_MSK   0x040100 /* Audio Int interrupt mask */

Definition at line 194 of file cx25821-reg.h.

#define AUD_E_INT_MSTAT   0x040108 /* Audio Int interrupt masked status */

Definition at line 196 of file cx25821-reg.h.

#define AUD_E_INT_SSTAT   0x04010C /* Audio Int interrupt set status */

Definition at line 197 of file cx25821-reg.h.

#define AUD_E_INT_STAT   0x040104 /* Audio Int interrupt status */

Definition at line 195 of file cx25821-reg.h.

#define AUD_EXT_INT_MSK   0x040060 /* Audio Ext interrupt mask */

Definition at line 229 of file cx25821-reg.h.

#define AUD_EXT_INT_MSTAT   0x040068 /* Audio Ext interrupt masked status */

Definition at line 231 of file cx25821-reg.h.

#define AUD_EXT_INT_SSTAT   0x04006C /* Audio Ext interrupt set status */

Definition at line 232 of file cx25821-reg.h.

#define AUD_EXT_INT_STAT   0x040064 /* Audio Ext interrupt status */

Definition at line 230 of file cx25821-reg.h.

#define AUD_INT_DMA_CTL   0x140500 /* Audio Int DMA control */

Definition at line 1365 of file cx25821-reg.h.

#define AUD_SRC_A_DMA   0x140008 /* Audio Int A DMA data port */

Definition at line 1286 of file cx25821-reg.h.

#define AUD_SRC_B_DMA   0x140108 /* Audio Int B DMA data port */

Definition at line 1299 of file cx25821-reg.h.

#define AUD_SRC_C_DMA   0x140208 /* Audio Int C DMA data port */

Definition at line 1312 of file cx25821-reg.h.

#define AUD_SRC_D_DMA   0x140308 /* Audio Int D DMA data port */

Definition at line 1325 of file cx25821-reg.h.

#define AUD_SRC_E_DMA   0x140400 /* Audio Int E DMA data port */

Definition at line 1337 of file cx25821-reg.h.

#define CLK_DELAY   0x110048 /* Clock delay */

Definition at line 1061 of file cx25821-reg.h.

#define CLK_RST   0x11002C

Definition at line 1085 of file cx25821-reg.h.

#define DEV_CNTRL2   0x040000 /* Device control */

Definition at line 62 of file cx25821-reg.h.

#define DMA10_CNT1   0x100124 /* DMA BuFFer Size : Ch#10 */

Definition at line 775 of file cx25821-reg.h.

#define DMA10_CNT2   0x1001A4 /* DMA Table Size : Ch#10 */

Definition at line 853 of file cx25821-reg.h.

#define DMA10_PTR1   0x100024 /* DMA Current Ptr : Ch#10 */

Definition at line 619 of file cx25821-reg.h.

#define DMA10_PTR2   0x1000A4 /* DMA Tab Ptr : Ch#10 */

Definition at line 697 of file cx25821-reg.h.

#define DMA11_CNT1   0x100128 /* DMA BuFFer Size : Ch#11 */

Definition at line 778 of file cx25821-reg.h.

#define DMA11_CNT2   0x1001A8 /* DMA Table Size : Ch#11 */

Definition at line 856 of file cx25821-reg.h.

#define DMA11_PTR1   0x100028 /* DMA Current Ptr : Ch#11 */

Definition at line 622 of file cx25821-reg.h.

#define DMA11_PTR2   0x1000A8 /* DMA Tab Ptr : Ch#11 */

Definition at line 700 of file cx25821-reg.h.

#define DMA12_CNT1   0x10012C /* DMA BuFFer Size : Ch#12 */

Definition at line 781 of file cx25821-reg.h.

#define DMA12_CNT2   0x1001AC /* DMA Table Size : Ch#12 */

Definition at line 859 of file cx25821-reg.h.

#define DMA12_PTR1   0x10002C /* DMA Current Ptr : Ch#12 */

Definition at line 625 of file cx25821-reg.h.

#define DMA12_PTR2   0x1000AC /* DMA Tab Ptr : Ch#12 */

Definition at line 703 of file cx25821-reg.h.

#define DMA13_CNT1   0x100130 /* DMA BuFFer Size : Ch#13 */

Definition at line 784 of file cx25821-reg.h.

#define DMA13_CNT2   0x1001B0 /* DMA Table Size : Ch#13 */

Definition at line 862 of file cx25821-reg.h.

#define DMA13_PTR1   0x100030 /* DMA Current Ptr : Ch#13 */

Definition at line 628 of file cx25821-reg.h.

#define DMA13_PTR2   0x1000B0 /* DMA Tab Ptr : Ch#13 */

Definition at line 706 of file cx25821-reg.h.

#define DMA14_CNT1   0x100134 /* DMA BuFFer Size : Ch#14 */

Definition at line 787 of file cx25821-reg.h.

#define DMA14_CNT2   0x1001B4 /* DMA Table Size : Ch#14 */

Definition at line 865 of file cx25821-reg.h.

#define DMA14_PTR1   0x100034 /* DMA Current Ptr : Ch#14 */

Definition at line 631 of file cx25821-reg.h.

#define DMA14_PTR2   0x1000B4 /* DMA Tab Ptr : Ch#14 */

Definition at line 709 of file cx25821-reg.h.

#define DMA15_CNT1   0x100138 /* DMA BuFFer Size : Ch#15 */

Definition at line 790 of file cx25821-reg.h.

#define DMA15_CNT2   0x1001B8 /* DMA Table Size : Ch#15 */

Definition at line 868 of file cx25821-reg.h.

#define DMA15_PTR1   0x100038 /* DMA Current Ptr : Ch#15 */

Definition at line 634 of file cx25821-reg.h.

#define DMA15_PTR2   0x1000B8 /* DMA Tab Ptr : Ch#15 */

Definition at line 712 of file cx25821-reg.h.

#define DMA16_CNT1   0x10013C /* DMA BuFFer Size : Ch#16 */

Definition at line 793 of file cx25821-reg.h.

#define DMA16_CNT2   0x1001BC /* DMA Table Size : Ch#16 */

Definition at line 871 of file cx25821-reg.h.

#define DMA16_PTR1   0x10003C /* DMA Current Ptr : Ch#16 */

Definition at line 637 of file cx25821-reg.h.

#define DMA16_PTR2   0x1000BC /* DMA Tab Ptr : Ch#16 */

Definition at line 715 of file cx25821-reg.h.

#define DMA17_CNT1   0x100140 /* DMA BuFFer Size : Ch#17 */

Definition at line 796 of file cx25821-reg.h.

#define DMA17_CNT2   0x1001C0 /* DMA Table Size : Ch#17 */

Definition at line 874 of file cx25821-reg.h.

#define DMA17_PTR1   0x100040 /* DMA Current Ptr : Ch#17 */

Definition at line 640 of file cx25821-reg.h.

#define DMA17_PTR2   0x1000C0 /* DMA Tab Ptr : Ch#17 */

Definition at line 718 of file cx25821-reg.h.

#define DMA18_CNT1   0x100144 /* DMA BuFFer Size : Ch#18 */

Definition at line 799 of file cx25821-reg.h.

#define DMA18_CNT2   0x1001C4 /* DMA Table Size : Ch#18 */

Definition at line 877 of file cx25821-reg.h.

#define DMA18_PTR1   0x100044 /* DMA Current Ptr : Ch#18 */

Definition at line 643 of file cx25821-reg.h.

#define DMA18_PTR2   0x1000C4 /* DMA Tab Ptr : Ch#18 */

Definition at line 721 of file cx25821-reg.h.

#define DMA19_CNT1   0x100148 /* DMA BuFFer Size : Ch#19 */

Definition at line 802 of file cx25821-reg.h.

#define DMA19_CNT2   0x1001C8 /* DMA Table Size : Ch#19 */

Definition at line 880 of file cx25821-reg.h.

#define DMA19_PTR1   0x100048 /* DMA Current Ptr : Ch#19 */

Definition at line 646 of file cx25821-reg.h.

#define DMA19_PTR2   0x1000C8 /* DMA Tab Ptr : Ch#19 */

Definition at line 724 of file cx25821-reg.h.

#define DMA1_CNT1   0x100100 /* DMA BuFFer Size : Ch#1 */

Definition at line 748 of file cx25821-reg.h.

#define DMA1_CNT2   0x100180 /* DMA Table Size : Ch#1 */

Definition at line 826 of file cx25821-reg.h.

#define DMA1_PTR1   0x100000 /* DMA Current Ptr : Ch#1 */

Definition at line 592 of file cx25821-reg.h.

#define DMA1_PTR2   0x100080 /* DMA Tab Ptr : Ch#1 */

Definition at line 670 of file cx25821-reg.h.

#define DMA20_CNT1   0x10014C /* DMA BuFFer Size : Ch#20 */

Definition at line 805 of file cx25821-reg.h.

#define DMA20_CNT2   0x1001CC /* DMA Table Size : Ch#20 */

Definition at line 883 of file cx25821-reg.h.

#define DMA20_PTR1   0x10004C /* DMA Current Ptr : Ch#20 */

Definition at line 649 of file cx25821-reg.h.

#define DMA20_PTR2   0x1000CC /* DMA Tab Ptr : Ch#20 */

Definition at line 727 of file cx25821-reg.h.

#define DMA21_CNT1   0x100150 /* DMA BuFFer Size : Ch#21 */

Definition at line 808 of file cx25821-reg.h.

#define DMA21_CNT2   0x1001D0 /* DMA Table Size : Ch#21 */

Definition at line 886 of file cx25821-reg.h.

#define DMA21_PTR1   0x100050 /* DMA Current Ptr : Ch#21 */

Definition at line 652 of file cx25821-reg.h.

#define DMA21_PTR2   0x1000D0 /* DMA Tab Ptr : Ch#21 */

Definition at line 730 of file cx25821-reg.h.

#define DMA22_CNT1   0x100154 /* DMA BuFFer Size : Ch#22 */

Definition at line 811 of file cx25821-reg.h.

#define DMA22_CNT2   0x1001D4 /* DMA Table Size : Ch#22 */

Definition at line 889 of file cx25821-reg.h.

#define DMA22_PTR1   0x100054 /* DMA Current Ptr : Ch#22 */

Definition at line 655 of file cx25821-reg.h.

#define DMA22_PTR2   0x1000D4 /* DMA Tab Ptr : Ch#22 */

Definition at line 733 of file cx25821-reg.h.

#define DMA23_CNT1   0x100158 /* DMA BuFFer Size : Ch#23 */

Definition at line 814 of file cx25821-reg.h.

#define DMA23_CNT2   0x1001D8 /* DMA Table Size : Ch#23 */

Definition at line 892 of file cx25821-reg.h.

#define DMA23_PTR1   0x100058 /* DMA Current Ptr : Ch#23 */

Definition at line 658 of file cx25821-reg.h.

#define DMA23_PTR2   0x1000D8 /* DMA Tab Ptr : Ch#23 */

Definition at line 736 of file cx25821-reg.h.

#define DMA24_CNT1   0x10015C /* DMA BuFFer Size : Ch#24 */

Definition at line 817 of file cx25821-reg.h.

#define DMA24_CNT2   0x1001DC /* DMA Table Size : Ch#24 */

Definition at line 895 of file cx25821-reg.h.

#define DMA24_PTR1   0x10005C /* DMA Current Ptr : Ch#24 */

Definition at line 661 of file cx25821-reg.h.

#define DMA24_PTR2   0x1000DC /* DMA Tab Ptr : Ch#24 */

Definition at line 739 of file cx25821-reg.h.

#define DMA25_CNT1   0x100160 /* DMA BuFFer Size : Ch#25 */

Definition at line 820 of file cx25821-reg.h.

#define DMA25_CNT2   0x1001E0 /* DMA Table Size : Ch#25 */

Definition at line 898 of file cx25821-reg.h.

#define DMA25_PTR1   0x100060 /* DMA Current Ptr : Ch#25 */

Definition at line 664 of file cx25821-reg.h.

#define DMA25_PTR2   0x1000E0 /* DMA Tab Ptr : Ch#25 */

Definition at line 742 of file cx25821-reg.h.

#define DMA26_CNT1   0x100164 /* DMA BuFFer Size : Ch#26 */

Definition at line 823 of file cx25821-reg.h.

#define DMA26_CNT2   0x1001E4 /* DMA Table Size : Ch#26 */

Definition at line 901 of file cx25821-reg.h.

#define DMA26_PTR1   0x100064 /* DMA Current Ptr : Ch#26 */

Definition at line 667 of file cx25821-reg.h.

#define DMA26_PTR2   0x1000E4 /* DMA Tab Ptr : Ch#26 */

Definition at line 745 of file cx25821-reg.h.

#define DMA2_CNT1   0x100104 /* DMA BuFFer Size : Ch#2 */

Definition at line 751 of file cx25821-reg.h.

#define DMA2_CNT2   0x100184 /* DMA Table Size : Ch#2 */

Definition at line 829 of file cx25821-reg.h.

#define DMA2_PTR1   0x100004 /* DMA Current Ptr : Ch#2 */

Definition at line 595 of file cx25821-reg.h.

#define DMA2_PTR2   0x100084 /* DMA Tab Ptr : Ch#2 */

Definition at line 673 of file cx25821-reg.h.

#define DMA3_CNT1   0x100108 /* DMA BuFFer Size : Ch#3 */

Definition at line 754 of file cx25821-reg.h.

#define DMA3_CNT2   0x100188 /* DMA Table Size : Ch#3 */

Definition at line 832 of file cx25821-reg.h.

#define DMA3_PTR1   0x100008 /* DMA Current Ptr : Ch#3 */

Definition at line 598 of file cx25821-reg.h.

#define DMA3_PTR2   0x100088 /* DMA Tab Ptr : Ch#3 */

Definition at line 676 of file cx25821-reg.h.

#define DMA4_CNT1   0x10010C /* DMA BuFFer Size : Ch#4 */

Definition at line 757 of file cx25821-reg.h.

#define DMA4_CNT2   0x10018C /* DMA Table Size : Ch#4 */

Definition at line 835 of file cx25821-reg.h.

#define DMA4_PTR1   0x10000C /* DMA Current Ptr : Ch#4 */

Definition at line 601 of file cx25821-reg.h.

#define DMA4_PTR2   0x10008C /* DMA Tab Ptr : Ch#4 */

Definition at line 679 of file cx25821-reg.h.

#define DMA5_CNT1   0x100110 /* DMA BuFFer Size : Ch#5 */

Definition at line 760 of file cx25821-reg.h.

#define DMA5_CNT2   0x100190 /* DMA Table Size : Ch#5 */

Definition at line 838 of file cx25821-reg.h.

#define DMA5_PTR1   0x100010 /* DMA Current Ptr : Ch#5 */

Definition at line 604 of file cx25821-reg.h.

#define DMA5_PTR2   0x100090 /* DMA Tab Ptr : Ch#5 */

Definition at line 682 of file cx25821-reg.h.

#define DMA6_CNT1   0x100114 /* DMA BuFFer Size : Ch#6 */

Definition at line 763 of file cx25821-reg.h.

#define DMA6_CNT2   0x100194 /* DMA Table Size : Ch#6 */

Definition at line 841 of file cx25821-reg.h.

#define DMA6_PTR1   0x100014 /* DMA Current Ptr : Ch#6 */

Definition at line 607 of file cx25821-reg.h.

#define DMA6_PTR2   0x100094 /* DMA Tab Ptr : Ch#6 */

Definition at line 685 of file cx25821-reg.h.

#define DMA7_CNT1   0x100118 /* DMA BuFFer Size : Ch#7 */

Definition at line 766 of file cx25821-reg.h.

#define DMA7_CNT2   0x100198 /* DMA Table Size : Ch#7 */

Definition at line 844 of file cx25821-reg.h.

#define DMA7_PTR1   0x100018 /* DMA Current Ptr : Ch#7 */

Definition at line 610 of file cx25821-reg.h.

#define DMA7_PTR2   0x100098 /* DMA Tab Ptr : Ch#7 */

Definition at line 688 of file cx25821-reg.h.

#define DMA8_CNT1   0x10011C /* DMA BuFFer Size : Ch#8 */

Definition at line 769 of file cx25821-reg.h.

#define DMA8_CNT2   0x10019C /* DMA Table Size : Ch#8 */

Definition at line 847 of file cx25821-reg.h.

#define DMA8_PTR1   0x10001C /* DMA Current Ptr : Ch#8 */

Definition at line 613 of file cx25821-reg.h.

#define DMA8_PTR2   0x10009C /* DMA Tab Ptr : Ch#8 */

Definition at line 691 of file cx25821-reg.h.

#define DMA9_CNT1   0x100120 /* DMA BuFFer Size : Ch#9 */

Definition at line 772 of file cx25821-reg.h.

#define DMA9_CNT2   0x1001A0 /* DMA Table Size : Ch#9 */

Definition at line 850 of file cx25821-reg.h.

#define DMA9_PTR1   0x100020 /* DMA Current Ptr : Ch#9 */

Definition at line 616 of file cx25821-reg.h.

#define DMA9_PTR2   0x1000A0 /* DMA Tab Ptr : Ch#9 */

Definition at line 694 of file cx25821-reg.h.

#define FLD_AL_RD_BERR_INT   (1 << 19)

Definition at line 82 of file cx25821-reg.h.

#define FLD_AL_WR_BERR_INT   (1 << 20)

Definition at line 81 of file cx25821-reg.h.

#define FLD_ALT_GPIO_OUT_SEL   0xF0000000

Definition at line 940 of file cx25821-reg.h.

#define FLD_APB_DMA_BERR_INT   (1 << 21)

Definition at line 80 of file cx25821-reg.h.

#define FLD_APB_FIFO_EN   0x00000001

Definition at line 1236 of file cx25821-reg.h.

#define FLD_APB_RISC_EN   0x00000010

Definition at line 1235 of file cx25821-reg.h.

#define FLD_AUD_A_GP_CNT   0x0000FFFF

Definition at line 1289 of file cx25821-reg.h.

#define FLD_AUD_B_GP_CNT   0x0000FFFF

Definition at line 1302 of file cx25821-reg.h.

#define FLD_AUD_C_GP_CNT   0x0000FFFF

Definition at line 1315 of file cx25821-reg.h.

#define FLD_AUD_CLK_ENABLE   0x00000200

Definition at line 1352 of file cx25821-reg.h.

#define FLD_AUD_CLK_SELECT_PLL_D   0x00001800

Definition at line 1358 of file cx25821-reg.h.

#define FLD_AUD_D_GP_CNT   0x0000FFFF

Definition at line 1328 of file cx25821-reg.h.

#define FLD_AUD_DST_A_FIFO_EN   0x00000001

Definition at line 1385 of file cx25821-reg.h.

#define FLD_AUD_DST_A_RISC_EN   0x00000100

Definition at line 1375 of file cx25821-reg.h.

#define FLD_AUD_DST_B_FIFO_EN   0x00000002

Definition at line 1384 of file cx25821-reg.h.

#define FLD_AUD_DST_B_RISC_EN   0x00000200

Definition at line 1374 of file cx25821-reg.h.

#define FLD_AUD_DST_C_FIFO_EN   0x00000004

Definition at line 1383 of file cx25821-reg.h.

#define FLD_AUD_DST_C_RISC_EN   0x00000400

Definition at line 1373 of file cx25821-reg.h.

#define FLD_AUD_DST_D_FIFO_EN   0x00000008

Definition at line 1382 of file cx25821-reg.h.

#define FLD_AUD_DST_D_RISC_EN   0x00000800

Definition at line 1372 of file cx25821-reg.h.

#define FLD_AUD_DST_ENABLE   0x00020000

Definition at line 1360 of file cx25821-reg.h.

#define FLD_AUD_DST_LN_LNGTH   0x00000FFF

Definition at line 1348 of file cx25821-reg.h.

#define FLD_AUD_DST_OF   0x00000100

Definition at line 204 of file cx25821-reg.h.

#define FLD_AUD_DST_OPC_ERR   0x00010000

Definition at line 200 of file cx25821-reg.h.

#define FLD_AUD_DST_PK_MODE   0x00004000

Definition at line 1350 of file cx25821-reg.h.

#define FLD_AUD_DST_RISCI1   0x00000001

Definition at line 208 of file cx25821-reg.h.

#define FLD_AUD_DST_RISCI2   0x00000010

Definition at line 206 of file cx25821-reg.h.

#define FLD_AUD_DST_SYNC   0x00001000

Definition at line 202 of file cx25821-reg.h.

#define FLD_AUD_E_GP_CNT   0x0000FFFF

Definition at line 1340 of file cx25821-reg.h.

#define FLD_AUD_EXT_OF   0x00000100

Definition at line 235 of file cx25821-reg.h.

#define FLD_AUD_EXT_OPC_ERR   0x00010000

Definition at line 233 of file cx25821-reg.h.

#define FLD_AUD_EXT_RISCI1   0x00000001

Definition at line 237 of file cx25821-reg.h.

#define FLD_AUD_EXT_RISCI2   0x00000010

Definition at line 236 of file cx25821-reg.h.

#define FLD_AUD_EXT_SYNC   0x00001000

Definition at line 234 of file cx25821-reg.h.

#define FLD_AUD_MASTER_MODE   0x00000002

Definition at line 1354 of file cx25821-reg.h.

#define FLD_AUD_SONY_MODE   0x00000001

Definition at line 1356 of file cx25821-reg.h.

#define FLD_AUD_SRC_A_FIFO_EN   0x00000010

Definition at line 1380 of file cx25821-reg.h.

#define FLD_AUD_SRC_A_RISC_EN   0x00001000

Definition at line 1370 of file cx25821-reg.h.

#define FLD_AUD_SRC_B_FIFO_EN   0x00000020

Definition at line 1379 of file cx25821-reg.h.

#define FLD_AUD_SRC_B_RISC_EN   0x00002000

Definition at line 1369 of file cx25821-reg.h.

#define FLD_AUD_SRC_C_FIFO_EN   0x00000040

Definition at line 1378 of file cx25821-reg.h.

#define FLD_AUD_SRC_C_RISC_EN   0x00004000

Definition at line 1368 of file cx25821-reg.h.

#define FLD_AUD_SRC_E_FIFO_EN   0x00000080

Definition at line 1377 of file cx25821-reg.h.

#define FLD_AUD_SRC_E_RISC_EN   0x00008000

Definition at line 1367 of file cx25821-reg.h.

#define FLD_AUD_SRC_ENABLE   0x00010000

Definition at line 1362 of file cx25821-reg.h.

#define FLD_AUD_SRC_OF   0x00000200

Definition at line 203 of file cx25821-reg.h.

#define FLD_AUD_SRC_OPC_ERR   0x00020000

Definition at line 199 of file cx25821-reg.h.

#define FLD_AUD_SRC_RISCI1   0x00000002

Definition at line 207 of file cx25821-reg.h.

#define FLD_AUD_SRC_RISCI2   0x00000020

Definition at line 205 of file cx25821-reg.h.

#define FLD_AUD_SRC_SYNC   0x00002000

Definition at line 201 of file cx25821-reg.h.

#define FLD_AUX_PLL_CLK_ALT_SEL   0x0F000000

Definition at line 951 of file cx25821-reg.h.

#define FLD_BRD   0x0000FFFF /* RW field - default 0x197 */

Definition at line 1552 of file cx25821-reg.h.

#define FLD_CFG_BNDRY_CK_EN   0x00000008

Definition at line 508 of file cx25821-reg.h.

#define FLD_CFG_BYTE_EN_CK_EN   0x00000004

Definition at line 509 of file cx25821-reg.h.

#define FLD_CFG_CORR_ERR_QUITE   0x00000020

Definition at line 506 of file cx25821-reg.h.

#define FLD_CFG_RCB_CK_EN   0x00000010

Definition at line 507 of file cx25821-reg.h.

#define FLD_CFG_RELAX_ORDER_MSK   0x00000002

Definition at line 510 of file cx25821-reg.h.

#define FLD_CFG_TAG_ORDER_EN   0x00000001

Definition at line 511 of file cx25821-reg.h.

#define FLD_CFG_UR_CPL_MODE   0x00000040

Definition at line 505 of file cx25821-reg.h.

#define FLD_DB   0xFFFFFFFF /* RW field - default 0 */

Definition at line 1556 of file cx25821-reg.h.

#define FLD_FRM_ERR   (1 << 2) /* RW field - default 0 */

Definition at line 1565 of file cx25821-reg.h.

#define FLD_FRM_ERR_EN   (1 << 6) /* RW field - default 0 */

Definition at line 1561 of file cx25821-reg.h.

#define FLD_GP_IN   0x0000FF00 /* GPIO: GP_IN status */

Definition at line 920 of file cx25821-reg.h.

#define FLD_GP_ISM_POL   0x00000007

Definition at line 926 of file cx25821-reg.h.

#define FLD_GP_ISM_SNS   0x00000070

Definition at line 925 of file cx25821-reg.h.

#define FLD_GP_OE   0x00FF0000 /* GPIO: GP_OE output enable */

Definition at line 919 of file cx25821-reg.h.

#define FLD_GP_OUT   0x000000FF /* GPIO: GP_OUT control */

Definition at line 921 of file cx25821-reg.h.

#define FLD_GPIO0_ALT_IN_SEL   0x0000000F

Definition at line 1047 of file cx25821-reg.h.

#define FLD_GPIO0_ALT_SEL   0x0000000F

Definition at line 1011 of file cx25821-reg.h.

#define FLD_GPIO0_INT   (1 << 0)

Definition at line 272 of file cx25821-reg.h.

#define FLD_GPIO10_ALT_IN_SEL   0x0000F000

Definition at line 1023 of file cx25821-reg.h.

#define FLD_GPIO10_ALT_SEL   0x0000F000

Definition at line 981 of file cx25821-reg.h.

#define FLD_GPIO1_ALT_IN_SEL   0x000000F0

Definition at line 1040 of file cx25821-reg.h.

#define FLD_GPIO1_ALT_SEL   0x000000F0

Definition at line 1001 of file cx25821-reg.h.

#define FLD_GPIO1_INT   (1 << 1)

Definition at line 271 of file cx25821-reg.h.

#define FLD_GPIO2_ALT_IN_SEL   0x00000F00

Definition at line 1033 of file cx25821-reg.h.

#define FLD_GPIO2_ALT_SEL   0x00000F00

Definition at line 991 of file cx25821-reg.h.

#define FLD_GPIO2_INT   (1 << 2)

Definition at line 270 of file cx25821-reg.h.

#define FLD_GPIO3_INT   (1 << 3)

Definition at line 269 of file cx25821-reg.h.

#define FLD_GPIO40_INT   (1 << 8)

Definition at line 261 of file cx25821-reg.h.

#define FLD_GPIO41_INT   (1 << 9)

Definition at line 260 of file cx25821-reg.h.

#define FLD_GPIO42_INT   (1 << 10)

Definition at line 259 of file cx25821-reg.h.

#define FLD_GPIO43_INT   (1 << 11)

Definition at line 258 of file cx25821-reg.h.

#define FLD_GPIO4_INT   (1 << 4)

Definition at line 268 of file cx25821-reg.h.

#define FLD_GPIO5_INT   (1 << 5)

Definition at line 267 of file cx25821-reg.h.

#define FLD_GPIO6_INT   (1 << 6)

Definition at line 266 of file cx25821-reg.h.

#define FLD_GPIO7_INT   (1 << 7)

Definition at line 265 of file cx25821-reg.h.

#define FLD_GPIO8_INT   (1 << 8)

Definition at line 264 of file cx25821-reg.h.

#define FLD_GPIO9_INT   (1 << 9)

Definition at line 263 of file cx25821-reg.h.

#define FLD_HAMMERHEAD_INT   (1 << 27)

Definition at line 69 of file cx25821-reg.h.

#define FLD_I2C_1_INT   (1 << 22)

Definition at line 78 of file cx25821-reg.h.

#define FLD_I2C_1_RACK   (1 << 23)

Definition at line 77 of file cx25821-reg.h.

#define FLD_I2C_2_INT   (1 << 24)

Definition at line 76 of file cx25821-reg.h.

#define FLD_I2C_2_RACK   (1 << 25)

Definition at line 75 of file cx25821-reg.h.

#define FLD_I2C_3_INT   (1 << 26)

Definition at line 74 of file cx25821-reg.h.

#define FLD_I2C_3_RACK   (1 << 27)

Definition at line 73 of file cx25821-reg.h.

#define FLD_I2C_DADDR   0xfe000000 /* RW [31:25] I2C Device Address */

Definition at line 1468 of file cx25821-reg.h.

#define FLD_I2C_DATA_LEN   0x00007000 /* RW [14:12] */

Definition at line 1486 of file cx25821-reg.h.

#define FLD_I2C_EXTEND   0x00000008 /* RW [3] */

Definition at line 1493 of file cx25821-reg.h.

#define FLD_I2C_NOSTOP   0x00000010 /* RW [4] */

Definition at line 1492 of file cx25821-reg.h.

#define FLD_I2C_PERIOD   0xFF000000 /* RW [31:24] */

Definition at line 1479 of file cx25821-reg.h.

#define FLD_I2C_RACK   0x00000001 /* RO [0] */

Definition at line 1505 of file cx25821-reg.h.

#define FLD_I2C_RDATA   0xFFFFFFFF /* RO [31:0] */

Definition at line 1500 of file cx25821-reg.h.

#define FLD_I2C_READ_SA   0x00000002 /* RW [1] */

Definition at line 1495 of file cx25821-reg.h.

#define FLD_I2C_READ_WRN   0x00000001 /* RW [0] */

Definition at line 1496 of file cx25821-reg.h.

#define FLD_I2C_SADDR   0x00FFFFFF /* RW [23:0] I2C Sub-address */

Definition at line 1471 of file cx25821-reg.h.

#define FLD_I2C_SADDR_INC   0x00000800 /* RW [11] */

Definition at line 1487 of file cx25821-reg.h.

#define FLD_I2C_SADDR_LEN   0x00000300 /* RW [9:8] */

Definition at line 1489 of file cx25821-reg.h.

#define FLD_I2C_SCL_IN   0x00200000 /* RW [21] */

Definition at line 1480 of file cx25821-reg.h.

#define FLD_I2C_SCL_OUT   0x00020000 /* RW [17] */

Definition at line 1483 of file cx25821-reg.h.

#define FLD_I2C_SDA_IN   0x00100000 /* RW [20] */

Definition at line 1481 of file cx25821-reg.h.

#define FLD_I2C_SDA_OUT   0x00010000 /* RW [16] */

Definition at line 1484 of file cx25821-reg.h.

#define FLD_I2C_SOFT   0x00000020 /* RW [5] */

Definition at line 1491 of file cx25821-reg.h.

#define FLD_I2C_SYNC   0x00000004 /* RW [2] */

Definition at line 1494 of file cx25821-reg.h.

#define FLD_I2C_WDATA   0xFFFFFFFF /* RW [31:0] */

Definition at line 1475 of file cx25821-reg.h.

#define FLD_I2C_XFER_IN_PROG   0x00000002 /* RO [1] */

Definition at line 1504 of file cx25821-reg.h.

#define FLD_IR_RX_ALT_SEL   0x000F0000

Definition at line 971 of file cx25821-reg.h.

#define FLD_IR_TX_ALT_SEL   0x00F00000

Definition at line 961 of file cx25821-reg.h.

#define FLD_IRQN_INT   (1 << 25)

Definition at line 71 of file cx25821-reg.h.

#define FLD_LOOP_BACK_EN   (1 << 7) /* RW field - default 0 */

Definition at line 1545 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_ADDR   0x00FF0000

Definition at line 1461 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_BUSY   0x40000000

Definition at line 1455 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_DATA   0x0000FFFF

Definition at line 1462 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_DMA_BUSY   0x08000000

Definition at line 1457 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_DMA_HOLD   0x10000000

Definition at line 1456 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_DMA_TYPE   0x04000000

Definition at line 1458 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_DMA_XACT   0x02000000

Definition at line 1459 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_GO   0x80000000

Definition at line 1454 of file cx25821-reg.h.

#define FLD_MB_HCMD_H_RW_N   0x01000000

Definition at line 1460 of file cx25821-reg.h.

#define FLD_MB_IF_FIFO_EN   0x00000001

Definition at line 1448 of file cx25821-reg.h.

#define FLD_MB_IF_LN_LNGTH   0x00000FFF

Definition at line 1451 of file cx25821-reg.h.

#define FLD_MB_IF_RISC_EN   0x00000010

Definition at line 1447 of file cx25821-reg.h.

#define FLD_MBIF_DST_OF   0x00000100

Definition at line 224 of file cx25821-reg.h.

#define FLD_MBIF_DST_OPC_ERR   0x00010000

Definition at line 222 of file cx25821-reg.h.

#define FLD_MBIF_DST_RISCI1   0x00000001

Definition at line 226 of file cx25821-reg.h.

#define FLD_MBIF_DST_RISCI2   0x00000010

Definition at line 225 of file cx25821-reg.h.

#define FLD_MBIF_DST_SYNC   0x00001000

Definition at line 223 of file cx25821-reg.h.

#define FLD_MOE_CLK_DIS   0x80000000 /* Disable MoE clock */

Definition at line 1062 of file cx25821-reg.h.

#define FLD_PECOS_SOFT_RESET   0x00000001

Definition at line 930 of file cx25821-reg.h.

#define FLD_RISC_RD_BERR_INT   (1 << 17)

Definition at line 84 of file cx25821-reg.h.

#define FLD_RISC_WR_BERR_INT   (1 << 18)

Definition at line 83 of file cx25821-reg.h.

#define FLD_RUN_RISC   0x00000020

Definition at line 63 of file cx25821-reg.h.

#define FLD_RX_EN   (1 << 1) /* RW field - default 0 */

Definition at line 1547 of file cx25821-reg.h.

#define FLD_RX_TRG_SZ   (3 << 2) /* RW field - default 0 */

Definition at line 1546 of file cx25821-reg.h.

#define FLD_RXD_CNT   (0x1F << 0) /* RW field - default 0 */

Definition at line 1572 of file cx25821-reg.h.

#define FLD_RXD_OVERFLOW   (1 << 3) /* RW field - default 0 */

Definition at line 1564 of file cx25821-reg.h.

#define FLD_RXD_RDY   (1 << 1) /* RW field - default 0 */

Definition at line 1566 of file cx25821-reg.h.

#define FLD_RXD_RDY_EN   (1 << 5) /* RW field - default 0 */

Definition at line 1562 of file cx25821-reg.h.

#define FLD_RXD_TIMEOUT_EN   (1 << 7) /* RW field - default 0 */

Definition at line 1560 of file cx25821-reg.h.

#define FLD_TM_INT   (1 << 28)

Definition at line 72 of file cx25821-reg.h.

#define FLD_TX_EN   (1 << 0) /* RW field - default 0 */

Definition at line 1548 of file cx25821-reg.h.

#define FLD_TXD_CNT   (0x1F << 8) /* RW field - default 0 */

Definition at line 1571 of file cx25821-reg.h.

#define FLD_TXD_EMPTY   (1 << 0) /* RW field - default 0 */

Definition at line 1567 of file cx25821-reg.h.

#define FLD_TXD_EMPTY_EN   (1 << 4) /* RW field - default 0 */

Definition at line 1563 of file cx25821-reg.h.

#define FLD_UART_INT   (1 << 26)

Definition at line 70 of file cx25821-reg.h.

#define FLD_USE_ALT_PLL_REF   0x00004000

Definition at line 1088 of file cx25821-reg.h.

#define FLD_VID_A_FORMAT   0x00000007

Definition at line 1103 of file cx25821-reg.h.

#define FLD_VID_A_GAMMA_DIS   0x00000008

Definition at line 1102 of file cx25821-reg.h.

#define FLD_VID_A_GAMMA_FACTOR   0x00000010

Definition at line 1104 of file cx25821-reg.h.

#define FLD_VID_A_INT   (1 << 0)

Definition at line 94 of file cx25821-reg.h.

#define FLD_VID_A_VIP_EXT   0x00000003

Definition at line 1108 of file cx25821-reg.h.

#define FLD_VID_B_FORMAT   0x00000007

Definition at line 1130 of file cx25821-reg.h.

#define FLD_VID_B_GAMMA_DIS   0x00000008

Definition at line 1129 of file cx25821-reg.h.

#define FLD_VID_B_GAMMA_FACTOR   0x00000010

Definition at line 1131 of file cx25821-reg.h.

#define FLD_VID_B_INT   (1 << 1)

Definition at line 93 of file cx25821-reg.h.

#define FLD_VID_B_LN_LNGTH   0x00000FFF

Definition at line 1122 of file cx25821-reg.h.

#define FLD_VID_B_SRC_SEL   0x00000000

Definition at line 1118 of file cx25821-reg.h.

#define FLD_VID_C_INT   (1 << 2)

Definition at line 92 of file cx25821-reg.h.

#define FLD_VID_C_LN_LNGTH   0x00000FFF

Definition at line 1138 of file cx25821-reg.h.

#define FLD_VID_D_INT   (1 << 3)

Definition at line 91 of file cx25821-reg.h.

#define FLD_VID_DST_ERRORS   (FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF)

Definition at line 167 of file cx25821-reg.h.

#define FLD_VID_DST_OF   0x00000100

Definition at line 161 of file cx25821-reg.h.

#define FLD_VID_DST_OPC_ERR   0x00010000

Definition at line 157 of file cx25821-reg.h.

#define FLD_VID_DST_RISC1   0x00000001

Definition at line 165 of file cx25821-reg.h.

#define FLD_VID_DST_RISC2   0x00000010

Definition at line 163 of file cx25821-reg.h.

#define FLD_VID_DST_SYNC   0x00001000

Definition at line 159 of file cx25821-reg.h.

#define FLD_VID_E_INT   (1 << 4)

Definition at line 90 of file cx25821-reg.h.

#define FLD_VID_F_INT   (1 << 5)

Definition at line 89 of file cx25821-reg.h.

#define FLD_VID_FIFO_EN   0x00000001

Definition at line 1176 of file cx25821-reg.h.

#define FLD_VID_G_INT   (1 << 6)

Definition at line 88 of file cx25821-reg.h.

#define FLD_VID_H_INT   (1 << 7)

Definition at line 87 of file cx25821-reg.h.

#define FLD_VID_I_CLK_NOE   0x00001000

Definition at line 1086 of file cx25821-reg.h.

#define FLD_VID_I_INT   (1 << 8)

Definition at line 86 of file cx25821-reg.h.

#define FLD_VID_J_CLK_NOE   0x00002000

Definition at line 1087 of file cx25821-reg.h.

#define FLD_VID_RISC_EN   0x00000010

Definition at line 1175 of file cx25821-reg.h.

#define FLD_VID_SRC_ERRORS   (FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF)

Definition at line 166 of file cx25821-reg.h.

#define FLD_VID_SRC_OPC_ERR   0x00020000

Definition at line 156 of file cx25821-reg.h.

#define FLD_VID_SRC_RISC1   0x00000002

Definition at line 164 of file cx25821-reg.h.

#define FLD_VID_SRC_RISC2   0x00000020

Definition at line 162 of file cx25821-reg.h.

#define FLD_VID_SRC_SYNC   0x00002000

Definition at line 158 of file cx25821-reg.h.

#define FLD_VID_SRC_UF   0x00000200

Definition at line 160 of file cx25821-reg.h.

#define FLD_VIP_MODE   0x00000001

Definition at line 1098 of file cx25821-reg.h.

#define GP0_IO   0x110010 /* GPIO output enables data I/O */

Definition at line 918 of file cx25821-reg.h.

#define GPIO_HI   0x110014 /* Upper WORD of GPIO pins [47:31] */

Definition at line 241 of file cx25821-reg.h.

#define GPIO_HI_INT_MSK   0x110040 /* GPIO interrupt mask */

Definition at line 252 of file cx25821-reg.h.

#define GPIO_HI_INT_MSTAT   0x110050 /* GPIO interrupt masked status */

Definition at line 254 of file cx25821-reg.h.

#define GPIO_HI_INT_STAT   0x110048 /* GPIO interrupt status */

Definition at line 253 of file cx25821-reg.h.

#define GPIO_HI_ISM_POL   0x110060 /* GPIO interrupt polarity */

Definition at line 256 of file cx25821-reg.h.

#define GPIO_HI_ISM_SNS   0x110058 /* GPIO interrupt sensitivity */

Definition at line 255 of file cx25821-reg.h.

#define GPIO_HI_OE   0x11001C /* Upper word of GPIO output enable [47:32] */

Definition at line 244 of file cx25821-reg.h.

#define GPIO_ISM   0x110014 /* GPIO interrupt sensitivity mode */

Definition at line 924 of file cx25821-reg.h.

#define GPIO_LO   0x110010 /* Lower of GPIO pins [31:0] */

Definition at line 240 of file cx25821-reg.h.

#define GPIO_LO_INT_MSK   0x11003C /* GPIO interrupt mask */

Definition at line 246 of file cx25821-reg.h.

#define GPIO_LO_INT_MSTAT   0x11004C /* GPIO interrupt masked status */

Definition at line 248 of file cx25821-reg.h.

#define GPIO_LO_INT_STAT   0x110044 /* GPIO interrupt status */

Definition at line 247 of file cx25821-reg.h.

#define GPIO_LO_ISM_POL   0x11005C /* GPIO interrupt polarity */

Definition at line 250 of file cx25821-reg.h.

#define GPIO_LO_ISM_SNS   0x110054 /* GPIO interrupt sensitivity */

Definition at line 249 of file cx25821-reg.h.

#define GPIO_LO_OE   0x110018 /* Lower of GPIO output enable [31:0] */

Definition at line 243 of file cx25821-reg.h.

#define I2C1_ADDR   0x180000 /* I2C #1 address */

Definition at line 1467 of file cx25821-reg.h.

#define I2C1_CTRL   0x180008 /* I2C #1 control */

Definition at line 1478 of file cx25821-reg.h.

#define I2C1_RDATA   0x18000C /* I2C #1 read data */

Definition at line 1499 of file cx25821-reg.h.

#define I2C1_STAT   0x180010 /* I2C #1 status */

Definition at line 1503 of file cx25821-reg.h.

#define I2C1_WDATA   0x180004 /* I2C #1 write data */

Definition at line 1474 of file cx25821-reg.h.

#define I2C2_ADDR   0x190000 /* I2C #2 address */

Definition at line 1510 of file cx25821-reg.h.

#define I2C2_CTRL   0x190008 /* I2C #2 control */

Definition at line 1516 of file cx25821-reg.h.

#define I2C2_RDATA   0x19000C /* I2C #2 read data */

Definition at line 1519 of file cx25821-reg.h.

#define I2C2_STAT   0x190010 /* I2C #2 status */

Definition at line 1522 of file cx25821-reg.h.

#define I2C2_WDATA   0x190004 /* I2C #2 write data */

Definition at line 1513 of file cx25821-reg.h.

#define I2C3_ADDR   0x1A0000 /* I2C #3 address */

Definition at line 1527 of file cx25821-reg.h.

#define I2C3_CTRL   0x1A0008 /* I2C #3 control */

Definition at line 1533 of file cx25821-reg.h.

#define I2C3_RDATA   0x1A000C /* I2C #3 read data */

Definition at line 1536 of file cx25821-reg.h.

#define I2C3_STAT   0x1A0010 /* I2C #3 status */

Definition at line 1539 of file cx25821-reg.h.

#define I2C3_WDATA   0x1A0004 /* I2C #3 write data */

Definition at line 1530 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_0   0x150024

Definition at line 1402 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_1   0x150028

Definition at line 1403 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_2   0x15002C

Definition at line 1404 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_3   0x150030

Definition at line 1405 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_4   0x150034

Definition at line 1406 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_5   0x150038

Definition at line 1407 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_6   0x15003C

Definition at line 1408 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_7   0x150040

Definition at line 1409 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_8   0x150044

Definition at line 1410 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_9   0x150048

Definition at line 1411 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_A   0x15004C

Definition at line 1412 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_B   0x150050

Definition at line 1413 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_C   0x150054

Definition at line 1414 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_D   0x150058

Definition at line 1415 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_E   0x15005C

Definition at line 1416 of file cx25821-reg.h.

#define MB_IF_A_DATA_STRUCT_F   0x150060

Definition at line 1417 of file cx25821-reg.h.

#define MB_IF_A_DMA   0x150000 /* MBIF A DMA data port */

Definition at line 1394 of file cx25821-reg.h.

#define MB_IF_A_DMA_CTRL   0x150010

Definition at line 1397 of file cx25821-reg.h.

#define MB_IF_A_GPCN   0x150008 /* MBIF A GP counter */

Definition at line 1395 of file cx25821-reg.h.

#define MB_IF_A_GPCN_CTRL   0x15000C

Definition at line 1396 of file cx25821-reg.h.

#define MB_IF_A_HCMD   0x15001C

Definition at line 1400 of file cx25821-reg.h.

#define MB_IF_A_HCONFIG   0x150020

Definition at line 1401 of file cx25821-reg.h.

#define MB_IF_A_HDMA_XFER_SZ   0x150018

Definition at line 1399 of file cx25821-reg.h.

#define MB_IF_A_LENGTH   0x150014

Definition at line 1398 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_0   0x160024

Definition at line 1429 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_1   0x160028

Definition at line 1430 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_2   0x16002C

Definition at line 1431 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_3   0x160030

Definition at line 1432 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_4   0x160034

Definition at line 1433 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_5   0x160038

Definition at line 1434 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_6   0x16003C

Definition at line 1435 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_7   0x160040

Definition at line 1436 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_8   0x160044

Definition at line 1437 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_9   0x160048

Definition at line 1438 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_A   0x16004C

Definition at line 1439 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_B   0x160050

Definition at line 1440 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_C   0x160054

Definition at line 1441 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_D   0x160058

Definition at line 1442 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_E   0x16005C

Definition at line 1443 of file cx25821-reg.h.

#define MB_IF_B_DATA_STRUCT_F   0x160060

Definition at line 1444 of file cx25821-reg.h.

#define MB_IF_B_DMA   0x160000 /* MBIF A DMA data port */

Definition at line 1421 of file cx25821-reg.h.

#define MB_IF_B_DMA_CTRL   0x160010

Definition at line 1424 of file cx25821-reg.h.

#define MB_IF_B_GPCN   0x160008 /* MBIF A GP counter */

Definition at line 1422 of file cx25821-reg.h.

#define MB_IF_B_GPCN_CTRL   0x16000C

Definition at line 1423 of file cx25821-reg.h.

#define MB_IF_B_HCMD   0x16001C

Definition at line 1427 of file cx25821-reg.h.

#define MB_IF_B_HCONFIG   0x160020

Definition at line 1428 of file cx25821-reg.h.

#define MB_IF_B_HDMA_XFER_SZ   0x160018

Definition at line 1426 of file cx25821-reg.h.

#define MB_IF_B_LENGTH   0x160014

Definition at line 1425 of file cx25821-reg.h.

#define MBIF_A_INT_MSK   0x040110 /* MBIF Int interrupt mask */

Definition at line 211 of file cx25821-reg.h.

#define MBIF_A_INT_MSTAT   0x040118 /* MBIF Int interrupt masked status */

Definition at line 213 of file cx25821-reg.h.

#define MBIF_A_INT_SSTAT   0x04011C /* MBIF Int interrupt set status */

Definition at line 214 of file cx25821-reg.h.

#define MBIF_A_INT_STAT   0x040114 /* MBIF Int interrupt status */

Definition at line 212 of file cx25821-reg.h.

#define MBIF_B_INT_MSK   0x040120 /* MBIF Int interrupt mask */

Definition at line 217 of file cx25821-reg.h.

#define MBIF_B_INT_MSTAT   0x040128 /* MBIF Int interrupt masked status */

Definition at line 219 of file cx25821-reg.h.

#define MBIF_B_INT_SSTAT   0x04012C /* MBIF Int interrupt set status */

Definition at line 220 of file cx25821-reg.h.

#define MBIF_B_INT_STAT   0x040124 /* MBIF Int interrupt status */

Definition at line 218 of file cx25821-reg.h.

#define MBIST_CTRL   0x110050 /* SRAM memory built-in self test control */

Definition at line 1068 of file cx25821-reg.h.

#define MBIST_STAT   0x110054 /* SRAM memory built-in self test status */

Definition at line 1071 of file cx25821-reg.h.

#define MC416_CTL   0x110028

Definition at line 935 of file cx25821-reg.h.

#define MC416_OEN   0x110024 /* Output enable of GPIO[18:3] */

Definition at line 934 of file cx25821-reg.h.

#define MC416_RWD   0x110020 /* MC416 GPIO[18:3] pin */

Definition at line 933 of file cx25821-reg.h.

#define MD_CH0_GRID_BLOCK_YCNT   0x170014

Definition at line 1576 of file cx25821-reg.h.

#define MD_CH1_GRID_BLOCK_YCNT   0x170094

Definition at line 1577 of file cx25821-reg.h.

#define MD_CH2_GRID_BLOCK_YCNT   0x170114

Definition at line 1578 of file cx25821-reg.h.

#define MD_CH3_GRID_BLOCK_YCNT   0x170194

Definition at line 1579 of file cx25821-reg.h.

#define MD_CH4_GRID_BLOCK_YCNT   0x170214

Definition at line 1580 of file cx25821-reg.h.

#define MD_CH5_GRID_BLOCK_YCNT   0x170294

Definition at line 1581 of file cx25821-reg.h.

#define MD_CH6_GRID_BLOCK_YCNT   0x170314

Definition at line 1582 of file cx25821-reg.h.

#define MD_CH7_GRID_BLOCK_YCNT   0x170394

Definition at line 1583 of file cx25821-reg.h.

#define PAD_CTRL   0x110068 /* Pad drive strength control */

Definition at line 1065 of file cx25821-reg.h.

#define PCI_INT_MSK   0x040010 /* PCI interrupt mask */

Definition at line 66 of file cx25821-reg.h.

#define PCI_INT_MSTAT   0x040018 /* PCI interrupt masked status */

Definition at line 68 of file cx25821-reg.h.

#define PCI_INT_STAT   0x040014 /* PCI interrupt status */

Definition at line 67 of file cx25821-reg.h.

#define PIXEL_ENGINE_VIP1   0

Definition at line 1589 of file cx25821-reg.h.

#define PIXEL_ENGINE_VIP2   1

Definition at line 1590 of file cx25821-reg.h.

#define PIXEL_FRMT_411   5

Definition at line 1586 of file cx25821-reg.h.

#define PIXEL_FRMT_422   4

Definition at line 1585 of file cx25821-reg.h.

#define PIXEL_FRMT_Y8   6

Definition at line 1587 of file cx25821-reg.h.

#define PLL_A_INT_FRAC   0x110088

Definition at line 1076 of file cx25821-reg.h.

#define PLL_A_POST_STAT_BIST   0x11008C

Definition at line 1077 of file cx25821-reg.h.

#define PLL_B_INT_FRAC   0x110090

Definition at line 1078 of file cx25821-reg.h.

#define PLL_B_POST_STAT_BIST   0x110094

Definition at line 1079 of file cx25821-reg.h.

#define PLL_C_INT_FRAC   0x110098

Definition at line 1080 of file cx25821-reg.h.

#define PLL_C_POST_STAT_BIST   0x11009C

Definition at line 1081 of file cx25821-reg.h.

#define PLL_D_INT_FRAC   0x1100A0

Definition at line 1082 of file cx25821-reg.h.

#define PLL_D_POST_STAT_BIST   0x1100A4

Definition at line 1083 of file cx25821-reg.h.

#define RDR_ACKLATTO   0x05036C

Definition at line 564 of file cx25821-reg.h.

#define RDR_AERCC   0x050118

Definition at line 397 of file cx25821-reg.h.

#define RDR_AERCEMSK   0x050114

Definition at line 394 of file cx25821-reg.h.

#define RDR_AERCESTA   0x050110

Definition at line 391 of file cx25821-reg.h.

#define RDR_AERHL0   0x05011C

Definition at line 400 of file cx25821-reg.h.

#define RDR_AERHL1   0x050120

Definition at line 403 of file cx25821-reg.h.

#define RDR_AERHL2   0x050124

Definition at line 406 of file cx25821-reg.h.

#define RDR_AERHL3   0x050128

Definition at line 409 of file cx25821-reg.h.

#define RDR_AERUEMSK   0x050108

Definition at line 385 of file cx25821-reg.h.

#define RDR_AERUESEV   0x05010C

Definition at line 388 of file cx25821-reg.h.

#define RDR_AERUESTA   0x050104

Definition at line 382 of file cx25821-reg.h.

#define RDR_AERXCAP   0x050100

Definition at line 379 of file cx25821-reg.h.

#define RDR_CFG0   0x050000

Definition at line 286 of file cx25821-reg.h.

#define RDR_CFG1   0x050004

Definition at line 290 of file cx25821-reg.h.

#define RDR_CFG2   0x050008

Definition at line 293 of file cx25821-reg.h.

#define RDR_CFG3   0x05000C

Definition at line 296 of file cx25821-reg.h.

#define RDR_CFG4   0x050010

Definition at line 299 of file cx25821-reg.h.

#define RDR_CFG5   0x050014

Definition at line 302 of file cx25821-reg.h.

#define RDR_CFG6   0x050018

Definition at line 305 of file cx25821-reg.h.

#define RDR_CFG7   0x05001C

Definition at line 308 of file cx25821-reg.h.

#define RDR_CFG8   0x050020

Definition at line 311 of file cx25821-reg.h.

#define RDR_CFG9   0x050024

Definition at line 314 of file cx25821-reg.h.

#define RDR_CFGA   0x050028

Definition at line 317 of file cx25821-reg.h.

#define RDR_CFGB   0x05002C

Definition at line 320 of file cx25821-reg.h.

#define RDR_CFGC   0x050030

Definition at line 324 of file cx25821-reg.h.

#define RDR_CFGD   0x050034

Definition at line 327 of file cx25821-reg.h.

#define RDR_CFGE   0x050038

Definition at line 330 of file cx25821-reg.h.

#define RDR_CFGF   0x05003C

Definition at line 333 of file cx25821-reg.h.

#define RDR_DLLCTRL   0x050364

Definition at line 558 of file cx25821-reg.h.

#define RDR_DLLSTAT   0x050360

Definition at line 555 of file cx25821-reg.h.

#define RDR_L0S_EXIT_LAT   0x050398

Definition at line 587 of file cx25821-reg.h.

#define RDR_MAC_LB_DATA   0x050394

Definition at line 584 of file cx25821-reg.h.

#define RDR_MACCTRL0   0x050388

Definition at line 575 of file cx25821-reg.h.

#define RDR_MACCTRL1   0x05038C

Definition at line 578 of file cx25821-reg.h.

#define RDR_MACCTRL2   0x050390

Definition at line 581 of file cx25821-reg.h.

#define RDR_MACSTAT0   0x050380

Definition at line 569 of file cx25821-reg.h.

#define RDR_MACSTAT1   0x050384

Definition at line 572 of file cx25821-reg.h.

#define RDR_MSIARL   0x0500A4

Definition at line 368 of file cx25821-reg.h.

#define RDR_MSIARU   0x0500A8

Definition at line 371 of file cx25821-reg.h.

#define RDR_MSICAP   0x0500A0

Definition at line 365 of file cx25821-reg.h.

#define RDR_MSIDATA   0x0500AC

Definition at line 374 of file cx25821-reg.h.

#define RDR_PECAP   0x050040

Definition at line 338 of file cx25821-reg.h.

#define RDR_PEDEVCAP   0x050044

Definition at line 341 of file cx25821-reg.h.

#define RDR_PEDEVSC   0x050048

Definition at line 344 of file cx25821-reg.h.

#define RDR_PELINKCAP   0x05004C

Definition at line 347 of file cx25821-reg.h.

#define RDR_PELINKSC   0x050050

Definition at line 350 of file cx25821-reg.h.

#define RDR_PMCSR   0x050084

Definition at line 356 of file cx25821-reg.h.

#define RDR_PMICAP   0x050080

Definition at line 353 of file cx25821-reg.h.

#define RDR_RDRCTL0   0x050308

Definition at line 490 of file cx25821-reg.h.

#define RDR_RDRCTL1   0x05030C

Definition at line 493 of file cx25821-reg.h.

#define RDR_RDRSTAT0   0x050300

Definition at line 484 of file cx25821-reg.h.

#define RDR_RDRSTAT1   0x050304

Definition at line 487 of file cx25821-reg.h.

#define RDR_REPLAYTO   0x050368

Definition at line 561 of file cx25821-reg.h.

#define RDR_REQCTRL   0x05032C

Definition at line 526 of file cx25821-reg.h.

#define RDR_REQEPA   0x050328

Definition at line 523 of file cx25821-reg.h.

#define RDR_REQRCAL   0x050320

Definition at line 517 of file cx25821-reg.h.

#define RDR_REQRCAU   0x050324

Definition at line 520 of file cx25821-reg.h.

#define RDR_REQSTAT   0x050330

Definition at line 529 of file cx25821-reg.h.

#define RDR_RX_VCR0_FC   0x050350

Definition at line 541 of file cx25821-reg.h.

#define RDR_RX_VCR1_FC   0x050354

Definition at line 544 of file cx25821-reg.h.

#define RDR_RX_VCR2_FC   0x050358

Definition at line 547 of file cx25821-reg.h.

#define RDR_RX_VCR3_FC   0x05035C

Definition at line 550 of file cx25821-reg.h.

#define RDR_SUSSYSTEM_ID_CFG   0x05002C

Definition at line 321 of file cx25821-reg.h.

#define RDR_TL_TEST   0x050334

Definition at line 532 of file cx25821-reg.h.

#define RDR_TLCTL0   0x050318

Definition at line 504 of file cx25821-reg.h.

#define RDR_TLCTL1   0x05031C

Definition at line 514 of file cx25821-reg.h.

#define RDR_TLSTAT0   0x050310

Definition at line 498 of file cx25821-reg.h.

#define RDR_TLSTAT1   0x050314

Definition at line 501 of file cx25821-reg.h.

#define RDR_VCARB0   0x050240

Definition at line 460 of file cx25821-reg.h.

#define RDR_VCARB1   0x050244

Definition at line 463 of file cx25821-reg.h.

#define RDR_VCARB2   0x050248

Definition at line 466 of file cx25821-reg.h.

#define RDR_VCARB3   0x05024C

Definition at line 469 of file cx25821-reg.h.

#define RDR_VCARB4   0x050250

Definition at line 472 of file cx25821-reg.h.

#define RDR_VCARB5   0x050254

Definition at line 475 of file cx25821-reg.h.

#define RDR_VCARB6   0x050258

Definition at line 478 of file cx25821-reg.h.

#define RDR_VCARB7   0x05025C

Definition at line 481 of file cx25821-reg.h.

#define RDR_VCCAP1   0x050204

Definition at line 415 of file cx25821-reg.h.

#define RDR_VCCAP2   0x050208

Definition at line 418 of file cx25821-reg.h.

#define RDR_VCR01_CTL   0x050348

Definition at line 535 of file cx25821-reg.h.

#define RDR_VCR0_CAP   0x050210

Definition at line 424 of file cx25821-reg.h.

#define RDR_VCR0_CTRL   0x050214

Definition at line 427 of file cx25821-reg.h.

#define RDR_VCR0_STAT   0x050218

Definition at line 430 of file cx25821-reg.h.

#define RDR_VCR1_CAP   0x05021C

Definition at line 433 of file cx25821-reg.h.

#define RDR_VCR1_CTRL   0x050220

Definition at line 436 of file cx25821-reg.h.

#define RDR_VCR1_STAT   0x050224

Definition at line 439 of file cx25821-reg.h.

#define RDR_VCR23_CTL   0x05034C

Definition at line 538 of file cx25821-reg.h.

#define RDR_VCR2_CAP   0x050228

Definition at line 442 of file cx25821-reg.h.

#define RDR_VCR2_CTRL   0x05022C

Definition at line 445 of file cx25821-reg.h.

#define RDR_VCR2_STAT   0x050230

Definition at line 448 of file cx25821-reg.h.

#define RDR_VCR3_CAP   0x050234

Definition at line 451 of file cx25821-reg.h.

#define RDR_VCR3_CTRL   0x050238

Definition at line 454 of file cx25821-reg.h.

#define RDR_VCR3_STAT   0x05023C

Definition at line 457 of file cx25821-reg.h.

#define RDR_VCSC   0x05020C

Definition at line 421 of file cx25821-reg.h.

#define RDR_VCXCAP   0x050200

Definition at line 412 of file cx25821-reg.h.

#define RDR_VENDOR_DEVICE_ID_CFG   0x050000

Definition at line 287 of file cx25821-reg.h.

#define RDR_VPDCAP   0x050090

Definition at line 359 of file cx25821-reg.h.

#define RDR_VPDDATA   0x050094

Definition at line 362 of file cx25821-reg.h.

#define RISC_CNT_INC   0x00010000

Definition at line 27 of file cx25821-reg.h.

#define RISC_CNT_RESET   0x00030000

Definition at line 28 of file cx25821-reg.h.

#define RISC_EOL   0x04000000

Definition at line 31 of file cx25821-reg.h.

#define RISC_IRQ1   0x01000000

Definition at line 29 of file cx25821-reg.h.

#define RISC_IRQ2   0x02000000

Definition at line 30 of file cx25821-reg.h.

#define RISC_JUMP   0x70000000

Definition at line 35 of file cx25821-reg.h.

#define RISC_NOOP   0xF0000000

Definition at line 49 of file cx25821-reg.h.

#define RISC_READ   0x90000000

Definition at line 38 of file cx25821-reg.h.

#define RISC_READC   0xA0000000

Definition at line 43 of file cx25821-reg.h.

#define RISC_RESYNC   0x80008000

Definition at line 37 of file cx25821-reg.h.

#define RISC_SKIP   0x20000000

Definition at line 34 of file cx25821-reg.h.

#define RISC_SOL   0x08000000

Definition at line 32 of file cx25821-reg.h.

#define RISC_SYNC   0x80000000

Definition at line 36 of file cx25821-reg.h.

#define RISC_SYNC_EVEN   0x00000200

Definition at line 46 of file cx25821-reg.h.

#define RISC_SYNC_EVEN_VBI   0x00000207

Definition at line 48 of file cx25821-reg.h.

#define RISC_SYNC_ODD   0x00000000

Definition at line 45 of file cx25821-reg.h.

#define RISC_SYNC_ODD_VBI   0x00000006

Definition at line 47 of file cx25821-reg.h.

#define RISC_WRITE   0x10000000

Definition at line 33 of file cx25821-reg.h.

#define RISC_WRITEC   0x50000000

Definition at line 42 of file cx25821-reg.h.

#define RISC_WRITECM   0xC0000000

Definition at line 40 of file cx25821-reg.h.

#define RISC_WRITECR   0xD0000000

Definition at line 41 of file cx25821-reg.h.

#define RISC_WRITERM   0xB0000000

Definition at line 39 of file cx25821-reg.h.

#define RX_RAM   0x010000 /* Receive SRAM */

Definition at line 57 of file cx25821-reg.h.

#define SOFT_RESET   0x11001C /* Output system reset reg */

Definition at line 929 of file cx25821-reg.h.

#define TC_REQ   0x040090 /* Rider PCI Express traFFic class request */

Definition at line 275 of file cx25821-reg.h.

#define TC_REQ_SET   0x040094 /* Rider PCI Express traFFic class request set */

Definition at line 278 of file cx25821-reg.h.

#define TEST_BUS_CTL1   0x110040 /* Test bus control register #1 */

Definition at line 1055 of file cx25821-reg.h.

#define TEST_BUS_CTL2   0x110044 /* Test bus control register #2 */

Definition at line 1058 of file cx25821-reg.h.

#define TM_CNT_LDW   0x110000 /* Timer : Counter low */

Definition at line 906 of file cx25821-reg.h.

#define TM_CNT_UW   0x110004 /* Timer : Counter high word */

Definition at line 909 of file cx25821-reg.h.

#define TM_LMT_LDW   0x110008 /* Timer : Limit low */

Definition at line 912 of file cx25821-reg.h.

#define TM_LMT_UW   0x11000C /* Timer : Limit high word */

Definition at line 915 of file cx25821-reg.h.

#define TX_SRAM   0x000000 /* Transmit SRAM */

Definition at line 54 of file cx25821-reg.h.

#define UART_BRD   0x1B0004 /* UART Baud Rate Divisor */

Definition at line 1551 of file cx25821-reg.h.

#define UART_CNT   0x1B0010 /* UART Tx/Rx FIFO Byte Count */

Definition at line 1570 of file cx25821-reg.h.

#define UART_CTL   0x1B0000 /* UART Control Register */

Definition at line 1544 of file cx25821-reg.h.

#define UART_DBUF   0x1B0008 /* UART Tx/Rx Data BuFFer */

Definition at line 1555 of file cx25821-reg.h.

#define UART_ISR   0x1B000C /* UART Interrupt Status */

Definition at line 1559 of file cx25821-reg.h.

#define VBI_A_DMA   0x130008 /* VBI A DMA data port */

Definition at line 1094 of file cx25821-reg.h.

#define VBI_B_DMA   0x130108 /* VBI B DMA data port */

Definition at line 1114 of file cx25821-reg.h.

#define VID_A_INT_MSK   0x040020 /* Video A interrupt mask */

Definition at line 97 of file cx25821-reg.h.

#define VID_A_INT_MSTAT   0x040028 /* Video A interrupt masked status */

Definition at line 99 of file cx25821-reg.h.

#define VID_A_INT_SSTAT   0x04002C /* Video A interrupt set status */

Definition at line 100 of file cx25821-reg.h.

#define VID_A_INT_STAT   0x040024 /* Video A interrupt status */

Definition at line 98 of file cx25821-reg.h.

#define VID_A_PIXEL_FRMT   0x130084 /* Video A pixel format */

Definition at line 1101 of file cx25821-reg.h.

#define VID_A_VBI_CTL   0x130088 /* Video A VBI miscellaneous control */

Definition at line 1107 of file cx25821-reg.h.

#define VID_A_VIP_CTL   0x130080 /* Video A VIP format control */

Definition at line 1097 of file cx25821-reg.h.

#define VID_B_DMA   0x130100 /* Video B DMA data port */

Definition at line 1111 of file cx25821-reg.h.

#define VID_B_INT_MSK   0x040030 /* Video B interrupt mask */

Definition at line 103 of file cx25821-reg.h.

#define VID_B_INT_MSTAT   0x040038 /* Video B interrupt masked status */

Definition at line 105 of file cx25821-reg.h.

#define VID_B_INT_SSTAT   0x04003C /* Video B interrupt set status */

Definition at line 106 of file cx25821-reg.h.

#define VID_B_INT_STAT   0x040034 /* Video B interrupt status */

Definition at line 104 of file cx25821-reg.h.

#define VID_B_LNGTH   0x130150 /* Video B line length */

Definition at line 1121 of file cx25821-reg.h.

#define VID_B_PIXEL_FRMT   0x130184 /* Video B pixel format */

Definition at line 1128 of file cx25821-reg.h.

#define VID_B_SRC_SEL   0x130144 /* Video B source select */

Definition at line 1117 of file cx25821-reg.h.

#define VID_B_VIP_CTL   0x130180 /* Video B VIP format control */

Definition at line 1125 of file cx25821-reg.h.

#define VID_C_DMA   0x130200 /* Video C DMA data port */

Definition at line 1134 of file cx25821-reg.h.

#define VID_C_INT_MSK   0x040040 /* Video C interrupt mask */

Definition at line 109 of file cx25821-reg.h.

#define VID_C_INT_MSTAT   0x040048 /* Video C interrupt masked status */

Definition at line 111 of file cx25821-reg.h.

#define VID_C_INT_SSTAT   0x04004C /* Video C interrupt set status */

Definition at line 112 of file cx25821-reg.h.

#define VID_C_INT_STAT   0x040044 /* Video C interrupt status */

Definition at line 110 of file cx25821-reg.h.

#define VID_C_LNGTH   0x130250 /* Video C line length */

Definition at line 1137 of file cx25821-reg.h.

#define VID_CH_CLK_SEL   0x11007C

Definition at line 1091 of file cx25821-reg.h.

#define VID_CH_MODE_SEL   0x110078

Definition at line 1090 of file cx25821-reg.h.

#define VID_D_INT_MSK   0x040050 /* Video D interrupt mask */

Definition at line 115 of file cx25821-reg.h.

#define VID_D_INT_MSTAT   0x040058 /* Video D interrupt masked status */

Definition at line 117 of file cx25821-reg.h.

#define VID_D_INT_SSTAT   0x04005C /* Video D interrupt set status */

Definition at line 118 of file cx25821-reg.h.

#define VID_D_INT_STAT   0x040054 /* Video D interrupt status */

Definition at line 116 of file cx25821-reg.h.

#define VID_DST_A_DMA_CTL   0x130040 /* Video A DMA control */

Definition at line 1166 of file cx25821-reg.h.

#define VID_DST_A_GPCNT   0x130020 /* Video A general purpose counter */

Definition at line 1144 of file cx25821-reg.h.

#define VID_DST_A_GPCNT_CTL   0x130030 /* Video A general purpose control */

Definition at line 1155 of file cx25821-reg.h.

#define VID_DST_A_PIX_FRMT   0x130084 /* Video A Pixel format */

Definition at line 1191 of file cx25821-reg.h.

#define VID_DST_A_VIP_CTL   0x130080 /* Video A VIP control */

Definition at line 1180 of file cx25821-reg.h.

#define VID_DST_B_DMA_CTL   0x130140 /* Video B DMA control */

Definition at line 1167 of file cx25821-reg.h.

#define VID_DST_B_GPCNT   0x130120 /* Video B general purpose counter */

Definition at line 1145 of file cx25821-reg.h.

#define VID_DST_B_GPCNT_CTL   0x130130 /* Video B general purpose control */

Definition at line 1156 of file cx25821-reg.h.

#define VID_DST_B_PIX_FRMT   0x130184 /* Video B Pixel format */

Definition at line 1192 of file cx25821-reg.h.

#define VID_DST_B_VIP_CTL   0x130180 /* Video B VIP control */

Definition at line 1181 of file cx25821-reg.h.

#define VID_DST_C_DMA_CTL   0x130240 /* Video C DMA control */

Definition at line 1168 of file cx25821-reg.h.

#define VID_DST_C_GPCNT   0x130220 /* Video C general purpose counter */

Definition at line 1146 of file cx25821-reg.h.

#define VID_DST_C_GPCNT_CTL   0x130230 /* Video C general purpose control */

Definition at line 1157 of file cx25821-reg.h.

#define VID_DST_C_PIX_FRMT   0x130284 /* Video C Pixel format */

Definition at line 1193 of file cx25821-reg.h.

#define VID_DST_C_VIP_CTL   0x130280 /* Video C VIP control */

Definition at line 1182 of file cx25821-reg.h.

#define VID_DST_D_DMA_CTL   0x130340 /* Video D DMA control */

Definition at line 1169 of file cx25821-reg.h.

#define VID_DST_D_GPCNT   0x130320 /* Video D general purpose counter */

Definition at line 1147 of file cx25821-reg.h.

#define VID_DST_D_GPCNT_CTL   0x130330 /* Video D general purpose control */

Definition at line 1158 of file cx25821-reg.h.

#define VID_DST_D_PIX_FRMT   0x130384 /* Video D Pixel format */

Definition at line 1194 of file cx25821-reg.h.

#define VID_DST_D_VIP_CTL   0x130380 /* Video D VIP control */

Definition at line 1183 of file cx25821-reg.h.

#define VID_DST_E_DMA_CTL   0x130440 /* Video E DMA control */

Definition at line 1170 of file cx25821-reg.h.

#define VID_DST_E_GPCNT   0x130420 /* Video E general purpose counter */

Definition at line 1148 of file cx25821-reg.h.

#define VID_DST_E_GPCNT_CTL   0x130430 /* Video E general purpose control */

Definition at line 1159 of file cx25821-reg.h.

#define VID_DST_E_PIX_FRMT   0x130484 /* Video E Pixel format */

Definition at line 1195 of file cx25821-reg.h.

#define VID_DST_E_VIP_CTL   0x130480 /* Video E VIP control */

Definition at line 1184 of file cx25821-reg.h.

#define VID_DST_F_DMA_CTL   0x130540 /* Video F DMA control */

Definition at line 1171 of file cx25821-reg.h.

#define VID_DST_F_GPCNT   0x130520 /* Video F general purpose counter */

Definition at line 1149 of file cx25821-reg.h.

#define VID_DST_F_GPCNT_CTL   0x130530 /* Video F general purpose control */

Definition at line 1160 of file cx25821-reg.h.

#define VID_DST_F_PIX_FRMT   0x130584 /* Video F Pixel format */

Definition at line 1196 of file cx25821-reg.h.

#define VID_DST_F_VIP_CTL   0x130580 /* Video F VIP control */

Definition at line 1185 of file cx25821-reg.h.

#define VID_DST_G_DMA_CTL   0x130640 /* Video G DMA control */

Definition at line 1172 of file cx25821-reg.h.

#define VID_DST_G_GPCNT   0x130620 /* Video G general purpose counter */

Definition at line 1150 of file cx25821-reg.h.

#define VID_DST_G_GPCNT_CTL   0x130630 /* Video G general purpose control */

Definition at line 1161 of file cx25821-reg.h.

#define VID_DST_G_PIX_FRMT   0x130684 /* Video G Pixel format */

Definition at line 1197 of file cx25821-reg.h.

#define VID_DST_G_VIP_CTL   0x130680 /* Video G VIP control */

Definition at line 1186 of file cx25821-reg.h.

#define VID_DST_H_DMA_CTL   0x130740 /* Video H DMA control */

Definition at line 1173 of file cx25821-reg.h.

#define VID_DST_H_GPCNT   0x130720 /* Video H general purpose counter */

Definition at line 1151 of file cx25821-reg.h.

#define VID_DST_H_GPCNT_CTL   0x130730 /* Video H general purpose control */

Definition at line 1162 of file cx25821-reg.h.

#define VID_DST_H_PIX_FRMT   0x130784 /* Video H Pixel format */

Definition at line 1198 of file cx25821-reg.h.

#define VID_DST_H_VIP_CTL   0x130780 /* Video H VIP control */

Definition at line 1187 of file cx25821-reg.h.

#define VID_E_INT_MSK   0x040060 /* Video E interrupt mask */

Definition at line 121 of file cx25821-reg.h.

#define VID_E_INT_MSTAT   0x040068 /* Video E interrupt masked status */

Definition at line 123 of file cx25821-reg.h.

#define VID_E_INT_SSTAT   0x04006C /* Video E interrupt set status */

Definition at line 124 of file cx25821-reg.h.

#define VID_E_INT_STAT   0x040064 /* Video E interrupt status */

Definition at line 122 of file cx25821-reg.h.

#define VID_F_INT_MSK   0x040070 /* Video F interrupt mask */

Definition at line 127 of file cx25821-reg.h.

#define VID_F_INT_MSTAT   0x040078 /* Video F interrupt masked status */

Definition at line 129 of file cx25821-reg.h.

#define VID_F_INT_SSTAT   0x04007C /* Video F interrupt set status */

Definition at line 130 of file cx25821-reg.h.

#define VID_F_INT_STAT   0x040074 /* Video F interrupt status */

Definition at line 128 of file cx25821-reg.h.

#define VID_G_INT_MSK   0x040080 /* Video G interrupt mask */

Definition at line 133 of file cx25821-reg.h.

#define VID_G_INT_MSTAT   0x040088 /* Video G interrupt masked status */

Definition at line 135 of file cx25821-reg.h.

#define VID_G_INT_SSTAT   0x04008C /* Video G interrupt set status */

Definition at line 136 of file cx25821-reg.h.

#define VID_G_INT_STAT   0x040084 /* Video G interrupt status */

Definition at line 134 of file cx25821-reg.h.

#define VID_H_INT_MSK   0x040090 /* Video H interrupt mask */

Definition at line 139 of file cx25821-reg.h.

#define VID_H_INT_MSTAT   0x040098 /* Video H interrupt masked status */

Definition at line 141 of file cx25821-reg.h.

#define VID_H_INT_SSTAT   0x04009C /* Video H interrupt set status */

Definition at line 142 of file cx25821-reg.h.

#define VID_H_INT_STAT   0x040094 /* Video H interrupt status */

Definition at line 140 of file cx25821-reg.h.

#define VID_I_INT_MSK   0x0400A0 /* Video I interrupt mask */

Definition at line 145 of file cx25821-reg.h.

#define VID_I_INT_MSTAT   0x0400A8 /* Video I interrupt masked status */

Definition at line 147 of file cx25821-reg.h.

#define VID_I_INT_SSTAT   0x0400AC /* Video I interrupt set status */

Definition at line 148 of file cx25821-reg.h.

#define VID_I_INT_STAT   0x0400A4 /* Video I interrupt status */

Definition at line 146 of file cx25821-reg.h.

#define VID_J_INT_MSK   0x0400B0 /* Video J interrupt mask */

Definition at line 151 of file cx25821-reg.h.

#define VID_J_INT_MSTAT   0x0400B8 /* Video J interrupt masked status */

Definition at line 153 of file cx25821-reg.h.

#define VID_J_INT_SSTAT   0x0400BC /* Video J interrupt set status */

Definition at line 154 of file cx25821-reg.h.

#define VID_J_INT_STAT   0x0400B4 /* Video J interrupt status */

Definition at line 152 of file cx25821-reg.h.

#define VID_SRC_A_ACTIVE_CTL1   0x130814 /* Video A active control 1 */

Definition at line 1251 of file cx25821-reg.h.

#define VID_SRC_A_ACTIVE_CTL2   0x130818 /* Video A active control 2 */

Definition at line 1262 of file cx25821-reg.h.

#define VID_SRC_A_CDT_SZ   0x13081C /* Video A CDT size */

Definition at line 1273 of file cx25821-reg.h.

#define VID_SRC_A_DMA_CTL   0x13080C /* Video A DMA control */

Definition at line 1226 of file cx25821-reg.h.

#define VID_SRC_A_FMT_CTL   0x130810 /* Video A format control */

Definition at line 1240 of file cx25821-reg.h.

#define VID_SRC_A_GPCNT   0x130808 /* Video A general purpose counter */

Definition at line 1215 of file cx25821-reg.h.

#define VID_SRC_A_GPCNT_CTL   0x130804 /* Video A general purpose control */

Definition at line 1204 of file cx25821-reg.h.

#define VID_SRC_B_ACTIVE_CTL1   0x130914 /* Video B active control 1 */

Definition at line 1252 of file cx25821-reg.h.

#define VID_SRC_B_ACTIVE_CTL2   0x130918 /* Video B active control 2 */

Definition at line 1263 of file cx25821-reg.h.

#define VID_SRC_B_CDT_SZ   0x13091C /* Video B CDT size */

Definition at line 1274 of file cx25821-reg.h.

#define VID_SRC_B_DMA_CTL   0x13090C /* Video B DMA control */

Definition at line 1227 of file cx25821-reg.h.

#define VID_SRC_B_FMT_CTL   0x130910 /* Video B format control */

Definition at line 1241 of file cx25821-reg.h.

#define VID_SRC_B_GPCNT   0x130908 /* Video B general purpose counter */

Definition at line 1216 of file cx25821-reg.h.

#define VID_SRC_B_GPCNT_CTL   0x130904 /* Video B general purpose control */

Definition at line 1205 of file cx25821-reg.h.

#define VID_SRC_C_ACTIVE_CTL1   0x130A14 /* Video C active control 1 */

Definition at line 1253 of file cx25821-reg.h.

#define VID_SRC_C_ACTIVE_CTL2   0x130A18 /* Video C active control 2 */

Definition at line 1264 of file cx25821-reg.h.

#define VID_SRC_C_CDT_SZ   0x130A1C /* Video C CDT size */

Definition at line 1275 of file cx25821-reg.h.

#define VID_SRC_C_DMA_CTL   0x130A0C /* Video C DMA control */

Definition at line 1228 of file cx25821-reg.h.

#define VID_SRC_C_FMT_CTL   0x130A10 /* Video C format control */

Definition at line 1242 of file cx25821-reg.h.

#define VID_SRC_C_GPCNT   0x130A08 /* Video C general purpose counter */

Definition at line 1217 of file cx25821-reg.h.

#define VID_SRC_C_GPCNT_CTL   0x130A04 /* Video C general purpose control */

Definition at line 1206 of file cx25821-reg.h.

#define VID_SRC_D_ACTIVE_CTL1   0x130B14 /* Video D active control 1 */

Definition at line 1254 of file cx25821-reg.h.

#define VID_SRC_D_ACTIVE_CTL2   0x130B18 /* Video D active control 2 */

Definition at line 1265 of file cx25821-reg.h.

#define VID_SRC_D_CDT_SZ   0x130B1C /* Video D CDT size */

Definition at line 1276 of file cx25821-reg.h.

#define VID_SRC_D_DMA_CTL   0x130B0C /* Video D DMA control */

Definition at line 1229 of file cx25821-reg.h.

#define VID_SRC_D_FMT_CTL   0x130B10 /* Video D format control */

Definition at line 1243 of file cx25821-reg.h.

#define VID_SRC_D_GPCNT   0x130B08 /* Video D general purpose counter */

Definition at line 1218 of file cx25821-reg.h.

#define VID_SRC_D_GPCNT_CTL   0x130B04 /* Video D general purpose control */

Definition at line 1207 of file cx25821-reg.h.

#define VID_SRC_E_ACTIVE_CTL1   0x130C14 /* Video E active control 1 */

Definition at line 1255 of file cx25821-reg.h.

#define VID_SRC_E_ACTIVE_CTL2   0x130C18 /* Video E active control 2 */

Definition at line 1266 of file cx25821-reg.h.

#define VID_SRC_E_CDT_SZ   0x130C1C /* Video E CDT size */

Definition at line 1277 of file cx25821-reg.h.

#define VID_SRC_E_DMA_CTL   0x130C0C /* Video E DMA control */

Definition at line 1230 of file cx25821-reg.h.

#define VID_SRC_E_FMT_CTL   0x130C10 /* Video E format control */

Definition at line 1244 of file cx25821-reg.h.

#define VID_SRC_E_GPCNT   0x130C08 /* Video E general purpose counter */

Definition at line 1219 of file cx25821-reg.h.

#define VID_SRC_E_GPCNT_CTL   0x130C04 /* Video E general purpose control */

Definition at line 1208 of file cx25821-reg.h.

#define VID_SRC_F_ACTIVE_CTL1   0x130D14 /* Video F active control 1 */

Definition at line 1256 of file cx25821-reg.h.

#define VID_SRC_F_ACTIVE_CTL2   0x130D18 /* Video F active control 2 */

Definition at line 1267 of file cx25821-reg.h.

#define VID_SRC_F_CDT_SZ   0x130D1C /* Video F CDT size */

Definition at line 1278 of file cx25821-reg.h.

#define VID_SRC_F_DMA_CTL   0x130D0C /* Video F DMA control */

Definition at line 1231 of file cx25821-reg.h.

#define VID_SRC_F_FMT_CTL   0x130D10 /* Video F format control */

Definition at line 1245 of file cx25821-reg.h.

#define VID_SRC_F_GPCNT   0x130D08 /* Video F general purpose counter */

Definition at line 1220 of file cx25821-reg.h.

#define VID_SRC_F_GPCNT_CTL   0x130D04 /* Video F general purpose control */

Definition at line 1209 of file cx25821-reg.h.

#define VID_SRC_I_ACTIVE_CTL1   0x130E14 /* Video I active control 1 */

Definition at line 1257 of file cx25821-reg.h.

#define VID_SRC_I_ACTIVE_CTL2   0x130E18 /* Video I active control 2 */

Definition at line 1268 of file cx25821-reg.h.

#define VID_SRC_I_CDT_SZ   0x130E1C /* Video I CDT size */

Definition at line 1279 of file cx25821-reg.h.

#define VID_SRC_I_DMA_CTL   0x130E0C /* Video I DMA control */

Definition at line 1232 of file cx25821-reg.h.

#define VID_SRC_I_FMT_CTL   0x130E10 /* Video I format control */

Definition at line 1246 of file cx25821-reg.h.

#define VID_SRC_I_GPCNT   0x130E08 /* Video I general purpose counter */

Definition at line 1221 of file cx25821-reg.h.

#define VID_SRC_I_GPCNT_CTL   0x130E04 /* Video I general purpose control */

Definition at line 1210 of file cx25821-reg.h.

#define VID_SRC_J_ACTIVE_CTL1   0x130F14 /* Video J active control 1 */

Definition at line 1258 of file cx25821-reg.h.

#define VID_SRC_J_ACTIVE_CTL2   0x130F18 /* Video J active control 2 */

Definition at line 1269 of file cx25821-reg.h.

#define VID_SRC_J_CDT_SZ   0x130F1C /* Video J CDT size */

Definition at line 1280 of file cx25821-reg.h.

#define VID_SRC_J_DMA_CTL   0x130F0C /* Video J DMA control */

Definition at line 1233 of file cx25821-reg.h.

#define VID_SRC_J_FMT_CTL   0x130F10 /* Video J format control */

Definition at line 1247 of file cx25821-reg.h.

#define VID_SRC_J_GPCNT   0x130F08 /* Video J general purpose counter */

Definition at line 1222 of file cx25821-reg.h.

#define VID_SRC_J_GPCNT_CTL   0x130F04 /* Video J general purpose control */

Definition at line 1211 of file cx25821-reg.h.

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