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cxio_hal.h
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1 /*
2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses. You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  * Redistribution and use in source and binary forms, with or
11  * without modification, are permitted provided that the following
12  * conditions are met:
13  *
14  * - Redistributions of source code must retain the above
15  * copyright notice, this list of conditions and the following
16  * disclaimer.
17  *
18  * - Redistributions in binary form must reproduce the above
19  * copyright notice, this list of conditions and the following
20  * disclaimer in the documentation and/or other materials
21  * provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef __CXIO_HAL_H__
33 #define __CXIO_HAL_H__
34 
35 #include <linux/list.h>
36 #include <linux/mutex.h>
37 #include <linux/kfifo.h>
38 
39 #include "t3_cpl.h"
40 #include "t3cdev.h"
41 #include "cxgb3_ctl_defs.h"
42 #include "cxio_wr.h"
43 
44 #define T3_CTRL_QP_ID FW_RI_SGEEC_START
45 #define T3_CTL_QP_TID FW_RI_TID_START
46 #define T3_CTRL_QP_SIZE_LOG2 8
47 #define T3_CTRL_CQ_ID 0
48 
49 #define T3_MAX_NUM_RI (1<<15)
50 #define T3_MAX_NUM_QP (1<<15)
51 #define T3_MAX_NUM_CQ (1<<15)
52 #define T3_MAX_NUM_PD (1<<15)
53 #define T3_MAX_PBL_SIZE 256
54 #define T3_MAX_RQ_SIZE 1024
55 #define T3_MAX_QP_DEPTH (T3_MAX_RQ_SIZE-1)
56 #define T3_MAX_CQ_DEPTH 65536
57 #define T3_MAX_NUM_STAG (1<<15)
58 #define T3_MAX_MR_SIZE 0x100000000ULL
59 #define T3_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
60 
61 #define T3_STAG_UNSET 0xffffffff
62 
63 #define T3_MAX_DEV_NAME_LEN 32
64 
65 #define CXIO_FW_MAJ 7
66 
67 struct cxio_hal_ctrl_qp {
68  u32 wptr;
69  u32 rptr;
70  struct mutex lock; /* for the wtpr, can sleep */
71  wait_queue_head_t waitq;/* wait for RspQ/CQE msg */
72  union t3_wr *workq; /* the work request queue */
73  dma_addr_t dma_addr; /* pci bus address of the workq */
74  DEFINE_DMA_UNMAP_ADDR(mapping);
75  void __iomem *doorbell;
76 };
77 
78 struct cxio_hal_resource {
79  struct kfifo tpt_fifo;
80  spinlock_t tpt_fifo_lock;
81  struct kfifo qpid_fifo;
82  spinlock_t qpid_fifo_lock;
83  struct kfifo cqid_fifo;
84  spinlock_t cqid_fifo_lock;
85  struct kfifo pdid_fifo;
86  spinlock_t pdid_fifo_lock;
87 };
88 
89 struct cxio_qpid_list {
90  struct list_head entry;
91  u32 qpid;
92 };
93 
94 struct cxio_ucontext {
95  struct list_head qpids;
96  struct mutex lock;
97 };
98 
99 struct cxio_rdev {
100  char dev_name[T3_MAX_DEV_NAME_LEN];
101  struct t3cdev *t3cdev_p;
102  struct rdma_info rnic_info;
103  struct adap_ports port_info;
104  struct cxio_hal_resource *rscp;
105  struct cxio_hal_ctrl_qp ctrl_qp;
106  void *ulp;
107  unsigned long qpshift;
108  u32 qpnr;
109  u32 qpmask;
110  struct cxio_ucontext uctx;
111  struct gen_pool *pbl_pool;
112  struct gen_pool *rqt_pool;
113  struct list_head entry;
114  struct ch_embedded_info fw_info;
115  u32 flags;
116 #define CXIO_ERROR_FATAL 1
117 };
118 
119 static inline int cxio_fatal_error(struct cxio_rdev *rdev_p)
120 {
121  return rdev_p->flags & CXIO_ERROR_FATAL;
122 }
123 
124 static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
125 {
126  return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
127 }
128 
129 typedef void (*cxio_hal_ev_callback_func_t) (struct cxio_rdev * rdev_p,
130  struct sk_buff * skb);
131 
132 #define RSPQ_CQID(rsp) (be32_to_cpu(rsp->cq_ptrid) & 0xffff)
133 #define RSPQ_CQPTR(rsp) ((be32_to_cpu(rsp->cq_ptrid) >> 16) & 0xffff)
134 #define RSPQ_GENBIT(rsp) ((be32_to_cpu(rsp->flags) >> 16) & 1)
135 #define RSPQ_OVERFLOW(rsp) ((be32_to_cpu(rsp->flags) >> 17) & 1)
136 #define RSPQ_AN(rsp) ((be32_to_cpu(rsp->flags) >> 18) & 1)
137 #define RSPQ_SE(rsp) ((be32_to_cpu(rsp->flags) >> 19) & 1)
138 #define RSPQ_NOTIFY(rsp) ((be32_to_cpu(rsp->flags) >> 20) & 1)
139 #define RSPQ_CQBRANCH(rsp) ((be32_to_cpu(rsp->flags) >> 21) & 1)
140 #define RSPQ_CREDIT_THRESH(rsp) ((be32_to_cpu(rsp->flags) >> 22) & 1)
141 
142 struct respQ_msg_t {
143  __be32 flags; /* flit 0 */
144  __be32 cq_ptrid;
145  __be64 rsvd; /* flit 1 */
146  struct t3_cqe cqe; /* flits 2-3 */
147 };
148 
149 enum t3_cq_opcode {
150  CQ_ARM_AN = 0x2,
151  CQ_ARM_SE = 0x6,
152  CQ_FORCE_AN = 0x3,
153  CQ_CREDIT_UPDATE = 0x7
154 };
155 
156 int cxio_rdev_open(struct cxio_rdev *rdev);
157 void cxio_rdev_close(struct cxio_rdev *rdev);
158 int cxio_hal_cq_op(struct cxio_rdev *rdev, struct t3_cq *cq,
159  enum t3_cq_opcode op, u32 credit);
160 int cxio_create_cq(struct cxio_rdev *rdev, struct t3_cq *cq, int kernel);
161 int cxio_destroy_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
162 int cxio_resize_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
163 void cxio_release_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
164 void cxio_init_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
165 int cxio_create_qp(struct cxio_rdev *rdev, u32 kernel_domain, struct t3_wq *wq,
166  struct cxio_ucontext *uctx);
167 int cxio_destroy_qp(struct cxio_rdev *rdev, struct t3_wq *wq,
168  struct cxio_ucontext *uctx);
169 int cxio_peek_cq(struct t3_wq *wr, struct t3_cq *cq, int opcode);
170 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
171  u32 pbl_addr, u32 pbl_size);
172 int cxio_register_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
173  enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
174  u8 page_size, u32 pbl_size, u32 pbl_addr);
175 int cxio_reregister_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
176  enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
177  u8 page_size, u32 pbl_size, u32 pbl_addr);
178 int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
179  u32 pbl_addr);
180 int cxio_allocate_window(struct cxio_rdev *rdev, u32 * stag, u32 pdid);
181 int cxio_allocate_stag(struct cxio_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr);
182 int cxio_deallocate_window(struct cxio_rdev *rdev, u32 stag);
183 int cxio_rdma_init(struct cxio_rdev *rdev, struct t3_rdma_init_attr *attr);
184 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
185 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
186 u32 cxio_hal_get_pdid(struct cxio_hal_resource *rscp);
187 void cxio_hal_put_pdid(struct cxio_hal_resource *rscp, u32 pdid);
188 int __init cxio_hal_init(void);
189 void __exit cxio_hal_exit(void);
190 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count);
191 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count);
192 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
193 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
194 void cxio_flush_hw_cq(struct t3_cq *cq);
195 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
196  u8 *cqe_flushed, u64 *cookie, u32 *credit);
197 int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb);
198 
199 #define MOD "iw_cxgb3: "
200 #define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
201 
202 #ifdef DEBUG
203 void cxio_dump_tpt(struct cxio_rdev *rev, u32 stag);
204 void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
205 void cxio_dump_wqe(union t3_wr *wqe);
206 void cxio_dump_wce(struct t3_cqe *wce);
207 void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents);
208 void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid);
209 #endif
210 
211 #endif
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