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19 #include <linux/device.h>
21 #include <linux/types.h>
23 #define MAX_SMI_DATA_BUF_SIZE (256 * 1024)
25 #define HC_ACTION_NONE (0)
26 #define HC_ACTION_HOST_CONTROL_POWEROFF BIT(1)
27 #define HC_ACTION_HOST_CONTROL_POWERCYCLE BIT(2)
29 #define HC_SMITYPE_NONE (0)
30 #define HC_SMITYPE_TYPE1 (1)
31 #define HC_SMITYPE_TYPE2 (2)
32 #define HC_SMITYPE_TYPE3 (3)
34 #define ESM_APM_CMD (0x0A0)
35 #define ESM_APM_POWER_CYCLE (0x10)
36 #define ESM_STATUS_CMD_UNSUCCESSFUL (-1)
38 #define CMOS_BASE_PORT (0x070)
39 #define CMOS_PAGE1_INDEX_PORT (0)
40 #define CMOS_PAGE1_DATA_PORT (1)
41 #define CMOS_PAGE2_INDEX_PORT_PIIX4 (2)
42 #define CMOS_PAGE2_DATA_PORT_PIIX4 (3)
43 #define PE1400_APM_CONTROL_PORT (0x0B0)
44 #define PCAT_APM_CONTROL_PORT (0x0B2)
45 #define PCAT_APM_STATUS_PORT (0x0B3)
46 #define PE1300_CMOS_CMD_STRUCT_PTR (0x38)
47 #define PE1400_CMOS_CMD_STRUCT_PTR (0x70)
49 #define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN (14)
50 #define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM (16)
52 #define TIMEOUT_USEC_SHORT_SEMA_BLOCKING (10000)
53 #define EXPIRED_TIMER (0)
55 #define SMI_CMD_MAGIC (0x534D4931)
57 #define DCDBAS_DEV_ATTR_RW(_name) \
58 DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
60 #define DCDBAS_DEV_ATTR_RO(_name) \
61 DEVICE_ATTR(_name,0400,_name##_show,NULL);
63 #define DCDBAS_DEV_ATTR_WO(_name) \
64 DEVICE_ATTR(_name,0200,NULL,_name##_store);
66 #define DCDBAS_BIN_ATTR_RW(_name) \
67 struct bin_attribute bin_attr_##_name = { \
68 .attr = { .name = __stringify(_name), \
70 .read = _name##_read, \
71 .write = _name##_write, \