dcr-regs.h File Reference

Go to the source code of this file.

Macros
#define	DCRN_CPR0_CONFIG_ADDR   0xc
#define	DCRN_CPR0_CONFIG_DATA   0xd
#define	DCRN_SDR0_CONFIG_ADDR   0xe
#define	DCRN_SDR0_CONFIG_DATA   0xf
#define	SDR0_PFC0   0x4100
#define	SDR0_PFC1   0x4101
#define	SDR0_PFC1_EPS   0x1c00000
#define	SDR0_PFC1_EPS_SHIFT   22
#define	SDR0_PFC1_RMII   0x02000000
#define	SDR0_MFR   0x4300
#define	SDR0_MFR_TAH0   0x80000000 /* TAHOE0 Enable */
#define	SDR0_MFR_TAH1   0x40000000 /* TAHOE1 Enable */
#define	SDR0_MFR_PCM   0x10000000 /* PPC440GP irq compat mode */
#define	SDR0_MFR_ECS   0x08000000 /* EMAC int clk */
#define	SDR0_MFR_T0TXFL   0x00080000
#define	SDR0_MFR_T0TXFH   0x00040000
#define	SDR0_MFR_T1TXFL   0x00020000
#define	SDR0_MFR_T1TXFH   0x00010000
#define	SDR0_MFR_E0TXFL   0x00008000
#define	SDR0_MFR_E0TXFH   0x00004000
#define	SDR0_MFR_E0RXFL   0x00002000
#define	SDR0_MFR_E0RXFH   0x00001000
#define	SDR0_MFR_E1TXFL   0x00000800
#define	SDR0_MFR_E1TXFH   0x00000400
#define	SDR0_MFR_E1RXFL   0x00000200
#define	SDR0_MFR_E1RXFH   0x00000100
#define	SDR0_MFR_E2TXFL   0x00000080
#define	SDR0_MFR_E2TXFH   0x00000040
#define	SDR0_MFR_E2RXFL   0x00000020
#define	SDR0_MFR_E2RXFH   0x00000010
#define	SDR0_MFR_E3TXFL   0x00000008
#define	SDR0_MFR_E3TXFH   0x00000004
#define	SDR0_MFR_E3RXFL   0x00000002
#define	SDR0_MFR_E3RXFH   0x00000001
#define	SDR0_UART0   0x0120
#define	SDR0_UART1   0x0121
#define	SDR0_UART2   0x0122
#define	SDR0_UART3   0x0123
#define	SDR0_CUST0   0x4000
#define	DCRN_SDR_ICINTSTAT   0x4510
#define	ICINTSTAT_ICRX   0x80000000
#define	ICINTSTAT_ICTX0   0x40000000
#define	ICINTSTAT_ICTX1   0x20000000
#define	ICINTSTAT_ICTX   0x60000000
#define	SDR0_ETH_CFG   0x4103
#define	SDR0_ETH_CFG_ECS   0x00000100 /* EMAC int clk source */
#define	DCRN_SRAM0_SB0CR   0x00
#define	DCRN_SRAM0_SB1CR   0x01
#define	DCRN_SRAM0_SB2CR   0x02
#define	DCRN_SRAM0_SB3CR   0x03
#define	SRAM_SBCR_BU_MASK   0x00000180
#define	SRAM_SBCR_BS_64KB   0x00000800
#define	SRAM_SBCR_BU_RO   0x00000080
#define	SRAM_SBCR_BU_RW   0x00000180
#define	DCRN_SRAM0_BEAR   0x04
#define	DCRN_SRAM0_BESR0   0x05
#define	DCRN_SRAM0_BESR1   0x06
#define	DCRN_SRAM0_PMEG   0x07
#define	DCRN_SRAM0_CID   0x08
#define	DCRN_SRAM0_REVID   0x09
#define	DCRN_SRAM0_DPC   0x0a
#define	SRAM_DPC_ENABLE   0x80000000
#define	DCRN_L2C0_CFG   0x00
#define	L2C_CFG_L2M   0x80000000
#define	L2C_CFG_ICU   0x40000000
#define	L2C_CFG_DCU   0x20000000
#define	L2C_CFG_DCW_MASK   0x1e000000
#define	L2C_CFG_TPC   0x01000000
#define	L2C_CFG_CPC   0x00800000
#define	L2C_CFG_FRAN   0x00200000
#define	L2C_CFG_SS_MASK   0x00180000
#define	L2C_CFG_SS_256   0x00000000
#define	L2C_CFG_CPIM   0x00040000
#define	L2C_CFG_TPIM   0x00020000
#define	L2C_CFG_LIM   0x00010000
#define	L2C_CFG_PMUX_MASK   0x00007000
#define	L2C_CFG_PMUX_SNP   0x00000000
#define	L2C_CFG_PMUX_IF   0x00001000
#define	L2C_CFG_PMUX_DF   0x00002000
#define	L2C_CFG_PMUX_DS   0x00003000
#define	L2C_CFG_PMIM   0x00000800
#define	L2C_CFG_TPEI   0x00000400
#define	L2C_CFG_CPEI   0x00000200
#define	L2C_CFG_NAM   0x00000100
#define	L2C_CFG_SMCM   0x00000080
#define	L2C_CFG_NBRM   0x00000040
#define	L2C_CFG_RDBW   0x00000008 /* only 460EX/GT */
#define	DCRN_L2C0_CMD   0x01
#define	L2C_CMD_CLR   0x80000000
#define	L2C_CMD_DIAG   0x40000000
#define	L2C_CMD_INV   0x20000000
#define	L2C_CMD_CCP   0x10000000
#define	L2C_CMD_CTE   0x08000000
#define	L2C_CMD_STRC   0x04000000
#define	L2C_CMD_STPC   0x02000000
#define	L2C_CMD_RPMC   0x01000000
#define	L2C_CMD_HCC   0x00800000
#define	DCRN_L2C0_ADDR   0x02
#define	DCRN_L2C0_DATA   0x03
#define	DCRN_L2C0_SR   0x04
#define	L2C_SR_CC   0x80000000
#define	L2C_SR_CPE   0x40000000
#define	L2C_SR_TPE   0x20000000
#define	L2C_SR_LRU   0x10000000
#define	L2C_SR_PCS   0x08000000
#define	DCRN_L2C0_REVID   0x05
#define	DCRN_L2C0_SNP0   0x06
#define	DCRN_L2C0_SNP1   0x07
#define	L2C_SNP_BA_MASK   0xffff0000
#define	L2C_SNP_SSR_MASK   0x0000f000
#define	L2C_SNP_SSR_32G   0x0000f000
#define	L2C_SNP_ESR   0x00000800
#define	DCRN_I2O0_IBAL   0x006
#define	DCRN_I2O0_IBAH   0x007
#define	I2O_REG_ENABLE   0x00000001 /* Enable I2O/DMA access */
#define	DCRN_SDR0_SRST   0x0200
#define	DCRN_SDR0_SRST_I2ODMA   (0x80000000 >> 15) /* Reset I2O/DMA */
#define	DCRN_MQ0_XORBA   0x04
#define	DCRN_MQ0_CF2H   0x06
#define	DCRN_MQ0_CFBHL   0x0f
#define	DCRN_MQ0_BAUH   0x10
#define	MQ0_CFBHL_TPLM   28
#define	MQ0_CFBHL_HBCL   23
#define	MQ0_CFBHL_POLY   15

Macro Definition Documentation

#define DCRN_CPR0_CONFIG_ADDR   0xc

Definition at line 28 of file dcr-regs.h.

#define DCRN_CPR0_CONFIG_DATA   0xd

Definition at line 29 of file dcr-regs.h.

#define DCRN_I2O0_IBAH   0x007

Definition at line 165 of file dcr-regs.h.

#define DCRN_I2O0_IBAL   0x006

Definition at line 164 of file dcr-regs.h.

#define DCRN_L2C0_ADDR   0x02

Definition at line 144 of file dcr-regs.h.

#define DCRN_L2C0_CFG   0x00

Definition at line 109 of file dcr-regs.h.

#define DCRN_L2C0_CMD   0x01

Definition at line 134 of file dcr-regs.h.

#define DCRN_L2C0_DATA   0x03

Definition at line 145 of file dcr-regs.h.

#define DCRN_L2C0_REVID   0x05

Definition at line 152 of file dcr-regs.h.

#define DCRN_L2C0_SNP0   0x06

Definition at line 153 of file dcr-regs.h.

#define DCRN_L2C0_SNP1   0x07

Definition at line 154 of file dcr-regs.h.

#define DCRN_L2C0_SR   0x04

Definition at line 146 of file dcr-regs.h.

#define DCRN_MQ0_BAUH   0x10

Definition at line 176 of file dcr-regs.h.

#define DCRN_MQ0_CF2H   0x06

Definition at line 174 of file dcr-regs.h.

#define DCRN_MQ0_CFBHL   0x0f

Definition at line 175 of file dcr-regs.h.

#define DCRN_MQ0_XORBA   0x04

Definition at line 173 of file dcr-regs.h.

#define DCRN_SDR0_CONFIG_ADDR   0xe

Definition at line 32 of file dcr-regs.h.

#define DCRN_SDR0_CONFIG_DATA   0xf

Definition at line 33 of file dcr-regs.h.

#define DCRN_SDR0_SRST   0x0200

Definition at line 169 of file dcr-regs.h.

#define DCRN_SDR0_SRST_I2ODMA   (0x80000000 >> 15) /* Reset I2O/DMA */

Definition at line 170 of file dcr-regs.h.

#define DCRN_SDR_ICINTSTAT   0x4510

Definition at line 72 of file dcr-regs.h.

#define DCRN_SRAM0_BEAR   0x04

Definition at line 95 of file dcr-regs.h.

#define DCRN_SRAM0_BESR0   0x05

Definition at line 96 of file dcr-regs.h.

#define DCRN_SRAM0_BESR1   0x06

Definition at line 97 of file dcr-regs.h.

#define DCRN_SRAM0_CID   0x08

Definition at line 99 of file dcr-regs.h.

#define DCRN_SRAM0_DPC   0x0a

Definition at line 101 of file dcr-regs.h.

#define DCRN_SRAM0_PMEG   0x07

Definition at line 98 of file dcr-regs.h.

#define DCRN_SRAM0_REVID   0x09

Definition at line 100 of file dcr-regs.h.

#define DCRN_SRAM0_SB0CR   0x00

Definition at line 87 of file dcr-regs.h.

#define DCRN_SRAM0_SB1CR   0x01

Definition at line 88 of file dcr-regs.h.

#define DCRN_SRAM0_SB2CR   0x02

Definition at line 89 of file dcr-regs.h.

#define DCRN_SRAM0_SB3CR   0x03

Definition at line 90 of file dcr-regs.h.

#define I2O_REG_ENABLE   0x00000001 /* Enable I2O/DMA access */

Definition at line 166 of file dcr-regs.h.

#define ICINTSTAT_ICRX   0x80000000

Definition at line 73 of file dcr-regs.h.

#define ICINTSTAT_ICTX   0x60000000

Definition at line 76 of file dcr-regs.h.

#define ICINTSTAT_ICTX0   0x40000000

Definition at line 74 of file dcr-regs.h.

#define ICINTSTAT_ICTX1   0x20000000

Definition at line 75 of file dcr-regs.h.

#define L2C_CFG_CPC   0x00800000

Definition at line 115 of file dcr-regs.h.

#define L2C_CFG_CPEI   0x00000200

Definition at line 129 of file dcr-regs.h.

#define L2C_CFG_CPIM   0x00040000

Definition at line 119 of file dcr-regs.h.

#define L2C_CFG_DCU   0x20000000

Definition at line 112 of file dcr-regs.h.

#define L2C_CFG_DCW_MASK   0x1e000000

Definition at line 113 of file dcr-regs.h.

#define L2C_CFG_FRAN   0x00200000

Definition at line 116 of file dcr-regs.h.

#define L2C_CFG_ICU   0x40000000

Definition at line 111 of file dcr-regs.h.

#define L2C_CFG_L2M   0x80000000

Definition at line 110 of file dcr-regs.h.

#define L2C_CFG_LIM   0x00010000

Definition at line 121 of file dcr-regs.h.

#define L2C_CFG_NAM   0x00000100

Definition at line 130 of file dcr-regs.h.

#define L2C_CFG_NBRM   0x00000040

Definition at line 132 of file dcr-regs.h.

#define L2C_CFG_PMIM   0x00000800

Definition at line 127 of file dcr-regs.h.

#define L2C_CFG_PMUX_DF   0x00002000

Definition at line 125 of file dcr-regs.h.

#define L2C_CFG_PMUX_DS   0x00003000

Definition at line 126 of file dcr-regs.h.

#define L2C_CFG_PMUX_IF   0x00001000

Definition at line 124 of file dcr-regs.h.

#define L2C_CFG_PMUX_MASK   0x00007000

Definition at line 122 of file dcr-regs.h.

#define L2C_CFG_PMUX_SNP   0x00000000

Definition at line 123 of file dcr-regs.h.

#define L2C_CFG_RDBW   0x00000008 /* only 460EX/GT */

Definition at line 133 of file dcr-regs.h.

#define L2C_CFG_SMCM   0x00000080

Definition at line 131 of file dcr-regs.h.

#define L2C_CFG_SS_256   0x00000000

Definition at line 118 of file dcr-regs.h.

#define L2C_CFG_SS_MASK   0x00180000

Definition at line 117 of file dcr-regs.h.

#define L2C_CFG_TPC   0x01000000

Definition at line 114 of file dcr-regs.h.

#define L2C_CFG_TPEI   0x00000400

Definition at line 128 of file dcr-regs.h.

#define L2C_CFG_TPIM   0x00020000

Definition at line 120 of file dcr-regs.h.

#define L2C_CMD_CCP   0x10000000

Definition at line 138 of file dcr-regs.h.

#define L2C_CMD_CLR   0x80000000

Definition at line 135 of file dcr-regs.h.

#define L2C_CMD_CTE   0x08000000

Definition at line 139 of file dcr-regs.h.

#define L2C_CMD_DIAG   0x40000000

Definition at line 136 of file dcr-regs.h.

#define L2C_CMD_HCC   0x00800000

Definition at line 143 of file dcr-regs.h.

#define L2C_CMD_INV   0x20000000

Definition at line 137 of file dcr-regs.h.

#define L2C_CMD_RPMC   0x01000000

Definition at line 142 of file dcr-regs.h.

#define L2C_CMD_STPC   0x02000000

Definition at line 141 of file dcr-regs.h.

#define L2C_CMD_STRC   0x04000000

Definition at line 140 of file dcr-regs.h.

#define L2C_SNP_BA_MASK   0xffff0000

Definition at line 155 of file dcr-regs.h.

#define L2C_SNP_ESR   0x00000800

Definition at line 158 of file dcr-regs.h.

#define L2C_SNP_SSR_32G   0x0000f000

Definition at line 157 of file dcr-regs.h.

#define L2C_SNP_SSR_MASK   0x0000f000

Definition at line 156 of file dcr-regs.h.

#define L2C_SR_CC   0x80000000

Definition at line 147 of file dcr-regs.h.

#define L2C_SR_CPE   0x40000000

Definition at line 148 of file dcr-regs.h.

#define L2C_SR_LRU   0x10000000

Definition at line 150 of file dcr-regs.h.

#define L2C_SR_PCS   0x08000000

Definition at line 151 of file dcr-regs.h.

#define L2C_SR_TPE   0x20000000

Definition at line 149 of file dcr-regs.h.

#define MQ0_CFBHL_HBCL   23

Definition at line 180 of file dcr-regs.h.

#define MQ0_CFBHL_POLY   15

Definition at line 181 of file dcr-regs.h.

#define MQ0_CFBHL_TPLM   28

Definition at line 179 of file dcr-regs.h.

#define SDR0_CUST0   0x4000

Definition at line 69 of file dcr-regs.h.

#define SDR0_ETH_CFG   0x4103

Definition at line 79 of file dcr-regs.h.

#define SDR0_ETH_CFG_ECS   0x00000100 /* EMAC int clk source */

Definition at line 80 of file dcr-regs.h.

#define SDR0_MFR   0x4300

Definition at line 40 of file dcr-regs.h.

#define SDR0_MFR_E0RXFH   0x00001000

Definition at line 52 of file dcr-regs.h.

#define SDR0_MFR_E0RXFL   0x00002000

Definition at line 51 of file dcr-regs.h.

#define SDR0_MFR_E0TXFH   0x00004000

Definition at line 50 of file dcr-regs.h.

#define SDR0_MFR_E0TXFL   0x00008000

Definition at line 49 of file dcr-regs.h.

#define SDR0_MFR_E1RXFH   0x00000100

Definition at line 56 of file dcr-regs.h.

#define SDR0_MFR_E1RXFL   0x00000200

Definition at line 55 of file dcr-regs.h.

#define SDR0_MFR_E1TXFH   0x00000400

Definition at line 54 of file dcr-regs.h.

#define SDR0_MFR_E1TXFL   0x00000800

Definition at line 53 of file dcr-regs.h.

#define SDR0_MFR_E2RXFH   0x00000010

Definition at line 60 of file dcr-regs.h.

#define SDR0_MFR_E2RXFL   0x00000020

Definition at line 59 of file dcr-regs.h.

#define SDR0_MFR_E2TXFH   0x00000040

Definition at line 58 of file dcr-regs.h.

#define SDR0_MFR_E2TXFL   0x00000080

Definition at line 57 of file dcr-regs.h.

#define SDR0_MFR_E3RXFH   0x00000001

Definition at line 64 of file dcr-regs.h.

#define SDR0_MFR_E3RXFL   0x00000002

Definition at line 63 of file dcr-regs.h.

#define SDR0_MFR_E3TXFH   0x00000004

Definition at line 62 of file dcr-regs.h.

#define SDR0_MFR_E3TXFL   0x00000008

Definition at line 61 of file dcr-regs.h.

#define SDR0_MFR_ECS   0x08000000 /* EMAC int clk */

Definition at line 44 of file dcr-regs.h.

#define SDR0_MFR_PCM   0x10000000 /* PPC440GP irq compat mode */

Definition at line 43 of file dcr-regs.h.

#define SDR0_MFR_T0TXFH   0x00040000

Definition at line 46 of file dcr-regs.h.

#define SDR0_MFR_T0TXFL   0x00080000

Definition at line 45 of file dcr-regs.h.

#define SDR0_MFR_T1TXFH   0x00010000

Definition at line 48 of file dcr-regs.h.

#define SDR0_MFR_T1TXFL   0x00020000

Definition at line 47 of file dcr-regs.h.

#define SDR0_MFR_TAH0   0x80000000 /* TAHOE0 Enable */

Definition at line 41 of file dcr-regs.h.

#define SDR0_MFR_TAH1   0x40000000 /* TAHOE1 Enable */

Definition at line 42 of file dcr-regs.h.

#define SDR0_PFC0   0x4100

Definition at line 35 of file dcr-regs.h.

#define SDR0_PFC1   0x4101

Definition at line 36 of file dcr-regs.h.

#define SDR0_PFC1_EPS   0x1c00000

Definition at line 37 of file dcr-regs.h.

#define SDR0_PFC1_EPS_SHIFT   22

Definition at line 38 of file dcr-regs.h.

#define SDR0_PFC1_RMII   0x02000000

Definition at line 39 of file dcr-regs.h.

#define SDR0_UART0   0x0120

Definition at line 65 of file dcr-regs.h.

#define SDR0_UART1   0x0121

Definition at line 66 of file dcr-regs.h.

#define SDR0_UART2   0x0122

Definition at line 67 of file dcr-regs.h.

#define SDR0_UART3   0x0123

Definition at line 68 of file dcr-regs.h.

#define SRAM_DPC_ENABLE   0x80000000

Definition at line 102 of file dcr-regs.h.

#define SRAM_SBCR_BS_64KB   0x00000800

Definition at line 92 of file dcr-regs.h.

#define SRAM_SBCR_BU_MASK   0x00000180

Definition at line 91 of file dcr-regs.h.

#define SRAM_SBCR_BU_RO   0x00000080

Definition at line 93 of file dcr-regs.h.

#define SRAM_SBCR_BU_RW   0x00000180

Definition at line 94 of file dcr-regs.h.