ddbridge-regs.h File Reference

Go to the source code of this file.

Macros
#define	CUR_REGISTERMAP_VERSION   0x10000
#define	HARDWARE_VERSION   0x00
#define	REGISTERMAP_VERSION   0x04
#define	SPI_CONTROL   0x10
#define	SPI_DATA   0x14
#define	INTERRUPT_BASE   (0x40)
#define	INTERRUPT_ENABLE   (INTERRUPT_BASE + 0x00)
#define	MSI0_ENABLE   (INTERRUPT_BASE + 0x00)
#define	MSI1_ENABLE   (INTERRUPT_BASE + 0x04)
#define	MSI2_ENABLE   (INTERRUPT_BASE + 0x08)
#define	MSI3_ENABLE   (INTERRUPT_BASE + 0x0C)
#define	MSI4_ENABLE   (INTERRUPT_BASE + 0x10)
#define	MSI5_ENABLE   (INTERRUPT_BASE + 0x14)
#define	MSI6_ENABLE   (INTERRUPT_BASE + 0x18)
#define	MSI7_ENABLE   (INTERRUPT_BASE + 0x1C)
#define	INTERRUPT_STATUS   (INTERRUPT_BASE + 0x20)
#define	INTERRUPT_ACK   (INTERRUPT_BASE + 0x20)
#define	INTMASK_I2C1   (0x00000001)
#define	INTMASK_I2C2   (0x00000002)
#define	INTMASK_I2C3   (0x00000004)
#define	INTMASK_I2C4   (0x00000008)
#define	INTMASK_CIRQ1   (0x00000010)
#define	INTMASK_CIRQ2   (0x00000020)
#define	INTMASK_CIRQ3   (0x00000040)
#define	INTMASK_CIRQ4   (0x00000080)
#define	INTMASK_TSINPUT1   (0x00000100)
#define	INTMASK_TSINPUT2   (0x00000200)
#define	INTMASK_TSINPUT3   (0x00000400)
#define	INTMASK_TSINPUT4   (0x00000800)
#define	INTMASK_TSINPUT5   (0x00001000)
#define	INTMASK_TSINPUT6   (0x00002000)
#define	INTMASK_TSINPUT7   (0x00004000)
#define	INTMASK_TSINPUT8   (0x00008000)
#define	INTMASK_TSOUTPUT1   (0x00010000)
#define	INTMASK_TSOUTPUT2   (0x00020000)
#define	INTMASK_TSOUTPUT3   (0x00040000)
#define	INTMASK_TSOUTPUT4   (0x00080000)
#define	I2C_BASE   (0x80) /* Byte offset */
#define	I2C_COMMAND   (0x00)
#define	I2C_TIMING   (0x04)
#define	I2C_TASKLENGTH   (0x08) /* High read, low write */
#define	I2C_TASKADDRESS   (0x0C) /* High read, low write */
#define	I2C_MONITOR   (0x1C)
#define	I2C_BASE_1   (I2C_BASE + 0x00)
#define	I2C_BASE_2   (I2C_BASE + 0x20)
#define	I2C_BASE_3   (I2C_BASE + 0x40)
#define	I2C_BASE_4   (I2C_BASE + 0x60)
#define	I2C_BASE_N(i)   (I2C_BASE + (i) * 0x20)
#define	I2C_TASKMEM_BASE   (0x1000) /* Byte offset */
#define	I2C_TASKMEM_SIZE   (0x1000)
#define	I2C_SPEED_400   (0x04030404)
#define	I2C_SPEED_200   (0x09080909)
#define	I2C_SPEED_154   (0x0C0B0C0C)
#define	I2C_SPEED_100   (0x13121313)
#define	I2C_SPEED_77   (0x19181919)
#define	I2C_SPEED_50   (0x27262727)
#define	DMA_BASE_WRITE   (0x100)
#define	DMA_BASE_READ   (0x140)
#define	DMA_CONTROL   (0x00) /* 64 */
#define	DMA_ERROR   (0x04) /* 65 ( only read instance ) */
#define	DMA_DIAG_CONTROL   (0x1C) /* 71 */
#define	DMA_DIAG_PACKETCOUNTER_LOW   (0x20) /* 72 */
#define	DMA_DIAG_PACKETCOUNTER_HIGH   (0x24) /* 73 */
#define	DMA_DIAG_TIMECOUNTER_LOW   (0x28) /* 74 */
#define	DMA_DIAG_TIMECOUNTER_HIGH   (0x2C) /* 75 */
#define	DMA_DIAG_RECHECKCOUNTER   (0x30) /* 76 ( Split completions on read ) */
#define	DMA_DIAG_WAITTIMEOUTINIT   (0x34) /* 77 */
#define	DMA_DIAG_WAITOVERFLOWCOUNTER   (0x38) /* 78 */
#define	DMA_DIAG_WAITCOUNTER   (0x3C) /* 79 */
#define	TS_INPUT_BASE   (0x200)
#define	TS_INPUT_CONTROL(i)   (TS_INPUT_BASE + (i) * 16 + 0x00)
#define	TS_OUTPUT_BASE   (0x280)
#define	TS_OUTPUT_CONTROL(i)   (TS_OUTPUT_BASE + (i) * 16 + 0x00)
#define	DMA_BUFFER_BASE   (0x300)
#define	DMA_BUFFER_CONTROL(i)   (DMA_BUFFER_BASE + (i) * 16 + 0x00)
#define	DMA_BUFFER_ACK(i)   (DMA_BUFFER_BASE + (i) * 16 + 0x04)
#define	DMA_BUFFER_CURRENT(i)   (DMA_BUFFER_BASE + (i) * 16 + 0x08)
#define	DMA_BUFFER_SIZE(i)   (DMA_BUFFER_BASE + (i) * 16 + 0x0c)
#define	DMA_BASE_ADDRESS_TABLE   (0x2000)
#define	DMA_BASE_ADDRESS_TABLE_ENTRIES   (512)

Macro Definition Documentation

#define CUR_REGISTERMAP_VERSION   0x10000

Definition at line 28 of file ddbridge-regs.h.

#define DMA_BASE_ADDRESS_TABLE   (0x2000)

Definition at line 149 of file ddbridge-regs.h.

#define DMA_BASE_ADDRESS_TABLE_ENTRIES   (512)

Definition at line 150 of file ddbridge-regs.h.

#define DMA_BASE_READ   (0x140)

Definition at line 118 of file ddbridge-regs.h.

#define DMA_BASE_WRITE   (0x100)

Definition at line 117 of file ddbridge-regs.h.

#define DMA_BUFFER_ACK

(

i

)

(DMA_BUFFER_BASE + (i) * 16 + 0x04)

Definition at line 145 of file ddbridge-regs.h.

#define DMA_BUFFER_BASE   (0x300)

Definition at line 142 of file ddbridge-regs.h.

#define DMA_BUFFER_CONTROL

(

i

)

(DMA_BUFFER_BASE + (i) * 16 + 0x00)

Definition at line 144 of file ddbridge-regs.h.

#define DMA_BUFFER_CURRENT

(

i

)

(DMA_BUFFER_BASE + (i) * 16 + 0x08)

Definition at line 146 of file ddbridge-regs.h.

#define DMA_BUFFER_SIZE

(

i

)

(DMA_BUFFER_BASE + (i) * 16 + 0x0c)

Definition at line 147 of file ddbridge-regs.h.

#define DMA_CONTROL   (0x00) /* 64 */

Definition at line 120 of file ddbridge-regs.h.

#define DMA_DIAG_CONTROL   (0x1C) /* 71 */

Definition at line 123 of file ddbridge-regs.h.

#define DMA_DIAG_PACKETCOUNTER_HIGH   (0x24) /* 73 */

Definition at line 125 of file ddbridge-regs.h.

#define DMA_DIAG_PACKETCOUNTER_LOW   (0x20) /* 72 */

Definition at line 124 of file ddbridge-regs.h.

#define DMA_DIAG_RECHECKCOUNTER   (0x30) /* 76 ( Split completions on read ) */

Definition at line 128 of file ddbridge-regs.h.

#define DMA_DIAG_TIMECOUNTER_HIGH   (0x2C) /* 75 */

Definition at line 127 of file ddbridge-regs.h.

#define DMA_DIAG_TIMECOUNTER_LOW   (0x28) /* 74 */

Definition at line 126 of file ddbridge-regs.h.

#define DMA_DIAG_WAITCOUNTER   (0x3C) /* 79 */

Definition at line 131 of file ddbridge-regs.h.

#define DMA_DIAG_WAITOVERFLOWCOUNTER   (0x38) /* 78 */

Definition at line 130 of file ddbridge-regs.h.

#define DMA_DIAG_WAITTIMEOUTINIT   (0x34) /* 77 */

Definition at line 129 of file ddbridge-regs.h.

#define DMA_ERROR   (0x04) /* 65 ( only read instance ) */

Definition at line 121 of file ddbridge-regs.h.

#define HARDWARE_VERSION   0x00

Definition at line 30 of file ddbridge-regs.h.

#define I2C_BASE   (0x80) /* Byte offset */

Definition at line 87 of file ddbridge-regs.h.

#define I2C_BASE_1   (I2C_BASE + 0x00)

Definition at line 96 of file ddbridge-regs.h.

#define I2C_BASE_2   (I2C_BASE + 0x20)

Definition at line 97 of file ddbridge-regs.h.

#define I2C_BASE_3   (I2C_BASE + 0x40)

Definition at line 98 of file ddbridge-regs.h.

#define I2C_BASE_4   (I2C_BASE + 0x60)

Definition at line 99 of file ddbridge-regs.h.

#define I2C_BASE_N

(

i

)

(I2C_BASE + (i) * 0x20)

Definition at line 101 of file ddbridge-regs.h.

#define I2C_COMMAND   (0x00)

Definition at line 89 of file ddbridge-regs.h.

#define I2C_MONITOR   (0x1C)

Definition at line 94 of file ddbridge-regs.h.

#define I2C_SPEED_100   (0x13121313)

Definition at line 109 of file ddbridge-regs.h.

#define I2C_SPEED_154   (0x0C0B0C0C)

Definition at line 108 of file ddbridge-regs.h.

#define I2C_SPEED_200   (0x09080909)

Definition at line 107 of file ddbridge-regs.h.

#define I2C_SPEED_400   (0x04030404)

Definition at line 106 of file ddbridge-regs.h.

#define I2C_SPEED_50   (0x27262727)

Definition at line 111 of file ddbridge-regs.h.

#define I2C_SPEED_77   (0x19181919)

Definition at line 110 of file ddbridge-regs.h.

#define I2C_TASKADDRESS   (0x0C) /* High read, low write */

Definition at line 92 of file ddbridge-regs.h.

#define I2C_TASKLENGTH   (0x08) /* High read, low write */

Definition at line 91 of file ddbridge-regs.h.

#define I2C_TASKMEM_BASE   (0x1000) /* Byte offset */

Definition at line 103 of file ddbridge-regs.h.

#define I2C_TASKMEM_SIZE   (0x1000)

Definition at line 104 of file ddbridge-regs.h.

#define I2C_TIMING   (0x04)

Definition at line 90 of file ddbridge-regs.h.

#define INTERRUPT_ACK   (INTERRUPT_BASE + 0x20)

Definition at line 58 of file ddbridge-regs.h.

#define INTERRUPT_BASE   (0x40)

Definition at line 45 of file ddbridge-regs.h.

#define INTERRUPT_ENABLE   (INTERRUPT_BASE + 0x00)

Definition at line 47 of file ddbridge-regs.h.

#define INTERRUPT_STATUS   (INTERRUPT_BASE + 0x20)

Definition at line 57 of file ddbridge-regs.h.

#define INTMASK_CIRQ1   (0x00000010)

Definition at line 65 of file ddbridge-regs.h.

#define INTMASK_CIRQ2   (0x00000020)

Definition at line 66 of file ddbridge-regs.h.

#define INTMASK_CIRQ3   (0x00000040)

Definition at line 67 of file ddbridge-regs.h.

#define INTMASK_CIRQ4   (0x00000080)

Definition at line 68 of file ddbridge-regs.h.

#define INTMASK_I2C1   (0x00000001)

Definition at line 60 of file ddbridge-regs.h.

#define INTMASK_I2C2   (0x00000002)

Definition at line 61 of file ddbridge-regs.h.

#define INTMASK_I2C3   (0x00000004)

Definition at line 62 of file ddbridge-regs.h.

#define INTMASK_I2C4   (0x00000008)

Definition at line 63 of file ddbridge-regs.h.

#define INTMASK_TSINPUT1   (0x00000100)

Definition at line 70 of file ddbridge-regs.h.

#define INTMASK_TSINPUT2   (0x00000200)

Definition at line 71 of file ddbridge-regs.h.

#define INTMASK_TSINPUT3   (0x00000400)

Definition at line 72 of file ddbridge-regs.h.

#define INTMASK_TSINPUT4   (0x00000800)

Definition at line 73 of file ddbridge-regs.h.

#define INTMASK_TSINPUT5   (0x00001000)

Definition at line 74 of file ddbridge-regs.h.

#define INTMASK_TSINPUT6   (0x00002000)

Definition at line 75 of file ddbridge-regs.h.

#define INTMASK_TSINPUT7   (0x00004000)

Definition at line 76 of file ddbridge-regs.h.

#define INTMASK_TSINPUT8   (0x00008000)

Definition at line 77 of file ddbridge-regs.h.

#define INTMASK_TSOUTPUT1   (0x00010000)

Definition at line 79 of file ddbridge-regs.h.

#define INTMASK_TSOUTPUT2   (0x00020000)

Definition at line 80 of file ddbridge-regs.h.

#define INTMASK_TSOUTPUT3   (0x00040000)

Definition at line 81 of file ddbridge-regs.h.

#define INTMASK_TSOUTPUT4   (0x00080000)

Definition at line 82 of file ddbridge-regs.h.

#define MSI0_ENABLE   (INTERRUPT_BASE + 0x00)

Definition at line 48 of file ddbridge-regs.h.

#define MSI1_ENABLE   (INTERRUPT_BASE + 0x04)

Definition at line 49 of file ddbridge-regs.h.

#define MSI2_ENABLE   (INTERRUPT_BASE + 0x08)

Definition at line 50 of file ddbridge-regs.h.

#define MSI3_ENABLE   (INTERRUPT_BASE + 0x0C)

Definition at line 51 of file ddbridge-regs.h.

#define MSI4_ENABLE   (INTERRUPT_BASE + 0x10)

Definition at line 52 of file ddbridge-regs.h.

#define MSI5_ENABLE   (INTERRUPT_BASE + 0x14)

Definition at line 53 of file ddbridge-regs.h.

#define MSI6_ENABLE   (INTERRUPT_BASE + 0x18)

Definition at line 54 of file ddbridge-regs.h.

#define MSI7_ENABLE   (INTERRUPT_BASE + 0x1C)

Definition at line 55 of file ddbridge-regs.h.

#define REGISTERMAP_VERSION   0x04

Definition at line 31 of file ddbridge-regs.h.

#define SPI_CONTROL   0x10

Definition at line 36 of file ddbridge-regs.h.

#define SPI_DATA   0x14

Definition at line 37 of file ddbridge-regs.h.

#define TS_INPUT_BASE   (0x200)

Definition at line 136 of file ddbridge-regs.h.

#define TS_INPUT_CONTROL

(

i

)

(TS_INPUT_BASE + (i) * 16 + 0x00)

Definition at line 137 of file ddbridge-regs.h.

#define TS_OUTPUT_BASE   (0x280)

Definition at line 139 of file ddbridge-regs.h.

#define TS_OUTPUT_CONTROL

(

i

)

(TS_OUTPUT_BASE + (i) * 16 + 0x00)

Definition at line 140 of file ddbridge-regs.h.