Macros
#define	REG_FIELD(scope, reg, field, value) REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )

#define	REG_FIELD_X_(value, shift) ((value) << shift)

#define	REG_STATE(scope, reg, field, symbolic_value) REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )

#define	REG_STATE_X_(k, shift) (k << shift)

#define	REG_MASK(scope, reg, field) REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )

#define	REG_MASK_X_(width, lsb) (((1 << width)-1) << lsb)

#define	REG_LSB(scope, reg, field) reg_##scope##_##reg##___##field##___lsb

#define	REG_BIT(scope, reg, field) reg_##scope##_##reg##___##field##___bit

#define	REG_ADDR(scope, inst, reg) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)

#define	REG_ADDR_X_(inst, offs) ((inst) + offs)

#define	REG_ADDR_VECT(scope, inst, reg, index)

#define	REG_ADDR_VECT_X_(inst, offs, index, stride) ((inst) + offs + (index) * stride)

#define	reg_ddr2_rw_cfg___col_width___lsb 0

#define	reg_ddr2_rw_cfg___col_width___width 4

#define	reg_ddr2_rw_cfg___nr_banks___lsb 4

#define	reg_ddr2_rw_cfg___nr_banks___width 1

#define	reg_ddr2_rw_cfg___nr_banks___bit 4

#define	reg_ddr2_rw_cfg___bw___lsb 5

#define	reg_ddr2_rw_cfg___bw___width 1

#define	reg_ddr2_rw_cfg___bw___bit 5

#define	reg_ddr2_rw_cfg___nr_ref___lsb 6

#define	reg_ddr2_rw_cfg___nr_ref___width 4

#define	reg_ddr2_rw_cfg___ref_interval___lsb 10

#define	reg_ddr2_rw_cfg___ref_interval___width 11

#define	reg_ddr2_rw_cfg___odt_ctrl___lsb 21

#define	reg_ddr2_rw_cfg___odt_ctrl___width 2

#define	reg_ddr2_rw_cfg___odt_mem___lsb 23

#define	reg_ddr2_rw_cfg___odt_mem___width 1

#define	reg_ddr2_rw_cfg___odt_mem___bit 23

#define	reg_ddr2_rw_cfg___imp_strength___lsb 24

#define	reg_ddr2_rw_cfg___imp_strength___width 1

#define	reg_ddr2_rw_cfg___imp_strength___bit 24

#define	reg_ddr2_rw_cfg___auto_imp_cal___lsb 25

#define	reg_ddr2_rw_cfg___auto_imp_cal___width 1

#define	reg_ddr2_rw_cfg___auto_imp_cal___bit 25

#define	reg_ddr2_rw_cfg___imp_cal_override___lsb 26

#define	reg_ddr2_rw_cfg___imp_cal_override___width 1

#define	reg_ddr2_rw_cfg___imp_cal_override___bit 26

#define	reg_ddr2_rw_cfg___dll_override___lsb 27

#define	reg_ddr2_rw_cfg___dll_override___width 1

#define	reg_ddr2_rw_cfg___dll_override___bit 27

#define	reg_ddr2_rw_cfg_offset 0

#define	reg_ddr2_rw_timing___wr___lsb 0

#define	reg_ddr2_rw_timing___wr___width 3

#define	reg_ddr2_rw_timing___rcd___lsb 3

#define	reg_ddr2_rw_timing___rcd___width 3

#define	reg_ddr2_rw_timing___rp___lsb 6

#define	reg_ddr2_rw_timing___rp___width 3

#define	reg_ddr2_rw_timing___ras___lsb 9

#define	reg_ddr2_rw_timing___ras___width 4

#define	reg_ddr2_rw_timing___rfc___lsb 13

#define	reg_ddr2_rw_timing___rfc___width 7

#define	reg_ddr2_rw_timing___rc___lsb 20

#define	reg_ddr2_rw_timing___rc___width 5

#define	reg_ddr2_rw_timing___rtp___lsb 25

#define	reg_ddr2_rw_timing___rtp___width 2

#define	reg_ddr2_rw_timing___rtw___lsb 27

#define	reg_ddr2_rw_timing___rtw___width 3

#define	reg_ddr2_rw_timing___wtr___lsb 30

#define	reg_ddr2_rw_timing___wtr___width 2

#define	reg_ddr2_rw_timing_offset 4

#define	reg_ddr2_rw_latency___cas___lsb 0

#define	reg_ddr2_rw_latency___cas___width 3

#define	reg_ddr2_rw_latency___additive___lsb 3

#define	reg_ddr2_rw_latency___additive___width 3

#define	reg_ddr2_rw_latency_offset 8

#define	reg_ddr2_rw_phy_cfg___en___lsb 0

#define	reg_ddr2_rw_phy_cfg___en___width 1

#define	reg_ddr2_rw_phy_cfg___en___bit 0

#define	reg_ddr2_rw_phy_cfg_offset 12

#define	reg_ddr2_rw_phy_ctrl___rst___lsb 0

#define	reg_ddr2_rw_phy_ctrl___rst___width 1

#define	reg_ddr2_rw_phy_ctrl___rst___bit 0

#define	reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1

#define	reg_ddr2_rw_phy_ctrl___cal_rst___width 1

#define	reg_ddr2_rw_phy_ctrl___cal_rst___bit 1

#define	reg_ddr2_rw_phy_ctrl___cal_start___lsb 2

#define	reg_ddr2_rw_phy_ctrl___cal_start___width 1

#define	reg_ddr2_rw_phy_ctrl___cal_start___bit 2

#define	reg_ddr2_rw_phy_ctrl_offset 16

#define	reg_ddr2_rw_ctrl___mrs_data___lsb 0

#define	reg_ddr2_rw_ctrl___mrs_data___width 16

#define	reg_ddr2_rw_ctrl___cmd___lsb 16

#define	reg_ddr2_rw_ctrl___cmd___width 8

#define	reg_ddr2_rw_ctrl_offset 20

#define	reg_ddr2_rw_pwr_down___self_ref___lsb 0

#define	reg_ddr2_rw_pwr_down___self_ref___width 2

#define	reg_ddr2_rw_pwr_down___phy_en___lsb 2

#define	reg_ddr2_rw_pwr_down___phy_en___width 1

#define	reg_ddr2_rw_pwr_down___phy_en___bit 2

#define	reg_ddr2_rw_pwr_down_offset 24

#define	reg_ddr2_r_stat___dll_lock___lsb 0

#define	reg_ddr2_r_stat___dll_lock___width 1

#define	reg_ddr2_r_stat___dll_lock___bit 0

#define	reg_ddr2_r_stat___dll_delay_code___lsb 1

#define	reg_ddr2_r_stat___dll_delay_code___width 7

#define	reg_ddr2_r_stat___imp_cal_done___lsb 8

#define	reg_ddr2_r_stat___imp_cal_done___width 1

#define	reg_ddr2_r_stat___imp_cal_done___bit 8

#define	reg_ddr2_r_stat___imp_cal_fault___lsb 9

#define	reg_ddr2_r_stat___imp_cal_fault___width 1

#define	reg_ddr2_r_stat___imp_cal_fault___bit 9

#define	reg_ddr2_r_stat___cal_imp_pu___lsb 10

#define	reg_ddr2_r_stat___cal_imp_pu___width 4

#define	reg_ddr2_r_stat___cal_imp_pd___lsb 14

#define	reg_ddr2_r_stat___cal_imp_pd___width 4

#define	reg_ddr2_r_stat_offset 28

#define	reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0

#define	reg_ddr2_rw_imp_ctrl___imp_pu___width 4

#define	reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4

#define	reg_ddr2_rw_imp_ctrl___imp_pd___width 4

#define	reg_ddr2_rw_imp_ctrl_offset 32

#define	STRIDE_ddr2_rw_dll_ctrl 4

#define	reg_ddr2_rw_dll_ctrl___mode___lsb 0

#define	reg_ddr2_rw_dll_ctrl___mode___width 1

#define	reg_ddr2_rw_dll_ctrl___mode___bit 0

#define	reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1

#define	reg_ddr2_rw_dll_ctrl___clk_delay___width 7

#define	reg_ddr2_rw_dll_ctrl_offset 36

#define	STRIDE_ddr2_rw_dqs_dll_ctrl 4

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21

#define	reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7

#define	reg_ddr2_rw_dqs_dll_ctrl_offset 52

#define	regk_ddr2_al0 0x00000000

#define	regk_ddr2_al1 0x00000008

#define	regk_ddr2_al2 0x00000010

#define	regk_ddr2_al3 0x00000018

#define	regk_ddr2_al4 0x00000020

#define	regk_ddr2_auto 0x00000003

#define	regk_ddr2_bank4 0x00000000

#define	regk_ddr2_bank8 0x00000001

#define	regk_ddr2_bl4 0x00000002

#define	regk_ddr2_bl8 0x00000003

#define	regk_ddr2_bt_il 0x00000008

#define	regk_ddr2_bt_seq 0x00000000

#define	regk_ddr2_bw16 0x00000001

#define	regk_ddr2_bw32 0x00000000

#define	regk_ddr2_cas2 0x00000020

#define	regk_ddr2_cas3 0x00000030

#define	regk_ddr2_cas4 0x00000040

#define	regk_ddr2_cas5 0x00000050

#define	regk_ddr2_deselect 0x000000c0

#define	regk_ddr2_dic_weak 0x00000002

#define	regk_ddr2_direct 0x00000001

#define	regk_ddr2_dis 0x00000000

#define	regk_ddr2_dll_dis 0x00000001

#define	regk_ddr2_dll_en 0x00000000

#define	regk_ddr2_dll_rst 0x00000100

#define	regk_ddr2_emrs 0x00000081

#define	regk_ddr2_emrs2 0x00000082

#define	regk_ddr2_emrs3 0x00000083

#define	regk_ddr2_full 0x00000001

#define	regk_ddr2_hi_ref_rate 0x00000080

#define	regk_ddr2_mrs 0x00000080

#define	regk_ddr2_no 0x00000000

#define	regk_ddr2_nop 0x000000b8

#define	regk_ddr2_ocd_adj 0x00000200

#define	regk_ddr2_ocd_default 0x00000380

#define	regk_ddr2_ocd_drive0 0x00000100

#define	regk_ddr2_ocd_drive1 0x00000080

#define	regk_ddr2_ocd_exit 0x00000000

#define	regk_ddr2_odt_dis 0x00000000

#define	regk_ddr2_offs 0x00000000

#define	regk_ddr2_pre 0x00000090

#define	regk_ddr2_pre_all 0x00000400

#define	regk_ddr2_pwr_down_fast 0x00000000

#define	regk_ddr2_pwr_down_slow 0x00001000

#define	regk_ddr2_ref 0x00000088

#define	regk_ddr2_rtt150 0x00000040

#define	regk_ddr2_rtt50 0x00000044

#define	regk_ddr2_rtt75 0x00000004

#define	regk_ddr2_rw_cfg_default 0x00186000

#define	regk_ddr2_rw_dll_ctrl_default 0x00000000

#define	regk_ddr2_rw_dll_ctrl_size 0x00000004

#define	regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000

#define	regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004

#define	regk_ddr2_rw_latency_default 0x00000000

#define	regk_ddr2_rw_phy_cfg_default 0x00000000

#define	regk_ddr2_rw_pwr_down_default 0x00000000

#define	regk_ddr2_rw_timing_default 0x00000000

#define	regk_ddr2_s1Gb 0x0000001a

#define	regk_ddr2_s256Mb 0x0000000f

#define	regk_ddr2_s2Gb 0x00000027

#define	regk_ddr2_s4Gb 0x00000042

#define	regk_ddr2_s512Mb 0x00000015

#define	regk_ddr2_temp0_85 0x00000618

#define	regk_ddr2_temp85_95 0x0000030c

#define	regk_ddr2_term150 0x00000002

#define	regk_ddr2_term50 0x00000003

#define	regk_ddr2_term75 0x00000001

#define	regk_ddr2_test 0x00000080

#define	regk_ddr2_weak 0x00000000

#define	regk_ddr2_wr2 0x00000200

#define	regk_ddr2_wr3 0x00000400

#define	regk_ddr2_yes 0x00000001

Macro Definition Documentation

#define REG_ADDR	(	scope,
		inst,
		reg
	)	REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)

Definition at line 41 of file ddr2_defs_asm.h.

#define REG_ADDR_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \

STRIDE_##scope##_##reg )

Definition at line 46 of file ddr2_defs_asm.h.

#define REG_ADDR_VECT_X_	(	inst,
		offs,
		index,
		stride
	)	((inst) + offs + (index) * stride)

Definition at line 49 of file ddr2_defs_asm.h.

#define REG_ADDR_X_	(	inst,
		offs
	)	((inst) + offs)

Definition at line 42 of file ddr2_defs_asm.h.

#define REG_BIT	(	scope,
		reg,
		field
	)	reg_##scope##_##reg##___##field##___bit

Definition at line 37 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___cal_imp_pd___lsb 14

Definition at line 160 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___cal_imp_pd___width 4

Definition at line 161 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___cal_imp_pu___lsb 10

Definition at line 158 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___cal_imp_pu___width 4

Definition at line 159 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___dll_delay_code___lsb 1

Definition at line 150 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___dll_delay_code___width 7

Definition at line 151 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___dll_lock___bit 0

Definition at line 149 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___dll_lock___lsb 0

Definition at line 147 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___dll_lock___width 1

Definition at line 148 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_done___bit 8

Definition at line 154 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_done___lsb 8

Definition at line 152 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_done___width 1

Definition at line 153 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_fault___bit 9

Definition at line 157 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_fault___lsb 9

Definition at line 155 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat___imp_cal_fault___width 1

Definition at line 156 of file ddr2_defs_asm.h.

#define reg_ddr2_r_stat_offset 28

Definition at line 162 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25

Definition at line 76 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25

Definition at line 74 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___auto_imp_cal___width 1

Definition at line 75 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___bw___bit 5

Definition at line 61 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___bw___lsb 5

Definition at line 59 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___bw___width 1

Definition at line 60 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___col_width___lsb 0

Definition at line 54 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___col_width___width 4

Definition at line 55 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___dll_override___bit 27

Definition at line 82 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___dll_override___lsb 27

Definition at line 80 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___dll_override___width 1

Definition at line 81 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_cal_override___bit 26

Definition at line 79 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26

Definition at line 77 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_cal_override___width 1

Definition at line 78 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_strength___bit 24

Definition at line 73 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_strength___lsb 24

Definition at line 71 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___imp_strength___width 1

Definition at line 72 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___nr_banks___bit 4

Definition at line 58 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___nr_banks___lsb 4

Definition at line 56 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___nr_banks___width 1

Definition at line 57 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___nr_ref___lsb 6

Definition at line 62 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___nr_ref___width 4

Definition at line 63 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21

Definition at line 66 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___odt_ctrl___width 2

Definition at line 67 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___odt_mem___bit 23

Definition at line 70 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___odt_mem___lsb 23

Definition at line 68 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___odt_mem___width 1

Definition at line 69 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___ref_interval___lsb 10

Definition at line 64 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg___ref_interval___width 11

Definition at line 65 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_cfg_offset 0

Definition at line 83 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_ctrl___cmd___lsb 16

Definition at line 134 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_ctrl___cmd___width 8

Definition at line 135 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_ctrl___mrs_data___lsb 0

Definition at line 132 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_ctrl___mrs_data___width 16

Definition at line 133 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_ctrl_offset 20

Definition at line 136 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1

Definition at line 176 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7

Definition at line 177 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl___mode___bit 0

Definition at line 175 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl___mode___lsb 0

Definition at line 173 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl___mode___width 1

Definition at line 174 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dll_ctrl_offset 36

Definition at line 178 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7

Definition at line 184 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7

Definition at line 185 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14

Definition at line 186 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7

Definition at line 187 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21

Definition at line 188 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7

Definition at line 189 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0

Definition at line 182 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7

Definition at line 183 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_dqs_dll_ctrl_offset 52

Definition at line 190 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4

Definition at line 167 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4

Definition at line 168 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0

Definition at line 165 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4

Definition at line 166 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_imp_ctrl_offset 32

Definition at line 169 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_latency___additive___lsb 3

Definition at line 109 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_latency___additive___width 3

Definition at line 110 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_latency___cas___lsb 0

Definition at line 107 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_latency___cas___width 3

Definition at line 108 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_latency_offset 8

Definition at line 111 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_cfg___en___bit 0

Definition at line 116 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_cfg___en___lsb 0

Definition at line 114 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_cfg___en___width 1

Definition at line 115 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_cfg_offset 12

Definition at line 117 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1

Definition at line 125 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1

Definition at line 123 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1

Definition at line 124 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2

Definition at line 128 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2

Definition at line 126 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___cal_start___width 1

Definition at line 127 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___rst___bit 0

Definition at line 122 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___rst___lsb 0

Definition at line 120 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl___rst___width 1

Definition at line 121 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_phy_ctrl_offset 16

Definition at line 129 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down___phy_en___bit 2

Definition at line 143 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down___phy_en___lsb 2

Definition at line 141 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down___phy_en___width 1

Definition at line 142 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down___self_ref___lsb 0

Definition at line 139 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down___self_ref___width 2

Definition at line 140 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_pwr_down_offset 24

Definition at line 144 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___ras___lsb 9

Definition at line 92 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___ras___width 4

Definition at line 93 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rc___lsb 20

Definition at line 96 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rc___width 5

Definition at line 97 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rcd___lsb 3

Definition at line 88 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rcd___width 3

Definition at line 89 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rfc___lsb 13

Definition at line 94 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rfc___width 7

Definition at line 95 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rp___lsb 6

Definition at line 90 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rp___width 3

Definition at line 91 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rtp___lsb 25

Definition at line 98 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rtp___width 2

Definition at line 99 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rtw___lsb 27

Definition at line 100 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___rtw___width 3

Definition at line 101 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___wr___lsb 0

Definition at line 86 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___wr___width 3

Definition at line 87 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___wtr___lsb 30

Definition at line 102 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing___wtr___width 2

Definition at line 103 of file ddr2_defs_asm.h.

#define reg_ddr2_rw_timing_offset 4

Definition at line 104 of file ddr2_defs_asm.h.

#define REG_FIELD	(	scope,
		reg,
		field,
		value
	)	REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )

Definition at line 15 of file ddr2_defs_asm.h.

#define REG_FIELD_X_	(	value,
		shift
	)	((value) << shift)

Definition at line 17 of file ddr2_defs_asm.h.

#define REG_LSB	(	scope,
		reg,
		field
	)	reg_##scope##_##reg##___##field##___lsb

Definition at line 33 of file ddr2_defs_asm.h.

#define REG_MASK	(	scope,
		reg,
		field
	)	REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )

Definition at line 27 of file ddr2_defs_asm.h.

#define REG_MASK_X_	(	width,
		lsb
	)	(((1 << width)-1) << lsb)

Definition at line 29 of file ddr2_defs_asm.h.

#define REG_STATE	(	scope,
		reg,
		field,
		symbolic_value
	)	REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )

Definition at line 21 of file ddr2_defs_asm.h.

#define REG_STATE_X_	(	k,
		shift
	)	(k << shift)

Definition at line 23 of file ddr2_defs_asm.h.

#define regk_ddr2_al0 0x00000000

Definition at line 194 of file ddr2_defs_asm.h.

#define regk_ddr2_al1 0x00000008

Definition at line 195 of file ddr2_defs_asm.h.

#define regk_ddr2_al2 0x00000010

Definition at line 196 of file ddr2_defs_asm.h.

#define regk_ddr2_al3 0x00000018

Definition at line 197 of file ddr2_defs_asm.h.

#define regk_ddr2_al4 0x00000020

Definition at line 198 of file ddr2_defs_asm.h.

#define regk_ddr2_auto 0x00000003

Definition at line 199 of file ddr2_defs_asm.h.

#define regk_ddr2_bank4 0x00000000

Definition at line 200 of file ddr2_defs_asm.h.

#define regk_ddr2_bank8 0x00000001

Definition at line 201 of file ddr2_defs_asm.h.

#define regk_ddr2_bl4 0x00000002

Definition at line 202 of file ddr2_defs_asm.h.

#define regk_ddr2_bl8 0x00000003

Definition at line 203 of file ddr2_defs_asm.h.

#define regk_ddr2_bt_il 0x00000008

Definition at line 204 of file ddr2_defs_asm.h.

#define regk_ddr2_bt_seq 0x00000000

Definition at line 205 of file ddr2_defs_asm.h.

#define regk_ddr2_bw16 0x00000001

Definition at line 206 of file ddr2_defs_asm.h.

#define regk_ddr2_bw32 0x00000000

Definition at line 207 of file ddr2_defs_asm.h.

#define regk_ddr2_cas2 0x00000020

Definition at line 208 of file ddr2_defs_asm.h.

#define regk_ddr2_cas3 0x00000030

Definition at line 209 of file ddr2_defs_asm.h.

#define regk_ddr2_cas4 0x00000040

Definition at line 210 of file ddr2_defs_asm.h.

#define regk_ddr2_cas5 0x00000050

Definition at line 211 of file ddr2_defs_asm.h.

#define regk_ddr2_deselect 0x000000c0

Definition at line 212 of file ddr2_defs_asm.h.

#define regk_ddr2_dic_weak 0x00000002

Definition at line 213 of file ddr2_defs_asm.h.

#define regk_ddr2_direct 0x00000001

Definition at line 214 of file ddr2_defs_asm.h.

#define regk_ddr2_dis 0x00000000

Definition at line 215 of file ddr2_defs_asm.h.

#define regk_ddr2_dll_dis 0x00000001

Definition at line 216 of file ddr2_defs_asm.h.

#define regk_ddr2_dll_en 0x00000000

Definition at line 217 of file ddr2_defs_asm.h.

#define regk_ddr2_dll_rst 0x00000100

Definition at line 218 of file ddr2_defs_asm.h.

#define regk_ddr2_emrs 0x00000081

Definition at line 219 of file ddr2_defs_asm.h.

#define regk_ddr2_emrs2 0x00000082

Definition at line 220 of file ddr2_defs_asm.h.

#define regk_ddr2_emrs3 0x00000083

Definition at line 221 of file ddr2_defs_asm.h.

#define regk_ddr2_full 0x00000001

Definition at line 222 of file ddr2_defs_asm.h.

#define regk_ddr2_hi_ref_rate 0x00000080

Definition at line 223 of file ddr2_defs_asm.h.

#define regk_ddr2_mrs 0x00000080

Definition at line 224 of file ddr2_defs_asm.h.

#define regk_ddr2_no 0x00000000

Definition at line 225 of file ddr2_defs_asm.h.

#define regk_ddr2_nop 0x000000b8

Definition at line 226 of file ddr2_defs_asm.h.

#define regk_ddr2_ocd_adj 0x00000200

Definition at line 227 of file ddr2_defs_asm.h.

#define regk_ddr2_ocd_default 0x00000380

Definition at line 228 of file ddr2_defs_asm.h.

#define regk_ddr2_ocd_drive0 0x00000100

Definition at line 229 of file ddr2_defs_asm.h.

#define regk_ddr2_ocd_drive1 0x00000080

Definition at line 230 of file ddr2_defs_asm.h.

#define regk_ddr2_ocd_exit 0x00000000

Definition at line 231 of file ddr2_defs_asm.h.

#define regk_ddr2_odt_dis 0x00000000

Definition at line 232 of file ddr2_defs_asm.h.

#define regk_ddr2_offs 0x00000000

Definition at line 233 of file ddr2_defs_asm.h.

#define regk_ddr2_pre 0x00000090

Definition at line 234 of file ddr2_defs_asm.h.

#define regk_ddr2_pre_all 0x00000400

Definition at line 235 of file ddr2_defs_asm.h.

#define regk_ddr2_pwr_down_fast 0x00000000

Definition at line 236 of file ddr2_defs_asm.h.

#define regk_ddr2_pwr_down_slow 0x00001000

Definition at line 237 of file ddr2_defs_asm.h.

#define regk_ddr2_ref 0x00000088

Definition at line 238 of file ddr2_defs_asm.h.

#define regk_ddr2_rtt150 0x00000040

Definition at line 239 of file ddr2_defs_asm.h.

#define regk_ddr2_rtt50 0x00000044

Definition at line 240 of file ddr2_defs_asm.h.

#define regk_ddr2_rtt75 0x00000004

Definition at line 241 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_cfg_default 0x00186000

Definition at line 242 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_dll_ctrl_default 0x00000000

Definition at line 243 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_dll_ctrl_size 0x00000004

Definition at line 244 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000

Definition at line 245 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004

Definition at line 246 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_latency_default 0x00000000

Definition at line 247 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_phy_cfg_default 0x00000000

Definition at line 248 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_pwr_down_default 0x00000000

Definition at line 249 of file ddr2_defs_asm.h.

#define regk_ddr2_rw_timing_default 0x00000000

Definition at line 250 of file ddr2_defs_asm.h.

#define regk_ddr2_s1Gb 0x0000001a

Definition at line 251 of file ddr2_defs_asm.h.

#define regk_ddr2_s256Mb 0x0000000f

Definition at line 252 of file ddr2_defs_asm.h.

#define regk_ddr2_s2Gb 0x00000027

Definition at line 253 of file ddr2_defs_asm.h.

#define regk_ddr2_s4Gb 0x00000042

Definition at line 254 of file ddr2_defs_asm.h.

#define regk_ddr2_s512Mb 0x00000015

Definition at line 255 of file ddr2_defs_asm.h.

#define regk_ddr2_temp0_85 0x00000618

Definition at line 256 of file ddr2_defs_asm.h.

#define regk_ddr2_temp85_95 0x0000030c

Definition at line 257 of file ddr2_defs_asm.h.

#define regk_ddr2_term150 0x00000002

Definition at line 258 of file ddr2_defs_asm.h.

#define regk_ddr2_term50 0x00000003

Definition at line 259 of file ddr2_defs_asm.h.

#define regk_ddr2_term75 0x00000001

Definition at line 260 of file ddr2_defs_asm.h.

#define regk_ddr2_test 0x00000080

Definition at line 261 of file ddr2_defs_asm.h.

#define regk_ddr2_weak 0x00000000

Definition at line 262 of file ddr2_defs_asm.h.

#define regk_ddr2_wr2 0x00000200

Definition at line 263 of file ddr2_defs_asm.h.

#define regk_ddr2_wr3 0x00000400

Definition at line 264 of file ddr2_defs_asm.h.

#define regk_ddr2_yes 0x00000001

Definition at line 265 of file ddr2_defs_asm.h.

#define STRIDE_ddr2_rw_dll_ctrl 4

Definition at line 171 of file ddr2_defs_asm.h.

#define STRIDE_ddr2_rw_dqs_dll_ctrl 4

Definition at line 180 of file ddr2_defs_asm.h.

Macros

Macro Definition Documentation